DTM

Data Conversion Circuits – D/A and A/D Converters 483 {Most D1 C1 Significant B1 Digit A1 (MSD) {Least D0 BCD Analog O/P C0 D/A Significant B0 Converter Digit A0 (LSD) Figure 12.10 BCD-input D/A converter. Example 12.1 An eight-bit D/A converter has a step size of 20 mV. Determine the full-scale output and percentage resolution. Solution • (1/28 × V = 20 × 10−3, where V is the voltage corresponding to a logic ‘1’. • This gives V = 20 × 10−3× 28 = 5.12V. • The full-scale output = [(2n− 1)/2n] × V = [(28− 1)/28] × 5.12 = (255/256) × 5.12 = 5.1V. • The percentage resolution = [1/(2n−1)] ×100 = 100/255 = 0 392%. • The percentage resolution can also be determined from: (Step size/full-scale output) × 100 = (20 × 10−3/5.1) × 100 = 0.392 %. Example 12.2 Refer to Fig. 12.11. This BCD D/A converter has a step size of 6.25 mV. Determine the full-scale output. Solution • A step size of 6.25 mV implies that A0 has a weight of 6.25 mV. • The weights of B0, C0 and D0 would respectively be 12.5, 25 and 50 mV. • Now, the weight of A1 will be 10 times the weight of A0, i.e. the weight of A1will be 62.5 mV. • The weights of B1, C1 and D1will accordingly be 125, 250 and 500 mV respectively. • On similar lines, the weights of A2, B2, C2 and D2 will respectively be 625 mV, 1.25 V, 2.5 V and 5 V. • For full-scale output, the input will be decimal 999. Each of the three four-bit groups will be 1001. • Therefore, the full-scale analogue output = 6.25 + 50 + 62.5 +500 + 625 + 5000 mV = 6.24375 V. • The full-scale analogue output can also be determined from the product of the step size and number of steps. That is, the full-scale output = 6.25 × 999 = 6.24375 V.

484 Digital Electronics MSD { D2C2 MSB B2 LSB A2 MSB D1 D/A O/P C1 Converter B1 LSB A1 MSB {LSD D0 LSB C0 B0 A0 Figure 12.11 BCD-input D/A converter (example 12.2). Example 12.3 A certain eight-bit D/A converter has a full-scale output of 5 mA and a full-scale error of ±0.25 % of full scale. Determine the range of expected analogue output for a digital input of 10000010. Solution Full-scale output Number of steps • Step size = 5 × 10−3 = 28 − 1 = 19.6 A • For a digital input of 10000010 (= 13010 the analogue output is given by 130 × 19.6 = 2.548 mA. • Error = 0 25 × 5 × 10−3 ± 100 = ± 12.5 A • The expected analogue output will therefore be in the range 2.5355–2.5605 mA. Example 12.4 An experimenter connects a four-bit ripple counter to a four-bit D/A converter to perform a staircase test using a 1 kHz clock as shown in Fig. 12.12. The output staircase waveform is shown in Fig. 12.13. The cause of the incorrect staircase signal is later determined to be a wrong connection between the counter output and the D/A converter input. What is it? Solution The correct staircase waveform would be generated at the output of the D/A converter if the counter outputs Q0 (LSB), Q1, Q2 and Q3 (MSB) were connected to the corresponding inputs