Laptop Repair Part 1 OCR_clone

_ _ _D ~~J !l~ 9 IMON 10 VR HO T# 11 NTC 12 vw iIlu-_t_E~J.ll1E~_t_/]t4Iii~f~COMP fflT~~~lli~T.i~ 1 8~Jf~ ~$ (8k.Q ~~.ll:k~ 300kHz) 13 14 lSEN3/F 3 ~lliifnjT.i~ 1 nGW.19 3 ;f§BtfflT~m~jfE::;f§~~mt. 3l!Cw..19 2 tI 15 B2 D1, pgfff\\ii~ FB2 ~ FB JJt4J8~Jf:*fflTifnjT.i~H~~ffi~1J~I ~:MJ.l. 3nGJ!..19 1 t~Bt, *:*x3'& 16 ISEN2 17 ISENI 18 VSEN 19 RTN 20 ISUMN 21 lSUMP 22 VDD 5V~~ VIN 24 PROG I iIl)i-_t_~~.lliif.lJlJ:I:&I3I~EEil15:. ifnjT.i~~ OOT ~Bi 25 BOOTI ~lliirnJT.i~ 1 I¥Jjg-*o §~ PHASE /]t4I 26 27 28 6!J29 LGATEI Fl!J.liiPnJT.i~ 1 1¥J~-*O~1i 30 PWM3 Fl!J.li~1J ~ 1 I¥J~=~ 31 VCCP pg fff\\Jmz;/J~ Jt 1¥J-mJt!, i ! H 32 LGATE2 ~J.li~\"iJ~ 1 I¥Jjg=*OJE 33 34 35 I¥J_-36 BOOT2 Et! J.li iIlI\"iJB 1 PHASE IJ!1J 37 LGATE Et!ffi~lHt 21¥J\"\"F G -]8'1- Scanned by CamScanner

PHASE 38 G UGATE 39 G 40 BOOTG 41 3~ ISUMNG ~~IJ 5V, ~$j-~ffl 9583J U-¥JJltIf!~ VR_ON ~AJtf~ffiJHji£;jlil~~DOO 9-68 p}TiF, VR_ON ;01~E/3 ;JC-o O.3V, ISL95831HRTZ If! VR_ON ;0~Jtffl~j~(lJ {ijg O.7V, ISL958311RTZ -o ~~Jt~I'fCJ./NI~ 0.75V. ~sa1 data manual the screenshot of the description of the input level threshold value ~~~in fi~!h-68tbe maximum value of VR_ON in the low level is O.3V.in the minimum aloe of VR_ON in the high level is O.7V,in the ISL95831IRTZ.the inrtbe liigh.level is O.7SV. •• _~ ~o.7;- D.3 ... G.7. ~ Vv Scanned by CamScanner

>-----1 RTN Figure 9-69 Three power supplies SVID wavefonn starting -186- Scanned by CamScanner

11¥J PROGl \"ftG.l.m~ 9-15. ·,{,:;'::Io.!~.~'figurationofPROG] pin of ISL9583I is shown in table 9-15. the configuration of PROG1 in the ISL95831 data manual(the original in English) .. RPROG1 VsoOT VR11CCMAX (A) (IIIIun) IV) With POWER·UP CONFIGURATION Max. (a) Typ. t+3%) 3-PH 2-PH 1-PH 0 99 66 33 0.61 0 93 62 31 1.13 0 87 58 29 1.74 0 81 54 I 27 0 75 50 25 0 69 46 23 0 63 42 21 0 67 38 19 111 67 38 19 63 42 21 46 23 50 25 54 27 III 29 82 31 88 33 are Scanned by CamScanner

lSL9S831 B~ PROG2 ~f£.mm~ 9-16. The configuration of PROG2 of ISL9S83I is shown in table 9-16. ¥191JM~: Give some examples to explain: ~~ PROG2 ~imii O~~Jil.tl±t!!Jlt, ~J:f~ii7mr.f~H?f1i751120·C, [email protected] tJ:l Eg~m.Ntk 33A. When PROG2 connects the ground through O~ resistance,the value of the over-temperature protection of the chip is 120·C,the maximum of the output current of the second path of the voltage regulator is 33A. ~~ PROG2 ~imi1 24.15~-X75*~et!~il.~tI!!.Bt, ~J:f~ii1liif*1?f1i:751 9S·C, ~ =~Ff!.lliWJlJ~~i)'trt\\:[email protected]:* 33A. When PROG2 pin connects the ground through 24.15k.... or infinitely-great resistance,the value of the over-temperature protection of the chip is 9S·C,the maximum value of the output current of the second path of the voltage regulator is 33A. SVID ~%~QOO 9-70 JiJT7J', j!)ll 751 SCK, j8i)l2 751 SVD. The waveform of SVID is shown in figure 9-70,the channell is SCK,the channel 2 is SVD. ~ 9-16 ISL9S831 • •-¥fl&~ PROG2 JJlPIC. Table 9-16 M1n.(4'6) 0.57 1.07 :2.19 3.07 5.33 6M 7.63 9.03 13.29 16.71 ISL95831 16 i;tJBtr=ftm 1119-71 The starting timing sequence o~ -188- Scanned by CamScanner

VDD--.J VR_ON - - . J r - - - S - l E - W - R A - T E - - - - 2.SmV/~s ~V;;;;:ID-- 800~1 COMMAND VOLTAGE DAC _ ____'\" ========~LIf m9-70 SVID ~* . ·..PGOOD lJr-- the waveform of SVlD ALERTo 00 9-71 ISL95831 JS~01J¥ ...P;N', ~JItjpJtBim~¥U O.7V (ISL95831 HRTZ B~~+ Scanned by CamScanner

When the chip again received the corresponding SVID signal of control second of power supply outputthe chip outputs a integrated graphics power supply. ~ 9-17 ISL958311¥iJ$~TVID .~*i-/l~ (~)c~~) Table 9-17 the standard table of serial VIN decoding of ISL95831 (the original in English) -190- Scanned by CamScanner

~g~ PWM EI!:Jga~M~ .... \"'o('f'J Yin ....··00000 hu YoM .~ \"\"'000 0..255OU 0 ..... 0~6000 0.58500 Oj65OO , • ..O...S..9..0..0..0 .......0.27000 0.60500 O.21SOO o.GJ.OOO • o~ll5Oo 0.....,. 0.61500 0 .62000 • • .\"\"!OO •.6Z500 0.>0000 ll..JOSOO • . GJOOO •0 •.UO.O 0.63500 0 '-JUDO • 0.64000 0.64500 =...0.>2000 r 15 1 0.65000 --, 0.65500 0 000 0.>1000 0 ~ 0.66000 :I. •0 :I. •r--.- 1 •5 • • :I. 01 :I. • •:I. ....D.....3....J....S....D........o 0.66500 • • :I. • :I. • • :I. • 0 .67000 •• •• :I. •• •:I. :I. • 0.87500 • • :I. I :I. :I. 0 •• •I :I. .-...-•:I. :I. A D.J'IODO.\".'-- 0.\"000 • • :I. •:I. 0 0 0 • •I :I. • :I. 0 • 066500 •• ...:I. :I. 0.69000 I· A 069500 • • ..-0 :I. C . . -0 :I. :I. 0 0 0.10000 :I. :I. 0 o 70~OO , -• .- 0 O.1J.OOO . . -I 0 0.71500 0 :I. 0,72000 0.12500 0 .73000 ----:I. \"- I :I. 0 O.13!iOO ..- 0 :I. 0.74000 0 :I. 0 0.14500 0 :I. 0 :I. • •-'- •.78000 •• • •:I. 0 0 :I. :I. 0 :I. 0 0.10000 0.10000 0 0 :I. • •0 :I. :I. .- 0• 0.70500 0.7TODO I :I. • • • •I :I. :I. • • •I :I. 0 :I. • ..-I :I. A ..77... • • • • ..-:I. :I. :I. :I. I •:I. 0 :I. :I. I • • • • ..-:I. I :I. :I. :I.:I. :I. C •• • ,• ...--:I. 0 :I. :I. :I. :I. • •• •• • -:I. :I. :I.•~ :I.10 • •• • --:I. :I. a ...- • -:I. I - • -. -1- :I.:I. E -:I. Scanned by CamScanner

JtR 6mmX6mm, QFN48 Ji~o 626S is commonly used in the motherboard of AMD CPU.as the output control of the CP \",1JQ'W6Q26s5up~pIlJyJjafnJ:dtfV*:D(Om1NllB9-7p2owJiJeTrjfs-u0pply.The ize of chip is 6mm*6mm.QF 48 packaged. in Dame ofISL6265 is shown in figure 9-72. .....-.-...' :1:: r- , :31 BOOT_NIl --- ..:'• I -.'• I I I II :35 SOCJT_O I I -- \"• I I :34 UGA~' I --\"., '·-f-.'I.U.-. ~\"\":~:• •GOlD :33 PKA5E_O I :3:2 PGND_O I I : J1 LGo\\TE_0 I :» MX: .I _-------------- :3 1..GATl:_, :21 POtCU :2] PHASE_' :_ UGATE-1 :a BOOT_' 1IIIIIi~ili.,i 119-72 ISL6265 i3IJjip~~ <JY!f!tOO) the pin name ofISL6265 (the top view) ~in,~m·tion ofISL6265 tbe~~u,'then it ill be Scanned by CamScanner

5.serial VIO identification pin clock pin,connects with AMO processor 6.the enable signal input,when its high level,ISL6265 is opened 7.connects the 117k Q resistance to the ground,sets the internal reference current 8.the over-current ofCORE_O and CORE_l setting signal input 9.CORE_O differential amplification output 1O.CORE_O feedback input,to the input end of the internal CORE_O error amplifier °II.CORE_ controller error amplifier output 12.from this pin connecting the resistance to COMPO to set the switch frequency,for example.6.81 ~ is 300kHz B.the positive input ofCORE_O current detection 14.the negative input ofCORE_O current detection 15.CORE_O voltage detection input 16.the input loop ofCORE_O voltage detection 17.the input loop of CORE_l voltage detection 18.ClRE_l voltage detection input 19.CORE_I differential amplification output 20.CORE 1 feedback input,to the input end 0 21.CORE_l controller error amplifier outp of the chip for 22.from this pin connecting the resistance example,6.81 K.. is 300kHz 23.the positive input of CORE_l current 24.the negative input of CORE_l currentd 25.CORE_l boot-strap end 26.CORE_I high-end MOSFET driver si 27.CORE_I phase pin,connects the 0 signal 28.the ground terminal 29.CORE_I low-end MOSFET drN 30.the internal MOSFET driver -194- Scanned by CamScanner

coRE. 0 low-end MOSFET driver signal output • grolDld temrlnal <;Xt>RE_Pl>hase pin,connects the output inductance.This pin is the loop of the high-end tube drive ~~~i~~~'~ MOSFET driver signal output ofNB power supply fNB power supplY,connects the output inductance.This pin is the loop of the high- driver signal output ofNB power supply is set to be 260kHz Scanned by CamScanner

JL 7 RBJAS )!~ 117kn ~J.fi~~±&, iilE~$~ilEft!mt - 8 OCSET CORE 0 ~ CORE I i1¥m:f~H?iiji1~~tt.JA 9 VDIFF 0 CORE 0 ~7t1iX:*:~ I±l 10 FB 0 CORE 0 &/~tNtrA, ~IJ~aII CORE 0 ~~1iX:*:ft((.Jt'UtrA~ 11 CaMP 0 CORE 0 ~*IJ~~~~:*:~1j1±l =*12 VWO MJ! -1' it}J!p i1 ~ EE!J.fi ilJ COMPO jfj 1iIf1f ~ ~ ~ , tl 6.81 k-..~ 300kHz 13 ISPO CORE 0 ft!¥ffL~~~iHII~A 14 JSNO CORE 0 Jtmt~~~ffJ.~i)'1A 15 VSENO CORE 0 Jtffi~~~!iu~A 16 RTNO CORE 0 Jtffi~wW!iu~A@]:m 17 RTN1 CORE I Jtffi~~~~A@]:m '51 }]ifJ ~ l$ lE !J.. VSEN1 18 VDIFF I CORE_l Jtffi~~~~A 19 FB 1 20 CaMP 1 CORE_I ~7tfD(:*:!ffij I±l 2] VWl CORE_I &tJt~A, iU~tffI CORE_l ~~1iX*ft((.JUUAjfIij 22 ISP I CORE_I ~$tJft.~~fD(*!iu~I±l 23 ISN 1 24 BOOT 1 JJd!1-ttlJl4Ja~ft!~.fi~UCaMPI jfj*iijf~Jt1f~~$., ~ 25 UGATE_l 26 6.81k...Jg 300kHz PHASE I 27 CORE_l 1t~_lE.A PGND 1 28 LGATE_I CORE_l lt~ajJ. A 29 30 PVCC CORE_l EJ~ 31 LGATE_O 32 PGND_O CORE_l ifti 33 PHASE_O CORE_I,\" ' ~iii_1f~1;bffi%a<J 34 UGATE_O @lS& 35 BOOT_O 36 BOOT_NB ~:Ii!!_ 37 UGATE_NB CORE 11 38 PHASE_NB ~~MOS 39 LGATE_NB 40 PGND_NB CORE oi ~:Ii!!. CORE_O @Ii! CORE 0 CORE 0 NB~ NBM NB IIDf!: NB -196- Scanned by CamScanner

vee YIN - 4.35 4.5 V 3.9 4.1 V Scanned by CamScanner

Figure 9-75 the screenshot of the description of the electrical features ofPWROK threshold value in lSL6265 data manual ISL6265 ~Jt:(£ PWROK 79f~eg-'fM, ;f1:/FtJ.tAt SVlD m4t-, ffij~fRtm VFIXEN i~JE(8 ~~, =/}~~T;ffi@egffi: VF1XEN j!*~U 1.2V ~ rWt~ 5V li:;(:j\"Mj;J;tAt PRE-PWROK METAL vro t~~, VlD ~IlB~egffim~ 9-19, iK#If1=~~r, SVC *1] SVD W79f~eg.sp:D;j, !iu~tI.1 ItI.fflg 1.1 V: SVC *1] SVD ~79~eg-'f81, ~tI:l egffilg 0.8V. When PWROK is low level,ISL6265 chip does not implement SVID instruction,but implement the corresponding voltage according to the state set by VFTXEN:when VF1XEN connects to 1.2V below or about 5V,implements PRE-PWROK METAL VID mode,the voltage configured by VIn is shown in table 9-19,in this working mode,when SVC and SVD are low level,the output voltage is 1.1 V;when SVC and SVD are high level,the output is 0.8V. ISL6265 A~ VFlXEN ii~~U 3.3V lI1fftAt VFIX fl~, VlD DC\"B9egffim~ 9-20, tE~ ;rHbta:r, SVC ~ SVD m79f~eg.ifD;j, fflltl:legffi lAY; SVC ~ SVD W79~eg.if1l1, ~tI.1 r:gfflg a.8V. ~ 9-19 ISL6265 trtJ PRE-PWROK METAL VlD ~;:t.iij svc SVD .illll!Bi 00 1.1 .9-20 VFIX .~. SVC SVD • ill is Bi 0I 1.0 I 0 0.9 1I 0.8 When VFlXEN of ISL6265 connects tb by VlD is shown in table 9-20 in this mode,Wli I AV;when SVC and SVD are high level,the 0 Table 9-19 PRE-PWROK METAL VID Table 9-20 VFIX mode decoding Figure 9-76 is the typical applicati ISL6265 B9Iffmtfi:mM 9-77 ~ The working process of ISL626S • ~ rPJ 1¥J~~~7J'll'trB], !i:rRJ§{1 -198- Scanned by CamScanner

p;traJ 1-2: vee ~A, *~li POR (4.3V) , 7t1lX;;t-j:f i:J U IfL. Time 1-2:Vee input and crossed POR(4.3 y),l0 complete the chip self reset. p;j'1iiJ 2-3: sve ~ SVD imlijH~jU:tL§.jrHfL,~9:JE pre_Metal VID f-U~. lime 2-3:SVe and SVD are pulled up or pulled low by the external.sets pre_Metal VlD code p;j'1iiJ 3-4: EN ~;Jgi\\ijI:\\!~,Fo, VDD;fo VDDNB TfJi5Ji5i;7], J::JlilJ pre_Metal VID f~:rt li1ltJCJit0 Time 3-4:after EN changing to be the high level, VDD and VDDNB starts up.rises to the value set by pre_Metal VID mode. JlitIiiJ 4-5: VDOPWRGD ~73ii1iJEg3f, j'~1F CPU f:j:l~EgBiEm-. Tune 4-5:VDDPWRGF changes to be the high level,indicates that CPU power supply has been normal. II'traJ 5-6: PWROK tt.JAiWi 1t->jZ, j~IF;t-j:f{fMb·~t15( SVI 1~~. TlDle 5-6:PWROK inputs the high level,indicates that the chip ready to receive SVI code. .~1: CPU ~i;b SVD, SVC 7f~1~~ SVI m~ 'J, Udrives 8VD and sve to start to transmit SVI instructions. -8: 181:;6265 ~~ SVI ~~m~ 0 :18E6265 responds to SVI code instructions. ~: If PWROK ~;Jg1~, ;5Jt!?JL~.Il: SVI ffJ~1iI), Jj:~gi;b CPU Eglli¥1J eta! VID li~l'Rmo 0K changes to be lowthe chip stops SVI decoding immediately,and drives ~Tn'!TI\"\"~ _by RreyWROK Metal VID. Scanned by CamScanner

* *veCPYCC YIN GND _-La1Vl00TA 8VD IVlCU>C1C ...IVC UQATEDI---J\"'1 -em PWROK BDDTI \"=?{ POCO. \"={ VlIEND L.....TEDI-_ _.J>:-+ VDO_PL.NE_STRAP IlTNO PGHDO 1 - - - - - - 1 VlIEN. -1------''------' _'I- RTN' ---J > - - - - _ ~0PINF1XEN ....... 1-\"\"\"'--........\"..-..., DCSETI-_---J _D.---O/w,-_--i .VIM +-------i- UGATI.I---~ t-'w..--u-_--1 COIR LGATI.I----'9 - -1------1 .---\"\"'IY-\"\"\"'T-;-' 1IP11-_ _--=:..----J + - - - - - - - i ... _I- ..,.. ---J t-'w..--II-.......,--i -. .--.,......_N--\"\"\"'T-; . . . . . . .----il--.....,--1~. . L -1 .... 00 9-76 Figure 9-76 z vec ~ooooV'\"t-t--r1i~ &Yc ---I'-'ooCl---+---+\"\"\"E .YO ---I'-'ooCl---+---+.-; ENABLE ---1--+--1 PWROK ---I--+-+--.....,-+.:= +_+_+---YDD IIIVODHB __ VO:=OGf ---1---+---+-\"\"\":\"\"\"'\" 111 fa] 9- 10: -200- Scanned by CamScanner

1ime 9·10:PWROK changes to be high,indicates that the chip readies to receive SVI ~diri1CU· ODS again. Jtt-rRJ 10-11: SVC, SVD f~~&lTO~ VID 1-~~o 'lime tQ-l1:SVC and SVD transmits new VID code. ~OO 11-12: ISL6265 ~z;/J CPU {,~rgrg&~1j SVI i&JER~wfrffio Tune 11-12:ISL6265 drives CPU power supply voltage to the new value set by SVl. Scanned by CamScanner

r it.6~*~n$] ~ tt3~~ !iL~;ff.=..#. t1i1 RTC tt3&-, #:.VL tt3~;fQJ6 ~~ ~J:. tt~at Jt£ ,$.-ft. ,$.~.i.~l-Arit. CT6 7-J1ftli#-M RTC tt3&-, *~n5J~tt3&-~~Atlf.JJ:.ttatJt. n jr, i#-fflii-ZQ5 6~*~i'frfJ~tt3&-vAJLAXl ~*~nrfJ.%ttS!. Chapter 10 Analysis of Quanta computer circuit There have three kinds of the protective isolation circuit of Quanta,the RTC circuit,standby circuit and the sequence of subsequent trigger power-on are basically no difference.This chapter mainly takes CT6 as an example to explain RTC circuit,protective isolation circuit and complete power-on sequence.In addition to explain the protective isolation circuit ofZQS and AXI. Analysis of Quanta CT6 RiC circuit }~Jt CT6 B~ RTC rt!.Jm±~~,*1m\"\"fJL~-M 32.768kHz, INTVRMEN. The RTC circuit of Quanta CT6 mainly includes RTCRST#, 32.768kHz, INTVRMEN. 1. VCCRTC ~mA\"J VCCRTC *~~~1«la~ VCCRT:G, The name ofVCCRTC ofthe South bridge • ICH Vc:I:RTC . . . . - . - - - - - - : : : : : III11H Figure to-t VCCRTC )g1'rt!.ffiB\"J*~, 1m1li ~i:t R196, D5 F~: ~ 3VPCU 1'= :JJoiU VCCRTC. l29=fiH11. OS PJJf.rt!.rt!.rlP.: 5VPCU r£3:J: R201 ~ 202- Scanned by CamScanner

U~J1l1 JJI4J_tI:l, [email protected]~ 3.1 V jL;(j, Jlt 3.1 V ilt~~ BTl ftrb.. gm ofVCCRTC voltage is shown in figure IO-2,when there is no extel11a1 power supply.is ~ is CMOS battery BTl with 3V through R196.D5;after 3VCPU producing (the principle of shown in 10.3 section),3VCPU with 3.3V is added to VCCRTC through D4,due to the A;li_mstiC' of the diode,DS will be cut-of'f,CMOS battery can save electricity.ln addition.the CMOS ~ in this clrcutt is a rechargeable battery:5VCPU produces 3.8V voltage through the partial pressure bf:BlOl and R203 to the B pole of Ql8,the triode Q18 will convert the voltage of 3 pin input to 1 pin ~thevOftiige is about 3.lV.this 3.1 V is directly charged to BTl. J111<r21:f ttHl7J'7 RTCRST#rfl*1mi, ep VCCRTC jf'ffi'J§, ~~u R198, C220 ~ot at ~.4tF.!f 1iJ~J.W. CMOS tD!:rt. ~ 10-2 also shows the origin of the RTCRST#.thal is,after VCCRTC being through R198,C220.G 1 is the short contact,CMOS discharged can be =CKL:Cl/C2: 18pF -> CL:12. Cl/C: lOpF -> CL Value 8.5pr. ~ ~ tpdnt for SMT Scanned by CamScanner

Figure 10-2 the screenshot ofRTC circuit 4. INTVRMEN i¥jmO~jH'l--l'itB(j{JR1'C f*~-IN1'VRMEN, ?tt&HJH~~A$lBa, Jltf*-'%?'£ ICH7 r*J-B-IXB~}:E)(Jg; Internal Voltage Regulator Enable: VCCRTC This signal enables the internal 1.05 V Suspend ICB7 internal VR enable sttap regulator when connected to VccR1'C. When INTVRMEN R2D6 332K connected to Vss, the internal regulator is disabled. Enable 1 (default) ICH IIffiIRMEN ( r*J 1m It lli ir.J li ft fj~: ili J3: l' f§ -'% i! ~ ¥~ Disable 0 R2ll5 VCCRTC, PJfflT7f~ r*.I{flI(j{J 1.05V q~H)1.ltllio 'O/F 3J3:l'f*-'%itf~¥~±t!!., r*J1m~lli~~lBZ~ffl 0) ~*i¥jm.~J3:l'ffl-'%, .~~.~M~~.o lltf*-'%tE C1'6 4J(j{J*~, :IlnOO 10-3 JiJT7f-:, 004J 00 10-] INTVRMEN ~ilHI&OO R205 1~ ff ~ ~, IN1'VRMEN Jm M R206 ft VCCR1'C J:ti/SJ~, i5tJ:EJg7f~i¥imr*J{flIa<J~lliBo Another key R1'C signal of the South bridge is INTVRMEN,is easily overlooked by many people,the definition of this signal in ICH7 is:lntemal Voltage Regulator Enable: This signal enables the internal 1.05 V Suspend regulator when connected to VccRTC. When connected to Vss, the internal regulator is disabled.Ifthe South bridge hasn't this signal,it will lead to not trigger fault.The origin of this signal is shown in figure 1O-3,in this fi OS is not installed,INTVRMEN is pulled up to be high by VCCR1'C through R206,and is set 9 ~ regulator to open the internal of the South bridge. Figure 10-3 the screenshot ofINTVRMEN eire • Analysis of Quanta @ ,nlJJt;:Jt;*~~j it C1'6 (j{Jf~HFIWi t:! Let's look at the full figure about the C1'6,is shown in figure 10-4. 00 10-4 4J, 0~Bt:I!Ek (1£: ~ -204- Scanned by CamScanner

. .i ~ ..\"•. ~ Lil~q~ ~ .:¢: 0 .\"=\"f\"I S~ .:nJ ,!, '\" ~ ~ j!:1T I=cE- ~ .O.,.lE.. \"t=-' U \"7 -0 ~ Scanned by CamScanner

-'f8~ ACOK, ~I]OO 10-5 JiJT7.J'o In the figure 10-4,the production of the common point(the battery and the adapter pass through this point together to supply the power to the system,then this point is cal1ed the common point)voltage VIN,need to go through PQI5,this P channel tube need to be conducted,and controlled by PQ4,and PQ4 is control1ed by ACOK with high level,is shown in figure 10-5. Figure 10-4 the figure ofCT6 protective isolation and the charging circuit VA BATTERY CHARGER ADAPTER 18.5V 6SW 3.S1A VIj 5ecoDd:BlM66790014 V\",\" POlS VA3 - - PR3D _ UII ~r*-~*~ ACOK B'-Jf=~: 1LOIII ~lI VA2 -~{fr-~ MAXI772 B'-J~Jt!..8iP 5f1J 4.096V B'-J~ftE~J.li <.~OO 10-7); MAX 1772 I¥J ACIN JJ!II 0 Let's look at the production of ACOK: and the adapter interface voltage VA2 suppl MAX 1772 produces LOO voltage 5.4V other path through PR40 and PR49 divided • -206- Scanned by CamScanner

-.... PRI~l At<>< 0 ~ '.... ~~• ''I'''' \"\" t 11110-6 MAXI772 B~ DCIN jf[) ACIN f.\\!JEi'\\-~ Figure 10-6 the circuit diagram of DCIN and ACIN of MAX 1772 r - - - - - - - - _ + _ DCIIJ r - - - - - t - LOO REF the internal block diagram ofthe LOO production of MAX 1772 eIN and ACOK in the MAX 1772 data manual is in the Scanned by CamScanner

grounded,YA3 through PQ5 internal resistance and PR46 divide into the voltage,after dividing into the voltage,the conducted condition of PQ 15 is satisfied,and produces the common voltage YIN. ADAPTER 18.5V 65W 3.51A \\'II VKJ. ~:BIM&679001. PO,S Pl., I PIMI PR30 PR3lI 4.711 4.7. FlII&J321Ii1lll41l111T\\& 11o.....'!'~\"':EMI:=-ofI 1l1(li ~SI-2\"modif\"ied PC17 +'~+i ::1 I~~ REV.B Figure 10-8 the production circuit ofVIN m7f-: it.2.;tr +ttSi~i.it:, -.*om 10-9 ~;f.', ~ ~~~~ttSi. ~*+~~~~~~~: Note:there is a circuit to be payed attention;as the battery mode,is the battery low-voltage prote:cti J!1-~~~9=t1¥J SL/C#~ D/C#~~~i:!m. SL/C# and D/C# in this circuit are used in ~~-Hm~~, SL/C#~ EC ~~~iiJ, fj!p, 4 }j!p7fim!fDtr:±l IE 3VPCU ..tt'[email protected], ~ij, PQ36 W/f'~~jM. Under the adapter mode,SUC is driven as • comparator PU lOis greater than 3 pin,4 pin 3YPCU,and added to S pole ofPQ36.AttlliS not be conducted. ~ltt!mJ:tr, SL/C#/Fill EC JE)(;, PRI46 *19C7.tlli~ PD19 (J(JttHILki, Sf, JltIl1 D/C#~1Jt EC !JgZ;b}!giffi~ ~$~I¥J~~~~. ~~EC~J~ -208- Scanned by CamScanner

er the battery mode,BLlC# is not defined by EC,the initial is low level. When VIN voila '(; orftJllPlUttbrough the series partial pressure of PR 14J and PR 146 and the clamping PD 19,it \\ also .P~ than the voltage of the comparator I pin. the comparator 4 pin output the low Icvcl.at this ~ C will be driven as high level by EC,make PD7 to be conducted, pull lo\\v the I pole 01 pQ4~ut-offPQ4 close the isolation circuit of the adapter.At the same time.EC receive BL/ # with loW I vel;ii1dicating that the battery voltage is enough. fI~.!it\"F~ VlN r4!J.liftkfl¥O 7.5Y ~rnt, bt~x~:t- 1 )J!4J )-.::.J:' J )J!4J. 4 1]1.II~iJ~IIII\"JIl!, ....~PRl44 JSF1=..Jt~1¥-J BLlC# (~El=J.fnt Batiery Low 7fHf). Mr-II EC ~Jl1J'ltJrll!,o OC ~~tJ<J BUC#4t>~fIltJ PQ34 ~jffi, ~t:£tL1IHt~-X*rr J IJLIJ. i~HT-bt~ ~~+!J;IJ)': r -y;I,;(j(J'h'j .witiJt~tr<J BUC#, i!1-§ lJJl r.[:J.~PJ ~~lJl. EP.itJ!.:r ).1 (~tlJ\"r)JfjE:. n 'W'l:ldl'fa:~ 1lJ. mOde,when YIN voltage falls below 7.5V,the comparator I pin will be bUtputthe high level,produces the high level of BLlC#(Batlcry Low i valid ~.~'F~I44infonn EC to execute outage.And the high level of BL/ II will &nci~:edtlcoDtinues to pull low the comparator 3 pin.and keeps the comparator Pl~~WIJys output the high level of BLlC#,the lock-in circuit can real ize the ~5liQ~.f8nctjon. When the adapter is inserted again,it can be unlocked. PR3I 100K11l P04 2N7002K L.F PQ38 2N7IllI2EL-F 21 Scanned by CamScanner

JL Analysis of Quanta CT6 power-on sequence circuit m0:Jtr2: VIN 1J~~~ MAX1999, f2ii PR79, PR80 7tff~ SHDN#, ~lDOO 10-10 ffT-jj;. 41iS MAXI999 n~I11=J*lID, MAX1999]A L003 Jjl;p~ LD05 Jjl;p7t§Willtrtf:l3V_AL SV_AL. jt r:p, 5V_AL Xi!ftl;t;:ftl'r..J VCC)]!P, 12J.,& ON3, ONS. vcc iEJitJ§, rz:~ 2V ~IiItlI, ON3, ONS iE'r~J§, MAXI 999 tyftjIJW3~~ PWM IfF, 7t~IJrz:~ 3VPCU, SVPCU. ;t;:ftI1\"F if'ffi §, 1f~41)'tltf:l PGOOD, itti¥tl HWPG. The common point VIN supplies to MAX I999,through PR79 and PR80 divide into the voltage to SHDN#.is shown in figure 10-10.According to the working principle of MAX1999,MAX1999 outputs 3V_AL,SV_AL respectively from L003 pin and LOOS pin.And SV_AL is sent to VCC pin of the chip.as well as ON3,ONS.When VCC is nonnal,it produces 2V reference voltage,and when ON3 and ON5 are nonnal,MAX1999 controls two paths of PWM work,produces 3VPCU,5VPCU respectively.After working of the chip being nonnal,open leak outputs PGOOD,and connects to HWPG. 5VPCU f2ii POlL PC63 !:3 1999_0L3 .1m, ~M: POll, PCS9 §~~~I±I+Iov. +10V fI}~rlPOIO, PC62, PC611t~rz:~+lSVo 5VPCU through PDl1,PC63 and 1999_D ePOll PC59rectifying.+10Vproduces+lSVtbroug)} ~ -210- Scanned by CamScanner

I .0 .::.: 0 0 ..~ ~~ ~ 0g ~II g : :: ~ I I .~ ~ ~'H • ~~ < ;~ •8 ~~ < Hit. ~ ~ Scanned by CamScanner

f=~(j15VPCU j!~ l~fJf(j1 V5REF_sus, ~IJOO 10-11 JiJTJJ'o Produced 5VPCU to send to V5REF_SUS of the South bridge,is shown in figure 10-11. 3VPCU It!ffif;tt~ EC, fi;g EC (U23) fflm It!ffi, :~1IJ 00 10-12 JiJTJJ' 0 3VPCU voltage is supplied to EC,to be EC(U23) standby voltage,is shown in figure 10-12. 5VPCU R218 '0 +'uC250 Figure) 0-11 V5REF_SUS power supply of the South bridge FigureE1C0-1j2H~ E3C2.s7ta6n8dkbHy zpo~w~erjsfup9p~ly, Jg EC mf;ftffl~l.Ij;tB<Jp;j\"~, :tm1ll10-13 .PJfJJ'o EC external 32.768kHz crystal oscillator,supplies the clock in the state of standby for EC,is shown in figure 10-13. _-..J&l-....+- ..J!&..,..,....II...--~- we - ... • ..::JT_ _ ~ 11110-13 3VPCU ~J1It!~.EI., It!~~p;j\", Jg Ee P.€8~ 3VPCU delayed through the resistance,ca~ EC PC87541,is shown in figure 10-14. EC jiR;i1 X-BUS .~~iillJ( BIOS ~ 00 10-16 JiffJJ'o BIOS B<Jf;ft1t!-&:J!3 EC reads the EC code stored in -212- Scanned by CamScanner

M.lIllIllgw~ 1()'1 Jigure lO-16.Thc pOwer slJppl) ofBlO ~,[~~~~ ~ .., - 11110-15 EC (('1 X·BUS ,',Jr.!:: Figure 1001S X-BU' bus of I:C 8 bit (1M Byte), TSSOP40 --C:::>!lI' 7] DO DO D1 lIZ DO 1M DO DO Dr Scanned by CamScanner

Figure 10-17 EC receives the switch signal EC tstl±l 55_ON )!JiOO 10-]8 jiJTffiJt!.N~F~3V_55, m~i!~T~*1¥JVCC5U53_3. EC sends S5_ON to produce 3V_S5 through the circuit as shown in figure ]O-18,and finally sends to VCC5US3_3 of the South bridge. YIN \"\"_SS ..,., PR171 .oo -..86_ON PQ!l1 tlr*, EC ~B1tst:±l RSMRST#£i Next,EC delays send RSMRST# to ffie RSMRST#~~7i¥.i~, • 5l:dLtR1, LID_EC#E8 3VF DNBSWON#591, )!Ji D20 jlfr7f' • RSMRST# is sent to AClN,LID_EC# are high(as s -214- Scanned by CamScanner

1 by 3VPCU).sends the pulse DNB WON#59I with \"high-low-high\" ~di'~;lQb:lI.erlS to DNBSWON# through D20 to send to PWRBTN# of the South bridge,is ~~Iute 10·21. 1\\R420D lvPCU PV-l modified R417 33KIB - \" \" ' - - - - \" - - t ! 015 - - - - - t - - - { =C:l>osLe1tDo _ECE C I l --' LID 00 10-20 SW I rt!:m Figure 10-20 SW I circuit \"\"\"\" OHRS~, --\"\"- .io..P.w...,o,;,i \"\"\"\"\",''.' 1OPII1.o1S nn\", CSI <:so om EC TO> 'EU QJ( RSMRST. 28 ~susSUSO.l.! Scanned by CamScanner

Jl upply i normal.open leak outputs POK.and connects to HWPG,is shown in figure 10. 210- Scanned by CamScanner

ab -- '7V('1:.Ba/IU» I __ --_Q I'iz 1.8V Output (/'J o § (D p.. ~ f¥I 10-23 I)~ {f.:t f1t rl! n S (/'J o § ~

- -+-• ..... ..c.:.:.:..>..-.. ,. \"\"\"\"\" \" ~MI /;;m--JII' MV-l modified 5... __nus for r= Cl ~~ all ~:rR\"1Y~I' l1-;I rc:o -'\"1 _QIII mSJ rr171KIF I>i= :::::::=I::::: lU/'OVmoo3IX5R l\"'f. PR16' ~LJ\\4 \".. H '10M:<: .7llrJ.OV/0r4=0'lXI1l1I~~::J rdlut~ ! ~I(J f\" ~ rlH'~ Vcs=I_L(A)+L_DCR(rnOHH)=V_ILl ~ SI-2 modifi.ed arEB- rEB- 5)g tl) ~

Figure 10-23 the producing circuit of the memory main power supply SUSON :?J-~~* PQ41 ~Ji!i. PQ39 :jjGlt. ;n:~~Ft!.-'f 15V B~ SUSD. tznOO 10-24 PJT7F:o The other path of SUSON conducts the PQ4I,PQ39 is cut off,produces SUSD with the high level 15V.is shown in figure 10-24. \"\"'56 ..... 1M 22A G \"\"\"OTC1oUEUA -II I¥J 10-24 SUSON t!11itlf'1:. SUSD Figure 10-24 SUSON control produced SUSD SUSD FIBlH~iI1IJ PQ37 fIl PQIO ~iiB, tz:1=. 5VSUS ~ 3VSUS, :mllllD-25 ffi7J'o SUSD is used to control PQ37 and PQlO conducted,produces 5VSUS and 3VSUS,is shown in figure 10-25. PCII L,ul••• M 'F 00 10-25 Figure 10-25 MAINON J=IBIUf~ tUfF [email protected]: MAINON is used to open the follo~ CD MAINON ~11iIJtz:1::P3fj~.iJt« M~o~~-~~~~~iJtl@.~~~ ~w~1±l VlTREF: ~fU VLooIN, S315 MAINON controls to produce the SMDDR_VTERM),is shown in figure to,; • and the reference voltage after getting -218- Scanned by CamScanner

3 it will output VTItests the voltage of VTr by VITSNS. the production of the memory load power supply Scanned by CamScanner

,. .i.... ~ ~ ~G ~ ~ s, Ii! ~ ii ~~ ~I s,• t~ ~'~II. 0 ~ i ~=' . . . . . . .U I W I J . (-r1~. I •~ \"H'CIXII7' R i . I h~~ 0 0.t!H'\" .Il: ~ I\" ~ 3~ D R ~II' ~ f~ I'II I I ~•B <If----! I .. • • •IN..I. -220- Scanned by CamScanner

the production circuit or +1.5V and = 1.05V 00 10-28 MAIND D~f\"~ iFlgure 10-28 the production of MAIND irSV ~+3V, :(WOO 10-29 FJT~o iDd +3V with the state of SO,is shown in figure 10-29. 3VPCU POlO Scanned by CamScanner

signal.it will lead to the common fault of power down for Quanta motherboard. 18~ MY16 IOPJ2.eSTO I ~~ VOLME lJPjJ ~~EC VOLME DNf. lIP --.... IOPJ5IPfS IOPJ8IPU _ ~ IOPJ7IBR1<L_RSTC ~ 10-30 EC ~~iU HWPG Figure 10-30 EC received HWPG m**Ji5EC 45c¥V HWPG J§, ~Bt£tl1 VR_ON ~ CPU t:tt~~):f 35 )Jtp, CPU ~Eg VeC_CORE, CPU ~~iE~J§, £tl11~Itfl¥J VR]WRGD_CK410#fIl~~fl¥J DELAY_VR_ PWRGOOD, :tmOO 10-31 JifTii-. After EC receiving HWPG,delays send VR_ON to 35 pin of the CPU power supply chip,is used to open CPU power supply vce_CORE,when the CPU power supply is normal,then sends VR_PWRGD_CK41O# with low level and DELAY_VR_PWRGDOOD with high level,is shown in figure 10-31. -222- Scanned by CamScanner

,. . ~ l ~ J .:iJ ='.... :::l 0- U - M :=I :;r.l Scanned by CamScanner

Figure 10-31 CPU power supply circuit VR_PWRGD_CK410#~ffJElIJ1~~)=-t, 1J1~~Jt:&ili~~IJ1~, :(mOO 10-32 Jifl7Fo VR_PWRGD_CK410# opens the clock chip,and the clock chip sends each clock,is shown in figure 10-32. :S=513=31 ~:~ =~= 8_01::::::;-, ,. .,....._.4e<::::J-IlIIl.,.,..\".....a.., - mVR_PWRGD_CK410#liiJlJ'.tlmrJ: CPU 1~Et!. E.~~iE'M\", :(mOO 10-33 f i . VR- PWRGD- CK410# is sent inverted,infonns the South bridge .\".., figure 10-33. CPU #t It!.~JttitI±lI¥.J DEfu '&ilil¥J PWROK .tD1:§, .I±l J CPU power supply chip sent by EC after receiving -224- Scanned by CamScanner

......a ••. ,.. 3VSUS 51-2 modified CIwlate La '.11 - = wWi'l(j(jIJ PWROK the South bridge received PWROK Scanned by CamS canner

ADn IRDYI 18.41 PAR ,e,.'AD,. IlJ'lE:I\\I'IIESUn. 1.,4' AD1I PERRI 1',41 '''9,.'AD20 SEAM 19,41 AD21 STl:lN ,...' ADZl TRO.... 19,41 FRAMEI 1.,41 AD23 AD24 NJ25 AD2ll I i ! IAD71 AD2ll AD29 AADD3J0, ::PAD~~~1N19t INTF. 11111 T RST +3V 1115 PAD CO18.71UI Tl81 PAD T112 PAD ~ J-f--C:> PI.lRST. 32.33 R'87 ',KIF 00 10-36 ~ffi::&:±l PLTRST#.f[l PCIRST# Figure 10-36 the South bridge sent PLTRST# and PCIRST# PLTRST#~9Jff-i&i!~7~tffi:1¥J RSTIN#JJtII, DELAY_VR]WRGOOD tBi!~7~t ffi: , ~IJ 00 I0-37 JiJTlJ'. One of the path of PLTRST# is sent to RSTIN# pin of the North bridge.DELAY_VR_PWRGOOD is also scotto the North bridge,is shown in figure 10-37. 16 is nm itifr5, ~tffi:Q::±l H_CPURST#!t OP :±l H_ADS#JIJ~tffi:B~ E8 JJI4J. ~ifJtfliJ~ fiX, , CPU B7H&~:I1I:. At last.the North bridge sendS H:.... receiving the reset,sends H_ADS# from signal from T4 test point,then indi started addressing. -226- Scanned by CamScanner

H ADS# 3 H ADSlBIIO 3 H ADSTB#1 3 H BNRtI 3 H_IIPRJ# 3 o H BREOIlO 3 H_CPURST# 3 H_DBSY# 3 H DEFERtI 3 H DPWR# 3 H_DRDY# 3 11110-38 ~t~~l±l CPURST# the North bridge sent CPURST# Acer as4733z) protective isolation circuit ;fltI1i 10-39 ffi7J' 0 !JI.\"\"'''5U..PL12 is shown in figure 10-39. VA1 Scanned by CamScanner

Figure 10-39 insert adapter to produce VAI VAl jiJi PDIO ~ PQ56 /tFi~¥U:it:0~,B VIN, :(Lolli 10-40 JiJi7i;. PQ561¥J~jBlf-·f!j:~, G fJ1~ffi~;f1IMfl£~5JZ, iliff)t~i.sl PQ5 I¥J I JJtIJ*O 6 JJtIJ~• .l1:, VAl iiJi PRl9 ~ PRI7 'tBi t-J 9.5V tiki • VAl reaches the common point VIN through PDlO and PQ56,is shown in figure I0-40.The conducted conduction of PQ56 is that the voltage of G pole should be low level relatively,that iS,1 pin and 6 pin of PQ5 should be cut off,VA2 partial pressure to be about 9.5V through PRI9 and PRI7. -228- Scanned by CamScanner

>~ ~ HII'~i' ~~ HI' ~p ~ \", HII'~I ~ ~,s ~• gi II &- >~ Ii 3 ~! E-\"?, ~ ~ ~ ,,1 ~ fl =~~ ON ;Z; ~! ,... :> 0 ON '<:t 6 ~ Scanned by CamScanner

Figure 10-40 the producing circuit diagram of VIN PQ5 ~1 I Jl!lI~ 6 JJtlJ~J1:~{tf~ 2 JJtlJ~7'.1~etJ.1f (PNP -=:m~), 2 Jl!lIEmitfm 3 JJ!IJ, tE. lj1JtfiJ~UgHu~~ 31l!111O 4 JJtlJ-JE~~J.I: (NPN -=:f&~), JiJTl;/- 5 Jl!lI D/C#~7:J{I£etJ.1f· D/C#* * *.EI r EC, lj!ffH~~BIJt, E13T*~fXJIJ~J:etJ.ilffi, J§mfjl:etJ.~*f=1:, EC xlitetJ.. D/C#~1ll; I:@. 'fL. JlJT l;/- VIN PI l;/-lt I±l The condition of I pin and 6 pin of PQ5 been cut off is that 2 pin should be high level(PNP triode),it also can be understood us 3 pin and 4 pin must be cut off{NPN triode),so 5 pin D/C should be low level.D/C# comes from EC,when used the adapter singly,due to the system just connected to the power,the subsequent stage power supply is not produced,EC has not power supply.D/C# is low level.DS/oC#VBI1N~,fcfain.c:om~eetoJu..tidf1irJetctDlyI.SCHARGE, {1£etJ.5jZ1Jt CHARGE. J1t~.Rff D/C#, Wi *BL/C#, ftHm ~ ~ffi ~ll: , ~Ie -B~ mUIJ J§ D/C#:t:J{I£ , etJ. ¥tl!. mJt r 7:J iWi. m r ~ tfT EC 81 ~ iNC ~ ;jft iYm etJ. ~ • The means of D/C#:DISCHARGE in the high level,CHARGE in the low level.This board just have D/C#,not BLlC#,according to the actual measurement,the adapter is low after detecting D/C#,and is high in the battery mode.Let's us analysis the adapter detection circuit of EC. VAl ~uPD1 ~PR78~ISL8873lI¥JDCIN~Et!, :tmOO 10-41 JiJT7.J'. VA I supplies the power to DCIN ofISL88731 through PDl and PR78,is shown in figure 10-41. VAl PRl81 I ...... AClH<::J----+----4-----' ;flHJ.!i ISL8873I I¥JI*J~~I!I C.roJ ~lJ VREF fflj I±l Et!lli I¥J IW-m:f£'dl~ A1 E~/4:.*f·t1ti'ii~:tmOO 10-43 Hf/$, ~ I±l Et!lli:f'ff-(i{!73 5.1 V, VDI} tflE/j\\T 30mA nt, ttylfJ [email protected]~:Ii: -230- Scanned by CamScanner

v (fi-(1H~i.) 0 mal block diagram(shown in figure 10-42) of ISL88731,ISL88731 will the description of the electrical characteristics about the the threshold F output voltage in the data manual is shown in the figure 10-43,the Output voltage is 5.1 V,when VDDP load current is less than 30mA,the F output voltage is 3.2V(the standard value). K ~i3I)J!p~5Z pin definition of ACIN and ACOK. Detection Input. Connect to a resistor divider from the AC adapter ut This open drain output is high impedance when ACIN is greater remains low when the ISL88731 is powered down. Connect a 10k 5.0 5.1 5.23 v 35 100 mV 3.168 3.2 v cation description about the threshold value or VDDP and voltage i!JEft~~JWiu\"tr 1±\\)Jt;p 0 ~ ACIN e£!.& 1'<0 T IS.Ilre ACOK ii~~tl VDDSMB )).~o • ;ACOK is the adapter detection output o 1J!ge 3.2V,ACOK open drain output,it 49 and PRl50,then is sent to VAl through the diode Scanned by CamScanner

II I I/) I I 11I1X J,t r II I. un: 10.. .11 1,;,11 ul,IlI(l11 (If III eric partIal pre ure rn:tfltfl:NJd'. CK ·n;\"JfM\"uHII, rl13VPCU PRJ31 L1-JFix nJ1ltf J,J III. IIf \\)),1n D' #J:J1l It! V-· PO IS iJ,t!l:. PQ39 (Ij G tl%11J fix ,'t! I. PO 9 'II. 1t!'l!!.fI!i . tzlll¥! 10-45 ffr/r-. rg7l!!.~J:t J 'I IJ tl!.thZ. VI . IHiirJ:J 'I: EC fr.Ji}t. rt!, EC f,'oL&IJfIJ:ffH~ PQI5 Id:J. I {-/,ji PR40,fU PR39 -rrlli, 1'039 7i:!F.:-~j!!L II th olt 'c f A I i not lo\\\\cr than the limit valuc.ACOK will open drain output3VPCU Ihr 1I·1t PR I I and i pulled up 10 be 3.3 V.then end to EC.A fter EC receiving this signal.can keep I) It he Ihe 10\\\\ I vel.PO 15 i cut off.G pole of P039 i pulled up to be the high level by V£N Ihr II 'h I'R40 dire tl .1'039 i cut otr.thc batte!) is isolatcd,is hown in figure 10-45.ln the battery m J Hr I pt lUll mall current VI through P039 diode.then produces the power supply of I dCI' I Ih hi h Ie el of D # nt by the adapter.and makes POlS conducted.VI paniaI pr 1II tltr III ·It I'R40 and PR39.P039 i conducted completely. [ ..... • ---' • ---' IAT 1111 , II 'un: IO-4S JJ 'J'. .loJ l~ r 11 \". Scanned by CamScanner

ItmC~.~ to through PD20,PQ52 from the adapter CN 17 to the common point VIN;and it ugh PQ55 from the battery CN 16 to the common point.is shown in figure 10- nneeted together to the G pole of PQ55.are BATDIS_G.lf BATDlS_G is high 11 be conducted,PQ55 will be cut off;on the contrarY,PQ52 will be cut off.PQ55 cted.lfit needs the adapter supply the power to the system,then BATDIS_G must and the voltage should be high enough(more than 23.5V). - VIN production circuit in partial Scanned by CamScanner