Dell 14-3478 17841-1

5 4 3 21 Main Func = KB Main Func = TPAD 3D3V_S0 3D3V_S5 Internal Keyboard Connector [20] KB_DET# 21 21 KB1 R6521 TP_VDD 0R0402-PAD-2-GP 32 NON_PTP 1 30 3D3V_TP_S5_R AFTP6519 1 KSI7 29 TP_VDD Discharge Circuit AFTP6523 1 KSI6 28 0R2J-2-GP AFTP6511 1 KSI4 R6520 21 AFTP6521 1 KSI2 27 AFTP6533 1 KSI5 26 AFTP6513 1 KSI1 25 R6522 AFTP6540 1 KSI3 24 Vinafix.com C6503 Q6505 AFTP6502 1 KSI0 23 SCD1U16V2KX-3GP G DY 100R3J-4-GP AFTP6507 1 KSO5 [24] KSI[0..7] AFTP6536 1 KSO4 22 12 TP_ON#_GATE D Q6205_Q D [24] KSO[0..16] AFTP6522 1 KSO7 21 AFTP6534 1 KSO6 20 R6509 DY AFTP6512 1 KSO8 19 TP_VDD 1 2 TP_LOCK# D AFTP6505 1 KSO3 R6516 D S C AFTP6518 1 KSO1 18 S 100KR2J-1-GP B AFTP6517 1 KSO2 1KR2J-1-GP AFTP6510 1 KSO0 17 TP_EN# 1 2 TP_ON#_GATE G 2N7002K-2-GP AFTP6520 1 KSO12 16 [24] TP_EN# 84.2N702.J31 AFTP6538 1 KSO16 15 TP_VDD D 2ND = 84.2N702.031 AFTP6508 1 KSO15 G 3rd = 84.07002.I31 AFTP6515 1 KSO13 14 RN6504 Q6504 AFTP6535 1 KSO14 13 SRN10KJ-5-GP DMP2130L-7-GP AFTP6539 1 KSO9 84.02130.031 AFTP6516 1 KSO11 12 DY DY DY 2ND = 84.03413.A31 AFTP6506 1 KSO10 11 AFTP6503 10 CAP_LED 9 8 TP_VDD 32 3D3V_S0 Precision Touch Pad Connector 7 41 2 6 R0R6351J-7L11-GDPY 5 4 3 Pin number Pin name 2 Support PTP TP_VDD 1 VDD DAT(I2C) AFTP6537 1 1 TP1 2 CLK(I2C) 31 9 3 GND PS2 [24] CLK_TP_SIO RN6503 1 4 TPCLK_C I2C1_SDA_R 1 4 ATTN PTW O-CON30-10-GP [24] DAT_TP_SIO 2 3 TPDATA_C I2C1_SCL_R 5 GPIO SRN33J-5-GP-U 2 DAT(PS2) 20.K0621.030 [20] I2C0_SCL_TCH_PAD R6518 NNOONN__PP11 TTPP 21C6504 R6513 INT_TP# 3 6 CLK(PS2) [20] I2C0_SDA_TCH_PAD R6519 2 0R2J-2-GP I2C1_SCL_R 21 TP_LOCK# 4 7 2nd= 20.K0592.030 2 0R2J-2-GP I2C1_SDA_R TPDATA_C 5 8 3nd= 20.K0565.030 I2C SCD1U16V2KX-3GP 4K7R2J-2-GP TPCLK_C 6 NON_PTP 7 CAP LED Control SC33P50V2JN-3GP AFTP6531 8 LOW actived from KBC GPIO 5V_S0 EC6502 1 10 SC33P50V2JN-3GP Q6502 EC6504 STAR-CON8-2-GP E SC33P50V2JN-3GP EC6501 020.K0182.0008 C SC33P50V2JN-3GP EC6503 2nd = 020.K0243.0008 R1 21 DY Change TP1 pin define , R2 21 pin1 connect VDD 1/26 [24] CAP_LED#_S R6508 1 2 CAP_LED_R# B CAP_LED_Q R6506 1 2 CAP_LED 21 0R0402-PAD 1KR2J-1-GP 21 RN2418-GP 1 CAP_LED Need to check if it is Active High or Active Low and check if there is PH on TPAD side. C 084.02418.0011 AFTP6532 5V_S0 TP_VDD 0502 Deleted KB2 21 R6512 32 RN6502 TP side has pull high 0524 Deleted KBBL1 block 0R0402-PAD 41 PTPSRN2K2J-1-GP TP_VDD Q6204_G I2C1_SCL_R I2C0_SCL_TCH_PAD Q6503 I2C1_SDA_R R6514 1 2 INT_TP# 16 10KR2J-L-GP 84.2N702.A3F 2 PTP 5 TP_VDD 1 2nd = 84.2N702.E3F TPCLK_C 1 3rd = 75.00601.07C 34 TPDATA_C 1 I2C1_SCL_R 1 I2C0_SDA_TCH_PAD 2N7002KDW -GP I2C1_SDA_R 1 INT_TP# 1 Vages install Non PTP TP_LOCK# 1 AFTP6529 AFTP6530 AFTP6524 AFTP6528 AFTP6527 AFTP6525 AFTP6526 SMBUS R6515 1 DDYY 2 0R2J-2-GP I2C1_SCL_R R6511 1 2 0R2J-2-GP I2C1_SDA_R [12,13,18,56,67] PCH_SMBCLK [12,13,18,56,67] PCH_SMBDATA EC6506 EC6505 Need to check with SW. 21 21 DY DY B [4,24] INT_TP# [24] TP_LOCK# SC33P50V2JN-3GP SC33P50V2JN-3GP AA <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Rev Key Board&Touch Pad A00 Size Document Number Custom Vegas SKL/KBL-U Date: Wednesday, November 08, 2017 Sheet 65 of 105 54321

5 43 21 D Main Func = IO Connector Vinafix.com I/O Board Connector D Cardreader [33] USB_PN5_C IOBD1 [33] USB_PP5_C 31 C USB3(USB2.0) [37] USB_PN2_C 1 B [37] USB_PP2_C 2 USB20_VCCA 3 4 3D3V_S0 5 6 Universal Jack AUD_AGND 7 8 [29] AUD_PORTA_L_R_B 9 C [29] AUD_PORTA_R_R_B 10 11 [29] SLEEVE_R 12 13 [29] RING2_R 14 15 [29] JACK_PLUG 16 17 AUD_AGND 18 19 0RR636J0-1L11-GDPY 2 20 21 22 23 24 25 26 27 28 29 30 32 ACES-CON30-9-GP-U2 20.K0510.030 2nd = 20.K0580.030 AUD_AGND Pitch: 1mm Power: 6 pins GND: 7 pins AGND: 2 Pins B USB_PN5_C 1 AFTP6601 AFTE14P-GP USB_PP5_C 1 AFTP6602 AFTE14P-GP USB_PN2_C 1 AFTP6603 AFTE14P-GP USB_PP2_C 1 AFTP6604 AFTE14P-GP RING2_R 1 AFTP6605 AFTE14P-GP AUD_PORTA_L_R_B 1 AFTP6606 AFTE14P-GP JACK_PLUG 1 AFTP6607 AFTE14P-GP AUD_PORTA_R_R_B 1 AFTP6608 AFTE14P-GP SLEEVE_R 1 AFTP6609 AFTE14P-GP USB20_VCCA 1 AFTP6610 AFTE14P-GP AUD_AGND 1 AFTP6611 AFTE14P-GP 1 AFTP6612 AFTE14P-GP A Wistron Confidential document, Anyone can not A Duplicate, Modify, Forward or any other purpose application without get Wistron permission <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title IO Board Connector Size Document Number Rev A3 Vegas SKL/KBL-U A00 Date: W ednesday, November 08, 2017 Sheet 66 of 105 543 21

54321 SSID = User.interface Free Fall Sensor DVT1 add FFS 2/18 Vinafix.com DD 3D3V_S0 R6701 1 2 3D3V_RUN_FFS 3D3V_S0 0R0603-PAD-2-GP-U SC10U6D3V3MX-GP 21 C6703 SCD1U16V2KX-3GP C6702 SCD1U16V2KX-3GP C6701 21 U6701 21 21 9 VDD FFS FFS DY 10 VDD_IO DY R6702 100KR2J-1-GP FFS CS 2 RES 5 HDD_FALL_INT [18] INT1 12 INT2 11 [12,13,18,56,65] PCH_SMBCLK 3D3V_RUN_FFS 1 SCL/SPC GND 6 [12,13,18,56,65] PCH_SMBDATA 4 SDA/SDI/SDO GND 7 3 SDO/SA0 GND 8 C C B LNG2DMTR-GP 074.LNG2D.00BZ 3D3V_S0 21 FFS R6703 61 100KR2J-1-GP 52 4 32 1 FALL_INT2 5V_S0 Q6701 3D3V_S0 2N7002KDW -GP DY FFS 84.2N702.A3F 100KR2J-1-GP 2nd = 084.27002.003F 2 12 1 R6705 3rd = 84.2N702.E3F DY R6704 100KR2J-1-GP HDD [60] FFS_INT2_Q PCHFFS_INT2 [20] B R0R627J0-621-GPDY 2 FFS R6707 1MR2J-1-GP 2014.04.24 Venrer suggest,reserve to prevent error trigger Note (1) Keep all signals are the same trace width. (included VDD, GND). (2) No VIA under IC bottom. Note <Core Design> A - no via, trace, under the sensor (keep out area around 2mm) - stay away from the screw hole or metal shield soldering joints Wistron Corporation - design PCB pad based on our sensor LGA pad size (add 0.1mm) - solder stencil opening to 90% of the PCB pad size 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, - mount the sensor near the center of mass of the NB as possible as you can Taipei Hsien 221, Taiwan, R.O.C. A Title 543 Free Fall Sensor Size Document Number Rev A3 Vegas SKL/KBL-U A00 Date: W ednesday, November 08, 2017 Sheet 67 of 105 21

54321 D C Main Func = Debug B Vinafix.com D ESPI Debug Connector 0607 Modify DBG1 15 TPAD14-OP-GP TP6801 1 ESPI_CLK_CON ESPI_RESET#_CON 1 C UART 0522 Modify TPAD14-OP-GP TP6802 1 ESPI_CS#_CON 20.F0765.014 3D3V_S0 TPAD14-OP-GP TP6803 1 ESPI_IO3_CON 2 [24,61] HOST_DEBUG_TX TPAD14-OP-GP TP6804 1 ESPI_IO2_CON 3 [20] UART_2_CTXD_DRXD TPAD14-OP-GP TP6805 1 ESPI_IO1_CON 4 [20] UART_2_CRXD_DTXD TPAD14-OP-GP TP6806 1 ESPI_IO0_CON 5 TPAD14-OP-GP TP6807 1 HOST_DEBUG_TX_CON 6 B UART_2_CTXD_DRXD_CON 7 HOST_DEBUG_TX R6807 D1ebug 2 0R2J-2-GP UART_2_CRXD_DTXD_CON 8 UART_2_CTXD_DRXD 2 0R2J-2-GP 9 UART_2_CRXD_DTXD R6808 DD11eebbuugg 2 0R2J-2-GP 10 R6809 11 12 BOM:DVT2 DY 13 14 16 DM-ACES-CON14-5-GP-01 ZZ.F0765.01401 <Core Design> A Wistron Corporation A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Document Number Dubug connector Rev A4 Vegas SKL/KBL-R A00 Date: Friday, November 10, 2017 Sheet 68 of 105 54321

5 43 2 1 Main Func = dGPU GFX & GPP, 85Ω 1 OF 7 GFX & GPP CLK, 85Ω 20170502 GPU1A [16] PEG_TX_GPU_P0 [16] PEG_TX_GPU_N0 Vinafix.comPEG_TX_GPU_P0 AF30 PCIE_RX0P PCIE_TX0P AH30 PEG_RX_GPU_P0 C7601 11OOPPSS22 SCD22U10V2KX-L1-GP PEG_RX_CPU_P0 [16] D PEG_TX_GPU_N0 AE31 PCIE_RX0N PCIE_TX0N AG31 PEG_RX_GPU_N0 C7602 SCD22U10V2KX-L1-GP PEG_RX_CPU_N0 [16] [16] PEG_TX_GPU_P1 PEG_TX_GPU_P1 [16] PEG_TX_GPU_N1 PEG_TX_GPU_N1 AE29 PCIE_RX1P PCIE_TX1P AG29 PEG_RX_GPU_P1 C7603 11OOPPSS22 SCD22U10V2KX-L1-GP PEG_RX_CPU_P1 [16] D [16] PEG_TX_GPU_P2 PEG_TX_GPU_P2 AD28 PCIE_RX1N PCIE_TX1N AF28 PEG_RX_GPU_N1 C7604 SCD22U10V2KX-L1-GP PEG_RX_CPU_N1 [16] C [16] PEG_TX_GPU_N2 PEG_TX_GPU_N2 B [16] PEG_TX_GPU_P3 PEG_TX_GPU_P3 AD30 PCIE_RX2P PCIE_TX2P AF27 PEG_RX_GPU_P2 C7605 11OOPPSS22 SCD22U10V2KX-L1-GP PEG_RX_CPU_P2 [16] [16] PEG_TX_GPU_N3 PEG_TX_GPU_N3 AC31 PCIE_RX2N PCIE_TX2N AF26 PEG_RX_GPU_N2 C7606 SCD22U10V2KX-L1-GP PEG_RX_CPU_N2 [16] C 3D3V_VGA_S0 AC29 PCIE_RX3P PCIE_TX3P AD27 PEG_RX_GPU_P3 C7607 11OOPPSS22 SCD22U10V2KX-L1-GP PEG_RX_CPU_P3 [16] AB28 PCIE_RX3N PCIE_TX3N AD26 PEG_RX_GPU_N3 C7608 SCD22U10V2KX-L1-GP PEG_RX_CPU_N3 [16] AB30 PCIE_RX4P PCIE_TX4P AC25 AA31 PCIE_RX4N PCIE_TX4N AB25 AA29 PCIE_RX5P PCIE_TX5P Y23 Y28 PCIE_RX5N PCIE_TX5N Y24 Y30 PCIE_RX6P PCIE_TX6P AB27 W31 PCIE_RX6N PCIE_TX6N AB26 W29 PCIE_RX7P PCIE_TX7P Y27 V28 PCIE_RX7N PCIE_TX7N Y26 V30 NC#V30 NC#W24 W24 U31 NC#U31 NC#W23 W23 U29 NC#U29 NC#V27 V27 T28 NC#T28 NC#U26 U26 T30 NC#T30 PCI EXPRESS INTERFACE NC#U24 U24 R31 NC#R31 NC#U23 U23 R29 NC#R29 NC#T26 T26 P28 NC#P28 NC#T27 T27 P30 NC#P30 NC#T24 T24 N31 NC#N31 NC#T23 T23 N29 NC#N29 NC#P27 P27 M28 NC#M28 NC#P26 P26 M30 NC#M30 NC#P24 P24 L31 NC#L31 NC#P23 P23 B DGPU_HOLD_RST# L29 NC#L29 NC#M27 M27 K30 NC#K30 NC#N26 N26 H L dGPU mode 21DYR7625 AK30 CLOCK H IGPU 2110KR2J-L-GPAK32 IGPU with BACO [18] PEG_CLK_CPU PCIE_REFCLKP [18] PEG_CLK_CPU# PCIE_REFCLKN R7623 1 2 CALIBRATION Y22 PCIE_CALR_TX 1K69R2F-2-GP 2 OPS 1 0R0402-PAD AA22 PCIE_CALR_RX R7601 PCIE_CALR_TX R7622 0D95V_VGA_S0 1KR2F-L1-GP PCIE_CALR_RX 2 PW RGOOD_TEST N10 TEST_PG R1K7R6128F-1OL1P-GSP 2 1OPS 2 DY 3 [20] DGPU_HOLD_RST# ATI_RST# R7621 1 2 VGA_RST# AL27 PERST# [17,31,55,61,63,91] PLT_RST# 1 0R0402-PAD D7601 DY SC47P50V2JN-3GP JET-XT-S3-GP BAW 56-5-GP C7609 OPS A <Core Design> A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title 076_GPU(1/5) PEG Rev Size Project Name Date: W ednesday, November 08, 2017 <Project Name> Sheet 76 of 105 54321

54321 Main Func = dGPU GPU1G 7 OF 7 GPU1E 5 OF 7 DP POWER NC/DP POWER AG15 NC_DP_VDDR#AG15 NC#AE11 AE11 AG16 NC_DP_VDDR#AG16 NC#AF11 AF11 AF16 NC_DP_VDDR#AF16 NC#AE13 AE13 AG17 NC_DP_VDDR#AG17 NC#AF13 AF13 AG18 NC_DP_VDDR#AG18 NC#AG8 AG8 AG19 NC_DP_VDDR#AG19 NC#AG10 AG10 AF14 DP_VDDR AA27Vinafix.com1.8V and 0.95V for Clock resourceDGNDGNDA31D8V_VGA_S0 DPLL_PVDD AB24 GND GND A30 R7704 1 AB324302mmAACGND GND AA13 2 0R0603-PAD D AC24 GND GND AA16 0D95V_VGA_S0 C AC26B GND GND AB10 R7705 1 21DY SCC771103U6D3V3MX-GPOPS21 C7711 21OPSC7710 B AC27 GND GND AB15 SC1U10V2KX-1GP SCD1U16V2KX-3GP AD25077_GPWU i(s2t/r5o) nDICGIoTrApLoOrUaTtionAGNDGNDAB6 AD32 GND GND AC9 DPLL_VDDC AG20 NC_DP_VDDC#AG20 NC#AF6 AF6 AE27 GND GND AD6 AG21 NC_DP_VDDC#AG21 NC#AF7 AF7 AF32 GND GND AD8 2 0R0603-PAD AF22 NC_DP_VDDC#AF22 NC#AF8 AF8 AG27 GND GND AE7 AG22 NC_DP_VDDC#AG22 NC#AF9 AF9 AH32 GND GND AG12 AD14 DP_VDDC GND GND AH10 NC_DP_VSSR#AG14 K28 GND GND AH28 OPS 21 C7715 21OPSC7714 NC_DP_VSSR#AH14 K32 GND GND B10 SC1U10V2KX-1GP SCD1U16V2KX-3GP NC_DP_VSSR#AM14 L27 GND GND B12 AG14 NC_DP_VSSR#AM16 AE1 M32 GND GND B14 AH14 NC_DP_VSSR#AM18 NC#AE1 AE3 N25 GND GND B16 AM14 NC_DP_VSSR#AF23 NC#AE3 AG1 N27 GND GND B18 AM16 NC_DP_VSSR#AG23 NC#AG1 AG6 P25 GND GND B20 AM18 NC_DP_VSSR#AM20 NC#AG6 AH5 P32 GND GND B22 AF23 NC_DP_VSSR#AM22 NC#AH5 AF10 R27 GND GND B24 AG23 NC_DP_VSSR#AM24 NC#AF10 AG9 T25 GND GND B26 GPU1F 6 OF 7 AM20 NC_DP_VSSR#AF19 NC#AG9 AH8 T32 GND GND B6 AM22 NC_DP_VSSR#AF20 NC#AH8 AM6 U25 GND GND B8 NC_VARY_BL AB11 BALL: AB11, AB12 AM24 DP_VSSR NC#AM6 AM8 U27 GND GND C1 NC_DIGON AB12 R16 : NC AF19 NC#AM8 AG7 V32 GND GND C32 MESO : VDDC AF20 NC#AG7 AG11 W25 GND GND E28 AE14 NC#AG11 W26 GND GND F10 W27 GND GND F12 Y25 GND GND F14 Y32 GND F16 GND F18 GND F2 NC_UPHYAB_TMDPA_TX0N AL15 AF17 NC_UPHYAB_DP_CALR NC#AE10 AE10 GND F20 NC_UPHYAB_TMDPA_TX0P AK14 M6 GND GND GND F22 NC_UPHYAB_TMDPA_TX1N AH16 JET-XT-S3-GP N13 GND GND F24 NC_UPHYAB_TMDPA_TX1P AJ15 N16 GND GND F26 NC_UPHYAB_TMDPA_TX2N AL17 OPS N18 GND GND F6 NC_UPHYAB_TMDPA_TX2P AK16 N21 GND GND F8 NC_UPHYAB_TMDPA_TX3N AH18 GND GND G10 NC_UPHYAB_TMDPA_TX3P AJ17 P6 GND GND G27 AL19 P9 GND GND G31 NC_TXOUT_L3P AK18 R12 GND GND G8 NC_TXOUT_L3N R15 GND GND H14 R17 GND GND H17 TMDP R20 GND GND H2 T13 GND GND H20 NC_UPHYAB_TMDPB_TX0N AH20 T16 GND GND H6 NC_UPHYAB_TMDPB_TX0P AJ19 T18 GND GND J27 NC_UPHYAB_TMDPB_TX1N AL21 T21 GND GND J31 NC_UPHYAB_TMDPB_TX1P AK20 T6 GND GND K11 U15 GND GND K2 U17 GND GND K22 U20 GND GND K6 U9 GND V13 GND NC_UPHYAB_TMDPB_TX2N AH22 <Core Design> V16 GND NC_UPHYAB_TMDPB_TX2P AJ21 V18 GND VSS_MECH A32 VSS_MECH1 1 TP7701 NC_UPHYAB_TMDPB_TX3N AL23 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, A Y10 GND VSS_MECH AM1 VSS_MECH2 1 TP7702 NC_UPHYAB_TMDPB_TX3P AK22 Taipei Hsien 221, Taiwan, R.O.C. Y15 GND VSS_MECH AM32 VSS_MECH3 1 TP7703 AK24 Y17 GND NC_TXOUT_U3P AJ23 Y20 GND NC_TXOUT_U3N R11 GND T11 GND Title AA11 GND M12 GND N11 GND V11 JET-XT-S3-GP JET-XT-S3-GP Size Project Name Rev OPS OPS Vegas SKL/KBL-U X00 Date: Wednesday, November 08, 2017 Sheet 77 of 105 54321

5 4321 Main Func = dGPU [81] DQA0_0 [81] DQA1_0 GPU1C 3 OF 7 [81] DQA0_1 [81] DQA1_1 D [81] DQA0_2 [81] DQA1_2 GDDR5/DDR3 GDDR5/DDR3 [81] DQA0_3 [81] DQA1_3 [81] DQA0_4 Vinafix.com [81] DQA1_4 DQ DQA0_0 K27 DQA0_0 MAA0_0 K17 MAA0_0 ADD [81] DQA0_5 [81] DQA1_5 DQA0_1 J29 DQA0_1 MAA0_1 J20 MAA0_1 [81] DQA0_6 [81] DQA1_6 Jet Setting DQA0_2 H30 DQA0_2 MEMORY INTERFACE MAA0_2 H23 MAA0_2 DM D [81] DQA0_7 [81] DQA1_7 DQA0_3 H32 DQA0_3 MAA0_3 G23 MAA0_3 DQS C [81] DQA0_8 [81] DQA1_8 R7809 1 OPS 2 120R2F-GP DQA0_4 G29 DQA0_4 MAA0_4 G24 MAA0_4 B [81] DQA0_9 [81] DQA1_9 DQA0_5 F28 DQA0_5 MAA0_5 H24 MAA0_5 Ctrl A [81] DQA0_10 [81] DQA1_10 DQA0_6 F32 DQA0_6 MAA0_6 J19 MAA0_6 CLK [81] DQA0_11 [81] DQA1_11 DQA0_7 F30 DQA0_7 MAA0_7 K19 MAA0_7 CMD [81] DQA0_12 [81] DQA1_12 DQA0_8 C30 DQA0_8 MAA0_8 G20 MAA0_8 Ctrl, CS [81] DQA0_13 [81] DQA1_13 DQA0_9 F27 DQA0_9 MAA0_9 L17 Ctrl [81] DQA0_14 [81] DQA1_14 DQA0_10 A28 DQA0_10 MAA1_0 J14 MAA1_0 CMD [81] DQA0_15 [81] DQA1_15 DQA0_11 C28 DQA0_11 MAA1_1 K14 MAA1_1 [81] DQA0_16 [81] DQA1_16 DQA0_12 E27 DQA0_12 MAA1_2 J11 MAA1_2 [81] DQA0_17 [81] DQA1_17 DQA0_13 G26 DQA0_13 MAA1_3 J13 MAA1_3 [81] DQA0_18 [81] DQA1_18 DQA0_14 D26 DQA0_14 MAA1_4 H11 MAA1_4 [81] DQA0_19 [81] DQA1_19 DQA0_15 F25 DQA0_15 MAA1_5 G11 MAA1_5 [81] DQA0_20 [81] DQA1_20 DQA0_16 A25 DQA0_16 MAA1_6 J16 MAA1_6 [81] DQA0_21 [81] DQA1_21 DQA0_17 C25 DQA0_17 MAA1_7 L15 MAA1_7 [81] DQA0_22 [81] DQA1_22 DQA0_18 E25 DQA0_18 MAA1_8 G14 MAA1_8 [81] DQA0_23 [81] DQA1_23 DQA0_19 D24 DQA0_19 MAA1_9 L16 [81] DQA0_24 [81] DQA1_24 DQA0_20 E23 DQA0_20 WCKA0_0 E32 W CKA0_0 [81] DQA0_25 [81] DQA1_25 DQA0_21 F23 DQA0_21 WCKA0#_0 E30 W CKA0b_0 [81] DQA0_26 [81] DQA1_26 DQA0_22 D22 DQA0_22 WCKA0_1 A21 W CKA0_1 [81] DQA0_27 [81] DQA1_27 DQA0_23 F21 DQA0_23 WCKA0#_1 C21 W CKA0b_1 [81] DQA0_28 [81] DQA1_28 DQA0_24 E21 DQA0_24 WCKA1_0 E13 W CKA1_0 [81] DQA0_29 [81] DQA1_29 DQA0_25 D20 DQA0_25 WCKA1#_0 D12 W CKA1b_0 [81] DQA0_30 [81] DQA1_30 DQA0_26 F19 DQA0_26 WCKA1_1 E3 W CKA1_1 [81] DQA0_31 [81] DQA1_31 DQA0_27 A19 DQA0_27 WCKA1#_1 F4 W CKA1b_1 DQA0_28 D18 DQA0_28 EDCA0_0 H28 [81] MAA0_0 DQA0_29 F17 DQA0_29 EDCA0_1 C27 EDCA0_0 DQA0_30 A17 DQA0_30 EDCA0_2 A23 EDCA0_1 [81] MAA0_1 DQA0_31 C17 DQA0_31 EDCA0_3 E19 EDCA0_2 DQA1_0 E17 DQA1_0 EDCA1_0 E15 EDCA0_3 [81] MAA0_2 DQA1_1 D16 DQA1_1 EDCA1_1 D10 EDCA1_0 DQA1_2 F15 DQA1_2 EDCA1_2 D6 EDCA1_1 [81] MAA0_3 Please MVREF drivers and Caps close to ASIC DQA1_3 A15 DQA1_3 EDCA1_3 G5 EDCA1_2 DQA1_4 D14 DQA1_4 DDBIA0_0 H27 EDCA1_3 [81] MAA0_4 DQA1_5 F13 DQA1_5 DDBIA0_1 A27 DQA1_6 A13 DQA1_6 DDBIA0_2 C23 DDBIA0_0 [81] MAA0_5 DQA1_7 C13 DQA1_7 DDBIA0_3 C19 DDBIA0_1 DQA1_8 E11 DQA1_8 DDBIA1_0 C15 DDBIA0_2 [81] MAA0_6 DQA1_9 A11 DQA1_9 DDBIA1_1 E9 DDBIA0_3 DQA1_10 C11 DQA1_10 DDBIA1_2 C5 DDBIA1_0 C [81] MAA0_7 DDR3/GDDR3 Memory Stuff Option(R16) DQA1_11 F11 DQA1_11 DDBIA1_3 H4 DDBIA1_1 [81] MAA0_8 DQA1_12 A9 DQA1_12 ADBIA0 L18 DDBIA1_2 DQA1_13 C9 DQA1_13 ADBIA1 K16 DDBIA1_3 [81] MAA1_0 MVDDQ GDDR5 GDDR3 DDR3 DQA1_14 F9 DQA1_14 H26 [81] MAA1_1 Ra 1.5V 1D35V 1.5V DQA1_15 D8 DQA1_15 CLKA0 H25 ADBIA0 [81] MAA1_2 Rb 40.2R 40.2R 40.2R DQA1_16 E7 DQA1_16 CLKA0# G9 ADBIA1 [81] MAA1_3 100R 100R 100R DQA1_17 A7 DQA1_17 H9 [81] MAA1_4 DQA1_18 C7 DQA1_18 CLKA1 G22 CLKA0 [81] MAA1_5 DQA1_19 F7 DQA1_19 CLKA1# G17 CLKA0b [81] MAA1_6 DQA1_20 A5 DQA1_20 RASA0# G19 [81] MAA1_7 DQA1_21 E5 DQA1_21 RASA1# G16 CLKA1 [81] MAA1_8 DQA1_22 C3 DQA1_22 CASA0# H22 CLKA1b DQA1_23 E1 DQA1_23 CASA1# J22 [81] EDCA0_0 1D35V_VGA_S0 1D35V_VGA_S0 3.24 DQA1_24 G7 DQA1_24 CSA0#_0 G13 RASA0b [81] EDCA0_1 DQA1_25 G6 DQA1_25 CSA0#_1 K13 RASA1b [81] EDCA0_2 R78172 12 1 Ra R7810 DQA1_26 G1 DQA1_26 CSA1#_0 K20 [81] EDCA0_3 21 40D2R2F-GP DQA1_27 G3 DQA1_27 CSA1#_1 J17 CASA0b Ra 40D2R2F-GP DQA1_28 DQA1_28 CKEA0 G25 CASA1b [81] EDCA1_0 2 12 1OPS DQA1_29 J6 DQA1_29 CKEA1 H10 [81] EDCA1_1 OPS 21 DQA1_30 J1 DQA1_30 WEA0# CSA0b_0 [81] EDCA1_2 DQA1_31 J3 DQA1_31 WEA1# [81] EDCA1_3 MVREFDA MVREFSA J5 CSA1b_0 MVREFDA [81] DDBIA0_0 Rb R7818 OPS C7805 Rb R7814 OPS C7801 MVREFSA K26 MVREFDA CKEA0 [81] DDBIA0_1 100R2F-L3-GP SC1U10V2KX-1GP 100R2F-L3-GP SC1U10V2KX-1GP J26 MVREFSA CKEA1 [81] DDBIA0_2 MEM_CALRP0 [81] DDBIA0_3 OPS OPS J25 NC#J25 W EA0b K25 MEM_CALRP0 W EA1b B [81] DDBIA1_0 [81] DDBIA1_1 DRAM_RST_VGA1 L10 DRAM_RST# [81] DDBIA1_2 [81] DDBIA1_3 Place all these componets very close to GPU (within 25mm) and keep all CLKTESTA K8 CLKTESTA components close to each other CLKTESTB L7 CLKTESTB [81] W CKA0_0 This basic topology should be used for DRAM_RST for DDR3/GDDR5 [81] W CKA0b_0 [81] W CKA0_1 [81] W CKA0b_1 [81] W CKA1_0 [81] W CKA1b_0 [81] W CKA1_1 [81] W CKA1b_1 C7822 DY DY C7821 21 JET-XT-S3-GP ??? SCD1U16V2KX-3GP 21 SCD1U16V2KX-3GP [81] ADBIA0 1D35V_VGA_S0 Difference with AMD OPS [81] ADBIA1 21DY R7802 CLKTESTB_C Debug only, for [81] CSA0b_0 212K2R2J-L1-GP CLKTESTA_C clock observation, [81] CSA1b_0 21 if not needed, DNI 21SC68P50V2JN-1GP [81] CKEA0 5K1R2F-2-GP R7803 21 [81] CKEA1 R7804 1OPS 2 DRAM_RST_R 1OPS 2 DRAM_RST_VGA1 21 [81] DRAM_RST SC100P50V2JN-3GP 0510 R7821 R7820 [81] W EA0b 49D9R2F-L1-GP C7802 51D1R2F-GP DY DY 51D1R2F-GP [81] W EA1b 10R2J-L-GP Follow AMD adding DY cap A [81] CASA0b [81] CASA1b OPS R7819 DY C7803 <Core Design> [81] RASA0b [81] RASA1b OPS [81] CLKA0 Wistron Corporation [81] CLKA0b [81] CLKA1 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, [81] CLKA1b Taipei Hsien 221, Taiwan, R.O.C. Title Size Project Name 078_GPU (3/5) VRAM I/F Rev Vegas SKL/KBL-U Date: W ednesday, November 08, 2017 Sheet 78 of 105 5 4321

54321 Main Func = dGPU #3 PS0 ~ PS3 Setting R16: DY GPU1B 2 OF 7 MESO : 上件 3D3V_VGA_S0 RN7905 MESO_U1 AMD suggest Aperture Size = 256MB 1D8V_VGA_S0 32 MESO_U3 R7903 2 DY NC#AF2 AF2 1D8V_VGA_S0 11001 1 5K1R2F-2-GP TESTEN SMB_CLK_VGA_R R7912 1 4 MESO 1 PINs for debug NC#AF4 AF4 SMB_DATA_VGA_R R7914 1 SRN10KJ-5-GP N9 AG3 2 12 1 L9 AG5 21 R7902 1OPS 2 1KR2F-L1-GP TESTEN 2 0R0402-PAD SMB_CLK_VGA AE9 DBG_DATA16 NC#AG3 R7926 Y11 DBG_DATA15 NC#AG5 AE8 DBG_DATA14 DPA OPS 8K45R2F-2-GP RN7904 2 0R0402-PAD SMB_DATA_VGA AD9 DBG_DATA13 AH3 R_pu 32 XO_IN AC10 DBG_DATA12 NC#AH3 AH1 XO_IN2 Vinafix.com3D3V_VGA_S0 AD7 DBG_DATA11 NC#AH1 PS_0 4 OPS 1 AC8 DBG_DATA10 AC7 DBG_DATA9 AK3 SRN10KJ-5-GP AB9 DBG_DATA8 DVO NC#AK3 AK1 AB8 DBG_DATA7 NC#AK1 AB7 DBG_DATA6 2KR2F-L1-GP DY C7918 14 10KR2J-L-GP AB4 DBG_DATA5 NC#AK5 AK5 R_pOdPS R7927 23 R7942 AB2 DBG_DATA4 NC#AM3 AM3 SCD082U16V2KX-GP Y8 DBG_DATA3 D 21 Y7 DBG_DATA2 D DBG_DATA1 R7904 DY DBG_DATA0 NC#AK6 AK6 0R2J-2-GP NC#AM5 AM5 1 DY 2DGPU_PWROK_R [19,24,85] DGPU_PWROK Q7903 DPB AJ7 AH6 G DY NC#AJ7 NC#AH6 D CLKREQ_PEG#0 [18] NC#AK8 AK8 1D8V_VGA_S0 11000 S NC#AL7 AL7 3D3V_VGA_S0 GEN3 2 12 1 21 2N7002K-2-GP W6 NC#W 6 R_puOPS R7928 V6 NC#V6 8K45R2F-2-GP R7943 1OPS 2 AC6 NC#AC6 V4 AC5 NC#AC5 NC#V4 U5 0R2J-2-GP AA5 NC#AA5 NC#U5 PS_1 RN7902 AA6 NC#AA6 NC#W 3 W3 OPS SRN4K7J-8-GP NC#V2 V2 2N7002KDW -GP SMB_CLK_VGA_R DPC Y4 R_pdOPS 2KR2F-L1-GP DY C7919 61 W5 R7929 [18,24,79] SML1_SMBCLK SMB_DATA_VGA_R NC#Y4 R7938 R7929 cgange to 2K ohm 1/21 SCD68U16V3KX-GP-U [18,24,79] SML1_SMBDATA 52 NC#W 5 16K2R2F-GP 680nF 4 OPS 3 MESO_U1 MESO_U3 U1 NC#U1 NC#AA3 AA3 NC#AA3 2 DY 1 Q7901 1 PLL_ANALOG_IN W1 NC#W 1 NC#Y2 Y2 U3 NC#U3 Y6 NC#Y6 NC#J8 J8 AA1 NC#AA1 TP7902 1D8V_VGA_S0 Circuit checklist Test only, 2 12 1 11000 Connect to GND through a 16.2-K resistor. 21 I2C The resistor is not needed on production. R7930 3D3V_VGA_S0 BALL: U10,T10,Y9,W10 R1 SCL PS_2 DY 8K45R2F-2-GP R16: NC R3 SDA R_pu MESO : VDDC NC_R AM26 NC_R 1 TP7922 AK26 21 TP7918 1 GPU_DPRSLP R7911 1 DY 2 GPU_DPRSLP_R U6 GPIO_0 GENERAL PURPOSE I/ONC_AVSSN#AK26 AL25 4K75R2F-1-GP DY C7920 R7921 AJ25 R7931 10KR2J-L-GP 0R2J-2-GP U10 NC_GPIO_1 NC_G AH24 R_pOdPS SCD68U16V3KX-GP-U T10 AG25 C R7937 1 2 GPU_PWR_LEVEL_R G Q7902 OPS SMB_DATA_VGA U8 NC_GPIO_2 NC_AVSSN#AJ25 AH26 680nF C 0R0402-PAD AJ27 [24] GPU_PWR_LEVEL OPS SMB_CLK_VGA U7 SMBDATA AD22 D GPIO_5_AC_BATT T9 SMBCLK NC_B AG24 GPIO_5_AC_BATT NC_AVSSN#AG25 AE22 [85] TOPAZ_OCP R7913 1 DY 2 T8 GPIO_6 AE23 R7941 S T7 DAC1 AD23 4K7R2J-2-GP 0R2J-2-GP NC_GPIO_7 NC_HSYNC 1 GPIO_8_ROMSO P10 AM12 NC_VSYNC 2 MESO1 TP7905 1 GPIO_9_ROMSI P4 GPIO_8_ROMSO NC_VSYNC R16 : DY TP7906 GPIO_9_ROMSI AK12 MESO : 上件 ## PS_3[3-1] => MEM_ID setting, need decide for AMD 2N7002K-2-GP TP7901 1 GPIO_10_ROMSCK P2 GPIO_10_ROMSCK AL11 1D8V_VGA_S0 AJ11 N6 NC_GPIO_11 NC_RSET N5 N3 NC_GPIO_12 2 12 1 Pre-PWROK METAL VID CODES NC_GPIO_13 NC_AVDD 21 Y9 VRAM R7932 JET_SVD N1 NC_GPIO_14 NC_AVSSQ 1 GPIO16_VGA M4 GPIO_15_PW RCNTL_0 3K24R2F-GP SVC SVD Output Voltage GPIO_16 NC_VDD1DI TP7903 1 GPIO_17_THERMAL_INT R6 R_pu TP7923 00 1.1 2 W 10 GPIO_17_THERMAL_INT NC_VSS1DI PS_3 NC_GPIO_18 R7922 1OPS GPIO_19_CTF M2 GPIO_19_CTF FutureASIC/SEYMOUR/PARK JET_SVC 01 1.0 10KR2J-L-GP P8 GPIO_20_PW RCNTL_1 CEC_1 P7 1 GPIO_22_ROMCS# N8 GPIO_21 VRAM 5K62R2F-GP DY C7921 AMD suggestion 1 0 0.9 GPIO_22_ROMCS# R_pd R7933 TP7910 1 H_VID3 AK10 MESO_SVD SCD01U50V2KX-L-GP TP7919 MESO_SVT 11 0.8 TP7920 1 H_VID4 AM10 GPIO_29 NC_SVI2#AK12 MESO_SVC GPIO_30 NC_SVI2#AL11 N7 CLKREQ# NC_SVI2#AJ11 [79,85] VGA_SVC R7919 1 2 0R0402-PAD JET_SVC BALL: AB13, W9, AC14 TP7907 1 JTAG_TRST#_VGA L6 JTAG_TRST# NC_GENLK_CLK AL13 [79,85] VGA_SVD R7920 1 2 0R0402-PAD JET_SVD R16: NC TP7908 1 JTAG_TDI_VGA L5 JTAG_TDI NC_GENLK_VSYNC AJ13 MESO : VDDC TP7911 1 JTAG_TCK_VGA L3 JTAG_TCK TP7912 1 JTAG_TMS_VGA L1 JTAG_TMS TP7913 1 JTAG_TDO_VGA K4 JTAG_TDO K7 TESTEN TESTEN AF24 NC#AF24 PW R_VGA_CORE_VDDIO AB13 NC_SW APLOCKA AG13 W8 NC_SW APLOCKB AH12 W9 21 W7 NC_GENERICA PS_0 AC19 PS_0 #3 21 NC_GENERICB PS_1 AD19 PS_1 21 AD10 NC_GENERICC PS_2 AE17 PS_2 B 10KR2J-L-GP AJ9 NC_GENERICD PS_3 AE20 PS_3 B R7923 AL9 NC_GENERICE_HPD4 DY 1 PX_EN NC#AJ9 MESO AC14 DBG_CNTL0 TP7904 AB16 NC_HPD1 10KR2J-L-GP PX_EN R7924 MESO_SVD MESO MESO_SVT MESO_SVC 10KR2J-L-GP R7940 [79,85] VGA_SVD R7944 1 MESO 2 0R2J-2-GP [85] VGA_SVT R7945 1 MESO 2 0R2J-2-GP AC16 NC_DBG_VREFG TS_A AE19 R7946 1 MESO 2 0R2J-2-GP [79,85] VGA_SVC MESO non-install BALL: AC11,AC13 R16: NC MESO : VDDC 21 DDC/AUX 21 NC_DDC1CLK AE6 21 AE5 10KR2J-L-GP PLL/CLOCK NC_DDC1DATA R7939 NC_AUX1P AD2 DY NC_AUX1N AD4 3D3V_S0 GPU thermal sensor 10KR2J-L-GP R7934 NC_DDC2CLK AC11 DY 3D3V_S0 3D3V_S0 NC_DDC2DATA AC13 RN7903 MESO R2613 1GPU T82 18K7R2F-GP GPU_ALERT# NC_AUX2P AD13 R2614 1GPU T82 2KR2F-L1-GP GPU_T_CRIT# GPU T8 SRN4K7J-8-GP 10KR2J-L-GP NC_AUX2N AD11 R7925 NC#AD20 AD20 MESO NC#AC20 AC20 XTL_27M_X1_VGA AM28 XTALIN 21 SCD1U16V2KX-3GP 41 XTL_27M_X2_VGA AK28 XTALOUT 21 C2618 32 XO_IN SCD1U16V2KX-3GP SVID PWR Sequencing 3D3V_VGA_S0 XO_IN AC22 XO_IN2 C2617 XO_IN2 AB22 NCT7718_DXP SCD1U16V2KX-3GP C2616 R16 R7919 R7920 PR8611 PC8607 / PR8612 PC8612 2 12 1 NC#AE16 AE16 THM262 61 SMB_CLK_THM_R 21 NC#AD16 AD16 GPU_T8 GPU T8 R7935 10KR2J-L-GP 10KR2J-L-GP NC_DDCVGACLK AC1 EC Q7905 C2614 1 8 SMB_CLK_THM_R [18,24,79] SML1_SMBCLK 52 NC_DDCVGADATA AC3 B SC2200P50V2KX-2GPSC10U6D3V3MX-GP 2 7 SMB_DATA_THM_R SEYMOUR/FutureASIC 21 C2615 3 VDD SCL 6 GPU_ALERT# 4GPU T83 1 GPU_DPLUS GPU T8 GPU T8 4 D+ SDA 5 DY TP7909 1 GPU_DMINUS T4 DPLUS THERMAL GPU_T_CRIT# D- ALERT# DY TP7914 T2 DMINUS T_CRIT# GND MLPS_EN# 21 LMBT3904LT1G-GP 21DY C7901 Q7904 SC6D8P50V2CN-DL-GP 1D8V_VGA_S0 13mA R5 NCT7718_DXN NCT7718W -GP 2N7002KDW -GP XTL_27M_X1_VGA R7936 OPS C7904 AD17 GPIO28_FDO 74.07718.0B9 O1PS 2 AC17 TSVDD Layout Note: [18,24,79] SML1_SMBDATA SMB_DATA_THM_R SC1U10V2KX-1GP TSVSS X7901 OPS Both DXN and DXP routing 10 mil trace width 4 OPS 121 and 10 mil spacing. Q2605 A OPS G 1MR2J-1-GP JET-XT-S3-GP [17,24,26] RESET_OUT# A 32R7901 S GPU T8 0: Enable MLPS, disable GPIO PINSTRAP OPS D PURE_HW_SHUTDOWN# [26,40] 1: Disable MLPS, enable GPIO PINSTRAP 2 GPU_T_CRIT_R# R2615 1 C7903 0R0402-PAD XTAL-27MHZ-159-GP SC6D8P50V2CN-DL-GP R_pu (Ω) R_pd (Ω) Bits [3:1] 2N7002K-2-GP XTL_27M_X2_VGA NC 4750 000 <Core Design> O1PS 2 84.2N702.J31 8450 2000 001 2ND = 84.2N702.031 Wistron Corporation 4530 2000 010 3rd = 84.07002.I31 Cap Value (nF) Bits [5:4] 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, 6980 4990 011 680 00 Taipei Hsien 221, Taiwan, R.O.C. 4530 4990 100 82 01 3240 5620 101 10 10 3400 10000 110 NC 11 Title 4750 NC 111 079_GPU (4/5) GPIO/STRAP Note: 0402 1% resistors are required. Size Project Name Rev Vegas SKL/KBL-U Date: Wednesday, November 08, 2017 Sheet 79 of 105 54321

5 4 321 Main Func = dGPU 20170502 0D95V_VGA_S0 AMD schematic Review need GPU1D 4 OF 7 1D8V_VGA_S0 10uF x 1, 2.2uFx5, 0.1uF x1, 0.01uF x1 PCIE_PVDD 0.1A 1D35V_VGA_S0 NC#AB23 AM30 21 C8010 C8016 Vinafix.com1AD NC#AC23 AB23 21 MEM I/O PCIE NC#AD24 AC23 DY OPS NC#AE24 AD24 21 H13 NC#AE25 AE24 21 H16 VDDR1 NC#AE26 AE25 DY C8008 OPS C8002 H19 VDDR1 NC#AF25 AE26 SC1U10V2KX-1GP SC10U6D3V3MX-GP 21 J10 VDDR1 NC#AG26 AF25 21 J23 VDDR1 AG26 21 J24 VDDR1 PCIE_VDDC OPS C8001 DY C8007 DY C8014 VDDR1 PCIE_VDDC L23 D SC10U6D3V3MX-GP SCD1U16V2KX-3GP SCD01U50V2KX-L-GP J9 VDDR1 PCIE_VDDC L24 C K10 VDDR1 PCIE_VDDC L25 K23 VDDR1 PCIE_VDDC L26 SC10U6D3V3MX-GP K24 VDDR1 PCIE_VDDC M22 SC10U6D3V3MX-GP VDDR1 PCIE_VDDC N22 1D35V_VGA_S0 K9 VDDR1 PCIE_VDDC N23 L11 VDDR1 PCIE_VDDC N24 L12 VDDR1 PCIE_VDDC R22 2.5A 0D95V_VGA_S0 L13 VDDR1 PCIE_VDDC T22 AMD schematic Review need 10uF x 2, 1uFx3, 0.1uF x2 L20 VDDR1 PCIE_VDDC U22 C800321 C8004 C8005 C8006 C8009 C8031 C8032 C8033 C8034 C8042 L21 VDDR1 V22 21 C8011 C8012 C8013 C8015 C8057 21 L22 21OPSOPS OPS OPS OPS OPS 21OPSDY DY DY DY DY DY OPS DY 21 21 21 21 21 21 21 21 21 21 SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP SCD1U16V2KX-3GP SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP SCD1U16V2KX-3GP SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP LEVEL 1D8V_VGA_S0 13mA AA20 TRANSLATION AA21 21 C8017 AB20 VDD_CT CORE VDDC AA15 AMD ORB 10U x 6 LF145M 4.7U x 6 VGA_CORE SC1U10V2KX-1GP AB21 VDD_CT VDDC N15 VDD_CT VDDC N17 OPS VDD_CT VDDC R13 2.2U x 16 1U x 20 VDDC R16 25mAC I/O VDDC R18 VDDC Y21 AA17 VDDR3 VDDC T12 21 C8018 C8019 C8020 C8021 C8022 C8023 C8025 C8026 C8027 AA18 VDDR3 VDDC T15 21OPSOPS OPS OPS OPS OPS OPS OPS OPS AB17 VDDR3 VDDC T17 21 AB18 VDDR3 VDDC T20 21 VDDC U13 21 VDDC U16 21 VDDC U18 21 VDDC V21 21 VDDC V15 21 VDDC V17 3D3V_VGA_S0 VDDC V20 VDDC Y13 21 C8024 V12 NC_VDDR4#V12 VDDC Y16 SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP Y12 NC_VDDR4#Y12 VDDC Y18 SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP U12 NC_VDDR4#U12 VDDC AA12 SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP OPS VDDC M11 VDDC N12 VDDC U11 NC on JET VGA_CORE AB13 U10 W9 Y9 W10 T10 AC14 AB12 AB11 AC11 AC13 1D8V_VGA_S0 Memory phase lock loop power: Dedicated POWER 21 C8028 C8029 C8030 C8035 C8036 C8037 C8058 C8059 C8060 analogue power in for memory PLLs MPV18 21OPSOPS OPS OPS OPS OPS OPS OPS OPS 21 L8001 1 OPS 2 MMZ1005S241C-GP 21 21 C8043 21 SC10U6D3V3MX-GP 21 21 OPS 21 21 21 C8045 21 SC1U10V2KX-1GP C8044 SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP SC10U6D3V3MX-GP OPS SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP OPS PLL R21 0D95V_VGA_S0 U21 1.4AEngine phase loop power: Dedicated analogue 1D8V_VGA_S0 power pin for engine PLL MPV18 BIF_VDDC BIF_VDDC SPV18 90mAB L8 MPLL_PVDD 21 L8002 1OPS 2 BLM15AG121SN-1GP C8065 SC1U10V2KX-1GP B ISOLATED 21 C8053 21 C8054 SPV18 OPS SC10U6D3V3MX-GP SC1U10V2KX-1GP 68.00084.921 75mA H7 SPLL_PVDD CORE I/O M13 5A OPS OPS M15 VDDCI M16 AMD ORB 10U x 2 Engine phase loop power: Dedicated digital SPV10 SPLL_VDDC VDDCI M17 1U x 3 LF145M 4.7U x 2 VGA_CORE SPLL_PVSS VDDCI M18 0.1U x2 1U x 3 C8051 C8052 100mA H8 VDDCI M20 0.1U x 2 VDDCI M21 J7 VDDCI N20 VDDCI 0D95V_VGA_S0 power pin for engine PLL VDDCI SPV10 21 C8046 C8047 C8048 C8049 C8050 21 21 21 21 21 21 L8003 1OPS 2 BLM15AG121SN-1GP OPS OPS OPS OPS OPS OPS OPS JET-XT-S3-GP 21 68.00084.921 21C8055 C8056 SCD1U16V2KX-3GP SC1U10V2KX-1GP SC4D7U6D3V3KX-GP 21SC1U10V2KX-1GPSCD1U16V2KX-3GP 21 21OPSOPS SCD1U16V2KX-3GP SC1U10V2KX-1GP SC4D7U6D3V3KX-GP 21 21 SC1U10V2KX-1GP 21 VGA_CORE VGA_CORE C8038 C8039 C8040 C8041 C8063 C8064 SC1U10V2KX-1GP C8062 OPS OPS OPS OPS OPS OPS SC1U10V2KX-1GP C8061 SC22U6D3V3MX-1-GP C8066 21OPS OPS OPS <Core Design> 21 A SC10U6D3V3MX-GP SC10U6D3V3MX-GP 21 A SC10U6D3V3MX-GP SC10U6D3V3MX-GP Wistron Corporation SC10U6D3V3MX-GP SC10U6D3V3MX-GP 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Project Name 080_GPU (5/5) PWR/GND Rev <Project Name> Date: W ednesday, November 08, 2017 Sheet 80 of 105 54321

5 4 3 21 SSID = Vram (GDDR5) [78] DQA0_0 1D35V_VGA_S0 VRAM1A 1 OF 2 1D35V_VGA_S0 VRAM2A 1 OF 2 [78] DQA0_1 [78] DQA0_2 OPSC5VDD VSS B5 C5 VDD OPS VSS B5 0510 [78] DQA0_3 VDD VSS B10 C10 VDD VSS B10 Follow AMD Change to 1% [78] DQA0_4 C10 VDD VSS D10 D11 VDD VSS D10 [78] DQA0_5 D11 VDD VSS G5 VDD VSS G5 1D35V_VGA_S0 [78] DQA0_6 VDD VSS G10 G1 VDD VSS G10 Close to VRAM1 [78] DQA0_7 G1 VDD VSS H1 G4 VDD VSS H1 [78] DQA0_8 G4 VDD VSS H14 G11 VDD VSS H14 R8101 1OPS 2 60D4R2F-GP CLKA0 [78] DQA0_9 G11 VDD VSS K1 G14 VDD VSS K1 R8102 1OPS 2 60D4R2F-GP CLKA0b [78] DQA0_10 G14 VDD VSS K14 L1 VDD VSS K14 [78] DQA0_11 L1 VDD VSS L5 L4 VDD VSS L5 1D35V_VGA_S0 [78] DQA0_12 L4 VDD VSS L10 L11 VDD VSS L10 Close to VRAM2 [78] DQA0_13 L11 VDD VSS P10 L14 VDD VSS P10 [78] DQA0_14 L14 VDD VSS T5 P11 VDD VSS T5 R8103 1OPS 2 60D4R2F-GP CLKA1 [78] DQA0_15 P11 VDD VSS T10 R5 VDD VSS T10 R8104 1OPS 2 60D4R2F-GP CLKA1b D [78] DQA0_16 R5 A1 R10 A1 [78] DQA0_17 R10 A3 A3 [78] DQA0_18 Vinafix.com1D35V_VGA_S0 A12 1D35V_VGA_S0 A12 [78] DQA0_19 A14 A14 [78] DQA0_20 B1 VDDQ VSSQ C1 B1 VDDQ VSSQ C1 Frame Buffer Patition A-Lower Half D [78] DQA0_21 B3 VDDQ VSSQ C3 B3 VDDQ VSSQ C3 C [78] DQA0_22 B12 VDDQ VSSQ C4 B12 VDDQ VSSQ C4 1D35V_VGA_S0 1D35V_VGA_S0 B [78] DQA0_23 B14 VDDQ VSSQ C11 B14 VDDQ VSSQ C11 [78] DQA0_24 D1 VDDQ VSSQ C12 D1 VDDQ VSSQ C12 [78] DQA0_25 D3 VDDQ VSSQ C14 D3 VDDQ VSSQ C14 [78] DQA0_26 D12 VDDQ VSSQ E1 D12 VDDQ VSSQ E1 [78] DQA0_27 D14 VDDQ VSSQ E3 D14 VDDQ VSSQ E3 [78] DQA0_28 E5 VDDQ VSSQ E12 E5 VDDQ VSSQ E12 [78] DQA0_29 E10 VDDQ VSSQ E14 E10 VDDQ VSSQ E14 [78] DQA0_30 F1 VDDQ VSSQ F5 F1 VDDQ VSSQ F5 [78] DQA0_31 F3 VDDQ VSSQ F10 F3 VDDQ VSSQ F10 F12 VDDQ VSSQ H2 F12 VDDQ VSSQ H2 [78] DQA1_0 F14 VDDQ VSSQ H13 F14 VDDQ VSSQ H13 0510 2 12 1 0510 2 12 1 [78] DQA1_1 G2 VDDQ VSSQ K2 G2 VDDQ VSSQ K2 Follow AMD to dummy Follow AMD to dummy [78] DQA1_2 G13 VDDQ VSSQ K13 G13 VDDQ VSSQ K13 21 OPS R8105 21 R8106 [78] DQA1_3 H3 VDDQ VSSQ M5 H3 VDDQ VSSQ M5 C8101 DY C8102 DY H12 VDDQ VSSQ M10 H12 VDDQ VSSQ M10 2K37R2F-GP OPS 2K37R2F-GP K3 VDDQ VSSQ N1 K3 VDDQ VSSQ N1 SC1U10V2KX-1GP SC1U10V2KX-1GP [78] DQA1_4 K12 VDDQ VSSQ N3 K12 VDDQ VSSQ N3 [78] DQA1_5 L2 VDDQ VSSQ N12 L2 VDDQ VSSQ N12 VREFC_A0 VREFC_A1 [78] DQA1_6 L13 VDDQ VSSQ N14 L13 VDDQ VSSQ N14 [78] DQA1_7 M1 VDDQ VSSQ R1 M1 VDDQ VSSQ R1 [78] DQA1_8 M3 VDDQ VSSQ R3 M3 VDDQ VSSQ R3 [78] DQA1_9 M12 VDDQ VSSQ R4 M12 VDDQ VSSQ R4 C8103 OPS OPS R810721 C8104 OPS21 R8108 M14 VDDQ VSSQ R11 M14 VDDQ VSSQ R11 SC1U10V2KX-1GP 5K49R2F-GP [78] DQA1_10 N5 VDDQ VSSQ R12 N5 VDDQ VSSQ R12 SC1U10V2KX-1GP OPS 5K49R2F-GP N10 VDDQ VSSQ R14 N10 VDDQ VSSQ R14 [78] DQA1_11 P1 VDDQ VSSQ U1 P1 VDDQ VSSQ U1 [78] DQA1_12 P3 VDDQ VSSQ U3 P3 VDDQ VSSQ U3 [78] DQA1_13 P12 VDDQ VSSQ U12 P12 VDDQ VSSQ U12 [78] DQA1_14 P14 VDDQ VSSQ U14 P14 VDDQ VSSQ U14 [78] DQA1_15 T1 VDDQ VSSQ A5 T1 VDDQ VSSQ A5 [78] DQA1_16 T3 VDDQ VSSQ U5 T3 VDDQ VSSQ U5 [78] DQA1_17 T12 VDDQ VSSQ T12 VDDQ VSSQ [78] DQA1_18 T14 VDDQ VSSQ T14 VDDQ VSSQ [78] DQA1_19 [78] DQA1_20 Place close VRAM2 VDD ball Place close VRAM1 VDD ball [78] DQA1_21 [78] DQA1_22 VREFC_A0 J14 VREFC VREFC_A1 J14 VREFC 1D35V_VGA_S0 1D35V_VGA_S0 VPP/NC#A5 VPP/NC#A5 [78] DQA1_23 VPP/NC#U5 VPP/NC#U5 0.1uF(X7R) 0.1uF(X7R) C [78] DQA1_24 A10 VREFD A10 VREFD K0402 ×4 K0402 ×4 U10 VREFD U10 VREFD [78] DQA1_25 [78] DQA1_26 0510 0510 Follow AMD to remove net Follow AMD to remove net 21 [78] DQA1_27 Symbol error for layout NCH5GQ2H24AFR-T2C-GP Symbol error for layout NCH5GQ2H24AFR-T2C-GP C8105 21C8106 C8107 C8108 C8109 C8110 C8111 C8112 [78] DQA1_28 21 OPS 21OPSOPSOPS OPS OPS OPS OPS 21 [78] DQA1_29 21 21 21 [78] DQA1_30 [78] DQA1_31 [78] MAA0_0 Normal(MF=0) Mirrored(MF=1) SCD1U16V2KX-3GP SCD1U16V2KX-3GP [78] MAA0_1 SCD1U16V2KX-3GP SCD1U16V2KX-3GP [78] MAA0_2 SCD1U16V2KX-3GP SCD1U16V2KX-3GP [78] MAA0_3 SCD1U16V2KX-3GP SCD1U16V2KX-3GP [78] MAA0_4 [78] MAA0_5 VRAM1B 2 OF 2 VRAM2B 2 OF 2 [78] MAA0_6 [78] MAA0_7 MAA0_7 K4 OPSA8/A7 DQ0 A4 DQA0_30 MAA1_0 K4 A8/A7 OPS DQ0 A4 DQA1_18 1D35V_VGA_S0 close VRAM2 VDDQ ball 1.0uF(X7R) 10uF(X5R) [78] MAA0_8 MAA0_1 H5 DQ1 A2 DQA0_28 MAA1_6 H5 DQ1 A2 DQA1_17 K0402 ×8 M0603 ×2 MAA0_0 H4 A9/A1 DQ2 B4 DQA0_31 MAA1_7 H4 A9/A1 DQ2 B4 DQA1_20 Place MAA0_6 K5 A10/A0 DQ3 B2 DQA0_29 MAA1_1 K5 A10/A0 DQ3 B2 DQA1_21 [78] MAA1_0 MAA0_8 J5 A11/A6 DQ4 E4 DQA0_24 3 MAA1_8 J5 A11/A6 DQ4 E4 DQA1_22 2 21C8113 C8114 C8115 C8116 C8117 C8118 C8119 C8120 C8121 C8122 [78] MAA1_1 A12/RFU#J5/NC#J5 DQ5 E2 DQA0_27 A12/RFU#J5/NC#J5 DQ5 E2 DQA1_16 3 21 [78] MAA1_2 MAA0_2 H11 BA0/A2 DQ6 F4 DQA0_25 2 MAA1_4 H11 BA0/A2 DQ6 F4 DQA1_23 1 21OPSOPSOPS OPS OPS OPS OPS OPS OPS OPS [78] MAA1_3 MAA0_5 K10 BA1/A5 DQ7 F2 DQA0_26 MAA1_3 K10 BA1/A5 DQ7 F2 DQA1_19 0 21 [78] MAA1_4 MAA0_4 K11 BA2/A4 DQ8 A11 DQA0_16 0 MAA1_2 K11 BA2/A4 DQ8 A11 DQA1_26 21 [78] MAA1_5 MAA0_3 H10 BA3/A3 DQ9 A13 DQA0_19 MAA1_5 H10 BA3/A3 DQ9 A13 DQA1_31 21 [78] MAA1_6 ABI# DQ10 B11 DQA0_18 1 ABI# DQ10 B11 DQA1_29 21 [78] MAA1_7 RAS# DQ11 B13 DQA0_17 RAS# DQ11 B13 DQA1_30 21 [78] MAA1_8 CS# DQ12 E11 DQA0_23 1D35V_VGA_S0 CS# DQ12 E11 DQA1_27 21 CAS# DQ13 E13 DQA0_21 CAS# DQ13 E13 DQA1_24 21 W E# DQ14 F11 DQA0_22 W E# DQ14 F11 DQA1_25 ADBIA0 J4 CK DQ15 F13 DQA0_20 ADBIA1 J4 CK DQ15 F13 DQA1_28 SC1U10V2KX-1GP SC1U10V2KX-1GP SC10U6D3V3MX-GP RASA0b G3 CK# DQ16 U11 DQA0_4 CASA1b G3 CK# DQ16 U11 DQA1_15 SC1U10V2KX-1GP SC1U10V2KX-1GP SC10U6D3V3MX-GP CSA0b_0 G12 CKE# DQ17 U13 DQA0_3 W EA1b G12 CKE# DQ17 U13 DQA1_14 SC1U10V2KX-1GP SC1U10V2KX-1GP CASA0b L3 DBI0# DQ18 T11 DQA0_5 RASA1b L3 DBI0# DQ18 T11 DQA1_13 SC1U10V2KX-1GP SC1U10V2KX-1GP W EA0b L12 DBI1# DQ19 T13 DQA0_2 CSA1b_0 L12 DBI1# DQ19 T13 DQA1_11 [78] DDBIA0_0 DBI2# DQ20 N11 DQA0_7 DBI2# DQ20 N11 DQA1_12 [78] DDBIA0_1 CLKA0 J12 DBI3# DQ21 N13 DQA0_1 CLKA1 J12 DBI3# DQ21 N13 DQA1_10 1D35V_VGA_S0 close VRAM1 VDDQ ball 1.0uF(X7R) 10uF(X5R) [78] DDBIA0_2 CLKA0b J11 RESET# DQ22 M11 DQA0_6 CLKA1b J11 RESET# DQ22 M11 DQA1_9 K0402 ×8 M0603 ×2 [78] DDBIA0_3 CKEA0 SEN DQ23 M13 DQA0_0 CKEA1 SEN DQ23 M13 DQA1_8 Place J3 ZQ DQ24 U4 DQA0_15 J3 ZQ DQ24 U4 DQA1_0 [78] DDBIA1_0 MF DQ25 U2 DQA0_8 MF DQ25 U2 DQA1_3 [78] DDBIA1_1 DDBIA0_3 D2 W CK01 DQ26 T4 DQA0_11 DDBIA1_2 D2 W CK01 DQ26 T4 DQA1_1 C812321 C8124 C8125 C8126 C8127 C8128 C8129 C8130 C8131 C8132 [78] DDBIA1_2 DDBIA0_2 D13 W CK01# DQ27 T2 DQA0_10 DDBIA1_3 D13 W CK01# DQ27 T2 DQA1_2 21 [78] DDBIA1_3 DDBIA0_0 P13 W CK23 DQ28 N4 DQA0_14 DDBIA1_1 P13 W CK23 DQ28 N4 DQA1_7 OPS 21OPSOPS OPS OPS OPS OPS OPS OPS OPS B DDBIA0_1 W CK23# DQ29 N2 DQA0_9 DDBIA1_0 W CK23# DQ29 N2 DQA1_4 21 [78] CSA0b_0 P2 DQ30 M4 DQA0_13 P2 DQ30 M4 DQA1_6 21 DQ31 M2 DQA0_12 DQ31 M2 DQA1_5 21 [78] WEA0b EDC0 C2 EDCA0_3 EDC0 C2 EDCA1_2 21 [78] RASA0b EDC1 C13 EDCA0_2 EDC1 C13 EDCA1_3 21 [78] CASA0b EDC2 R13 EDCA0_0 EDC2 R13 EDCA1_1 21 EDC3 R2 EDCA0_1 EDC3 R2 EDCA1_0 21 [78] CSA1b_0 [78] WEA1b DRAM_RST J2 DRAM_RST J2 [78] RASA1b R8111 111OOOPPPSSS 2 1KR2J-L2-GP SEN_A0 J10 R8113 111OOOPPPSSS 2 1KR2J-L2-GP SEN_A1 J10 SC1U10V2KX-1GP SC1U10V2KX-1GP SC10U6D3V3MX-GP [78] CASA1b R8110 2 120R2F-GP ZQ_A0 J13 R8109 2 120R2F-GP ZQ_A1 J13 SC1U10V2KX-1GP SC1U10V2KX-1GP SC10U6D3V3MX-GP R8112 2 1KR2J-L2-GP MF_A0 R8114 2 1KR2J-L2-GP MF_A1 SC1U10V2KX-1GP SC1U10V2KX-1GP J1 J1 SC1U10V2KX-1GP SC1U10V2KX-1GP WCKA0_1 D4 WCKA1_1 D4 WCKA0b_1 D5 WCKA1b_1 D5 WCKA0_0 P4 WCKA1_0 P4 WCKA0b_0 P5 WCKA1b_0 P5 [78] ADBIA0 H5GQ2H24AFR-T2C-GP H5GQ2H24AFR-T2C-GP [78] ADBIA1 [78] CLKA0 [78] CLKA0b [78] CKEA0 [78] CLKA1 [78] CLKA1b [78] CKEA1 [78] WCKA0_0 A [78] WCKA0b_0 [78] WCKA0_1 <Core Design> [78] WCKA0b_1 [78] WCKA1_0 [78] WCKA1b_0 [78] WCKA1_1 [78] WCKA1b_1 [78] EDCA0_0 [78] EDCA0_1 [78] EDCA0_2 [78] EDCA0_3 A [78] EDCA1_0 [78] EDCA1_1 [78] EDCA1_2 [78] EDCA1_3 [78] DRAM_RST Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Rev GPU-VRAM1,2 (1/4) A00 Size Document Number A2 Vegas SKL/KBL-R Date: Wednesday, November 08, 2017 Sheet 81 of 105 543 21

54321 Main Func = dGPU power DCBATOUT PWR_DCBATOUT_VGA_CORE2 DCBATOUT PWR_DCBATOUT_VGA_CORE1 PG8511 1 1 PG8501 12 12 0926 Modify PC8502 voltage PWR_VGA_CORE_LGATE_NB 2 10KR2J-L-GPPWR_VGA_CORE_UGATE_LX_NB 2 GAP-CLOSE-PW R 1st source: 075.06994.0037 PR8502 GAP-CLOSE-PW R PG8512 2nd source: 075.00998.0073 PG8502 OPS 12 12 GAP-CLOSE-PW R 10KR2J-L-GP GAP-CLOSE-PW R PG8513 PR8501 PG8503 12 12 OPS GAP-CLOSE-PW R GAP-CLOSE-PW R PG8514 3D3V_VGA_S0 PR8503 1OO1PPSS 2 10KR2F-L1-GP EN/DEM_VGA Vinafix.com PG8504 PC8502 2 12 12 SCD1U25V2KX-1-DL-GP GAP-CLOSE-PW R PW R_DCBATOUT_VGA_CORE1 GAP-CLOSE-PW R PG8515 D 1D8V_VGA_S0 PR8546 11MESO 2 0R2J-2-GP PW R_VGA_CORE_VDDIO PG8505 PU8502 PU8503 SCD1U25V2KX-GP D 3D3V_VGA_S0 PR8505 2 0R0402-PAD 12 12 FDMS3600-02-RJK0215-COLAY-GP FDMS3600-02-RJK0215-COLAY-GP PC8530 C GAP-CLOSE-PW R SC10U25V5KX-L-GP B GAP-CLOSE-PW R PG8516 2 2 PC8529 PG8506 3 3 SC10U25V5KX-L-GP 12 12 14 14 PC8528 GAP-CLOSE-PW R 10 SC4D7U25V5KX-L2-GP GAP-CLOSE-PW R 695 BOM 10 9 PC8527 7 SC4D7U25V5KX-L2-GP 7 86 PC8526 PC8503 1OPS2 SC1KP50V2KX-L-1-GP 86 5 OPS 21 OPS OPS OPS OPS 21 5 21 21 21 PU8201_39 PU8201_36 5V_S5 PU8501 ISUMP_NB 40 ISUMN_NB 39 VSEN_NB 38 FB_NB 37 COMP_NB 36 PGOOD_NB 35 LGATE_NB 34 PHASE_NB 33 UGATE_NB 32 BOOT_NB 31 ZZ.00215.037 ZZ.00215.037 5V_S5 PR8507 PC8507 SCD22U25V3KX-GP PR8506 1OPS 2 PW R_VGA_CORE_NTC_NB 1 30 PWR_VGA_CORE_BOOT2 1OPS 2 PWR_VGA_CORE__BOOT2_1 1 O2PS PR8510 PW R_VGA_CORE_IMON_NB 2 NTC_NB BOOT2 29 100KR2F-L3-GP PW R_VGA_CORE_SVC 3 IMON_NB UGATE2 28 PWR_VGA_CORE_UGATE2 2D2R3F-L-GP 21 1R2F-GP 1 2 PWR_VGA_CORE_UGATE1 TDC=34A PR8508 1OPS 2 PW R_VGA_CORE_VR_HOT# 4 SVC PHASE2 27 OPS PC8508 SC1U10V2KX-1GP OCP<??A PW R_VGA_CORE_SVD 5 VR_HOT# LGATE2 26 100KR2F-L3-GP 2 6 SVD 25 PW R_VGA_CORE_PHASE2 VGA_CORE PR8509 1 VDDIO VDDP 24 [79] VGA_SVC 0R0402-PAD SVT VDD 23 OPS [79] TOPAZ_OCP PR8511 1 2 ENABLE 22 PW R_VGA_CORE_LGATE2 [79] VGA_SVD PW ROK LGATE1 21 0R0402-PAD IMON PHASE1 PL8501 OPS PW R_VGA_CORE_VDDIO PR8512 1 2 GND UGATE1 [79] VGA_SVT PW R_VGA_CORE_PHASE1 12 0R0402-PAD BOOT1 PW R_VGA_CORE_VDD 12 PW R_VGA_CORE_LGATE1 IND-D33UH-7-GP-U PR8513 1 2 PW R_VGA_CORE_SVT 7 PW R_VGA_CORE_LGATE1 PC8509 SC1U10V2KX-1GP 1 GAP-CLOSE-PWR-3-GP SE330U2VDM-4-GPOPSOPS PW R_VGA_CORE_ENABLE 8 OPS 68.R3310.201 PT8507 0R0402-PAD PW R_VGA_CORE_PW ROK 9 PR8541 12 PR8514 1 2 PW R_VGA_CORE_IMON 10 PW R_VGA_CORE_PHASE1 12 PG8507 SE330U2VDM-4-GP21 ISL62771HRTZ-GP-U 2D2R3J-2-GP DY PT8506 21 0R0402-PAD PW R_VGA_CORE_UGATE1 PC8510 74.62O7P71S.033 PW R_VGA_SNUB1 GAP-CLOSE-PWR-3-GP PR8515 SCD22U25V3KX-GP 12 PWR_VGA_CORE_VO1 PD8501 PWR_VGA_CORE_BOOT1 1OPS 2PWR_VGA_CORE__BOOT1_1 1 O2PS PC8506 DY PG8508 [20,86] DGPU_PWR_EN K DY AEN/DEM_VGA 21 41 2D2R3F-L-GP SC330P50V2KX-3GP PWR_VGA_CORE_PH1 21 RB551VM-30TE-17-GP 3D3V_VGA_S0 2 C PR8516 OPS PC8511 NTC 133KR2F-GP SC1KP50V2KX-L-1-GP ISEN2 [86] EN/DEM_VGA OPS ISEN1 1 ISUMP ISUMN VSEN RTN FB COMP PGOOD PE_GPIO1 is for 11 PR8518 PR8517 79.33719.20C79.33719.20C turning off PWR IC 12 1KR2J-1-GP 13 PWR_VGA_CORE_ISUMP 1 OPS 2 14 15 3K65R2F-1-GP 16 17 18 19 20 PWR_VGA_CORE_RTN PW R_VGA_CORE_PGOOD 12 OPS 1 PR8520 2 PWR_VGA_CORE_VSEN PWR_VGA_CORE_ISUMN 0R0402-PAD DGPU_PWROK [19,24,79] PWR_VGA_CORE_ISUMP PWR_VGA_CORE_ISEN1 PC8512 PWR_VGA_CORE_ISEN1 PR8519 1OPS 2 PWR_VGA_CORE_ISEN2 SC100P50V2JN-3GP PWR_VGA_CORE_NTC 2 OPS 10KR2F-L1-GP OPS 2 1R2F-GP PC8513 PW R_VGA_CORE_VSUM- PR8521 1 SC1KP50V2KX-L-1-GP PW R_VGA_CORE_FB PR8523 2 OPS 1 PWR_VGA_CORE_FB_R 1OPS2 301R2F-GP PW R_VGA_CORE_ISEN2 PR8522 1OPS 2 10KR2J-L-GP 21 OPS PW R_VGA_CORE_COMP PC8514 OPS PR8525 PW R_VGA_CORE_VSEN 21 PR8524 1OPS 2 100KR2F-L3-GP SC180P50V2JN-1GP 1K13R2F-1-GP 1st source: 075.06994.0037 OPS OPS 2nd source: 075.00998.0073 OPS 2OPS1PW R_VGA_CORE_FB2_R1 PR8526 PR8527 PC8516 PW R_DCBATOUT_VGA_CORE2 PWR_VGA_CORE_COMP_1 1 OPS2 PR8529 OPS 2 1OPS 2 2K61R2F-1-GP SC330P50V2KX-3GP PR852821 PC8515 33KR2F-GP 2KR2F-L1-GP SC330P50V2KX-3GP 32K4R2F-1-GP DY SCD22U10V2KX-L1-GP PU8504 PU8505 SCD1U25V2KX-GP PC8518 FDMS3600-02-RJK0215-COLAY-GP FDMS3600-02-RJK0215-COLAY-GP PC8521 SCD22U10V2KX-L1-GP SC10U25V5KX-L-GP PC8517 2 PC8531 3 SC10U25V5KX-L-GP 14 PC8519 10 SC4D7U25V5KX-L2-GP 9 PC8532 7 SC4D7U25V5KX-L2-GP 86 PC8520 21 5 2 OPS21 OPS OPS OPS OPS 21 21 3 21 14 21 21 1VGA_VSUM2-_1 1 659 BOM 10 21 2 PR8531 1OPS 2 10R2J-L-GP 7 21 PR8530 1 86 21 5 0R0402-PAD SCD1U25V2KX-GP B PC8523 PC8501 VGA_VDD_RUN_FB_L 1 SCD022U25V2KX-DLGP PC8522 11KR2F-L-GP PR8532 OPS DY OPS SCD01U50V2KX-L-GP TP8501 ZZ.00215.037 ZZ.00215.037 1OPS2 PR8533 PC8524 VGA_VDD_RUN_FB_H 1 PW R_VGA_CORE_UGATE2 NTC-10K-29-GP-U SC330P50V2KX-3GP TP8502 VGA_CORE OPS 1DY 2 PR8535 1OPS 2 10R2J-L-GP PR8536 1 PR8534 2 0R0402-PAD 1OPS 2 PW R_VGA_CORE_VSUM- 2 21 1K65R2F-GP PC8525 VGA_CORE OPS SCD1U25V2KX-GP PL8502 OPS PW R_VGA_CORE_PHASE2 12 PW R_VGA_CORE_PW ROK 1 PR8544 2 PW R_VGA_CORE_LGATE2 1 IND-D33UH-7-GP-U PW R_VGA_CORE_PGOOD 0R0402-PAD PR8542 68.R3310.201 PC8534 PC8535 2D2R3J-2-GP DY 12 PG8509 PG8510 21 12 21 21 SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SE330U2VDM-4-GP PWR_VGA_CORE_VO2 GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP PWR_VGA_CORE_PH2 79.33719.20C PT8508OPS OPS OPS PW R_VGA_SNUB2 12 PC8533 PR8539 1 DY 2 PW R_VGA_CORE_EN_R# 2 SC330P50V2KX-3GP 3D3V_S5 100KR2J-1-GP DY PQ8501 16 VGA_CORE PR8537 2N7002KDW -GP 25 A DY 34 PWR_VGA_CORE_ISUMP 1 OPS 2 21 A 3K65R2F-1-GP DY PR8545 PWR_VGA_CORE_ISEN2PR8538 1OPS 2 100R2J-L-GP 10KR2F-L1-GP EN/DEM_VGA PQ8206_3 PW R_VGA_CORE_VSUM- <Core Design> PW R_VGA_CORE_ISEN1 PR8540 1 OPS 2 Wistron Corporation 1R2F-GP 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. PR8543 1OPS 2 10KR2J-L-GP Title Flash/RTC Size Document Number Rev A2 Turis/Vegas KBL-R A00 Date: Wednesday, November 08, 2017 Sheet 85 of 105 54 321

5 4 3 21 Main Func = dGPU 3D3V_S0 to 3D3V_VGA_S0 Transfer GPU PWR Sequencing 3D3V_S0 1D8V_S5 400mA 1D8V_VGA_S0 0926 Modify PC8502 voltage PQ8607 DY 3D3V_VGA_S0 3D3V_VGAS0 1D8V_VGA_S0 DMP2130L-7-GP => 0D95V_VGA_S0/1D8V_VGA_S0 25mA S OPS 3D3V_S5 Vinafix.comPR8601 1 DY 2 0R2J-2-GP D DY OPS 21 21 21 21 G 21 3D3V_VGA_S0 OPS SCD1U16V2KX-3GPPR8650DYPC8634DY PC8636 DSC1U10V2KX-1GP D OPS 10KR2J-L-GP SD G DY DY 21 084.03419.0031 POQP86S09 => 1D5V_VGA_S0 SCD1U25V2KX-1-DL-GP D SC22U6D3V3MX-1-DL-GP 21 PC8635 SC22U6D3V3MX-1-DL-GP 21 21 21 100KR2J-1-GP PJA3419-GP 2PKR28R6521J-L11O-GPPS 2 1D8V_VGA_EN_R# 21 PR8619 16 G 3D3V_VGA discharge => VGA_CORE 1D8V_VGA_EN# 84.02130.031 100KR2J-1-GP 25 2nd = 84.00102.031 PR8606 DY PC8601 34 0D95V_VGA_EN PR8603 1OPS 2 1D8V_VGA_EN G PQ8608 3rd = 84.03413.B31 SCD1U16V2KX-3GP 3.3V_RUN_VGA_1 2 1 PC8603 SCD1U16V2KX-3GP 1KR2J-1-GP PC8605 DY PR8609 OPS PC8604 3.3V_ALW_1 75R2F-2-GP D All the ASIC supplies must reach their respective nominal OPS PC8612 SCD22U10V2KX-L1-GP S voltages withing 20ms of the start of the ramp-up sequence, though a shorter ramp-up duration is preferred. The maximum 2N7002K-2-GP slew rate on all rails is 50mV/us. PQ8604 OPS 2N7002KDW-GP It is recommended that the 3.3V rail ramp up first. [20,85] DGPU_PWR_EN 1P0RK8R6621J-L-1OGPPS 2 DGPU_PWR_EN_R It is recommended that the 0.95V rail reach at least 90% of its High Active normal value no later than 2ms from the start of VDDC ramping 21 up. OPS PC8602 SCD47U25V3KX-1GP PWR_0D95V_PVDD 3D3V_S5 C C PG8601 B 21 SYW232 for 0.95V_S5 21 21 GAP-CLOSE-PWR 21 PG8602 PC8621 DY PC8622 PC8623 21 OPS OPS SC1U10V2KX-1GP DCBATOUT PWR_DCBATOUT_1D35V SC10U6D3V3MX-GP SC10U6D3V3MX-GP PG8651 3D3V_S5 GAP-CLOSE-PWR GAP-CLOSE-PWR-3-GP 12 SC1U10V2KX-1GP21 PC8655 OPS PU8601 Design Current =1.35A SC10U25V5KX-L-GP PG8652 PC8652 PR8674 PC8656 MagLayer. 6.86 x 6.47 x 3.0mm 5 NC#5 IN 3 GAP-CLOSE-PWR-3-GP DCR: 5~5.5mOhm SCD1U25V2KX-GP 0R0603-PAD-1-GP-U SCD1U25V2KX-GP Idc :15.5A , Isat : 25A 12 PC8651 PWR_1D35V_BOOT 1 2PWR_1D35V_BOOT_A 1 O2PS PL8651 IND-D68UH-36-GP-U design current = 3.56A 8 OPS 1 PWR_0D95V_FB PWR_0D95V 0D95V_VGA_S0 2 PWR_1D35V_VCC PU8651 1D35V_VGA_S0 3D3V_VGA_S0 4 SGND FB 6 0D95V_VGA_S0_PG PL8601 PG8603 9 PG 7 PWR_0D95V_PHASE 12 PWR_1D35V_VCC OPS PWR_1D35V_PH PR862521 PGND LX 1 OPS 2 10KR2J-L-GP PGND EN 0D95V_VGA_EN_R GAP-CLOSE-PWR 17 VCC LX#6 6 PWR_1D35V_PG 1 OPS 2 PG8604 19 PWR_1D35V_VCC OPS 21 15 BYP LX#19 20 68.R681A.10A PC8661 IND-1UH-281-GP 21R1 12 21 LX#20 PC8660 0D95V_VGA_EN PR8622 21 10 PC8659 GAP-CLOSE-PWR 21 12 PC8658 16 PC8657 PC8654 21 OPS SYW232DFC-GP OPS SC2D2U10V3KX-L-GP 7 21 74.00232.033 8 21 PC8624 18 21 21 21 PWR_DCBATOUT_1D35V OPS 2 OPS OPS OPS DY 30K1R2F-L-GPOPS 3 4 IN#2 NC#10 PG8653 12 PR8621 1 2 SC22U6D3V3MX-1-GP 5 IN#3 NC#12 GAP-CLOSE-PWR-3-GP 0R0402-PAD SC22U6D3V3MX-1-GP IN#4 NC#16 SC22P50V2JN-4GP IN#5 PC8625 PC8626 OPS OPS OPS OPS PWR_1D35V_EN 11 EN GND SC22U6D3V3MX-1-DL-GP 21DY PC8607 PWR_0D95V_FB 21 1 BS GND SCD1U16V2KX-3GP 21 PWR_1D35V_BOOT 9 PG GND SC22U6D3V3MX-1-DL-GP R25P1RK816R223F-GPOPS ILMT GND PWR_1D35V_FB_A PWR_1D35V_PG 13 FB SC22U6D3V3MX-1-DL-GP PWR_1V35V_ILMT 14 SC22U6D3V3MX-1-DL-GP 21 PWR_1D35V_FB SC22U6D3V3MX-1-DL-GP SY8286RAC-GP PC8662 21 PR8675 2 12 1 PR8673 074.08286.0B43 SC470P50V2KX-L-GP OPS OPS 24K9R2F-L-GP 100KR2J-1-GP 1OPS 2 3D3V_S5 VOUT=0.6*(1+(R1/R2)) Close Pin1 B PR8676 Vo=0.6x(1+R1/R2) =0.6x(1+30.1/51.1) OPS 16K5R2F-2-GP =0.953 PG8655 PR8677 1 DY 2 PWR_1D35V_VCC 3D3V_S5 0R2J-2-GP 0D95V_VGA_S0_PG GAP-CLOSE-PWR-3-GP PR8624 1 2 10KR2J-L-GP 21 D8601 21 0D95V_VGA_EN_R 2 OPS PR8671 OPS 3 3.3V_RUN_VGA_1 0D95V_VGA_S0_PG 0R0402-PAD-1-GP 1 2015/02/09 modify 1MR2J-1-GP 1D8V_VGA_EN PR8672 EN rating 23V OPS D8602 BAT54C-12-GP 21 EN Rising Threshold : 0.8V 2 ILIM LOW , ILIM=6.5A [85] EN/DEM_VGA 75.00054.A7D ILIM FLOAT , ILIM=9.5A PWR_1D35V_EN OPS 3 3.3V_RUN_VGA_1 ILIM HIGH , ILIM=12.5A 1 BAT54C-12-GP 75.00054.A7D For power down sequence 2015/02/09 modify AA <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title GPU Discrete Power Size Document Number Rev Vegas SKL/KBL-U Custom A00 Date: Wednesday, November 08, 2017 Sheet 86 of 105 54321

5 4 32 1 Main Func = UnusedParts H6 H11 H16 H17 HOLE335R178-GP HT85BE95R29-U-5-GP HOLE384X421R115-GP H1 H2 H3 H4 H5 H7 H8 H9 H10 HT85B85X925R29-S-GP H12 H13 H14 H15 HOLE335R178-GP HOLE335R178-GP HOLE335R178-GP HOLE335R178-GP HOLE335R178-GP HOLE335R178-GP HOLE335R178-GP HOLE335R115-GP HT85B85X925R29-S-GPHOLE276R91-GP HOLE335R115-GP HOLE335R115-GP HOLE335R115-GP 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Vinafix.comZZ.00PAD.7F1 ZZ.00PAD.7F1 ZZ.00PAD.7F1 ZZ.00PAD.7F1 ZZ.00PAD.7F1 ZZ.00PAD.7F1 ZZ.00PAD.7F1 ZZ.00PAD.7F1 ZZ.00PAD.D01 ZZ.00PAD.D01 ZZ.00PAD.D81 ZZ.00PAD.D01 ZZ.00PAD.D01 ZZ.00PAD.D81 ZZ.00PAD.CZ1 ZZ.00PAD.D31 ZZ.SCREW.681 D D 0502 Changed PN 0512 Deleted HS2 DCBATOUT 0927 Change acoustic solution C 1101 Change acoustic solution HS1 SPR1 SPR2 SPR3 SPR5 SPR4 STF237R128H128-3-GP SPRING-63-GP SPRING-63-GP SPRING-63-GP SPRING-63-GP SPRING-43-GP-U 1 1 1 1 1 1 21 21 DY PSTE83930U125VM-11-GOPPS PT8902 ST100U25VDM-1-GP Spring Spring Spring Spring Spring 34.4LO45.201 34.15J03.001 34.4Y806.001 34.4Y806.001 34.4Y806.001 34.4Y806.001 2nd = 34.4LO45.301 For acoustic noice Main Func = EMI & RF Capacitors For RF solution DVT1 3/2 AUD_AGND 3D3V_S0 5V_S0 +VCCGT 1D35V_VGA_S0 VGA_CORE DY DY DY DY DY DY DY DY DY EC9753 EC9752 EC9751 EC9750 EC9746 SC1KP50V2KX-L-1-GP EC9745 EC9743 EC9744 EC9739 EC9731 EC9729 EC9728 EC9730 EC9726 EC9725 EC9727 FC9708 FC9707 FC9706 SCD1U25V2KX-GP FC9704 FC9703 FC9702 EC9710 EC9709 EC9708 EC9707 EC9706 EC9705 EC9704 EC9703 EC9702 EC9701 Mind the voltage rating of the caps. C DCBATOUT 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 DY DY DY DY DY DY DY DY DY DY DY DY DY DY DY DY SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP SCD1U25V2KX-GP SCD1U25V2KX-GP SC1U10V2KX-1GP SCD1U25V2KX-GP SCD1U25V2KX-GP SC1KP50V2KX-L-1-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SC1KP50V2KX-L-1-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SC1KP50V2KX-L-1-GP SCD1U25V2KX-GP 0921 Uninstall 1D2V_S3 3D3V_S5 DY DY EC9714 0921 Uninstall 0921 Install EC9711 DY DY EC9717 EC9716 EC9715 EC9713 EC9712 21 EC8909 EC8928 21 EC8908 EC8927 21 EC8907 EC8926 21 EC8906 EC8925 21 EC8905 EC8924 21 EC8904 EC8923 21 EC8903 EC8922 EC8902 EC8921 EC8901 EC8920 21 EC8919 21 EC8918 21 EC8917 21 EC8916 21 21 21 21 21 21 21 21 21 21 DY DY DY 21 21 21 21 21 21 21 21 B SCD1U25V2KX-GP SCD1U25V2KX-GP SC1KP50V2KX-L-1-GP B SCD1U25V2KX-GP SCD1U25V2KX-GP SC1KP50V2KX-L-1-GP SCD1U25V2KX-GP 5V_S0 SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP EC8915 EC8914 EC8913 EC8912 EC8911 EC8910 EC9724 21 EC9723 21 EC9722 21 EC9721 21 21 EC9720 21 EC9719 DY DY EC9718 21 21 21 21 21 21 21 DY DY SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP 3D3V_S0 DCBATOUT 5V_S5 A DY DY DY SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP 5 4 EC9748 <Core Design> A EC9740 EC9749 EC9747 EC9742 EC9741 EC9734 EC9733 EC9732 EC9738 EC9737 EC9736 EC9735 21 21 21 21 21 21 21 12 21 12 12 21 21 DY Wistron Corporation SC1KP50V2KX-L-1-GP 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, SC1KP50V2KX-L-1-GP Taipei Hsien 221, Taiwan, R.O.C. 3 Title Rev UNUSED PARTS/EMI Capacitors A00 Size Document Number 105 A3 Vegas SKL/KBL-U Date: W ednesday, November 08, 2017 Sheet 89 of 21

54321 SSID = TPM ??? RTC Gen9 power 3D3V_S5 R1 3D3V_TPM R9149 1TPM_652x Vinafix.com 0R2J-2-GP SCD1U16V2KX-3GP C9116 SC2200P50V2KX-2GP C9115 SC2200P50V2KX-2GP C9114 D 3D3V_S0 21 21 21 DY DY TPM D R9150 1 2 0R0402-PAD-2-GP 05R232Change to 0402 0920 Change to Pad 3D3V_S0 3D3V_S5 TPM IC Mounted Unmounted 0R0402-PAD-2-GP C9109R9145 3D3V_TPM R109K1R402J1T-LP-GMP 2 NPC65x R1 R2 21 2 1 DY R91460R2J-L-GP SCD1U16V2KX-3GP 21 2 1 NPC75x R2 [18] SPI_CS_ROM_N2 R9130 1 2 0R0402-PAD SPI_CS2#_R_TPM2 R1 [18,25] SPI_SO_ROM R9132 TTTPPP111 MMM 2 33R2J-2-GP SPI_SO_ROM_TPM2 C R9133 2 33R2J-2-GP SPI_SI_ROM_TPM2 C [18,25] SPI_SI_ROM R9138 2 33R2J-2-GP SPI_CLK_ROM_TPM2 [18,25] SPI_CLK_ROM SC4D7U6D3V3KX-GP C9112 modify 0.1u->4.7uTPM TPM 20160627(DVT1) modify from 3D3V_S5_PCH to 3D3V_S5 3D3V_S0 20160909(DVT2) U9103 +UZ12_TPM 8 VDD SDA/GPIO0 29 TPM_GPIO0 1R09K1R212J1T-LP-GMP 2 TPM_VDD14 GPIO1/SCL 30 TPM_GPIO2 R109K1R202J1-L-DGYP 2 3D3V_S5 3D3V_TPM_1 14 VHIO GPX/GPIO2 3 TPM_GPIO4 2RK921R222J1-L1D-GYP 2 SPI_CS2#_R_TPM2 22 VHIO GPIO3/BADD 6 CLKRUN#/GPIO4/SINT# 13 R9143 1 2 R9144 1 2 TPM_VSB 1 VSB RESERVED#12 12 0R0402-PAD-2-GP SCD1U16V2KX-3GP 0R0402-PAD-2-GP C9108 TPM21 SC4D7U6D3V3KX-GP TPM SPI_SO_ROM_TPM2 24 LAD0/MISO NC#2 2 21C9106 SPI_SI_ROM_TPM2 21 LAD1/MOSI NC#7 7 B PIRQA# R9152 1 2 SPI_IRQ#_TPM2 18 LAD2/SPI_IRQ# TPM NC#10 10 B PLT_RST# 15 LAD3 NC#11 11 0R0402-PAD-2-GP NC#25 25 NC#26 26 R9136 1 2 PLT_RST#_Q_TPM2 17 LRESET#/SPI_RST#/SRESET# NC#31 31 SPI_CLK_ROM_TPM2 19 LCLK/SCLK 0R0402-PAD-2-GP SPI_CS2#_R_TPM2 20 LFRAME#/SCS# SERIRQ_TPM 27 SERIRQ 28 LPCPD# 3D3V_TPM 21 GND 9 GND 16 R9147 1 2 TPM_VDD14 TPM R9141 4 GND 23 0512 Deleted C9110 10KR2J-L-GP 5 GND 32 0R0402-PAD-2-GP 0523 Modify C9113 PP GND 33 TEST SC4D7U6D3V3KX-GP TPM C9113 TPM SCD1U16V2KX-3GP C9111 TPM_65x SCD1U16V2KX-3GP C9107 21 NPCT750JAAYX-GP <Core Design> 21 21 071.00750.0003 A Wistron Corporation A [17,31,55,61,63,76] PLT_RST# 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, [16] PIRQA# Taipei Hsien 221, Taiwan, R.O.C. 5 Title Size Document Number TPM Rev A4 Vegas SKL/KBL-U A00 Date: Wednesday, November 08, 2017 Sheet 91 of 105 4 321

54321 SSID = Finger Print Vinafix.com [16] USB_CPU_PN8 R9203 1 2 0R0402-PAD-2-GP USB_PN8_C D D [16] USB_CPU_PP8 R9204 1 2 0R0402-PAD-2-GP USB_PP8_C 3D3V_S0 0524 Follow new FPR pin define FPR1 8 6 21 2 1 0R0402-PAD-2-GP C9202R9202 5 21 USB_PP8_C 4 USB_PN8_C 3 FPR 2 C FP_PWR 1 C 7 FPR SC1U10V2KX-1GP FPR SCD1U16V2KX-3GP HRS-CON6-15-GP C9201 020.K0237.0006 2nd = 020.K0002.0006 For EMI Reserved 1 USB_PP8_C 1 USB_PN8_C ED9201 USB_PP8_C 1 I/O1 I/O4 6 USB_PN8_C 3D3V_S0 B SC22P50V2JN-4GP 2 GND DYVDD 5 B EC9202 3 4 DY DY SC22P50V2JN-4GP I/O2 I/O3 EC9201 2 2 AZC099-04S-2-GP 075.09904.0A7C Layout Note: close to FPR1 AFTE14P-GP AFTP8902 1 FP_PWR <Core Design> AFTE14P-GP AFTP8903 1 USB_PN8_C AFTE14P-GP AFTP8904 1 USB_PP8_C A Wistron Corporation A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Finger Print Size Document Number Rev A4 Vegas SKL/KBL-U A00 Date: Wednesday, November 08, 2017 Sheet 92 of 102 54 321

5 4 3 21 D D Vinafix.com PCH_JTAG_TMS test point XDP_TMS test point test point PCH_JTAG_TDI test point XDP_TDI XDP_TCLK C XDP_TCK_JTAGX XDP_TDO_CPU PCH_JTAG_TDO C B B <Core Design> A Wistron Corporation A 543 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Debug (XDP debug) Size Document Number Rev A4 Vegas SKL/KBL-U Date: Wednesday, November 08, 2017 Sheet 99 of A00 1 105 2

54321 CLK Block Diagram Vinafix.com Intel CPU KBL-R D M_A_CLK0 D C CK0_T DDR0_CKP[0] B DDR4 DIMM1 CK0_C M_A_CLK0# DDR0_CKN[0] CK1_T M_A_CLK1 DDR0_CKP[1] CK1_C M_A_CLK1# DDR0_CKN[1] CK0_T M_B_CLK0 DDR1_CKP[0] CLKOUT_PCIE_P1 PEG_CLK1_CPU REFCLKP0 WLAN M_B_CLK0# DDR1_CKN[0] CLKOUT_PCIE_N1 PEG_CLK1_CPU# REFCLKN0 NGFF DIMM2 CK0_C DDR4 M_B_CLK1 DDR1_CKP[1] CK1_T M_B_CLK1# DDR1_CKN[1] CK1_C LAN RTL8106E/RTL8111G CLKOUT_PCIE_P2 PEG_CLK2_CPU REFCLK_P C CK CLKA0 CLKOUT_PCIE_N2 PEG_CLK2_CPU# REFCLK_N CK# CLKA0b VRAM1 GPU AMD R17-M1-30 LANXIN CKXTAL1 VRAM2 CK CLKA0 ‧ CLKA0 PEX_REFCLK# PEG_CLK_CPU# CLKOUT_PCIE_N0 X3001 CK# CLKA0b ‧ CLKA0# PEX_REFCLK PEG_CLK_CPU CLKOUT_PCIE_P0 25MHz LANXOUT CKXTAL2 VRAM3 CK CLKA1 XTAL_IN 27MHZ_IN CK# CLKA1b X7901 HDA_BITCLK / Audio 27MHz HDA_BCLK/I2S0_SCLK HDA_CODEC_BITCLK Realtek ALC3223 VRAM4 CK CLKA1 ‧ CLKA1 XTAL_OUT 27MHZ_OUT 2R22R7223J HDA_BITCLK_CODEC_R BIT-CLK CK# CLKA1b ‧ CLKA1# B KBC MEC1416-NU-D0-GP RTC_X1 RTCX1 GPP_A9/CLKOUT_LPC0/ESPI_CLK ESPI_CLK_CPU ESPI_CLK GPIO034/PCI_CLK/ESPI_CLK X1901 1R15R820F4 32.768KHz RTC_X2 RTCX2 XTAL24_IN XTAL24_IN X1801 24MHz XTAL24_OUT XTAL24_OUT AA <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title CLK Block Diagram Size Document Number Rev A2 Vegas SKL/KBL-U A00 Date: Wednesday, November 08, 2017 Sheet 100 of 105 54321

5 4 3 2 1 D Change notes - Page Modify List OWNER DATE VERSON DATE Vinafix.com D C C B B <Core Design> A A 543 Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Change History Size Document Number Rev A3 Vegas SKL/KBL-U A00 Date: W ednesday, November 08, 2017 Sheet 101 of 105 21

5 43 2 1 D KBL-U/Y Timing Diagram for G3 to S0/M0 [Non Deep Sx Platform] POWER UP SEQUENCE DIAGRAM (NON Deep Sx Platform) D Red: Power Rail abcde fghi Orange: Output from KBC Light Blue: Output from CPU 1 2 3a 4 4a 4b 5 6 7 8 8a 8b 9 10 DC BT+ SI7121DN-T1-GE3 d Page43 a Battery Page43 3V_5V_EN Page43 V8P10-5300M3-86A Vinafix.com AC +DC_IN AON7403 a Adapter in Page43 Page43 AD+ EN1 EN2 e Charger 3D3V_S5 ISL88739 DCBATOUT VIN TPS51225RUKR ACOK Page44 DC/DC (3.3V/5V) 5V_S5 35 b PWR_CHG_ACOK Page45 DDR_VTT_PG_CTRL Level SM_PGCNTL_R PR4474 Page44 3D3V_AUX_S5 f Shifter d R2446 3V_5V_POK Page24 3V_5V_EN Delay 10ms SIO_SLP_S4# R4009 SIO_SLP_S3# c ALWON SLP_S4# SLP_S3# DDR_PG_CTL KBC_PWRBTN# VCI_OUT/ GPIO34 DPWROK GPIO036 1 VCI_IN0#/ GPIO163 GPIO66 PCH_RSMRST# The DSW rails must be stable for at least PM_RSMRST# 10 ms before DSW_PWROK is asserted to PCH. f DSW_PWROK SIO_PWRBTN# ACOK_IN b VCI_OVRD_IN/ GPIO20 RSMRST# KBL-R GPIO164 h RSMRST_PWRGD# TBD KBC 2 PWRBTN# MEC1416 ALL_SYS_PWRGD and VR_RDY assert, GPIO36 delay 10ms; PCH_PWROK assert. GPIO57 RSMRST#_KBC: Delay 10 ms after receive AND 8b RSMRST_PWRGD# and PM_SLP_SUS#. RESET_OUT# SIO_SLP_S0# RSMRST#_KBC PM_SUSWARN# 10 PCH_PLTRST# GPIO107 PCH_PWROK SLP_S0# GPIO02 SUSWARN# ALL_SYS_PWRGD assert, 9 delay 10ms; PCH_PWROK assert. PROCPWRGD 7 ALL_SYS_PWRGD GPIO81 i SUSACK# PLTRST# It is recommended that SYS_PWROK be asserted after AND both PWROK assertion and processor core VR PWRGD assertion. C PM_SLP_S4# GPIO44 8d H_VCCST_PWRGD Level Shifter ALL_SYS_PWRGD C GPIO01 3 VCCST_PWRGD PM_SLP_S3# 4 8c SYS_PWROK 74LVC1G07GW Page17 GPIO141 SYS_PWROK Page24 ALL_SYS_PWRGD assert, EXT_PWR_GATE# 6 PWR_VDDQ_PG 7 delay 100ms; SYS_PWROK assert. EXT_PWR_GATE# e RSMRST_PWRGD# ALL_SYS_PWRGD SLP_SUS# h DY 3D3V_S5 SVID Transanctions DS3 SIO_SLP_SUS# IMVP8 PCH_ALW_ON Vin 3D3V_S5_PCH 6 PWR_VDDQ_PG CPU SVID Rails SA/Core/GT/GTx EN SW VR_RDY VR_ON SY6288C10CAC VR_READY (DS3) Page41 8a PWR_DCBATOUT_1D0V 1D0V_S5 VIN 1D0V_PWR Vin 3V_5V_POK 0R 0402 RSMRST_PWRGD# 3V_5V_POK LX 1D0V_S5_PWRGD 5 SIO_SLP_S3# APE8939GN3 +VCCIO +VCCSTG EN 0R 0402 f 0R 0402 h f EN AOZ2262QI g SW PGOOD g 1D8V_S5_PWROK DY0R 0402 Page53 Page40 1D0V_S5_PWRGD 1D0V_PWR VCCPRIM_CORE 0R g 5V_S5 3D3V_S5 1D0V_S5 5V_S5 3D3V_S5 5V_S5 Vin1 Vin2 3 Vin VDD 4 AP22966DC85 SIO_SLP_S3# EN VOut1 5V_S0 VOut2 3D3V_S0 Vin VCNTL SIO_SLP_S4# 3V_5V_POK EN SW +V1.00U_CPU(VCCST) EN Vout 1D8V_S5 f APE8939GN3 Page40 APL5930KAI 1D8V_S5_PWROK PGOOD Page40 Page54 g B B 1D8V_S5 0R +V1.8A_SIP 3D3V_S5 3 Vin 4a LX SIO_SLP_S4# 2D5V_S3 EN PWR_2D5V_PG APL5930KAI PGOOD 4b Page54 AMD GPU Power sequence For DDR4 power sequence 4b PWR_2D5V_PG S5 1D2V_S3 4c 3D3V_VGAS0 2D5V_S3 SIO_SLP_S3# RT8231AGQW 0D6V_S0 => 0D95V_VGA_S0/1D8V_VGA_S0 1D2V_S3 PWR_VDDQ_PG 0D6V_S0 5 S3 6 => 1D5V_VGA_S0 PGOOD Page51 20ms => VGA_CORE All the ASIC supplies must reach their respective nominal voltages withing of the start of the ramp-up sequence, though a shorter ramp-up duration is preferred. The maximum slew rate on all rails is 50mV/us. It is recommended that the 3.3V rail ramp up first. It is recommended that the 0.95V rail reach at least 90% of its normal value no later than 2ms from the start of VDDC ramping up. 3D3V_VGA_S0 0D95V_VGA_S0/ 1D8V_VGA_S0 1D5V_VGA_S0 VGA_CORE A A <Core Design> Wistron Corporation 21F, 88, Sec.1, Hs in Tai Wu Rd., Hs ichih, Taipei Hs ien 221, Taiwan, R.O.C. Title Rev A00 Power Sequence Size Docum ent Num ber A0 Vegas SKL/KBL-U Date: Wednes day, Novem ber 08, 2017 Sheet 102 of 105 543 2 1

5432 1 Adapter DCBATOUT 3V_5V_POK D Battery RT8231AGQW EN(S5) 2D5V_PWROK EN/DEM_VGA 0D95V_VGA_S0_PG VR_EN AOZ2262QI-10 EN C EN(S3) EN SM_PGCNTL EN EN ISL95859AHRTZ 53 B Vina5fi1 x.com 46 ISL62771HRTZ SY8288RAC-GP 86 86 Charger CSD97396Q4M 48 CSD97396Q4M 47 ISL95808HRZ 50 ISL88739HRZ VGA_CORE 1D35V_VGA_S0 D C BT+ 44 0D6V_S0 1D2V_S3 B +VCCSA +VCCGT VCC_CORE 0 ohm 0 ohm 0 ohm 3V_5V_EN +VDDQ_CPU_CLK GTX_CORE GT_CORE EN TPS51225RUKR 45 5V_S5 3D3V_S5 USB_PWR_EN# PM_SLP_S3# PM_SLP_S3# SIO_SLP_S4# 3V_5V_POK 3D3V_VGA_S0 PM_LAN_ENABLE EN EN SY6288DAAC x2 EN EN EN EN EN 0 ohm AP22966DC8 40 DMP2130L 35 APL5930KAI APL5930KAI SYW232DFC 86 31 51 54 3D3V_LAN_S5 USB20_VCCA 5V_S0 3D3V_S0 2D5V_S3 1D8V_S5 0D95V_VGA_S0 3D3V_S5_PCH 1D0V_S5 USB30_VCCC 3D3V_S5_KBC 0 ohm 0 ohm 0 ohm +VCCPDSW_3P3 ODD_PWR_5V DGPU_PWR_EN 3D3V_VGA_S0 TPAN_VDD 5V_HDMI_S0 RT9724GB 55 EN PJA3419 86 EN 5V_HDD_S0 +5V_AVDD DMP2130L 86 +5V_PVDD LCDVDD 3D3V_VGA_S0 +3V_1D8V_DVDD +V1.8A_SIP 1D8V_VGA_S0 APE8939GN3 40 VDD_DAC_33 AVCC33 +V1.00U_CPU 0 ohm APE8939GN3 0 ohm 3D3V_WLAN_S0 3D3V_CAMERA_S0 0 ohm +VCCPRIM_CORE 41 42 +VCCIO +V1.00A_SIP +VCCST_CPU 0 ohm 0 ohm 0 ohm +VCCSTG +VCCAPLL_1P0 +VCCMPHYGTAON_1P0_LS_SIP +VCCAMPHYPLL_1P0 AA <Core Design> Power Shape Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Regulator LDO Switch Title Power Block Diagram Size Document Number Rev Custom Vegas SKL/KBL-U A00 Date: Wednesday, November 08, 2017 Sheet 103 of 105 54321

AB C DE PCH SMBus Block Diagram 3D3V_S0 KBC SMBus Block Diagram 3D3V_S5_PCH 1 ‧ TP_VDD 2 ‧ Vinafi3Dx3V._cS0om SRN10KJ-5-GP ‧ SRN2K2J-1-GP ‧ SMBus Address:0xA0/0xA1 DIMM 1 SRN10KJ-5-GP 1 2 GPP_C0/SMBCLK MEM_SMBCLK ‧ ‧PCH_SMBCLK SCL TouchPad Conn. 3 GPP_C1/SMBDATA ‧ PCH_SMBDATA SDA ‧MEM_SMBDATA GPIO114/PS2_CLK0 CLK_TP_SIO SRN33J TPCLK_C TPCLK GPIO115/PS2_DAT0 DAT_TP_SIO TPDATA_C TPDATA SMBus Address:0xA0/0xA1 ‧ ‧ DIMM 2 2N7002SPT 3D3V_AUX_KBC ‧PCH_SMBCLK SCL ‧ ‧ PCH_SMBDATA SDA 3D3V_S5_PCH TPAD SRN4K7J-8-GP ‧ ‧PCH_SMBCLK SCL GPIO010/SMB01_CLK/SMB01_CLK18 ‧ SMBCLK1 SRN100J PBAT_SMBCLK1 Battery Conn. ‧ PCH_SMBDATA SDA GPIO007/SMB01_DATA/SMB01_DATA18 ‧SMBDA1 PBAT_SMBDAT1 SRN2K2J-1-GP CLK_SMB DAT_SMB SMBus address:16 GPP_C3/SML0CLK SML0_SMBCLK ‧PCH_SMBCLK LNG2DMTR ISL88739 GPP_C4/SML0DATA SML0_SMBDATA ‧ PCH_SMBDATA SCL/SPC SCL SDA/SDI/SDO MEC1416 SDA SMBus address:12 0R2J PCH_SMBCLK RTD2166 0R2J PCH_SMBDATA SMBCLK2 SMB_SCL 3D3V_VGA_S0 SMBDA2 SMB_SDA(Janus Only) ‧ PCH 3D3V_VGA_S0 GPIO013/SMB02_CLK/SMB02_CLK18 GPIO012/SMB02_DATA/SMB02_DATA18 3D3V_S5_PCH SMBus Address: 0x94/0x95/0x96/0x97 SRN2K2J-8-GP SMBus Address:0x9E/0x9F ‧SRN4K7J-8-GP dGPU GPP_C6/SML1CLK ‧ ‧SML1_SMBCLK SMB_CLK_VGA ‧ SMBCLK SMB_DATA_VGA ‧ SMBDATA ‧ ‧3 GPP_C7/SML1DATA SML1_SMBDATA SMBus Address:0x82/0x83 SMBus Address:0x98/0x99 SCL Thermal GPU T8 SDL NCT7718W 3D3V_S0 5V_S0 ‧ 3D3V_S0 ‧ SRN2K2J-1-GP ‧ SRN2K2J-1-GP GPP_E18/DDPB_CTRLCLK ‧CPU_DP1_CTRL_CLK DDC_CLK_HDMI ‧ HDMI CONN GPP_E19/DDPB_CTRLDATA ‧CPU_DP1_CTRL_DATA ‧ ‧‧ DDC_DATA_HDMI 2N7002DW-1-GP 4 4 <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title SMBUS Block Diagram Rev VegasSize Document Number Custom SKL/KBL-U A00 Date: Wednesday, November 08, 2017 Sheet 104 of 105 ABCDE

ABCDE Thermal Block Diagram Audio Block Diagram 3D3V_S5_PCH 3VD3inV_aS0fix.com 1 Thermal 1 SPKR_L+ NCT7718 Codec SPKR_L- SPEAKER PCH EN 3V/5V SPKR_R- SPKR_R+ HP MIC SML1CLK/GPIO75 ALC3204 COMBO SML1DATA/GPIO74 ‧SML1_CLK ‧SMB_CLK_VGA_R SCL PURE_HW_SHUTDOWN# ‧SML1_DATA ‧ SMB_DATA_VGA_R SDA 2N7002 T_CRIT# GPU_T_CRIT# 2N7002 AUD_HP1_JACK_L AUD_HP1_JACK_R 0R2J SLEEVE RING2 0R2J SMBDA2 Put under CPU(T8 HW shutdown) SMBCLK2 DMIC_DATA_R R2714 GPIO012/SMB02_DATA/SMB02_DATA18 VGA GPIO0/DMIC-DATA12 DMIC_CLK_R DMIC_DATA R17M-M1-30 GPIO1/DMIC-CLK 2 SMBCLK 0R2J-2-GP HDMI 2 SMBDATA GPIO013/SMB02_CLK/SMB02_CLK18 R2716 DMIC_CLK KBC 0R2J-2-GP MEC1416 GPIO056/PWM3 GPIO050/TACH0 FAN1_DAC_1 TACH FAN_TACH1 FAN 3 3 VIN 5V FAN_VCC1 VIN VSET VOUT FAN CONTROL <Core Design> APL5606AKI 4 Wistron Corporation 4 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Thermal/Audio Block Diagram Size Document Number Rev Custom Vegas SKL/KBL-U A00 Date: Wednesday, November 08, 2017 Sheet 105 of 105 ABCDE