BCA 111 DCLD

Combinational Logic Circuits 143 6.5.2 Four-bit Ripple Carry Adder To add 4-bit binary numbers, 4 full adders have to be used. Each full adder inputs a Cin, which is the Cout of the previous adder. This kind of adder is a Ripple Carry Adder, since each carry bit “ripples” to the next full adder. Only the first full adder can be replaced by a half adder. The block diagram of 4-bit Ripple Carry Adder is shown below. Block Diagram B3 A3 B2 A2 B1 A1 B4 A4 Final ba ba ba ba C2 carry C4 Full Adder C3 Full Adder C2 Full Adder Full Adder Input C5 Cc C C C carry S S S S S4 S3 S2 S1 Fig. 9.23: The 4-bit Ripple Adder C4 C3 C2 C1 + A4 A3 A2 A1 C5 B4 B3 B2 B1 S4 S3 S2 S1 The layout of ripple carry adder is simple, which allows for fast design time; however, the ripple carry adder is relatively slow, since each full adder must wait for the carry bit to be calculated from the previous full adder. 6.5.3 BCD Adder The BCD adder is used to add 2 BCD numbers. The BCD numbers can be added as simple binary addition as long as the decimal sum is 9 or less than 9. However, when this sum exceeds 9, the sum becomes invalid. To obtain correct sum, we will have to add 6 (0110) to incorrect sum. CU IDOL SELF LEARNING MATERIAL (SLM)

144 Digital Circuits and Logic Designs Circuit Diagram C4 =Y A4 A3 A2 A1 B4 B3 B2 B1 CE = 0 1 3 8 10 16 4 7 11 VCC GND IC7483 S4 S3 S3 S3 7408N 7432N 7432N 7408N A4 A3 A2 A1 B4 B3 B2 B1 Carry 1 3 8 10 16 4 7 11 CE = 0 ignored IC7483 VCC GND 15 2 6 9 S4 S3 S2 S1 Fig. 9.24: BCD Adder Te above diagram shows 4-bit BCD adder that adds two BCD codes A4A3A2A1 and B4B3B2B1 to produce BCD output S4S3S2S1. The upper IC 7483 add the input bits as usual and produce the output sum as C4S4S3S2S1 which can be correct or incorrect depending on the sum. The OR gate is used to find if the sum exceeds 9 or not. If the output of OR gate is 1, then it means that the sum is more than 9, and if the output is 0, then it means that the sum is less than or equal to 9. The lower IC 7483 is used to add 0110 (6) to incorrect sum when the output of OR gate is 1. For example: To add 2 BCD numbers 0111 (7) and 0101 (5) If we add decimal number 7 + 5 = 12 > 9, hence incorrect BCD output. Therefore, 610 has to be added to it to make it valid. The following operation is carried out by the above circuit in the following manner: CU IDOL SELF LEARNING MATERIAL (SLM)

Combinational Logic Circuits 145 The upper four gates produce the following output: A3 A2 A1 A0 = 0111 + B3 B2 B1 B0 = 0101 C S3 S2 S1 S0 = 1100 = 12 Hence, it is invalid output. Since the output of the OR gate is equal to 1, it indicates that the sum is invalid. Therefore, 0110 gets added to the invalid sum to create a valid BCD output. Therefore, the correct output is S4S3S2S1 = 1100 + 0110 = 10010 = 0001 0010 (1210). 6.5.4 Excess-3 Adder The Excess-3 adder is used to add 2 Excess-3 numbers. Two excess-3 numbers are first added using the basic laws of binary addition. If carry is generated, then 0011 (310) is added to the sum, and if carry is not generated, then 0011 (310) is subtracted from the sum. The result obtained after this operation is in Excess-3 form. x3x2x1x0 y3y2y1y0 C4 Binary Adder Co = 0 S3S2S1S0 1 0 00 C4 Binary Adder Co = 0 not used Result Digit 1 Result Digit 0 Fig. 9.25: Excess-3 Adder Note: Above diagram is to be added. We forgot to add it. CU IDOL SELF LEARNING MATERIAL (SLM)

146 Digital Circuits and Logic Designs The above diagram shows 4-bit Excess-3 adder that adds two Excess-3 codes A4A3A2A1 and B4B3B2B1 to produce Excess-3 output S4S3S2S1. The upper IC 7483 add the input bits as usual and produce the output sum as Cout S4S3S2S1. If carry is present, then the lower IC 7483 adds 0011 to the above sum, and if carry is absent, then 0011 is subtracted from the sum. The subtraction is carried by using 2’s compliment subtraction method. 2’s compliment of 0011, i.e., 1101 is added to the sum to produce final excess-3. For example: To add 2 excess-3 numbers 0111 (7) and 0101 (5) If we add excess-3 numbers 710 + 510, carry is generated. Therefore, 310 has to be added to it to get excess-3 equivalent. The following operation is carried out by the above circuit in the following manner: The upper four gates produce the following output: A3 A2 A1 A0 = 1010 (710 in excess-3 is 7 + 3 = 1010 = 1010) + B3 B2 B1 B0 = 1000 (510 in excess-3 is 5 + 3 = 810 = 1000) C S3 S2 S1 S0 = 10010 This output is connected to B4B3B2B1 of lower IC 7482. The carry output is connected to A1, compliment of carry is connected to A3, A2 and Vcc to A0. Thus, when carry is 1, 0011 gets added to the sum. Therefore, the excess output is S4S3S2S1 = 0010 + 0011 = 0101. Similarly, to add 2 excess-3 numbers 0100 (4) and 0011 (3). If we add excess-3 numbers 410 + 310, no carry is generated. Therefore, 310 has to be subtracted from it to get excess-3 equivalent. The following operation is carried out by the above circuit in the following manner: The upper four gates produce the following output: A3 A2 A1 A0 = 0111 (410 in excess-3 is 4 + 3 = 710 = 0111) + B3 B2 B1 B0 = 0110 (310 in excess-3 is 3 + 3 = 610 = 0110) C S3 S2 S1 S0 = 1101 CU IDOL SELF LEARNING MATERIAL (SLM)

Combinational Logic Circuits 147 This output is connected to B4B3B2B1 of lower IC 7482. The carry output is connected to A1, compliment of carry is connected to A3, A2 and Vcc to A0. Thus, when carry is 0, 1101 gets added to the sum Therefore, the excess output is S4S3S2S1 9.7 Subtractor A Binary Subtractor is a decision making circuit that subtracts two binary numbers from each other, for example, X (minuend) – Y (subtrahend) to find the resulting difference between the two numbers. The binary subtractor produces a DIFFERENCE, ‘D’ by using a BORROW bit, ‘B’ from the previous column. The subtraction of one binary number from another is exactly same as subtracting two decimal numbers, but as the binary number system is a Base-2 numbering system, it uses only “0” and “1”. Binary Subtraction can take many forms but the rules for subtraction are the same whichever process we use. As binary notation only has two digits, subtracting a “0” from a “0” or a “1” leaves the result unchanged as 0 – 0 = 0 and 1 – 0 = 1. Subtracting a “1” from a “1” results in a “0”, but subtracting a “1” from a “0” requires a borrow. In other words, 0 – 1 requires a borrow. Subtractor circuits are of two types: Half subtractor and Full subtractor. 1. Half Subtractor: A half subtractor is a logical circuit that performs a subtraction operation on two binary digits. The half subtractor produces a difference (D) and a borrow bit (B) for the next stage. If X and Y are the input bits, then difference bit (D) is the X-OR of X and Y and the borrow bit (B) will be the AND of compliment of X and Y. Thus, a half subtractor circuit can be easily constructed using one X-OR gate, one NOT gate and one AND gate. The truth table, schematic representation and circuit diagram of a half subtractor are shown in the figure below. CU IDOL SELF LEARNING MATERIAL (SLM)

148 Digital Circuits and Logic Designs Circuit Diagram D X Y B Fig. 9.26: Half Subtractor Table 9.11: Truth Table Input Output X Y Difference (D) Borrow (B) 00 0 0 01 1 1 10 1 0 11 0 0 dsd Half D=A–B Boolean Equation Subtractor B0 Symbol Difference – D = A X  Y X  YX  YYX B Borrow – B = X  Y Fig. 9.27: Symbol of Half Subtractor Disadvantage of the Half Subtractor circuit is that when used as a binary subtractor, there is no provision for a “Borrow-in” from the previous circuit when subtracting multiple data bits from each other. Then we need to use a “full binary subtractor” circuit to take borrow-in input from the previous circuit. 2. Full Subtractor: This type of subtractor is a little more difficult to implement than a half subtractor. The main difference between a half subtractor and a full subtractor is that the full CU IDOL SELF LEARNING MATERIAL (SLM)

Combinational Logic Circuits 149 subtractor has three inputs and two outputs. The first two inputs are X and Y and the third input is a borrow designated as Bin. Thus, the combinational circuit of a “ full subtractor ” performs the operation of subtraction on three binary bits producing outputs for the difference D and borrow Bout. Just like the binary adder circuit, the full subtractor can be constructed by connecting two half subtractors together, with the first half subtractor passing its borrow to the second half subtractor as follows: Logic Diagram Half Subtractor XY Half Subtractor (XY)Bin Diff. X DIFF. (XY) Bin(XY) BOUT DIFF. HS X.Y HS >1 Y BORROW BORROW BIN Fig. 9.28: Logic Diagram Full Subtractor Circuit Diagram X (X Y) DIFF =1 Y =1 BIN X (X Y).BIN & & X Y BOUT >1 Fig. 9.29: Full Subtractor Table 9.12: Truth Table Input Output Bin Y X Difference (D) Borrow (Bout) 0 00 0 0 CU IDOL SELF LEARNING MATERIAL (SLM)

150 Digital Circuits and Logic Designs 0 01 1 0 0 10 1 1 0 11 0 0 1 00 1 1 1 01 0 0 1 10 0 1 1 11 1 1 Boolean Equation Difference – D = X  Y  Bin  Borrow – Bout = X  Y  X  Y Bin Symbol X DIFFERENCE Y D BIN BORROW OUTPUTS Inputs OUT BOUT Fig. 9.30: Symbol of Full Subtractor 3. N-bit Binary Subtractor: As with the binary adder, we can also have n number of 1-bit full binary subtractor connected or “cascaded ” together to subtract two parallel n-bit numbers from each other. For example, two 4-bit binary numbers. As said before that the only difference between a full adder and a full subtractor was the inversion of one of the inputs. So, by using an n-bit adder and n number of inverters (NOT Gates), the process of subtraction becomes an addition as we can use two’s complement notation on all the bits in the subtrahend and set the carry input of the least significant bit to a logic “1” (HIGH). Four-bit Parallel Subtractor To perform the subtraction of binary numbers with more than one bit is performed through the parallel subtractors. This parallel subtractor can be designed in several ways, including combination of half and full subtractors, all full subtractors, all full adders with subtrahend CU IDOL SELF LEARNING MATERIAL (SLM)

Combinational Logic Circuits 151 complement input, etc. The below figure shows a 4-bit parallel binary subtractor formed by connecting one half subtractor and three full subtractors. In this subtractor, 4-bit minuend A3A2A1A0 is subtracted by 4-bit subtrahend B3B2B1B0 and gives the difference output D3D2D1D0. The borrow output of each subtractor is connected as the borrow input to the next preceding subtractor. Circuit Diagram B2 A2 B1 A1 B0 A0 B3 A3 Cout Cin Cout Cin Cout Cin Cout Cin S3 S2 S1 S0 Fig. 9.31: Four-bit Parallel Subtractor It is also possible to design a 4-bit parallel subtractor 4 full adders as shown in the above figure. This circuit performs the subtraction operation by considering the principle that the addition of minuend and the complement of the subtrahend is equivalent to the subtraction process. The subtraction of A by B is obtained by taking 2’s complement of B and adding it to A. The 2’s complement of B is obtained by taking 1’s complement and adding 1 to the least significant pair of bits. Hence, in this circuit, 1’s complement of B is obtained with the inverters (NOT gate) and 1 can be added to the sum through the input carry. CU IDOL SELF LEARNING MATERIAL (SLM)

152 Digital Circuits and Logic Designs Examples: Q.1. Explain Full Adder using Half Adder. Solution: A full adder can also be constructed from two half adders and an OR gate, as shown in the diagram below. Consider the addition of A + B + Cin. This can be grouped as (A + B) + Cin where A + B represents the output of the half adder that receives A and B inputs. This partial sum is added to Cin by the other half adder, yielding the complete sum bit S. If any of the half adder logic produces a carry, there will be an output carry. Thus, Cout will be an OR function of the half adder Carry outputs. Logic Diagram A A C Cout HALF S B B ADDER S AC HALF Cin B ADDER S Fig. 9.32: Full Adder using Half Adder Circuit Diagram A BS Ci Co Fig. 9.33: Full Adder using Half Adder Circuit Diagram Boolean Equation S = A  B Cin Cout = ((AB). Cin) + (a. B) = ( A . B + A . B) . Cin + A . B CU IDOL SELF LEARNING MATERIAL (SLM)

Combinational Logic Circuits 153 = A . B. Cin + A. B . Cin + A . B = A . B. Cin + A . B . Cin + A. B ( 1 + Cin) = A . B . Cin + A . B . Cin + A. B + A . B. Cin = B . Cin ( A + A) + A . B . Cin + A. B = B. Cin+ A. B . Cin + A. B = B.Cin+ A. B . Cin + A. B (1 + Cin) = B. Cin + A. B .Cin + A. B + A. B. Cin = B. Cin + A . B + A. Cin (B+ B ) = B . Cin + A. B + A.Cin = A. B + A. Cin ++ B.Cin Q.2. Explain 2:1 Multiplexer. Solution: As the name suggests, the functioning D0 of this multiplexer is very clear. It will have 2 input D1 2:1 signals, 1 output signal and select line is calculated as 2 = 21, therefore 1 select line. The Strobe or Enable pin MUX (E) determines the operating condition of the E Multiplexer. If E = 1, the multiplexer is in the working condition. If E = 0, the multiplexer will not work. The S0 block diagram and truth table as given aside. Output (Y) ds 0 0 Enable (E) Select Input (m) D0 D1 00 01 10 11 CU IDOL SELF LEARNING MATERIAL (SLM)

154 Digital Circuits and Logic Designs S D1 D0 Q. 3. Combinational logic circuit Solution: Combinational logic circuits are made up from basic logic AND, OR or NOT gates that are “combined” or connected together to produce more complicated switching circuits. As combinational logic circuits are made up from individual logic gates, they can also be considered as “decision making circuits” and combinational logic is about combining logic gates together to process two or more signals in order to produce at least one output signal according to the logical function of each logic gate. Common combinational circuits made up from individual logic gates include Multiplexers, Decoders and Demultiplexers, Full and Half Adders, etc. Classification of Combinational Logic Combinational Logic Circuit Arithmetic and Data Code Logical Transmission Converters Functions Adders Multiplexers Binary Subtractors Demultiplexers BCD Encoders 7-Segment Comparators Decoders PLDs CU IDOL SELF LEARNING MATERIAL (SLM)

Combinational Logic Circuits 155 Q. 4. Excess-3 Adder The Excess-3 adder is used to add 2 excess-3 numbers. Two excess-3 numbers are first added using the basic laws of binary addition. If carry is generated, then 0011(310) is added to the sum and if carry is not generated then 0011(310) is subtracted from the sum. The result obtained after this operation is in Excess-3 form. Diagram shows 4-bit Excess-3 adder that adds two Excess-3 codes A4A3A2A1 and B4B3B2B1 to produce Excess-3 output S4S3S2S1. x3x2x1x0 y3y2y1y0 C4 Binary Adder Co = 0 S3S2S1S0 1 0 00 Binary Adder Co = 0 C4 not used Result Digit 1 Result Digit 0 Fig. 9.34: Excess-3 Adder The upper IC 7483 add the input bits as usual and produce the output sum as Cout S4S3S2S1. If carry is present, then the lower IC 7483 adds 0011 to the above sum, and if carry is absent, then 0011 is subtracted from the sum. The subtraction is carried by using 2’s compliment subtraction method. 2’s compliment of 0011, i.e., 1101 is added to the sum to produce final excess-3. For example: To add 2 excess-3 numbers 0111 (7) and 0101 (5) If we add excess-3 numbers 710 + 510, carry is generated. Therefore, 310 has to be added to it to get excess-3 equivalent. The following operation is carried out by the above circuit in the following manner: CU IDOL SELF LEARNING MATERIAL (SLM)

156 Digital Circuits and Logic Designs The upper four gates produce the following output: A3 A2 A1 A0 = 1010 (710 in excess-3 is 7 + 3 = 1010 = 1010) + B3 B2 B1 B0 = 1000 (510 in excess-3 is 5 + 3 = 810 = 1000) C S3 S2 S1 S0 = 10010 This output is connected to B4B3B2B1 of lower IC 7482. The carry output is connected to A1, compliment of carry is connected to A3, A2 and Vcc to A0. Thus, when carry is 1, 0011 gets added to the sum. Therefore, the excess output is S4S3S2S1 = 0010 + 0011 = 0101. Similarly, to add 2 excess-3 numbers 0100 (4) and 0011 (3). If we add excess-3 numbers 410 + 310, no carry is generated. Therefore, 310 has to be subtracted from it to get excess-3 equivalent. The following operation is carried out by the above circuit in the following manner: The upper four gates produce the following output: A3 A2 A1 A0 = 0111 (410 in excess-3 is 4 + 3 = 710 = 0111) + B3 B2 B1 B0 = 0110 (310 in excess-3 is 3 + 3 = 610 = 0110) C S3 S2 S1 S0 = 1101 This output is connected to B4B3B2B1 of lower IC 7482. The carry output is connected to A1, compliment of carry is connected to A3, A2 and Vcc to A0. Thus, when carry is 0, 1101 gets added to the sum. Therefore, the excess output is S4S3S2S1. 9.8 Summary In digital circuit theory, combinational logic sometimes also referred to as time-independent logic is a type of digital logic which is implemented by Boolean circuits, where the output is a pure function of the present input only. This is in contrast to sequential logic, in which the output depends not only on the present input but also on the history of the input. In other words, CU IDOL SELF LEARNING MATERIAL (SLM)

Combinational Logic Circuits 157 sequential logic has memory while combinational logic does not. Combinational logic is used in computer circuits to perform Boolean algebra on input signals and on stored data. Practical computer circuits normally contain a mixture of combinational and sequential logic. For example, the part of an arithmetic logic unit, or ALU, that does mathematical calculations is constructed using combinational logic. Other circuits used in computers, such as half adders, full adders, half subtractors, full subtractors, multiplexers, demultiplexers, encoders and decoders are also made by using combinational logic. Practical design of combinational logic systems may require consideration of the finite time required for practical logical elements to react to changes in their inputs. Where an output is the result of the combination of several different paths with differing numbers of switching elements, the output may momentarily change state before settling at the final state, as the changes propagate along different paths. 9.9 Key Words/Abbreviations  Multiplexers: MUX operates on several inputs but provide a single output.  Demultiplexers: DEMUX simply reverses the operation of MUX and operates on single input but transmits the data to multiple outputs.  Encoders: The encoder will convert the information from one format to another format, i.e., like electrical signals to counters.  Decoders: The decoder is a circuit used to change the code into a set of signals. 9.10 Learning Activity 1. What is combinational circuit? ----------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------- CU IDOL SELF LEARNING MATERIAL (SLM)

158 Digital Circuits and Logic Designs 2. What is difference between combinational and sequential circuit? ----------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------- 9.11 Unit End Questions (MCQ and Descriptive) A. Descriptive Type Questions 1. Define combinational circuits and sequential circuits. 2. Draw the block diagram of Multiplexer, Demultiplexer, Adder and Subtractor. 3. Explain functioning of Multiplexer, Demultiplexer, Adder and Subtractor. B. Multiple Choice/Objective Type Questions 1. Which of the following combinations of logic gates can decode binary 1101? (a) One 4-input AND gate (b) One 4-input AND gate, one inverter (c) One 4-input AND gate, one OR gate (d) One 4-input NAND gate, one inverter 2. What is the indication of a short to ground in the output of a driving gate? (a) Only the output of the defective gate is affected (b) There is a signal loss to all load gates (c) The node may be stuck in either the HIGH or the LOW state (d) The affected node will be stuck in the HIGH state 3. For the device shown here, assume the D input is LOW, both S inputs are LOW and the input is LOW. What is the status of the Y’ outputs? (a) All are HIGH (b) All are LOW (c) All but Y0 are LOW (d) All but Y0 are HIGH CU IDOL SELF LEARNING MATERIAL (SLM)

Combinational Logic Circuits 159 D Y0 Y1 S0 Y2 S1 Y3 EN 9. The carry propagation can be expressed as __________. (a) Cp = AB (b) Cp = A + B (c) All but Y0 are LOW (d) All but Y0 are HIGH Answers 1. (b), 2. (b), 3. (d), 4. (b), 5. (d) 9.12 References 1. https://www.electronics-tutorials.ws/combination/combhtml 2. https://www.watelectronics.com/different-types-encoder-decoder-applications/   CU IDOL SELF LEARNING MATERIAL (SLM)

UNIT 10 MICROPROCESSOR 1 Structure: 10.0 Learning Objectives 10.1 Introduction 10.2 Historical Background of Microprocessor and Application of Microprocessor 10.3 8085 Microprocessor Architecture 10.4 Pin Diagram of 8085 10.5 Summary 10.6 Key Words/Abbreviations 10.7 Learning Activity 10.8 Unit End Questions (MCQ and Descriptive) 10.9 References 10.0 Learning Objectives After studying this unit, you will be able to:  Define microprocessor  Draw the block diagram of microprocessor 8085  Explain functioning of different components of microprocessor 8085  Describe pin diagram of microprocessor 8085 CU IDOL SELF LEARNING MATERIAL (SLM)

Microprocessor 1 161 10.1 Introduction A microprocessor is a computer processor that incorporates the functions of a central processing unit on a single integrated circuit (IC) or sometimes up to 8 integrated circuits. The microprocessor is a multipurpose, clock driven, register based, digital integrated circuit that accepts binary data as input, processes it according to instructions stored in its memory and provides results (also in binary form) as output. Microprocessors contain both combinational logic and sequential digital logic. Microprocessors operate on numbers and symbols represented in the binary number system. Single-chip processors increase reliability because there are many fewer electrical connections that could fail. As microprocessor designs improve, the cost of manufacturing a chip (with smaller components built on a semiconductor chip the same size) generally stays the same according to Rock's law. Before microprocessors, small computers had been built using racks of circuit boards with many medium- and small-scale integrated circuits. Microprocessors combined this into one or a few large-scale ICs. Continued increase in microprocessor capacity have since rendered other forms of computers almost completely obsolete (see history of computing hardware), with one or more microprocessors used in everything from the smallest embedded systems and handheld devices to the largest mainframes and supercomputers. 10.2 Historical Background of Microprocessor and Application of Microprocessor (a) Historical Background of Microprocessor The advent of low-cost computers on integrated circuits has transformed modern society. General-purpose microprocessors in personal computers are used for computation, text editing, multimedia display, and communication over the Internet. Many more microprocessors are part of embedded systems, providing digital control over myriad objects from appliances to automobiles to cellular phones and industrial process control. The microprocessor has origins in the development of the MOSFET (metal-oxide- semiconductor field-effect transistor, or MOS transistor), which was first demonstrated by CU IDOL SELF LEARNING MATERIAL (SLM)

162 Digital Circuits and Logic Designs Mohamed M. Atalla and Dawon Kahng of Bell Labs in 1960. Following the development of MOS integrated circuit chips in the early 1960s, MOS chips reached higher transistor density and lower manufacturing costs than bipolar integrated circuits by 1964. MOS chips further increased in complexity at a rate predicted by Moore's law, leading to large-scale integration (LSI) with hundreds of transistors on a single MOS chip by the late 1960s. The application of MOS LSI chips computing was the basis for the first microprocessors, as engineers began recognizing that a complete computer processor could be contained on several MOS LSI chips. Designers in the late 1960s were striving to integrate the central processing unit (CPU) functions of a computer onto a handful of MOS LSI chips, called microprocessor unit (MPU) chipsets. In 1969, Lee Boysel, based on the 8-bit arithmetic logic units (3800/3804) he designed earlier at Fairchild, created the Four-Phase Systems Inc. AL-1, an 8-bit CPU slice that was expandable to 32-bits. In 1970, Steve Geller and Ray Holt of Garrett Ai Research designed the MP944 chipset to implement the F-14A Central Air Data Computer on six MOS chips fabricated by AMI. The Four-phase Systems AL and Garrett Ai Research MP944 were the first multi-chip microprocessors, developed with multiple MOS LSI chips. The first single-chip microprocessor was the Intel 4004, released on a single MOS LSI chip in 1971. The single-chip microprocessor was made possible with the development of MOS silicon-gate technology (SGT). The earliest MOS transistors had aluminium metal gates, which Italian engineer Federico Faggin replaced with silicon self-aligned gates to develop the first silicon-gate MOS chip at Fairchild Semiconductor in 1968. Faggin later joined Intel and used his silicon-gate MOS technology to develop the 4004, along with Marcian Hoff, Stanley Mazor and Masatoshi Shima in 1971. The 4004 was designed for Busicom, which had earlier proposed a multi-chip design in 1969, before Faggin’s team at Intel changed it into a new single-chip design. Intel introduced the first commercial microprocessor, the 4-bit Intel 4004, in 1971. It was soon followed by the 8-bit microprocessor Intel 8008 in 1972. The first microprocessors that emerged in the early 1970s were used for electronic calculators, using binary-coded decimal (BCD) arithmetic on 4-bit words. Other embedded uses of 4-bit and 8-bit microprocessors, such as terminals, printers, various kinds of automation etc., CU IDOL SELF LEARNING MATERIAL (SLM)

Microprocessor 1 163 followed soon after. Affordable 8-bit microprocessors with 16-bit addressing also led to the first general-purpose microcomputers from the mid-1970s on. The first use of the term “microprocessor” is attributed to Viatron Computer Systems describing the custom integrated circuit used in their System 21 small computer system announced in 1968. Since the early 1970s, the increase in capacity of microprocessors has followed Moore’s law; this originally suggested that the number of components that can be fitted onto a chip doubles every year. With present technology, it is actually every two years, and as a result Moore later changed the period to two years. A microprocessor is a computer processor that incorporates the functions of a central processing unit on a single integrated circuit (IC), or sometimes up to 8 integrated circuits. The microprocessor is a multipurpose, clock driven, register based, digital integrated circuit that accepts binary data as input, processes it according to instructions stored in its memory and provides results (also in binary form) as output. Microprocessors contain both combinational logic and sequential digital logic. Microprocessors operate on numbers and symbols represented in the binary number system. The integration of a whole CPU onto a single or a few integrated circuits greatly reduced the cost of processing power. Integrated circuit processors are produced in large numbers by highly automated metal-oxide-semiconductor (MOS) fabrication processes, resulting in a low unit price. Single-chip processors increase reliability because there are many fewer electrical connections that could fail. As microprocessor designs improve, the cost of manufacturing a chip (with smaller components built on a semiconductor chip the same size) generally stays the same according to Rock’s law. Before microprocessors, small computers had been built using racks of circuit boards with many medium- and small-scale integrated circuits. Microprocessors combined this into one or a few large-scale ICs. Continued increases in microprocessor capacity have since rendered other forms of computers almost completely obsolete (see history of computing hardware), with one or CU IDOL SELF LEARNING MATERIAL (SLM)

164 Digital Circuits and Logic Designs more microprocessors used in everything from the smallest embedded systems and handheld devices to the largest mainframes and supercomputers. (b) Application of Microprocessor The use of microprocessor in toys, entertainment equipment and home applications is making them more entertaining and full of features. The use of microprocessors is more widespread and popular. Now, the Microprocessors are used in: 1. Calculators 2. Accounting system 3. Games machine 4. Complex industrial controllers 5. Traffic light control 6. Data acquisition systems 7. Multi user, multi-function environments 8. Military applications 9. Communication systems 10.3 8085 Microprocessor Architecture (a) Control Unit Generates signals within uP to carry out the instruction, which has been decoded. In reality, it causes certain connections between blocks of the uP to be opened or closed, so that data goes where it is required, and so that ALU operations occur. (b) Arithmetic Logic Unit The ALU performs the actual numerical and logic operation such as ‘add’, ‘subtract’, ‘AND’, ‘OR’, etc. Uses data from memory and from Accumulator to perform arithmetic. Always stores result of operation in Accumulator. CU IDOL SELF LEARNING MATERIAL (SLM)

Microprocessor 1 165 (c) Registers The 8085/8080A programming model includes six registers, one accumulator, and one flag register, as shown in Figure. ACCUMULATOR A (8) FLAG REGISTER B (8) C (8) D (8) E (8) H (8) L (8) Stack Pointer (SP) (16) Program Counter (PC) (16) Data Bus Address Bus 8 Lines Bidirectional 16 Lines undirectional Fig. 10.1: Programming Model In addition, it has two 16-bit registers: the stack pointer and the program counter. They are described briefly as follows. The 8085/8080A has six general-purpose registers to store 8-bit data; these are identified as B, C, D, E, H, and L as shown in the figure 10.1. They can be combined as register pairs – BC, DE, and HL – to perform some 16-bit operations. The programmer can use these registers to store or copy data into the registers by using data copy instructions. (d) Accumulator The accumulator is an 8-bit register that is a part of arithmetic/logic unit (ALU). This register is used to store 8-bit data and to perform arithmetic and logical operations. The result of an operation is stored in the accumulator. The accumulator is also identified as register A. (e) Flags The ALU includes five flip-flops, which are set or reset after an operation according to data conditions of the result in the accumulator and other registers. They are called Zero (Z), Carry CU IDOL SELF LEARNING MATERIAL (SLM)

166 Digital Circuits and Logic Designs (CY), Sign (S), Parity (P), and Auxiliary Carry (AC) flags. They are listed in the Table and their bit positions in the flag register are shown in the Figure below. Fig. 10.2: Flag Format in 8085 The most commonly used flags are Zero, Carry, and Sign. The microprocessor uses these flags to test data conditions. For example, after an addition of two numbers, if the sum in the accumulator id larger than eight bits, the flip-flop uses to indicate a carry – called the Carry flag (CY) – is set to one. When an arithmetic operation results in zero, the flip-flop called the Zero(Z) flag is set to one. The first Figure shows an 8-bit register, called the flag register, adjacent to the accumulator. However, it is not used as a register; five bit positions out of eight are used to store the outputs of the five flip- flops. The flags are stored in the 8-bit register so that the programmer can examine these flags (data conditions) by accessing the register through an instruction. These flags have critical importance in the decision-making process of the micro- processor. The conditions (set or reset) of the flags are tested through the software instructions. For example, the instruction JC (Jump on Carry) is implemented to change the sequence of a program when CY flag is set. The thorough understanding of flag is essential in writing assembly language programs. (f) Program Counter (PC) This 16-bit register deals with sequencing the execution of instructions. This register is a memory pointer. Memory locations have 16-bit addresses, and that is why this is a 16-bit register. The microprocessor uses this register to sequence the execution of the instructions. The function of the program counter is to point to the memory address from which the next byte is to be fetched. When a byte (machine code) is being fetched, the program counter is incremented by one to point to the next memory location CU IDOL SELF LEARNING MATERIAL (SLM)

Microprocessor 1 167 (g) Stack Pointer (SP) The stack pointer is also a 16-bit register used as a memory pointer. It points to a memory location in R/W memory, called the stack. The beginning of the stack is defined by loading 16-bit address in the stack pointer. The stack concept is explained in the unit “Stack and Subroutines.” (h) Instruction Register/Decoder Temporary store for the current instruction of a program. Latest instruction sent here from memory prior to execution. Decoder then takes instruction and ‘decodes’ or interprets the instruction. Decoded instruction then passed to next stage. (i) Memory Address Register Holds address, received from PC, of next program instruction. Feeds the address bus with addresses of location of the program under execution. (j) Control Generator Generates signals within uP to carry out the instruction which has been decoded. In reality causes certain connections between blocks of the uP to be opened or closed, so that data goes where it is required, and so ALU operations occur. (k) Register Selector This block controls the use of the register stack in the example. Just a logic circuit which switches between different registers in the set will receive instructions from Control Unit. (l) General Purpose Registers It requires extra registers for versatility. Can be used to store additional data during a program. More complex processors may have a variety of differently named registers. CU IDOL SELF LEARNING MATERIAL (SLM)

168 Digital Circuits and Logic Designs INTA RST 6.5 TRAP SID SOD Serial I/O control NTR RST 5.5 RST 7.5 Interrupt control 8-Bit Internal data bus Accumulator Temp Flag flip- B C reg. flops REG REG Instruction D E register REG REG Instruction H L decoder and REG REG machine Stack pointer cycle Arithmetic Program counter logic unit encoding Incrementer/dec (ALU) rementer X2 X1 GND+5V address latch CLK DMA Address Address GEN buffer Data buffer Control Status Reset CLK GEN READY RD WR ALE S0 S1 IO/M HOLD HLDA RESET IN RESET OUT AD7 - AD0 Fig. 10.3: Block Diagram of 8085 Microprocessor The architecture of 8085 microprocessor mainly includes the timing and control unit, Arithmetic and logic unit, decoder, instruction register, interrupt control, a register array, serial input/output control. The most important part of the microprocessor is the central processing unit. CU IDOL SELF LEARNING MATERIAL (SLM)

Microprocessor 1 169 10.4 Pin Diagram of 8085 X1 VCC X2 RESET OUT HOLD HLDA SOD CLK (OUT) SID TRAP RESET IN RST7.5 READY RST6.5 IO/M RST5.5 S1 INTR RD INTA WR AD0 ALE AD1 S0 AD2 A15 AD3 A14 AD4 A13 AD5 A12 A11 AD6 A10 AD7 A9 Vss A8 Fig. 10.4: Pin Diagram of 8085 Properties Single + 5V Supply 4 Vectored Interrupts (One is Non-maskable) Serial In/Serial Out Port Decimal, Binary, and Double Precision Arithmetic Direct Addressing Capability to 64K bytes of memory The Intel 8085A is a new generation, complete 8 bit parallel central processing unit (CPU). The 8085A uses a multiplexed data bus. The address is split between the 8bit address bus and the 8bit data bus. Figures are at the end of the document. CU IDOL SELF LEARNING MATERIAL (SLM)

170 Digital Circuits and Logic Designs Pin Description The following describes the function of each pin: (a) A6 - A1s (Output 3 State): Address Bus; The most significant 8 bits of the memory address or the 8 bits of the I/0 address,3 stated during Hold and Halt modes. (b) AD0 - 7 (Input/Output 3 State): Multiplexed Address/Data Bus; Lower 8 bits of the memory address (or I/0 address) appear on the bus during the first clock cycle of a machine state. It then becomes the data bus during the second and third clock cycles. 3 stated during Hold and Halt modes. (c) ALE (Output): Address Latch Enable: It occurs during the first clock cycle of a machine state and enables the address to get latched into the on chip latch of peripherals. The falling edge of ALE is set to guarantee setup and hold times for the address information. ALE can also be used to strobe the status information. ALE is never 3 stated. (d) SO, S1 (Output): Data Bus Status: Encoded status of the bus cycle: S1 S0 OO HALT 01 WRITE 10 READ 11 FETCH S1 can be used as an advanced R/W status. (e) RD (Output 3 State): READ; indicates the selected memory or 1/0 device is to be read and that the Data Bus is available for the data transfer. (f) WR (Output 3 State): WRITE; indicates the data on the Data Bus is to be written into the selected memory or 1/0 location. Data is set up at the trailing edge of WR. 3stated during Hold and Halt modes. (g) READY (Input): If Ready is high during a read or write cycle, it indicates that the memory or peripheral is ready to send or receive data. If Ready is low, the CPU will wait for Ready to go high before completing the read or write cycle. CU IDOL SELF LEARNING MATERIAL (SLM)

Microprocessor 1 171 (h) HOLD (Input): HOLD; indicates that another Master is requesting the use of the Address and Data Buses. The CPU, upon receiving the Hold request. will relinquish the use of buses as soon as the completion of the current machine cycle. Internal processing can continue. The processor can regain the buses only after the Hold is removed. When the Hold is acknowledged, the Address, Data, RD, WR, and IO/M lines are 3stated. (i) HLDA (Output): HOLD ACKNOWLEDGE; indicates that the CPU has received the Hold request and that it will relinquish the buses in the next clock cycle. HLDA goes low after the Hold request is removed. The CPU takes the buses one half clock cycle after HLDA goes low. (j) INTR (Input): INTERRUPT REQUEST; is used as a general purpose interrupt. It is sampled only during the next to the last clock cycle of the instruction. If it is active, the Program Counter (PC) will be inhibited from incrementing and an INTA will be issued. During this cycle a RESTART or CALL instruction can be inserted to jump to the interrupt service routine. The INTR is enabled and disabled by software. It is disabled by Reset and immediately after an interrupt is accepted. (k) INTA (Output): INTERRUPT ACKNOWLEDGE; is used instead of (and has the same timing as) RD during the Instruction cycle after an INTR is accepted. It can be used to activate the 8259 Interrupt chip or some other interrupt port. RST 5.5 RST 6.5 - (Inputs) RST 7.5 RESTART INTERRUPTS; These three inputs have the same timing as I NTR except they cause an internal RESTART to be automatically inserted. RST 7.5 ~~ Highest Priority RST 6.5 Modern Priority RST 5.5 o Lowest Priority The priority of these interrupts is ordered as shown above. These interrupts have a higher priority than the INTR. CU IDOL SELF LEARNING MATERIAL (SLM)

172 Digital Circuits and Logic Designs (l) TRAP (Input): Trap interrupt is a non-maskable restart interrupt. It is recognized at the same time as INTR. It is unaffected by any mask or Interrupt Enable. It has the highest priority of any interrupt. (m) RESET IN (Input): Reset sets the Program Counter to zero and resets the Interrupt Enable and HLDA flip flops. None of the other flags or registers (except the instruction register) are affected. The CPU is held in the reset condition as long as Reset is applied (n) RESET OUT (Output): Indicates CPU is being reset. Can be used as a system RESET. The signal is synchronized to the processor clock. (o) X1, X2 (Input): Crystal or R/C network connections to set the internal clock generator X1 can also be an external clock input instead of a crystal. The input frequency is divided by 2 to give the internal operating frequency. (p) CLK (Output): Clock Output for use as a system clock when a crystal or R/ C network is used as an input to the CPU. The period of CLK is twice the X1, X2 input period. (q) IO/M (Output): IO/M indicates whether the Read/Write is to memory or I/O Tristated during Hold and Halt modes. (r) SID (Input): Serial input data line The data on this line is loaded into accumulator bit 7 whenever a RIM instruction is executed. (s) SOD (Output): Serial output data line. The output SOD is set or reset as specified by the SIM instruction. (t) Vcc: +5 volt supply. (u) Vss: Ground Reference. Examples: Q. 1. Explain application of microprocessor. Solution: The use of microprocessor in toys, entertainment equipment and home applications is making them more entertaining and full of features. The use of microprocessors is more widespread and popular.Now the Microprocessors are used in: CU IDOL SELF LEARNING MATERIAL (SLM)

Microprocessor 1 173 1. Calculators 2. Accounting system 3. Games machine 4. Complex Industrial Controllers 5. Traffic light Control 6. Data acquisition systems 7. Multi user, multi-function environments 8. Military applications 9. Communication systems Q 2. Explain term Microprocessor. Solution: A microprocessor is a computer processor that incorporates the functions of a central processing unit on a single integrated circuit (IC), or sometimes up to 8 integrated circuits. The microprocessor is a multipurpose, clock driven, register based, digital integrated circuit that accepts binary data as input, processes it according to instructions stored in its memory and provides results (also in binary form) as output. Microprocessors contain both combinational logic and sequential digital logic. Microprocessors operate on numbers and symbols represented in the binary number system. The integration of a whole CPU onto a single or a few integrated circuits greatly reduced the cost of processing power. Integrated circuit processors are produced in large numbers by highly automated metal-oxide-semiconductor (MOS) fabrication processes, resulting in a low unit price. Single-chip processors increase reliability because there are many fewer electrical connections that could fail. As microprocessor designs improve, the cost of manufacturing a chip (with smaller components built on a semiconductor chip the same size) generally stays the same according to Rock’s law. Before microprocessors, small computers had been built using racks of circuit boards with many medium- and small-scale integrated circuits. Microprocessors combined this into one or a few large-scale ICs. Continued increases in microprocessor capacity have since rendered other CU IDOL SELF LEARNING MATERIAL (SLM)

174 Digital Circuits and Logic Designs forms of computers almost completely obsolete (see history of computing hardware), with one or more microprocessors used in everything from the smallest embedded systems and handheld devices to the largest mainframes and supercomputers. Q 3. Draw the block diagram of 8085 Microprocessor. INTA RST 6.5 TRAP SID SOD Serial I/O control NTR RST 5.5 RST 7.5 Interrupt control 8-Bit Internal data bus Accumulator Temp Flag flip- Instruction B C reg. flops register REG REG Instruction D E decoder and REG REG machine H L cycle REG REG encoding Stack pointer Arithmetic Program counter logic unit Incrementer/ (ALU) decrementer address latch X2 X1 GND+5V CLK Address Address GEN buffer Data buffer Control Status DMA Reset CLK GEN READY RD WR ALE S0 S1 IO/M HOLD HLDA RESET IN RESET OUT A13 - A5 AD7 - AD0 Fig. 10.5 10.5 Summary A device that uses a microprocessor is normally capable of many functions, such as word processing, calculation, and communication via Internet or telephone. However, for the device to work properly, the microprocessor itself has to communicate with other parts of the device. For example, a microprocessor would need to communicate with the video display to control the CU IDOL SELF LEARNING MATERIAL (SLM)

Microprocessor 1 175 output data that a program may produce. Therefore, a microprocessor would act as device's “brain” in that it transmits, receives and interprets the data needed to operate a device. 10.6 Key Words/Abbreviations  PC: Program counter.  Interpreter: program that can analyze and execute a program line by line. 10.7 Learning Activity 1. What is Microprocessor? ----------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------- 2. Draw the block diagram of microprocessor. ----------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------- 10.8 Unit End Questions (MCQ and Descriptive) A. Descriptive Type Questions 1. Define microprocessor. 2. Draw the block diagram of microprocessor 8085. 3. Explain functioning of different components of microprocessor 8085. 4. Describe pin diagram of microprocessor 8085. B. Multiple Choice/Objective Type Questions 1. In 8085 microprocessor, how many interrupts are maskable? (a) two (b) three (c) four (d) five CU IDOL SELF LEARNING MATERIAL (SLM)

176 Digital Circuits and Logic Designs 2. Which stack is used in 8085 microprocessor? (a) FIFO (b) FILO (c) LIFO (d) LILO 3. In an instruction of 8085 microprocessor, how many bytes are present? (a) 1 or 2 (b) 1,2 or 3 (c) 1 only (d) 2 or 3 4. Which one of the following addressing technique is not used in the 8085 microprocessor? (a) register (b) immediate (c) register indirect (d) relative 5. Which of the following register of 8085 microprocessor is not a part of programming language? (a) Instruction register (b) memory addressing (c) status register (d) temporary register Answers 1. (c), 2. (c), 3. (b), 4. (d), 5. (c) 10.9 References 1. https://www.google.com/search?q=microprocessor&rlz=1C1CHBF_enIN862IN8 62&oq=microprocesso r&aqs=chrome..69i57j0l4j69i60l3.8450j0j7&sourceid=chrome&ie=UTF-8 2. https://www.tutorialspoint.com/microprocessor/microprocessor_overview.htm 3. https://www.techwalla.com/articles/why-is-a-microprocessor-important 4. https://inspirit.net.in/viewer/Li9ib29rcy9hY2FkZW1pYy84MDg1IE1pY3JvcHJvY2V zc29yIC0gUmFtZXNoIEdhb25rYXIucGRm   CU IDOL SELF LEARNING MATERIAL (SLM)

UNIT 11 MICROPROCESSOR 2 Structure: 11.0 Learning Objectives 11.1 Introduction 11.2 Historical Background of Microprocessor and Application of Microprocessor 11.3 Memory Input and Output 11.4 Peripheral Mapped Input and Output 11.5 RISC V/S CISC Processor 11.6 Summary 11.7 Key Words/Abbreviations 11.8 Learning Activity 11.9 Unit End Questions (MCQ and Descriptive) 11.10 References 11.0 Learning Objectives After studying this unit, you will be able to:  Define interrupt mechanism of 8085 microprocessor  Define I/O devices  Explain functioning of RISC v/s CISC processors. CU IDOL SELF LEARNING MATERIAL (SLM)

178 Digital Circuits and Logic Designs 11.1 Introduction When microprocessor receives any interrupt signal from peripheral(s) which are requesting its services, it stops its current execution and program control is transferred to a sub-routine by generating CALL signal and after executing sub-routine by generating RET signal again program control is transferred to main program from where it had stopped. When microprocessor receives interrupt signals, it sends an acknowledgement (INTA) to the peripheral which is requesting for its service. Interrupts can be classified into various categories based on different parameters: In RISC the instruction set size is small while in CISC the instruction set size is large. RISC uses fixed format (32 bits) and mostly register-based instructions whereas CISC uses variable format ranges from 16-64 bits per instruction. RISC uses a single clock and limited addressing mode (i.e., 3-5). 11.2 Historical Background of Microprocessor and Application of Microprocessor 11.1 8085 Interrupts Interrupts are the signals generated by the external devices to request the microprocessor to perform a task. There are 5 interrupt signals, i.e., TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR. I. Interrupt are classified into following groups based on their parameter − 1. Vector interrupt: In this type of interrupt, the interrupt address is known to the processor. For example: RST7.5, RST6.5, RST5.5, TRAP. 2. Non-vector interrupt: In this type of interrupt, the interrupt address is not known to the processor so, the interrupt address needs to be sent externally by the device to perform interrupts. For example: INTR. 3. Maskable interrupt: In this type of interrupt, we can disable the interrupt by writing some instructions into the program. For example: RST7.5, RST6.5, RST5.5. CU IDOL SELF LEARNING MATERIAL (SLM)

Microprocessor 2 179 4. Non-maskable interrupt: In this type of interrupt, we cannot disable the interrupt by writing some instructions into the program. For example: TRAP. 5. Software interrupt: In this type of interrupt, the programmer has to add the instructions into the program to execute the interrupt. There are 8 software interrupts in 8085, i.e., RST0, RST1, RST2, RST3, RST4, RST5, RST6 and RST7. 6. Hardware interrupt: There are 5 interrupt pins in 8085 used as hardware interrupts, i.e. TRAP, RST7.5, RST6.5, RST5.5 and INTA. Note: NTA is not an interrupt, it is used by the microprocessor for sending acknowledgement. TRAP has the highest priority, then RST7.5 and so on. II. Interrupt Service Routine (ISR) A small program or a routine that when executed, services the corresponding interrupting source is called an ISR. 1. TRAP: It is a non-maskable interrupt, having the highest priority among all interrupts. By default, it is enabled until it gets acknowledged. In case of failure, it executes as ISR and sends the data to backup memory. This interrupt transfers the control to the location 0024H. 2. RST7.5: It is a maskable interrupt, having the second highest priority among all interrupts. When this interrupt is executed, the processor saves the content of the PC register into the stack and branches to 003CH address. 3. RST 6.5: It is a maskable interrupt, having the third highest priority among all interrupts. When this interrupt is executed, the processor saves the content of the PC register into the stack and branches to 0034H address. 4. RST 5.5: It is a maskable interrupt. When this interrupt is executed, the processor saves the content of the PC register into the stack and branches to 002CH address. 5. INTR: It is a maskable interrupt, having the lowest priority among all interrupts. It can be disabled by resetting the microprocessor. CU IDOL SELF LEARNING MATERIAL (SLM)

180 Digital Circuits and Logic Designs When INTR signal goes high, the following events can occur:  The microprocessor checks the status of INTR signal during the execution of each instruction.  When the INTR signal is high, then the microprocessor completes its current instruction and sends active low interrupt acknowledge signal.  When instructions are received, then the microprocessor saves the address of the next instruction on stack and executes the received instruction. Interrupts are the signals generated by the external devices to request the microprocessor to perform a task. There are 5 interrupt signals, i.e., TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR. 11.3 Memory Input and Output I/O is any general-purpose port used by processor/controller to handle peripherals connected to it. I/O mapped have a separate address space from the memory. So, total addressed capacity is the number of I/O connected and a memory connected. Separate I/O-related instructions are used to access I/O. A separate signal is used for addressing an I/O device. Memory-mapped I/O share the memory space with external memory. So, total addressed capacity is memory connected only. This is underutilisation of resources if your processor supports I/O-mapped I/O. In this case, instructions used to access I/Os are the same as that used for memory. Let's take an example of the 8085 processor. It has 16 address lines i.e. addressing capacity of 64 KB memory. It supports I/O-mapped I/O. It can address up to 256 I/O. If we connect I/O to it an I/O-mapped I/O, then it can address 256 I/O + 64 KB memory. And special instructions IN and OUT are used to access the peripherals. Here, we fully utilize the addressing capacity of the processor. If the peripherals are connected in memory mapped fashion, then total devices it can address is only 64K. This is underutilisation of the resource. And only memory-accessing instructions like MVI, MOV, LOAD, SAVE are used to access the I/O devices. The Intel family of microprocessors like 8085, 8086, 80386, Pentium, and Zilog family of microprocessors like Z- 80, Z-8000, etc. provide I/O-mapped I/O facility, in addition to providing memory-mapped I/O. CU IDOL SELF LEARNING MATERIAL (SLM)

Microprocessor 2 181 So, some I/O ports can be connected as I/O-mapped I/O ports, and some others as memory- mapped I/O ports in an Intel processor-based system. But Motorola family of microprocessors like 6800, 68000, 68020, etc. provide only memory-mapped I/O. Thus, we can say that an Intel processor is better compared with a Motorola processor, as far as addressing of I/O ports is concerned.After the discussions stated earlier it is not possible for us to conclude to the extent of which scheme of addressing the Input-Output port is better. Both of them have their advantages and disadvantages. The family of microprocessors which belong to the Intel family-like 8085, 8086, 80386, Pentium, and Zilog family of microprocessors like Z-80, Z-8000, etc. provide the facility of Input-Output mapping to Input-Output facility. We provide the facility of memory mapped input output also in the processor-based system manufactured by Intel. But the family of microprocessors which belong to Motorola like 6800, 68000, 68020 provides only memory mapped input output. Hence, we can conclude that the processor which belong to Intel family is far better compared with the processor of Motorola as far the addressing of the Input-Output ports is concerned. Address Bus Data Bus Control Bus Memory I/O Device Fig. 11.1: Diagram of Memory I/O CU IDOL SELF LEARNING MATERIAL (SLM)

182 Digital Circuits and Logic Designs 11.4 Peripheral Mapped Input and Output Peripheral and Memory Mapped I/O Interfacing. IN instruction is used to access input device and OUT instruction is used to access output device. Each I/O device is identified by a unique 8- bit address assigned to it. Peripheral Mapped I/O Interfacing In peripheral mapped I/O interfacing, the I/O devices are treated differently from memory chips. In this method the control signals I/O read (IOR) and I/O write (IOW), which are derived from the IO/M, RD and WR signals of the 8085, are used to activate input and output devices, respectively. Since the control signals used to access input and output devices are different, and all I/O device use 8-bit address, a maximum of 256 (28) input devices and 256 output devices can be interfaced with 8085. Status of IOR IOR and IOW signals in 8085. Table 11.1: Peripheral mapped I/O interfacing IO/ M RD WR IOR IOW Operation 1 1 01 0 1 I/O read operation 0 10 1 0 I/O write operation XX 1 1 Memory read or write operation +5V +5V 10K 10K 10K D7 V GND D6 74LS244 8085 D0 1G 2G A7 8-bit DIPswitch A6 A5 A4 NAND A3 A2 A1 OR A0 IOR Fig. 11.2: Block Diagram of Peripheral Mapped I/O The memory is the storage area where all the inputs are stored before processing and the outputs are stored after processing of inputs. CU IDOL SELF LEARNING MATERIAL (SLM)

Microprocessor 2 183 Many devices provide input to computer and a space is required to store and queue all these inputs, before they are processed by the CPU. An output unit performs the reverse operation of that of an input unit. It supplies information obtained from data processing to outside world. Hence, it links a computer with its external environment. As computers work with binary code, results produced are also in binary form. Therefore, before supplying the results to outside world, the system must convert them to human acceptable (readable) form. Units called output interfaces accomplish this task. Output interfaces match the unique physical or electrical characteristics of output devices (terminals, printers, etc.) to the requirements of an external environment.  Difference between Memory Mapped I/O and I/O Mapped I/O. Memory Mapped I/O I/O Mapped I/O 1. In this device address si 16 bit. Thus A0 to 1. In this I/O device address is 8 bit. Thus A0 to A15 lines are used to generate device A7 or A8 to A15 lines are used to generate address. device address. 2. MEMR and MEMW control signals are used 2. IOR and IOW control signals are used to to control read and write I/O operations. control read and write I/O operations. 3. Instructions available are I.D>A addr, STA 3. Instructions are available are IN and OUT. addr, LDAX rp, STAX rp, MOV M,R, MOV R,M ADD M, CMP M etc. 4. Data transfer is between any register and I/O 4. Data transfer is between accumulator and I/O device. device. 5. Maximum number of I/O devices are 65536 5. Maximum number of I/O devices. (theoretically). 6. Execution speed using LDA addr, STA addr 6. Execution speed is 10 t-states. is 13 T-state and 7 T-states for MOV M< r and MOV r, M instructions. 7. Decoding 16 bit address may require more 7. Decoding 8 bit address will require less hardware. hardware. CU IDOL SELF LEARNING MATERIAL (SLM)

184 Digital Circuits and Logic Designs 11.5 RISC V/S CISC Processor 1. RISC (Reduced Instruction Set Computer) Processor: It is known as Reduced Instruction Set Computer. It is a type of microprocessor that has a limited number of instructions. They can execute their instructions very fast because instructions are very small and simple. RISC chips require fewer transistors which make them cheaper to design and produce. In RISC, the instruction set contains simple and basic instructions from which more complex instruction can be produced. Most instructions complete in one cycle, which allows the processor to handle many instructions at same time. In this, instructions are register based and data transfer takes place from register to register Register File ALU Control Unit FPU DCache MMXU . Fig. 11.3: Diagram of RISC Processor 2. CISC Processor (Complex Instruction Set Computer): It is known as Complex Instruction Set Computer .It was first developed by Intel. It contains large number of complex instructions.In this instructions are not register based.Instructions cannot be completed in one machine cycle. Data transfer is from memory to memory. Micro programmed control unit is found in CISC. Also, they have variable instruction formats CU IDOL SELF LEARNING MATERIAL (SLM)

Microprocessor 2 185 Control Unit Instruction and Data Path Micro Program Control Cache Memory Main Memory Fig. 11.4: Diagram of CISC Processor  RISC V/S CISC Processor. Architectural CISC RISC Characteristics Instruction size and Large set of instructions with variable Small set of instructions with fixed format formats (16-64 bits per instruction). format (32 bit). Data transfer Memory to memory. Register to register. CPU control Most micro coded using control Mostly hardwired without control memory (ROM) but modern CISC use memory. hardwired control. Instruction type Not register based instructions. Register based instructions. Memory access More memory access. Less memory access. Clocks Includes multi-clocks. Includes single clock. Instruction nature Instructions are complex. Instructions are reduced and simple. CU IDOL SELF LEARNING MATERIAL (SLM)

186 Digital Circuits and Logic Designs Exercise: Q 1. Explain classification of interrupt. Solution: 1. Vector interrupt: In this type of interrupt, the interrupt address is known to the processor. For example: RST7.5, RST6.5, RST5.5, TRAP. 2. Non-vector interrupt: In this type of interrupt, the interrupt address is not known to the processor so, the interrupt address needs to be sent externally by the device to perform interrupts. For example: INTR. 3. Maskable interrupt: In this type of interrupt, we can disable the interrupt by writing some instructions into the program. For example: RST 7.5, RST 6.5, RST 5.5. 4. Non-maskable interrupt: In this type of interrupt, we cannot disable the interrupt by writing some instructions into the program. For example: TRAP. 5. Software interrupt: In this type of interrupt, the programmer has to add the instructions into the program to execute the interrupt. There are 8 software interrupts in 8085, i.e., RST 0, RST 1, RST 2, RST 3, RST 4, RST 5, RST 6 and RST7. 6. Hardware interrupt: There are 5 interrupt pins in 8085 used as hardware interrupts, i.e., TRAP, RST 7.5, RST 6.5, RST 5.5 and INTA. Note: NTA is not an interrupt, it is used by the microprocessor for sending acknowledgement. TRAP has the highest priority, then RST7.5 and so on. Q 2. Explain the difference between RISC and CISC. Solution: Architectural Complex Instruction Set Computer Reduced Instruction Set Computer Characteristics (CISC) (RISC) Instruction size and Large set of instructions with Small set of instructions with fixed format format variable formats (16-64 bits per (32 bit). instruction). Data transfer Memory to memory. Register to register. CU IDOL SELF LEARNING MATERIAL (SLM)

Microprocessor 2 187 CPU control Most micro coded using control Mostly hardwired without control memory (ROM) but modern CISC memory. Instruction type use hardwired control. Memory access Clocks Not register based instructions. Register based instructions. Instruction nature More memory access. Less memory access. Includes multi-clocks. Includes single clock. Instructions are complex. Instructions are reduced and simple. Q 3. Define Memory Input and Output. Solution: I/O is any general-purpose port used by processor/controller to handle peripherals connected to it. I/O mapped I/O have a separate address space from the memory. So, total addressed capacity is the number of I/O connected and a memory connected. Separate I/O-related instructions are used to access I/O. A separate signal is used for addressing an I/O device. Memory-mapped I/O share the memory space with external memory. So, total addressed capacity is memory connected only. This is underutilisation of resources if your processor supports I/O-mapped I/O. In this case, instructions used to access I/O are the same as that used for memory. Let’s take an example of the 8085 processor. It has 16 address lines, i.e., addressing capacity of 64 KB memory. It supports I/O-mapped I/O. It can address up to 256 I/O. If we connect I/O to it an I/O-mapped I/O, then it can address 256 I/O + 64 KB memory. And special instructions IN and OUT are used to access the peripherals. Here, we fully utilize the addressing capacity of the processor.If the peripherals are connected in memory mapped fashion, then total devices it can address is only 64K. This is underutilisation of the resource. And only memory-accessing instructions like MVI, MOV, LOAD and SAVE are used to access the I/O devices. The Intel family of microprocessors like 8085, 8086, 80386, Pentium, and Zilog family of microprocessors like Z-80, Z-8000, etc. provide I/O-mapped I/O facility, in addition to providing memory-mapped I/O. So some I/O ports can be connected as I/O-mapped I/O ports, and some CU IDOL SELF LEARNING MATERIAL (SLM)

188 Digital Circuits and Logic Designs others as memory-mapped I/O ports in an Intel processor-based system. But Motorola family of microprocessors like 6800, 68000, 68020, etc. provide only memory-mapped I/O. Thus, we can say that an Intel processor is better compared with a Motorola processor, as far as addressing of I/O ports is concerned.After the discussions stated earlier, it is not possible for us to conclude to the extent of which scheme of addressing the Input-Output port is better. Both of them have their advantages and disadvantages. The family of microprocessors which belong to the Intel family like 8085, 8086, 80386, Pentium, and Zilog family of microprocessors like Z-80, Z-8000, etc. provide the facility of Input-Output mapping to Input-Output facility. We provide the facility of memory mapped Input Output also In the processor-based system manufactured by Intel. But the family of microprocessors which belong to Motorola like 6800, 68000, 68020 provides only Memory mapped Input Output. Hence, we can conclude that the processor which belong to Intel family is far better compared with the processor of Motorola as far the addressing of the Input-Output ports is concerned. Address Bus Data Bus Control Bus Memory I/O Device Fig. 11.5 CU IDOL SELF LEARNING MATERIAL (SLM)

Microprocessor 2 189 11.6 Summary Interrupts in 8086 microprocessor. An interrupt is a condition that halts the microprocessor temporarily to work on a different task and then return to its previous task. Interrupt is an event or signal that request to attention of CPU. This halt allows peripheral devices to access the microprocessor. Memory mapped I/O is mapped into the same address space as program memory and/or user memory, and is accessed in the same way. I/O mapped I/O (also known as port mapped I/O) uses a separate, dedicated address space and is accessed via a dedicated set of microprocessor instructions. 11.7 Key Words/Abbreviations  RISC: Reduced Instruction Set Computer.  CISC: Complex Instruction Set Computer. 11.8 Learning Activity 1. Why interrupt are used in 8085? ----------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------- 2. What is difference between RISC and CISC? ----------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------- CU IDOL SELF LEARNING MATERIAL (SLM)

190 Digital Circuits and Logic Designs 11.9 Unit End Questions (MCQ and Descriptive) A. Descriptive Type Questions 1. Define interrupt mechanism of 8085 microprocessor. 2. Define I/O devices. 3. Explain functioning of RISC v/s CISC processors. B. Multiple Choice/Objective Type Questions 1. Which are the processor based on RISC? (a) SPARC (b) 80386 (c) MC680 (d) MC6400 2. Which of the following processor uses in Harvard architecture ? (a) Intel (b) Motorola (c) University of Bekeley (d) MIPS 3. How memory is accessed in RISC architecture? (a) Load and store instruction (b) Opcode instruction (c) Memory instruction (d) Bus instruction 4 . Who coined term RISC? (a) David Patterson (b) Von Neuman (c) Micheal Flynn (d) Harvard 5. Which of the following is an 8 bit RISC Harvard architecture? (a) AVR (b) Zilog80 (c) 8051 (d) Motorola Answers 1. (a), 2. (c), 3. (a), 4. (a), 5. (a) CU IDOL SELF LEARNING MATERIAL (SLM)

Microprocessor 2 191 11.10 References 1 https://www.google.com/search?q=risc+and+cisc+difference&oq=risc+and+cisc& aqs=chrome.2.69i57j0l7.8729j1j7&sourceid=chrome&ie=UTF-8 2. https://www.tutorialspoint.com/microprocessor/microprocessor_8085_addressing_ modes_and_interrupts.htm 3. https://easyengineering.net/microprocessors-books/   CU IDOL SELF LEARNING MATERIAL (SLM)

PRACTICAL LOGIC GATES UNIT 1 1. Verification of the truth tables of TTL gates (7400, 7402, 7404, 7408, 7432 and 7486). Aim: Verification of the truth tables of TTL gates (7400, 7402, 7404, 7408, 7432 and 7486) Apparatus: ICs 7400, 7402, 7404, 7408, 7432 and 7486, Logic Trainer Kit, Connecting Wires. I. TWO-INPUT NAND GATE Pin Diagram Symbol A Y A.B 1 Vcc 14 B 2 7400 I 13 Truth Table C 12 AB 37 00 01 A.B 44 10 1 11 1 5 11 1 0 0 10 0 9 6 7 Gnd 8 Fig. p1.1: Symbol, Pin Diagram and Truth Table Two-input NAND gate CU IDOL SELF LEARNING MATERIAL (SLM)