BCA 111 DCLD

Logic Gates 193 II. NOR Gate: Pin Diagram Symbol 1 Vcc 14 A F A+B I B 7402 13 C Truth Table A+B 1 2 AB 1 37 00 1 4 4 12 01 0 10 11 11 0 10 52 6 9 7 Gnd 8 Fig. p1.2: Symbol, Pin Diagram and Truth Table Two-input NOR gate III. NOT GATE Symbol Pin Diagram A Y =A 1 I Vcc 14 7404N C 13 2 7 Truth Table 3 4 12 AA 0 11 01 4 4 10 5 10 9 6 7 Gnd 8 Fig. p1.3: Symbol, Pin Diagram and Truth Table One-input NOT gate CU IDOL SELF LEARNING MATERIAL (SLM)

194 Digital Circuits and Logic Designs IV. AND GATE Symbol Pin Diagram A Y= A.B 1 Vcc 14 B 7408N 2 I 13 Truth Table C 12 A B A.B 00 0 37 01 0 4 4 11 10 0 5 11 1 0 10 9 8 6 7 Gnd 8 Fig. p1.4: Symbol, Pin Diagram and Truth Table Two input NOT gate V. OR GATE: Symbol Pin Diagram A F=A+B B 7432 1 I Vcc 14 2 C 13 12 37 Truth Table 4 4 11 5 3 10 A B A+B 29 00 0 6 01 1 7 Gnd 8 10 1 11 1 Fig. p1.5: Symbol, Pin Diagram and Truth Table Two input OR gate CU IDOL SELF LEARNING MATERIAL (SLM)

Logic Gates 195 VI. X-OR GATE: Pin Diagram: 14 Symbol: 13 A Y= AB + AB 1 12 B 2 11 7486N I 10 C 9 TRUTH TABLE: 37 4 8 A B AB + AB 4 8 000 5 6 011 6 101 7 Gnd 11 0 Fig. p1.6: Symbol, Pin Diagram and Truth Table Two input X-OR gate Conclusion: Hence, truth tables of TTL gates (7400, 7402, 7404, 7408, 7432 and 7486) studied and verified. 2. Design the basic gates using NAND gate. Aim: Design the basic gates using NAND gate. Apparatus: IC 7400, Logic Trainer Kit, Connecting Wires. (i) Implementation of NAND Gate as NOT: This is the circuit diagram of a NAND gate used to make work like a NOT gate, the original logic gate diagram of NOT gate is given besides. CU IDOL SELF LEARNING MATERIAL (SLM)

196 A’ A Digital Circuits and Logic Designs A A’ Fig. p1.7: Implementation of NAND Gate as NOT gate (ii) Implementation of NAND Gate as OR Gate: AB Output 00 0 01 OR 1 10 11 1 1 Fig. p1.8: Implementation of NAND Gate as OR gate The above diagram is of an OR gate made from combinations of NAND gates, arranged in a proper manner. The truth table of an OR gate is also given beside the diagram. Truth Table: A B Output 0 00 0 11 1 01 1 11 (iii) Implementation of NAND Gate as AND Gate: X X. Y Y Fig. p1.9: Implementation of NAND Gate as AND Gate CU IDOL SELF LEARNING MATERIAL (SLM)

Logic Gates 197 The above diagram is of an AND gate made from NAND gate. So, we can see that all the three basic gates can be made by only using NAND gates, that’s why this gate is called Universal Gate, and it is appropriate. Conclusion: Hence, basic gates using NAND gate designed and verified. 3. Design the basic gates using NOR gate. Aim: Design the basic gates using NOR gate. Apparatus: IC 7402, Logic Trainer Kit, Connecting Wires. (i) Implementation of NOR Gate as OR Gate: a a OR b b Fig. p1.10: Implementation of NOR Gate as OR Gate The above diagram is of an OR gate made by only using NOR gates. The output of this gate is exactly similar to that of a single OR gate. We can see the circuit arrangement of OR gate using, NOR gate is similar to that of AND gate using NAND gates. (ii) Implementation of NOR Gate as AND Gate: a a AND b b Fig. p1.11: Implementation of NOR Gate as AND Gate The above diagram as the name suggests is of AND gate using only NOR gate, again we can see that the circuit diagram of AND gate using only NOR gate is exactly similar to that of OR CU IDOL SELF LEARNING MATERIAL (SLM)

198 Digital Circuits and Logic Designs gate using only NAND gates. Now, we will finally see how we can make a NOT gate by using only NOR gates. (ii) Implementation of NOR Gate as NOT Gate: a NOT a Fig. p1.12: Implementation of NOR Gate as NOT Gate The above diagram is of a NOT gate made by using a NOR gate. The circuit diagram is similar to that of NOT gate made by using only NAND gate. Conclusion: Hence, basic gates using NOR gate designed and verified.   CU IDOL SELF LEARNING MATERIAL (SLM)

PRACTICAL COMBINATIONAL UNIT 2 CIRCUITS 1. Verification of the truth table of the Multiplexer 74150. Aim: To design and implement Multiplexer using logic gates and study of IC 74150. Apparatus Required: 3 input AND gate, OR gate, trainer kit, patch chords. Theory: Multiplexer Multiplexer means transmitting a large number of information units over a smaller number of channels or lines. A digital multiplexer is a combinational circuit that selects binary information from one of many input lines and directs it to a single output line. The selection of a particular input line is controlled by a set of selection lines. Normally. there are 2n input line and n selection lines whose bit combination determine which input is selected. Block Diagram: I3 I2 4 × 1 Multiplexer I1 I0 S1 S0 Fig. p2.1: Multiplexer A multiplexer (or mux), also known as a data selector, is a device that selects between several analog or digital input signals and forwards it to a single output line. A multiplexer of {display style 2^{n}} inputs has {display style n} select lines, which are used to select which CU IDOL SELF LEARNING MATERIAL (SLM)

200 Digital Circuits and Logic Designs input line to send to the output Multiplexers are mainly used to increase the amount of data that can be sent over the network within a certain amount of time and bandwidth. Multiplexers can also be used to implement Boolean functions of multiple variables. An electronic multiplexer makes it possible for several signals to share one device or resource, for example, one A/D converter or one communication line, instead of having one device per input signal. Conversely, a demultiplexer (or demux) is a device taking a single input and selecting signals of the output of the compatible mux, which is connected to the single input, and a shared selection line. A multiplexer is often used with a complementary demultiplexer on the receiving end. Procedure: 1. Connections are given as per circuit diagram. 2. Logical inputs are given as per circuit diagram. 3. Observe the output and verify the truth table. Circuit Diagram: S1 S0 D0 D1 D2 D3 7404 7404 74LS11 Y 7432 74LS11 7432 74LS11 7432 74LS11 Fig. p2.2: Multiplexer using Logic Gates CU IDOL SELF LEARNING MATERIAL (SLM)

Combinational Circuits 201 Table 1: Truth Table of Multiplexer IO S1 S0 I/P D0 D1 D2 D3 0 0 0 000 0 0 0 0 0 0 011 0 0 0 1 0 1 100 0 0 0 1 0 1 110 1 0 1 000 0 0 010 0 1 100 0 0 110 0 0 Pin Diagram: E7 1 24 VCC E6 2 E5 3 I 23 E8 22 E9 E4 4 C E3 5 21 E10 E2 6 7 E1 7 20 E11 E0 8 ST 9 4 Q 10 19 E12 11 D 12 1 18 E13 GND 5 17 E14 0 16 E15 15 A 14 B 13 C Fig. p2.3: Pin Diagram 8085 Result: Thus, the design and implementation of Multiplexer using logic gates and study of IC 74150. CU IDOL SELF LEARNING MATERIAL (SLM)

202 Digital Circuits and Logic Designs 2. Verification of the truth table of the Demultiplexer 74154. Aim: To design and implement De multiplexer using logic gates and study and IC 74154. Apparatus Required: 3 input AND gate, OR gate, trainer kit, patch chords Theory: Demultiplexer The function of Demultiplexer is in contrast to multiplexer function. It takes information from one line and distributes it to a given number of output lines. For this reason, the demultiplexer is also known as a data distributor. Decoder can also be used as demultiplexer. In the 1:4 demultiplexer circuit, the data input line goes to all of the AND gates. The data select lines enable only one gate at a time and the data on the data input line will pass through the selected gate to the associated data output line. Block Diagram: DATA I/P 1×4 D0 DEMUX D1 DATA O/P D2 D3 S1 S0 Fig. p2.4: Block Diagram of Demultiplexer A demultiplexer (or demux) is a device that takes a single input line and routes it to one of several digital output lines. A demultiplexer of 2n outputs has n select lines, which are used to select which output line to send the input. A demultiplexer is also called a data distributor. Demultiplexers can be used to implement general purpose logic. By setting the input to true, the demux behaves as a decoder.The reverse of the digital demultiplexer is the digital multiplexer. Procedure: 1. Connections are given as per circuit diagram. 2. Logical inputs are given as per circuit diagram. CU IDOL SELF LEARNING MATERIAL (SLM)

Combinational Circuits 203 3. Observe the output and verify the truth table. Circuit Diagram: S1 S0 I/P 7404 7404 74LS11 D0 74LS11 D1 74LS11 D2 D3 74LS11 Fig. p2.5: Demultiplexer using Logic gates Table 2: Truth Table of Demultiplexer IO S1 S0 I/P D0 D1 D2 D3 0 000 0 0 0 0 011 0 0 0 0 100 0 0 0 0 110 1 0 0 1 000 0 0 0 1 010 0 1 0 1 100 0 0 0 1 110 0 0 1 CU IDOL SELF LEARNING MATERIAL (SLM)

204 Digital Circuits and Logic Designs Pin Diagram: Q0 1 24 VCC Q1 2 I 23 A Q2 3 C 22 B Q3 4 7 21 C Q4 5 4 20 D Q5 6 1 19 FE2 Q6 7 5 Q7 8 Q8 9 18 FE1 Q9 10 4 Q10 11 GND 12 17 Q15 16 Q14 15 Q13 14 Q12 13 Q11 Fig. p2.6: Pin Diagram of IC 74154 Result: Thus, the design and implementation of Multiplexer using logic gates and study of IC 74154. 3. Design and verification of the truth tables of half adder and full adder circuits using gates 7483. Aim: To design and construct half adder, full adder circuits and verify the truth table using logic gates. Apparatus: Ic,Trainer Kit, Patch Cords. Theory: Half Adder: A half adder has two inputs for the two bits to be added and two outputs one from the sum ‘ S ’ and other from the carry ‘ c ’ into the higher adder position. Above circuit is called as a carry signal from the addition of the less significant bits sum from the X-OR Gate the carry out from the AND gate. CU IDOL SELF LEARNING MATERIAL (SLM)

Combinational Circuits 205 Full Adder: A full adder is a combinational circuit that forms the arithmetic sum of input; it consists of three inputs and two outputs. A full adder is useful to add three bits at a time but a half adder cannot do so. In full adder, sum output will be taken from X-OR Gate, carry output will be taken from OR Gate. Circuit Diagram of Adder: X Y Cin XOR XOR S AND AND C First half-adder Second half-adder OR Fig. p2.7.(a): Half Adder Fig. p2.7. (b): Full Adder Procedure: (i) Connections are given as per circuit diagram. (ii) Logical inputs are given as per circuit diagram. (iii) Observe the output and verify the truth table. Truth Table: (a) Half adder Table 3: Truth Table of Half Adder Input Output A B Sum Carry 0000 0110 1010 1101 CU IDOL SELF LEARNING MATERIAL (SLM)

206 Digital Circuits and Logic Designs (b) Full Adder Table 4: Truth Table of Full Adder Input Output A B Cin Sum Carry 00000 00110 01010 01101 10010 10101 11001 11111 K-map for Half Adder: For Carry For Sum AB 0 1 AB 0 1 0 00 00 1 1 01 11 0 Carry AB S  AB  AB Fig. p2.9: K-map for Half Adder K-map for Full Adder: For Carry (Cout) For Sumt A BCin 00 01 11 10 A BCin 00 01 11 10 0 00 1 0 0 01 0 1 1 01 1 1 1 10 1 0 Cout =AB +ACin + BCin Sum  ABCin  ABCin  ABCin  ABCin Fig. p2.10: K-map for Full Adder CU IDOL SELF LEARNING MATERIAL (SLM)

Combinational Circuits 207 Result: Hence, construct half adder, full adder circuits and verify the truth table using logic gates. 4. Design and construct half subtractor and full subtractor circuits and verify the truth table using logic gates. Aim: To design and construct half adder, full adder, half subtractor and full subtractor circuits and verify the truth table using logic gates. Apparatus: Ic,Trainer Kit, Patch Cords. Theory: 1. Half Subtractor: The half subtractor is constructed using X-OR and AND Gate. The half subtractor has two input and two outputs. The outputs are difference and borrow. The difference can be applied using X-OR Gate, borrow output can be implemented using an AND Gate and an inverter. 2. Full Subtractor: The full subtractor is a combination of X-OR, AND, OR, NOT Gates. In a full subtractor, the logic circuit should have three inputs and two outputs. The first half subtractor will be C and A B. The output will be difference output of full subtractor. The expression AB assembles the borrow output of the half subtractor and the second term is the inverted difference output of first X-OR. Logic Diagram: Fig. p2.11 (a): Half Subtractor Fig. p2.11 (b): Full Subtractor CU IDOL SELF LEARNING MATERIAL (SLM)

208 Digital Circuits and Logic Designs Procedure: (i) Connections are given as per circuit diagram. (ii) Logical inputs are given as per circuit diagram. (iii) Observe the output and verify the truth table. Truth Table: (a) Half Subtractor Table 5: Truth Table of Half Substractor Input Output XY DB 00 00 01 11 10 10 11 00 (b) Full Subtractor Table 6: Truth Table of Full Substractor A Input Output 0 0 B C Difference Borrow 0 0 0000 1 1 0111 1 1 1011 1101 0010 0100 1000 1111 CU IDOL SELF LEARNING MATERIAL (SLM)

Combinational Circuits 209 K-map for Half Subtractor: For Difference For Borrow AB 0 0 AB 0 1 0 01 0 01 1 10 1 00 Difference  AB  AB Borrow  AB  AB Fig. p2.13: K-map for Half Subtractor K-map for Full Subtractor: For D For Bout A BBin 00 01 11 10 A BBin 00 01 11 10 0 01 0 1 0 01 1 1 1 10 1 0 0 D  ABBin  ABBin  ABBin  ABBin 1 00 1 Bout  ABin  AB  BBin Fig. p2.14: K-map for Full Subtractor Result: Hence, construct half subtractor, full subtractor circuits and verify the truth table using logic gates.   CU IDOL SELF LEARNING MATERIAL (SLM)

PRACTICAL MICROPROCESSOR UNIT 3 1. Design and test of an SR Flip-flop using NAND and NOR gate Aim: To design an SR Flip-flop using NAND and NOR gate. Apparatus Required: IC, trainer kit, patch chords. Theory: A flip-flop is basically a bistable multi-vibrator type circuit other name of this circuits are trigger circuit, two toggle circuit, one bit storage cell or latch. Block Diagram SQ RQ Procedure: Qn and Qn : Present states 1. Connections are given as per circuit diagram. Qn+1 and Qn+1 : Next states 2. Logical inputs are given as per circuit diagram. 3. Observe the output and verify the truth table. Fig. p3.1: Block Diagram Circuit Diagram: RS Flip-flop with NOR Gate R Q Q S Fig. p3.2: Circuit Diagram of SR Flip-flop CU IDOL SELF LEARNING MATERIAL (SLM)

Microprocessor 211 Operation of RS Flip-flop R (0) 1Q No change Case 1: When R = 0 and S = 0 and Q = 0, Q = 1 When S = 0, R = 0 and Q = 0, Q = 1, a ‘0’ comes S 2Q (0) No change out from the upper NOR gate corresponding to Q = 0. Now, the lower NOR gate has both input ‘0’and hence a ‘1’ comes out from the lower NOR gate corresponding to Q = 1. Fig. p3.3: Operation of SR Flip-flop Case 2: When R = 0 and S = 1 and Q = 0, Q = 1 When S = 1, R = 0 and Q = 0, Q = 1, a ‘ 0 ’ comes out from the upper NOR gate corresponding to Q = 0. Now, the lower NOR gate has one input ‘0’ and other input as 1(Q = 0, S = 1). Hence, a ‘0’ comes out from the lower NOR gate corresponding to Q = 0. This Q = 0 is fed as input to upper NOR gate making (0) 1 (1) R = 0 and Q = 0, this time a “1” come upper NOR gate. R (0) Now, the lower NOR gate has both input as 1(Q = 1, S = 1). Hence, a ‘0’ comes out from the lower NOR gate (1) corresponding to Q = 0. S 2 (1) (0) Fig. p3.4: Operation of SR Flip-flop This process repeats till the output is fixed or settled. Hence, at the end when R = 0, S = 0, Flip-flop goes out Q = 1 and Q = 0. Hence, when R = 0, S = 1, Flip-flop goes in set state. CU IDOL SELF LEARNING MATERIAL (SLM)

212 Digital Circuits and Logic Designs Case 3: When R = 1 and S = 0 and Q = 1, Q = 0 (1) 1 (0) R Q When S = 0, R = 1 and Q=1, Q = 0, a ‘0’ comes out from the upper NOR gate corresponding to Q = 0. Now, (1) the lower NOR gate has both input as ‘0’ (Q = 0, S = 0). Hence, a ‘1’ comes out from the lower NOR gate (0) 2 (1) corresponding to Q = 1. This Q = 1 is fed as input to S upper NOR gate making R =1 and Q = 1, this time a “0” come upper NOR gate. (0) Fig. p3.5: Operation of SR Flip-flop Now, the lower NOR gate has both input as 0(Q = 0, S = 0). Hence, a ‘1’ comes out from the lower NOR gate corresponding to Q = 1. This process repeats till the output is fixed or settled. Case 4: When R = 1 and S = 1 and Q = 1, Q = 0 When S = 1, R = 1 and Q = 1, Q = 0, a ‘1’ comes out from the upper NAND gate corresponding to Q = 1. Now, the lower NAND gate has both input ‘1’ and hence a ‘0’ comes out from the lower NAND gate corresponding to Q = 0. Hence, when R = 0, S = 0, Flip-flop remain in last state or no change state. Truth Table: Table 1: Operation of SR Flip-flop STATE RQ NO CHANGE S 0 PREVIOUS STATE 0 10 RESET 0 01 SET 1 1X 1 FORBIDDEN RS Flip-flop with NAND Gate S Clock R Fig. p3.6: Circuit Diagram of SR Flip-flop with NAND Gate CU IDOL SELF LEARNING MATERIAL (SLM)

Microprocessor 213 Operation: Case 1: S = 1, R = 0 (Set Condition) If S = 1 and R = 0, the output of gate A = 0 and B = 1. Now, with clock = 1, S = 0, R = 1 and flip-flop set Q = 1 and Q = 0. Case 2: S = 0, R = 1 (Reset Condition) If S = 0 and R = 1, the output of gate A = 1 and B = 0. Thus, with clock = 1, S = 1, R = 0 and flip-flop set Q = 0 and Q = 1. Case 3: S = 1, R = 1 (Illegal/Forbidden Condition) With S = 1 and R = 1, the output of both gates will be 0. It is a forbidden condition state or a race condition. Case 4: S = 0, R = 0 (Last State Condition) When both S = 0, R = 0 and clock = 1 the output A & B gate = 1 which keeps the flip-flop in last state. Truth Table: Table 2: Truth Table Operation of RS Flip-flop SR Q STATE 1 1 PREVIOUS STATE NO CHANGE 10 0 RESET 01 1 SET 00 X FORBIDDEN Result: Thus, design and test of an SR flip-flop using NAND and NOR gate. 2. Verify the truth table of J-K flip-flop Aim: To verify the truth table of J-K flip-flop. Apparatus: IC, trainer kit, patch chords. Theory: JK flip-flop is improvement over RS flip-flop in which forbidden condition is defined, figure shows JK flip-flop using RS flip-flop. J and K are called control inputs. When J = CU IDOL SELF LEARNING MATERIAL (SLM)

214 Digital Circuits and Logic Designs 0, K = 0 irrespective of the clock pulse both the AND gate are disabled resulting S = 0, R = 0. Therefore, output Q-remains in the last state. If J = 1, K = 0, the lower AND gate is disabled, i.e., S =1, R = 0 which sets the flip-flop as soon as clock edge comes since upper AND gate is enabled. If J = 0, K = 1, the upper AND gate is disable, hence it is impossible to set the flip-flop, but the flip-flop can be reset provided if it is not already in Reset condition, i.e., if Q = 1, the lower AND gate produce a reset trigger as soon as clock edge comes therefore output will reset to ‘0’. If J = 1, K = 1, it is possible to set or reset the flip-flop if Q = 0 in last state Q will be 1 and the upper AND gate produce a set trigger to force Q = 1. On the other hand, if Q = 1 in the last state, the lower AND gate produce a reset trigger to force Q = 0. In either way, Q always changes in opposite state. This is known as toggling meaning switching to opposite state. Diagram: Truth Table: Fig. p3.7: Circuit Diagram of JK Flip-flop Table 3: Truth Table of JK Flip-flop J K CLK Q Q Comment 0 0  Q Q LATCH 1 0  1 0 SET 0 1  0 1 RESET 1 1  Q Q TOGGLE CU IDOL SELF LEARNING MATERIAL (SLM)

Microprocessor 215 Procedure: 1. Connections are given as per circuit diagram. 2. Logical inputs are given as per circuit diagram. 3. Observe the output and verify the truth table. Circuit Diagram: Fig. p3.8: Circuit Diagram of JK Flip-flop Operation: 1. Reset condition: (J = 0, K = 1): When J = 0, K = 1, Q = 1 and Ǭ = 0, the lower NAND gate passes a reset trigger as soon as clock becomes +ve. This forces Q to become ‘O’ and Ǭ = ‘1’. Hence, J = 0 and K = 1 means reset the flip-flop on +ve edge clock 2. Set condition: (J = 1, K = 0): When J = 1 and K = 0 and Q = 0 and Ǭ = 1, the upper NAND gate passes a set trigger as soon as the +ve clock arrives. This forces Q to high and Ǭ to low. Hence, J =1 and K = 0 means that on +ve clock it will flip-flop. Truth Table: Table 4: Truth Table of Operation of JK Flip-flop Data Input Outputs Inputs Outputs JK Final 00 Last Qn State Ǭn S R Ǭn + 1 00 = Ǭn Last state 10 0 1 00 0 10 = 1 Set 1 0 00 1 0 1 10 1 1 0 00 1 CU IDOL SELF LEARNING MATERIAL (SLM)

216 Digital Circuits and Logic Designs 01 0 10 0 0 = 0 Reset 1 0 = Ǭn toggle 01 1 00 1 0 0 1 11 0 11 11 1 00 Result: Thus, design and test of an JK Flip-flop. 3. Verify the truth table of D flip-flop Aim: To verify the truth table of D flip-flop. Apparatus: IC, trainer kit, patch chords. Theory: The RS flip-flop has two data inputs S and R generating two signals to drive a flip- flop is disadvantageous. Again, there is possibility of R and S being 1 resulting in forbidden condition of the flip-flop. This results in design of D-flip-flop, which requires a single data Input D to drive the flip-flop. Figure shows D-flip-flop using RS flip-flop. This is design by connecting S to R Input through Inverter and Input is labeled as D. Diagram: Procedure: 1. Connections are given as per circuit diagram. 2. Logical inputs are given as per circuit diagram. 3. Observe the output and verify the truth Fig. p.3.9: Truth Table of Operation table. of JK Flip-flop CU IDOL SELF LEARNING MATERIAL (SLM)

Microprocessor 217 Circuit Diagram: Operation: When clock = 0 irrespective of value of D – both AND gate are disabled resulting S = 0, R = 0 under this condition Y will remain in the last state. When clock is 1, D = 1, the upper AND gate is enabled whereas the lower AND gate is disabled due to Inverter. Fig. p3.10: Circuit Diagram of JK Flip-flop This results in S = 1, R = 0. Therefore, Y = 1, i.e., the value of Y follows the value of D in presence of clock. When clock = 1, D = 0, the upper AND gate is disabled whereas the lower AND gate is enabled due to Inverter. Truth Table: Table 5: Truth Table of D Flip-flop Input Output Dn Qn+1 00 11 Result: Thus, design and test of an D flip-flop. 4. Study of 8085 Microprocessor Kit Aim: To study of 8085 Microprocessor Kit. 8085 is an 8-bit general purpose capable of addressing 64-kbytes of memory and 256 I/O device. This device has 40 pins, require +5v supply and can operate with 3.125 mhz single phase. CU IDOL SELF LEARNING MATERIAL (SLM)

218 Digital Circuits and Logic Designs Fig. p3.11: Pin Diagram of 8085 Functional Layout of 8085 Microprocessor All 40 signals are classified into 6 groups; those are: (1) Address bus multiplexed address, (2) Data bus, (3) Control and status signal, (4) Power supply and frequency signal, (5) Interrupt and peripheral initiated signal and (6) Serial IO signal. I. Unidirectional Address Bus (A8-A15): 8085 has 8 address lines A8-A15 which are unidirectional and this address lines used as higher order address bus. It is not multiplexed. II. Multiplex Address/Data Bus (AD0-AD7): This signal lines are bi-directional and is Multiplexed, i.e., it can be used as lower order address bus A0 to A7 and 8-bit data bus D0 CU IDOL SELF LEARNING MATERIAL (SLM)

Microprocessor 219 to D7. In early part of execution cycle (T1 State), this lines are used as address bus and during later part of cycle, this lines are used ad data bus. Thus, address/data bus operate in timeshare mode. This technique is called as multiplexing. Multiplexing means many into one operation.The lower order address bus and data bus can be separated using the signals ALE and latch. so that separate address bus A0-A7 can be generated. These signals are used to identify the nature of operation along with special signal ALE to indicate beginning of operation.  ALE (Address Latch Enable/Pin 30): This positive going pulse generated every time the 8085 starts the operation. It indicates that the bits AD0-AD7 has valid address on it. This signal is used to latch this address, so that separate set of address lines A0-A7 can be generated.  RD (Pin 32): This is a read control signal which is active low (negative going). A low level on RD indicates that the selected memory or I/O device to perform read operation and the data bus is available for data transfer.  WR (Pin 31): This is a write control signal which is active low (negative going). A low level on WR indicates that data on the data Bus is to be written in selected memory or I/O location.  IO/M (Pin 34): This is status signal use to differentiate between memory and I/O operation. When this signal is low, it indicates memory operation and when this signal is high it indicates I/O operation. These three control lines, RD, WR and IO/M functions together. The following table show the truth table. Table 6: Truth Table for Memory and I/O Control IO/ M WR RD Action 0 1 0 Memory read 0 0 1 Memory write 1 1 0 I/o read 1 0 1 I/o write CU IDOL SELF LEARNING MATERIAL (SLM)

220 Digital Circuits and Logic Designs X 0 0 Illegal X 1 1 No memory or I/O access  S1, S0 (PIN 33, 29): S0 and S1 are status output pins. They indicate to the outside world the current operation being performed by the 8085. Using S0, S1 and IO/M, advance information of the 8085. Tri State (high impedance) X – unspecified Activities can be decoded. Table shows the machine cycle status. Most 8085 circuits do not make use of the status pins, i.e., rarely used. Power Supply and Clock Frequency Signals of 8085 To make compatible with TTL power supplies, the 8085 requires only a VCC of +5v and ground. Ground is called VSS (substrate voltage) because the 8085 is a MOS device.  VCC (Pin 40): +5 volt power supply.  VSS (Pin 20): Ground reference. All signals are measured or checked with respect to this pin.  X1, X2 (Pin 1, 2): The 8085 does not require an external clock generator,crystal is connected between the X1 and X2 inputs of the 8085. The input frequency of the crystal is divided by 2 to produce the internal reference frequency. The CLK OUT is a same frequency of the 8085’s internal clock. It is used to synchronize the rest of system to the 8085. Maximum operating clock frequency of 8085 is 3.125 Mhz which can be obtain by connecting crystal of 6.25 Mhz between X1 and X2.  TRAP (Pin 6): Trap is highest priority, Non-maskable interrupt. when trap is received, starts the program execution from location (4.5 * 8)h. i.e why trap is called as vectored interrupt.  RST 7.5, 6.5, 5.5 (Pin 7, 8, 9): This are restart interrupts or vectored interrupt when recognized by start program execution from fixed memory location listed below. This are CU IDOL SELF LEARNING MATERIAL (SLM)

Microprocessor 221 maskable interrupts and has priority lower than trap, but among themselves RST 7.5 has highest priority followed by 6.5 and 5.5.  INTR (Pin 10): Interrupt request signal used as general purpose interrupt. it has lowest priority and it is maskable interrupt.  INTA (Pin 11): This is active low signal. This signal is acknowledgement sent by when INTR is recognized. interrupt acknowledge is used instead of RD during the instruction cycle after an INTR is accepted.  READY (Pin 35): It is used in two sense whether a peripheral is ready for data transfer. If ready is high during a read or write cycle, it indicates that the memory or peripheral is ready to send or receive data. If ready is low, the CPU will wait till ready to go high before completing the read or write cycle. Basically this signal is used to delay the read/ write cycle and to interface slower peripherals.  Reset in (Pin 36): This signal may activated by reset button or other source. When reset in is at an active-low level, the internal operation of microprocessor stops. During reset the program counter is set to 0000h. It also sends a high signal to reset out. When reset in goes to inactive-high level, the 8085 will fetch an instruction from memory location 0000h. When 8085 is reset, the following events occur: 1. Program counter is reset to 0000h. 2. The instruction register is cleared. 3. Interrupts are disabled. 4. The RST7.5, RST 6.5, RST 5.5 are masked. 5. All tri-state bus lines except ALE are floated.  Reset out (Pin 3): A high signal on reset out indicates that the CPU is being reset, i.e the program counter, instruction register and so on are being reset to zero. The reset out signal goes to peripheral chips and is used to reset other devices in the system.  Hold (Pin 39): This is an externally initiated signal. HOLD indicates that another peripheral device such as DMA controller is requesting the use of Address and Data CU IDOL SELF LEARNING MATERIAL (SLM)

222 Digital Circuits and Logic Designs buses. The CPU, upon receiving the Hold request, will relinquish(release) the use of the bus as soon as upon the completion of the current bus transfer. It floats Address, Data bus, RD, WR, IO/M and ALE Control signals. Internal processing can continue. The processor can regain the bus only after the hold is removed.  HLDA (Pin 38): Hold acknowledge indicates that the CPU has received the hold request and that it will relinquish the bus in the next clock cycle. HLDA goes low after the hold request is removed. Signals Responsible for Serial I/O Communication in 8085 The 8085 has two signal for implementing the serial transmission.  SID (Pin 5): This is a serial input data line. The data on this line is loaded into bit 7 of accumulator whenever a RIM instruction is executed.  SOD (Pin 4): This is a serial output data line. The output SOD is set or reset as specified by SIM instruction. Architecture of 8085 8085 is an 8-bit microprocessor, it has 40 pins fabricated on single LSI chip. 8085 operates with single +5V DC supply and its clock speed is about 3.125Mhz.The architecture shows following functional units: 1. Timing and Control Unit 2. Arithmetic and Logic Unit 3. Address and Data Buffer 4. Instruction Register and Decoder 5. CPU Register Array 6. Interrupt Control 7. Serial Control 1. Timing and Control Unit: Timing and control unit generates timing and control signals which are necessary for the execution of the instruction. This unit synchronizes all the P CU IDOL SELF LEARNING MATERIAL (SLM)

Microprocessor 223 operations with the clock and generate signals necessary for communication between the microprocessor and peripherals. It also generates RD and WR indicating availability of data on data bus 2. Address and Data Buffer: The 8085 contains unidirectional address bus buffer and a bi- directional data bus buffer. These buffers isolate the internal bus system of the 8085 from the external system bus and provide enough current gain to drive few memory and I/O chips. INTA RST 6.5 TRAP SID SOD Serial I/O control NTR RST 5.5 RST 7.5 Interrupt control 8-Bit Internal data bus Accumulator Temp Flag flip- Instruction B C reg. flops register REG REG Instruction D E decoder and REG REG machine H L cycle REG REG encoding Stack pointer Arithmetic Program counter logic unit Incrementer/ (ALU) decrementer X2 X1 GND+5V address latch CLK Control Address Address GEN buffer Data buffer Status DMA Reset CLK GEN READY RD WR ALE S0 S1 IO/M HOLD HLDA RESET IN RESET OUT A13 - A5 AD7 - AD0 Fig. p3.12: Block Diagram of Architecture of 8085 3. Arithmetic and Logic Unit: The ALU carries out the arithmetic and logic operations, i.e., computing function. The arithmetic operation performed are addition, subtraction, increment, decrement, etc. CU IDOL SELF LEARNING MATERIAL (SLM)

224 Digital Circuits and Logic Designs The logical operation performed are AND, OR, EXOR, Complement, Shift Compare, etc. ALU consists of: 1. Accumulator 2. Temporary Register 3. Flag Register 1. Accumulator: Accumulator is a 8-bit register. The results of nearly all arithmetic and logical operations on data are stored in the accumulator. Also, accumulator is used as one of the source register for arithmetic and logical operation. It is also called as register A. It is the only register for which there are rotate instructions. It is used to enable and disable the interrupt system. It is only register to have data transfer between input and output devices. It is accessible to user through instruction. 2. Temporary Register: Temporary register is 8 bit register. This register stores the operands of arithmetic and logic operation for short period of times. This register is not available to the programmer. 3. Flag Register: The flag register contains five single bit flags, and three unused bits The flags are affected by the arithmetic and logic operation in ALU. In most of these operations, result is stored in accumulator. Therefore, the flags generally reflects data condition in the accumulator with some exception. The five flags are: (i) S – Sign Flag (ii) Z – Zero Flag (iii) AC – Auxiliary Carry Flag (iv) P – Parity Flag (v) C – Carry Flag 7. Carry Flag (CF): The carry flag is set when the result of an operation produces a number that will not fit into the 8-bit accumulator. Thus, the carry flag reflects the final CU IDOL SELF LEARNING MATERIAL (SLM)

Microprocessor 225 carry out of the most significant bit of any arithmetic operation. The carry flag also serves as a borrow for subtraction. 8. Zero Flag (ZF): The zero flag is one of he most useful flag. The zero flag is set if ALU operation results in 00H. Flag is reset if the result is not 00H. This flag is modified by the result in the accumulator as well as the other register. 9. Parity Flag (PF): The parity flag is set to 1 if an arithmetic or logic instruction generates an even number of 1s in accumulator, i.e., even parity. The flag is 0 if the arithmetic or logic instruction containing an odd number of 1s, in accumulator, i.e., odd parity. The parity flag is the least used of all the flags. Instruction Register and Decoder During the fetch cycle, the op-code of an instruction is stored in the instruction register. This op-code then transferred into the instruction decoder and machine cycle encoder. The decoder decodes the instruction and establishes the sequence of the events to follow. The instruction register is not programmable and it is not available to the programmer. CPU Registers Array of 8085 Microprocessor There various type of registers in Intel 8085. There register are used for storage manipulation of data and instruction. The different registers are 1. Temporary Register: Other than one 8-bit temporary register there are two more register W and Z. These register are used to hold temporary data during execution of some instruction. This register are non programmable and cannot be accessed through any instruction. 2. General purpose register: The 8085 has six general-purpose registers. These registers are identified as B, C, D, E, H and L. These are 8-bit registers: CPU can either load a register from the 8 bit internal data bus or output the register contents to this data bus. These registers can be combined to form register pairs BC, DE and HL. Register pairs are used to perform some 16-bit operations. CU IDOL SELF LEARNING MATERIAL (SLM)

226 Digital Circuits and Logic Designs Accumulator Register 16-bit Accumulator A (8) Flag Register Arrays Address B (8) ALU D (8) Memory Pointed Bus H (8) Flags Registers 8-bit Data Instruction Bus Decoder Stack Pointer (SP) Program Counter (PC) Timing and Control Unit Control Data Bus Address Bus (a) Signals 8 16 Lines Lines Biodirectional Undirectional Fig. p3.13: Block Diagram of CPU Array Register 3. Program Counter (PC): The program counter is used to hold an 16-bit address. The contents of the program counter always points to the memory location from where the next instruction or data byte is to fetched. The program counter is incremented automatically after each instruction or data byte is fetched from memory. After resetting the content of PC = 0000H. 4. Stack Pointer (SP): The stack pointer is a 16 bit register. The stack pointer contains the address of the last data byte written into read/write memory called the stack. Stack pointer is always loaded with the maximum address of memory. While storing the data stack pointer decrements by two and while retrieving the data the stack pointer is incremented by two. 5. Interrupt Control: The 8085 has five hardware interrupt inputs as TRAP, RST7.5, RST6.5, RST5.5 and INTR. Also, the 8085 has interrupt acknowledgment output line as INTA. When interrupt occurs, it is to acknowledge or not to be acknowledge, when generate INTA signal is decided by Interrupt control. 6. Serial I/O Control: Serial communication is basically used to reduce number wires in long distance communication. For serial communication 8085 has two signals: (i) SID (ii) SOD CU IDOL SELF LEARNING MATERIAL (SLM)

Microprocessor 227 The serial input data enters the 8085 from SID input. The SOD output is where the serial data leaves the 8085.The serial transmission is controlled by Serial I/O control. CU IDOL SELF LEARNING MATERIAL (SLM)

228 Digital Circuits and Logic Designs Program No.1 Aim: Study of Intel 8085 Microprocessor Kit. Introduction This section briefs the hardware and software facilities available in both the trainers Micro- 85 EBl and Micro-85 EB2. Micro-85 EBl is a powerful Microprocessor Trainer with basic features such as 24 TTL lines using 8255 Hardware Single Stepping and Software Single Stepping of user programs. In addition to the above features, Micro-85 EB2 has RS232C compatible serial port, Bus Expansion for interfacing VBMB series of add-on cards and 24 TTL I/O lines. A separate switch is provided for learning more about hardware. interrupts. There is also provision to add multi output power supply for interfacing experiment boards. Fig. p314: Intel 8085 Microprocessor Kit CU IDOL SELF LEARNING MATERIAL (SLM)

Microprocessor 229 Specifications: Hardware Specifications 1. Processor and Clock Frequency: Intel 8085A at 6.144 MHz clock. 2. Memory: Monitor EPROM : 0000 - 1FFF EPROM- Expansion : 2000 - 3FFF & COOO - FFFF System RAM : 4000 - 5FFF Monitor Data Area : 4000 - 40FF (Reserved) User RAM Area : 4100 - 5FFF RAM- Expansion : 6000 - BFFF Note: The RAM area from 4000 - 40FF should not be accessed by the user since it is used as scratch pad by the Monitor program. 3. Input/Output: Parallel: 48 TTL: I/O lines using two number of 8255 (only 24: I/O line. available in micro-85 EB1). Serial: One number of RS232C compatible Serial interfaces using 8251A – USART. Timer: Three channel 16-bit Programmable Timer using 8253. Channel 0 is used as baud rate clock generator for 8251A USART. Channel 1 is used for in single stepping user programs. Channel 2 is used for Hardware Single Stepping user programs. 4. Display: 6 digit, 0.3”, 7 Segment Red LED Display with filter. 4 digits for address display and 2 digits for data display. Keyboard: 21 Keys soft keyboard including command keys and hexadecimal keys. CU IDOL SELF LEARNING MATERIAL (SLM)

230 Digital Circuits and Logic Designs 4. Audio Cassette Interface with file management. 5. Battery Backup: On-board Battery backup facility is provided for the available RAM. 6. Hardware Single Step: This facility allows the user to execute programs at machine cycle level using a separate switch. 7. System Power Consumption: Micro-85 EB2 Micro-85 EBl + 5 V @ 1 Amp +5V @ 500 mA + 12 V@ 200 mA - 12 V @ l00 mA Software Specifications Micro-S5 EB contains a high performance 8K bytes monitor program. It is designed to respond to user input, RS232C serial communications, tape interface, etc. The following is a simple description of the key functions. Out of the 21 keys in the keyboard, 16 are hexadecimal, command and register keys and the remaining are stand-alone keys. Key Function Summary RES This RES key allows you to terminate any present activity and to return your Micro-85 INT EB to an initialized state. When pressed, the µ..85 sign-on message appears in the display for a few seconds and the monitor will display command prompt “-” in the left most digit. Maskable interrupt connected to CPU's RST 7.5 interrupt. DEC Decrement the address by one and display contents. EXEC Display the previous register contents. DEC Execute a particular program after selecting the address through GO command. INC Increment address by one and display its contents. CU IDOL SELF LEARNING MATERIAL (SLM)

Microprocessor 231 The 16 Hexadecimal keys have either a dual or a triple role to play. 1. It functions as a Hex key entry when a address or data entry is required. 2. It functions as the Register key entry during Register command. 3. It functions as command key when pressed directly after command prompt. Note: The Hex-key function summary below is in the order: 1. Hex key. 2. Command key 3. Register key. Key Function Summary 1. Hex key entry \"0\" 2. This key is for substituting memory contents When NEXT key is pressed immediate1y, it takes the user to the start address for entering user programs, 4100 Hex (User RAM). 3. Register key “E” (i) Hex key entry “0” (ii) This key is for substituting memory contents When NEXT key is pressed immediate1y after this it takes the user to the start address for entering user programs, 4100 Hex (User RAM). (iii) Register key “E” 1 (i) Hex key entry “1” D (ii) Examine the 8085A registers and modify the same. (iii) Register key “D” 1 (i) Hex key entry “2” D (ii) Writes data from memory on to audiotape. (iii) Register key “D” 3 (i) Hex key entry “3” 8 (ii) Retrieve data from an audiotape to memory. (iii) Register key “B” CU IDOL SELF LEARNING MATERIAL (SLM)

232 Digital Circuits and Logic Designs 4 (i) Hex key entry “4”. (ii) Block search for a byte. F (iii) Register key “F”. (i) Hex key entry “5”. 5 (ii) Fill a block of RAM memory with desired data. (iii) Register key “A”. A (i) Hex key entry \"6\" (ii) Transmit/Receive data to/from the serial port. The TW/TR 6 keys are used for sending/receiving respectively L (iii) Register key “L”. (i) Hex key entry “7” 7 (ii) Register key “H” H (i) Hex key entry “8” (ii) Start running a particular program 8 (iii) Register key “I” (i) Hex key entry “9” I (ii) Single step a program instruction by instruction. (iii) Register key “PCL” 9 (i) Hex key entry “A” (ii) Function key F3 F3 [0] = Input a byte from a port PL P3 [1] = Output a byte to a port A (iii) Register key “PCH” (iv) Used with SNG key for hardware single stepping. PH (i) Hex key entry “B” (ii) Check a particular block for blank. B (iii) Register key “SPL” (i) Hex key entry “C” SL (ii) Move block of memory to another block (iii) Register key “SPH” C SH CU IDOL SELF LEARNING MATERIAL (SLM)

Microprocessor 233 D E (i) Hex key entry “D” F (ii) Compare two memory blocks. (i) Hex key entry \"E\" (ii) Insert bytes into memory (RAM) . (i) Hex key entry \"F\" (ii) Delete bytes from memory (RAM) . CU IDOL SELF LEARNING MATERIAL (SLM)

234 Digital Circuits and Logic Designs Program No - 2 Aim: Program to find addition of two 8-bit numbers. SL. MEMORY MACHINE MNEMONICS OPERANDS COMMENTS NO. ADDRESS CODE LXI 21,01,24 MOV H,2401 PLACE ADDRESS OF 1ST 1 2000 A,M NUMBER IN H-L 7E INX H REGISTER PAIR 2 2003 ADD M 23 2403 MOVE THE CONTENTS OF 3 2004 STA MEMORY ADDRESSED 86 HLT BY H-L REGISTER PAIR 4 2005 TO THE ACCUMULATOR 32,03,24 5 2006 76 INCREMENT THE 6 2009 CONTENTS OF H-L REGISTER PAIR BY 1 Data: ADD THE 2ND NO. IN THE 1ST NO. AND THE RESULT IN THE ACCUMULATOR STORE RESULT IN MEMORY LOCATION 2403 STOP 2401-48H 2402-56H Result: 2403-9EH CU IDOL SELF LEARNING MATERIAL (SLM)

Microprocessor 235 Program No. 3 Aim: Program to find subtraction of two 8-bit numbers. SL. MEMORY MACHINE MNEMONICS OPERANDS COMMENTS NO. ADDRESS CODE LXI MOV H,2401 PLACE ADDRESS OF 1ST 1 2000 21,01,24 INX A,M NUMBER IN H-L REGISTER SUB H 2 2003 7E M PAIR 3 2004 23 INX 4 2005 96 MOV H MOVE THE FIRST NUMBER M,A IN ACCUMULATOR 5 2006 23 HLT 6 2007 77 ADD 1 TO THE CONTENTS OF H-L REGISTER PAIR 7 2008 76 SUBTRACT 2ND NUMBER Output: DATA FROM THE FIRST NUMBER AND THE RESULT IS PLACED IN THE ACCUMULATOR GET MEMORY ADDRESS 2403 IN THE H-L PAIR MOVE THE CONTENTS OF ACCUMULATOR TO THE MEMORY LOCATION WHOSE ADDRESS IS IN THE H- L REGISTER PAIR STOP 48H Result:15   CU IDOL SELF LEARNING MATERIAL (SLM)

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