CU-BCA-SEM-IV-Computer System Architecture-Second Draft

 Shift micro-operations are those micro-operations that are used for serial transfer of information. These are also used in conjunction with arithmetic micro-operation, logic micro-operation, and other data-processing operations.  Subtraction is done by adding A to the 2's complement of B. The output carry is transferred to flip-flop E, where it can be checked to determine the relative magnitudes of two numbers. The add-overflow flip-flop AVF holds the overflow bit when A and B are added 5.9 LEARNING ACTIVITY 1. Discuss the topic on micro operation ___________________________________________________________________________ _____________________________________________________________________ 2. Conduct a seminar on arithmetic operation ___________________________________________________________________________ ____________________________________________________________________ 5.10 UNIT END QUESTIONS A. Descriptive Questions Short Questions 1. What is micro operation? 2. What is arithmetic micro operation? 3. What is Logic operation? 4. What is arithmetic operation? 5. What is shift operation? Long Questions 1. List and Explain types of micro operation. 2. Explain the concept of logic operation. 3. Explain arithmetic operation. 4. Explain shift operation. 5. List Rules for Subtraction by 2’s Complementing. B. Multiple Choice Questions 1. Which operations are used for addition, subtraction, increment, and decrement and complement function? 101 CU IDOL SELF LEARNING MATERIAL (SLM)

a. Bus b. Memory transfer c. Arithmetic operation d. All of these 2. Which are the operation that a computer performs on data that put in register? a. Register transfer b. Arithmetic c. Logical d. All of these 3. What does micro operation is shown as. a. R1->R2 b. R1<-R2 c. Both a and b d. None of these 4. What is the Operation of memory transfer are? a. Read b. Write c. Both a and b d. None of these 5. What is the Arithmetic operation are carried by such micro operation on stored numeric data available in? a. Register b. Data c. Both a and b d. None of these Answers 1-d, 2-d, 3-b, 4-c, 5-a. 102 CU IDOL SELF LEARNING MATERIAL (SLM)

5.11 REFERENCES References  M. Morris Mano, Computer System Architecture, 3rd Edition, Pearson.  William Stallings, Computer Organization and Architecture, 8th Edition, Pearson.  Joe Grimes, in Encyclopaedia of Physical Science and Technology (Third Edition), 2003 Textbooks  Das, Biplab; Paul, Avijit Kumar; De, Debashis (2019-08-16). \"An unconventional Arithmetic Logic Unit design and computing in Actin Quantum Cellular Automata\". Microsystem Technologies.  Victor V. Zhirnov, Ralph K. CavinIII, in Microsystems for Bioelectronics (Second Edition), 2015  Samuel C. Lee, in Encyclopaedia of Physical Science and Technology (Third Edition), 2003 Website  https://www.javatpoint.com  https://www.geeksforgeeks.org  https://www.computerscience.gcse.guru 103 CU IDOL SELF LEARNING MATERIAL (SLM)

UNIT – 6: BASIC COMPUTER INSTRUCTIONS PART I STRUCTURE 6.0 Learning Objectives 6.1 Introduction 6.2 Introduction to Instruction 6.3 Types of Instructions 6.3.1 Data Transfer 6.3.2 Data Processing 6.3.3 Control 6.4 Memory Reference 6.5 I/O Reference 6.6 Register Reference 6.7 Summary 6.8 Keywords 6.9 Learning Activity 6.10 Unit End Questions 6.11 References 6.0 LEARNING OBJECTIVES After studying this unit, you will be able to:  Describe the introduction to instruction.  Explain the types of Instructions.  Illustrate about Memory Reference. 6.1 INTRODUCTION An instruction is an order given to a computer processor by a computer program. At the lowest level, each instruction is a sequence of 0s and 1s that describes a physical operation the computer is to perform (such as \"Add\") and, depending on the particular instruction type, 104 CU IDOL SELF LEARNING MATERIAL (SLM)

the specification of special storage areas called registers that may contain data to be used in carrying out the instruction, or the location in computer memory of data. In a computer's assembler language, each language statement generally corresponds to a single processor instruction. In high-level languages, a language statement generally results (after program compilation) in multiple processor instructions. In assembler language, a macro instruction is one that, during processing by the assembler program, expands to become multiple instructions (based on a previously coded macro definition). 6.2 INTRODUCTION TO INSTRUCTION When referring to the computer processor, instructions are a segment of code containing steps that need to be executed by the processor. For a computer to know how to do anything, it must be provided instructions. For example, asking the computer to draw a square requires a set of instructions telling the computer how to draw the square. In Logo, a user could complete this task by giving the computer the below set of instructions. The picture is an example of the results. Forward 100 Right 90 Forward 100 Right 90 Forward 100 Right 90 Forward 100 Figure 6.1: Square in logo 105 CU IDOL SELF LEARNING MATERIAL (SLM)

A computer is given instructions by a human using a keyboard or another input device. To interpret these instructions, the computer uses an operating system or software that's also programmed by a human to translate user commands into something the computer can understand. The computer is able to process these instructions by following the computer's instruction set. 6.3 TYPES OF INSTRUCTIONS There are 3 types of instructions: 6.3.1 Data Transfer Data transfer instructions transfer the data between memory and processor registers, processor registers, and I/O devices, and from one processor register to another. There are eight commonly used data transfer instructions. Each instruction is represented by a mnemonic symbol. The table shows the eight data transfer instructions and their respective mnemonic symbols. Data Transfer Instructions Name Mnemonic Symbols Load LD Store ST Move MOV Exchange XCH Input In Output OUT Push PUSH Pop POP 106 Table 6.1: Data transfer instructions CU IDOL SELF LEARNING MATERIAL (SLM)

The instructions can be described as follows −  Load − the load instruction is used to transfer data from the memory to a processor register, which is usually an accumulator.  Store − the store instruction transfers data from processor registers to memory.  Move − the move instruction transfers data from processor register to memory or memory to processor register or between processor registers itself.  Exchange − the exchange instruction swaps information either between two registers or between a register and a memory word.  Input − the input instruction transfers data between the processor register and the input terminal.  Output − the output instruction transfers data between the processor register and the output terminal.  Push and Pop − the push and pop instructions transfer data between a processor register and memory stack. All these instructions are associated with a variety of addressing modes. Some assembly language instructions use different mnemonic symbols just to differentiate between the different addressing modes. Example − the mnemonic symbols for load immediate is LDI. Thus, it is necessary to be familiar with various addressing modes and different types of instructions to write efficient assembly language programs for a computer. 6.3.2 Data Processing Data processing refers to the transformation raw data into meaningful output.Data can be done manually using a pen and paper, mechanically using simple devices e.g. typewriter or electronically using modern data processing toolset computers Data collection involves getting the data/facts needed for processing from the point of its origin to the computer Data Input- the collected data is converted into machine-readable form by an input device, and send into the machine. Processing is the transformation of the input data to a more meaningful form (information) in the CPU Output is the production of the required information, which may be input in future. 107 CU IDOL SELF LEARNING MATERIAL (SLM)

Figure 6.2: Stages of Data Processing Cycle Data processing methods 1. Manual Data Processing In manual data processing, data is processed manually without using any machine or tool to get required results. In manual data processing, all the calculations and logical operations are performed manually on the data. Similarly, data is transferred manually from one place to another. This method of data processing is very slow and errors may occur in the output. Mostly, is processed manually in many small business firms as well as government offices & institutions. In an educational institute, for example, marks sheets, fee receipts, and other financial calculations (or transactions) are performed by hand. This method is avoided as far as possible because of the very high probability of error, labour intensive and very time consuming. This type of data processing forms the very primitive stage when technology was not available or it was not affordable. With the advancement in technology the dependency on manual methods has drastically decreased. 2. Mechanical Data Processing In mechanical data processing method, data is processed by using different devices like typewriters, mechanical printers or other mechanical devices. This method of data processing 108 CU IDOL SELF LEARNING MATERIAL (SLM)

is faster and more accurate than manual data processing. These are faster than the manual mode but still forms the early stages of data processing. With invention and evolution of more complex machines with better computing power this type of processing also started fading away. Examination boards and printing press use mechanical data processing devices frequently. 3. Electronic Data Processing Electronic data processing or EDP is the modern technique to process data. The data is processed through computer; Data and set of instructions are given to the computer as input and the computer automatically processes the data according to the given set of instructions. The computer is also known as electronic data processing machine. This method of processing data is very fast and accurate. For example, in a computerized education environment results of students are prepared through computer; in banks, accounts of customers are maintained (or processed) through computers etc. a. Batch Processing Batch Processing is a method where the information to be organized is sorted into groups to allow for efficient and sequential processing. Online Processing is a method that utilizes Internet connections and equipment directly attached to a computer. It is used mainly for information recording and research. Real-Time Processing is a technique that has the ability to respond almost immediately to various signals in order to acquire and process information. Distributed Processing is commonly utilized by remote workstations connected to one big central workstation or server. ATMs are good examples of this data processing method. b. Online Processing This is a method that utilizes Internet connections and equipment directly attached to a computer. This allows for the data stored in one place and being used at altogether different place. Cloud computing can be considered as an example which uses this type of processing. It is used mainly for information recording and research. c. Real-Time Processing This technique has the ability to respond almost immediately to various signals in order to acquire and process information. These involve high maintenanceand upfront cost attributed to very advanced technology and computing power. Time saved is maximum in this case as the output is seen in real time. For example in banking transactions Example of real time processing 109  Airline reservation systems  Theatre (cinema) booking  Hotel reservations CU IDOL SELF LEARNING MATERIAL (SLM)

 Banking systems  Police enquiry systems  Chemical processing plants  Hospitals to monitor the progress of a patient  Missile control systems Advantages  Provides up-to-date information  The information is readily available for instant decision-making  Provides better services to users/customers.  Fast &reliable  Reduces circulation of hardcopies. Disadvantages  Require complex Os & are very expensive  Not easy to develop  Real time systems usually use 2 or more processors to share the workloads, which is expensive.  Require large communication equipment. d. Distributed Processing This method is commonly utilized by remote workstations connected to one big central workstation or server. ATMs are good examples of this data processing method. All the end machines run on a fixed software located at a particular place and makes use of exactly same information and sets of instruction. 6.3.3 Control Program Control Instructions are the machine code that are used by machine or in assembly language by user to command the processor act accordingly. These instructions are of various types. These are used in assembly language by user also. But in level language, user code is translated into machine code and thus instructions are passed to instruct the processor do the task. Types of Program Control Instructions: There are different types of Program Control Instructions: 110 CU IDOL SELF LEARNING MATERIAL (SLM)

1. Compare Instruction Compare instruction is specifically provided, which is similar to a subtract instruction except the result is not stored anywhere, but flags are set according to the result. Example: CMP R1, R2; 2. Unconditional Branch Instruction It causes an unconditional change of execution sequence to a new location. Example: JUMP L2 Mov R3, R1 goto L2 3. Conditional Branch Instruction A conditional branch instruction is used to examine the values stored in the condition code register to determine whether the specific condition exists and to branch if it does. Example: Assembly Code: BE R1, R2, L1 Compiler allocates R1 for x and R2 for y High Level Code: if (x==y) goto L1; 4. Subroutines A subroutine is a program fragment that lives in user space, performs a well-defined task. It is invoked by another user program and returns control to the calling program when finished. Example: CALL and RET 5. Halting Instructions  NOP Instruction – NOP is no operation. It cause no change in the processor state other than an advancement of the program counter. It can be used to synchronize timing.  HALT – It brings the processor to an orderly halt, remaining in an idle state until restarted by interrupt, trace, reset or external action. 6. Interrupt Instructions Interrupt is a mechanism by which an I/O or an instruction can suspend the normal execution of processor and get itself serviced. 111 CU IDOL SELF LEARNING MATERIAL (SLM)

 RESET – It reset the processor. This may include any or all setting registers to an initial value or setting program counter to standard starting location.  TRAP – It is non-mask able edge and level triggered interrupt. TRAP has the highest priority and vectored interrupt.  INTR – It is level triggered and mask able interrupt. It has the lowest priority. It can be disabled by resetting the processor. 6.4 MEMORY REFERENCE In order to specify the micro operations needed for the execution of each instruction, it is necessary that the function that they are intended to perform be defined precisely. Some instructions have an ambiguous description. This is because the explanation of an instruction in words is usually lengthy, and not enough space is available in the table for such a lengthy explanation. We will now show that the function of the memory-reference instructions can be defined precisely by means of register transfer notation. The decoded D; for i = 0, 1, 2, 3, 4, 5, and 6 from the operation decoder that belongs to each instruction is included in the table. The effective address of the instruction is in the address register AR and was placed there during timing signal T2 when I = 0, or during timing signal T3 when I = 1. The execution of the memory-reference instructions starts with timing signal T4• The symbolic description of each instruction is specified in the table in terms of register transfer notation. The actual execution of the instruction in the bus system will require a sequence of micro operations. This is because data stored in memory cannot be processed directly. The data must be read from memory to a register where they can be operated on with logic circuits. We now explain the operation of each instruction and list the control functions and micro operations needed for their execution. A flowchart that summarizes all the micro operations is presented at the end of this section 112 CU IDOL SELF LEARNING MATERIAL (SLM)

Table 6.2: Memory reference instructions AND to AC This is an instruction that perform the AND logic operation on pairs of bits in AC and the memory word specified by the effective address. The result ofthe operation is transferred to AC. The micro operations that execute this instruction are: D0T4: DR <- M [AR] D0T5: AC <- AC /\\ DR, SC <--- 0 The control function for this instruction uses the operation decoder D0 since this output of the decoder is active when the instruction has an AND operation whose binary code value 000. Two timing signals are needed to execute the instruction. The clock transition associatedwith timing signal T4 transfers the operand from memory into DR. The clock transition associated with the next timing signal T5 transfers to AC the result of the AND logic operation between the contents of DR and AC. The same clock transition clears SC to 0, transferring control to timing signal T0 to start a new instruction cycle. ADD to AC This instruction adds the content of the memory word specified by the effective address to the value of AC. The sum is transferred into AC and the output carry Cout is transferred to the E (extended accumulator) flip-flop. The micro operations needed to execute this instruction are D1T4: DR← M [AR] D1T5: AC← AC + DR, E← Cout, SC ← 0 113 CU IDOL SELF LEARNING MATERIAL (SLM)

Same Two timing signals, T, and T5, are used again but with operation decoder D1 instead of D0, which was used for the AND instruction. After the instruction is fetched from memory and decoded, only one output of the operation decoder will be active, and that output determines the sequence of micro operations that the control follows during the execution of a memory-reference instruction. LDA: Load to AC This instruction transfers the memory word specified by the effective address to AC. The micro operations needed to execute this instruction are D2T4: DR← M [AR] D2T5: AC← DR, Looking back at the bus system shown in Fig. 5-4 we note that there is no direct path from the bus into AC. The adder and logic circuit receive information from DR which can be transferred into AC. Therefore, it is necessary to read the memory word into DR first and then transfer the content of DR into AC. The reason for not connecting the bus to the inputs of AC is the delay encountered in the adder and logic circuit. It is assumed that the time it takes to read from memory and transfer the word through the bus as well as the adder and logic circuit is more than the time of one clock cycle. By not connecting the bus to the inputs of AC we can maintain one clock cycle per microoperation. STA: Store AC This instruction stores the content of AC into the memory word specified by the effective address. Since the output of AC is applied to the bus and the data input of memory is connected to the bus, we can execute this instruction with one microoperation: D3T4: M [AR] ← AC, SC ← 0 BUN: Branch Unconditionally This instruction transfers the program to the instruction specified by the effective address. Remember that PC holds the address of the instruction to be read from memory in the next instruction cycle. PC is incremented at time T1 to prepare it for the address of the next instruction in the program sequence. The BUN instruction allows the programmer to specify an instruction out of sequence and we say that the program branches (or jumps) unconditionally. The instruction is executed with one microoperation: D4T4: PC ← AR, SC ← 0 The effective address from AR is transferred through the common bus to PC .Resetting SC to 0 transfers control to T0• The next instruction is then fetched and executed from the memory address given by the new value in PC. 114 CU IDOL SELF LEARNING MATERIAL (SLM)

BSA: Branch and Save Return Address This instruction is useful for branching to a portion of the program called a subroutine or procedure. When executed, the BSA instruction stores the address of the next instruction in sequence (which is available in PC) into a memory location specified by the effective address. The effective address plus one is then transferred to PC to serve as the address of the first instruction in the subroutine. This operation was specified with the following register transfer: M [AR] <-- PC, PC <-- AR + I A numerical example that demonstrates how this instruction is used with a subroutine is shown in Fig. 5-10. The BSA instruction is assumed to be in memory at address 20. The I bit is 0 and the address part of the instruction has the binary equivalent of 135. After the fetch and decode phases, PC contains 21, which is the address of the next instruction in the program (referred to as the return address). AR holds the effective address 135. This is shown in part (a) of the figure. The BSA instruction performs the following numerical operation: M [135] <-- 21, PC <-- 135 + 1 = 136 The result of this operation is shown in part (b) of the figure. The return address 21 is stored in memory location 135 and control continues with the subroutine program starting from address 136. The return to the original program (at address 21) is accomplished by means of an indirect BUN instruction placed at the end of the subroutine. When this instruction is executed, control goes to the indirect phase to read the effective address at location 135, where it finds the previously saved address 21. When the BUN instruction is executed, the effective address 21 is transferred to PC. The next instruction cycle finds PC with the value 21, so control continues to execute the instruction at the return address. ISZ: Increment and Skip if Zero This instruction increments the word specified by the effective address, and if the incremented value is equal to 0, PC is incremented by 1. The programmer usually stores a negative number (in 2's complement) in the memory word. As this negative number is repeatedly incremented by one, it eventually reaches the value of zero. At that time PC is incremented by one in order to skip the next instruction in the program. Since it is not possible to increment a word inside the memory, it is necessary to read the word into DR, increment DR, and store the word back into memory. This is done with the following sequence of micro operations: D6T4: DR <-- M [AR] D6T5: DR <-- DR + 1 D, T, M [AR] <-- DR, if (DR = 0) then (PC ← PC + 1), SC ← 0 115 CU IDOL SELF LEARNING MATERIAL (SLM)

Control Flowchart A flowchart showing all micro operations for the execution of the seven memory-reference instructions is shown in Fig. 5-11. The control functions are indicated on top of each box. The micro operations that are performed during time T4, T5, or T, depend on the operation code value. This is indicated in the flowchart by six different paths, one of which the control takes after the instruction is decoded. The sequence counter SC is cleared to 0 with the last timing signal in each case. This causes a transfer of control to time signal T0 to start the next instruction cycle. Note that we need only seven timing signals to execute the longest instruction (ISZ). The computer can be designed with a 3-bit sequence counter. The reason for using a 4-bit counter for SC is to provide additional timing signals for other instructions that are presented in the problems section. 6.5 I/O REFERENCE The I/O instructions of the 80386 provide access to the processor's I/O ports for the transfer of data to and from peripheral devices. These instructions have as one operand the address of a port in the I/O address space. There are two classes of I/O instruction:  Those that transfer a single item (byte, word, or double word) located in a register.  Those that transfer strings of items (strings of bytes, words, or double words) located in memory. These are known as \"string I/O instructions\" or \"block I/O instructions\". Register I/O Instructions The I/O instructions IN and OUT are provided to move data between I/O ports and the EAX (32-bit I/O), the AX (16-bit I/O), or AL (8-bit I/O) general registers. IN and OUT instructions address I/O ports either directly, with the address of one of up to 256 port addresses coded in the instruction, or indirectly via the DX register to one of up to 64K port addresses. IN (Input from Port) transfers a byte, word, or double word from an input port to AL, AX, or EAX. If a program specifies AL with the IN instruction, the processor transfers 8 bits from the selected port to AL. If a program specifies AX with the IN instruction, the processor transfers 16 bits from the port to AX. If a program specifies EAX with the IN instruction, the processor transfers 32 bits from the port to EAX. OUT (Output to Port) transfers a byte, word, or double word to an output port from AL, AX, or EAX. The program can specify the number of the port using the same methods as the IN instruction. 116 CU IDOL SELF LEARNING MATERIAL (SLM)

Figure 6.3: Memory Mapped I/O Block I/O Instructions The block (or string) I/O instructions INS and OUTS move blocks of data between I/O ports and memory space. Block I/O instructions use the DX register to specify the address of a port in the I/O address space. INS and OUTS use DX to specify:  8-bit ports numbered 0 through 65535  16-bit ports numbered 0, 2, 4, . . . , 65532, 65534  32-bit ports numbered 0, 4, 8, . . . , 65528, 65532 Block I/O instructions use either SI or DI to designate the source or destination memory address. For each transfer, SI or DI are automatically either incremented or decremented as specified by the direction bit in the flags register. INS and OUTS, when used with repeat prefixes, cause block input or output operations. REP, the repeat prefix, modifies INS and OUTS to provide a means of transferring blocks of data between an I/O port and memory. These block I/O instructions are string primitives (refer also to Chapter 3 for more on string primitives). They simplify programming and increase the speed of data transfer by eliminating the need to use a separate LOOP instruction or an intermediate register to hold the data. The string I/O primitives can operate on byte strings, word strings, or double word strings. After each transfer, the memory address in ESI or EDI is updated by 1 for byte operands, by 2 for word operands, or by 4 for double word operands. The value in the direction flag (DF) determines whether the processor automatically increments ESI or EDI (DF=0) or whether it automatically decrements these registers (DF=1). INS (Input String from Port) transfers a byte or a word string element from an input port to memory. The mnemonics INSB, INSW, and INSD are variants that explicitly specify the size 117 CU IDOL SELF LEARNING MATERIAL (SLM)

of the operand. If a program specifies INSB, the processor transfers 8 bits from the selected port to the memory location indicated by ES: EDI. If a program specifies INSW, the processor transfers 16 bits from the port to the memory location indicated by ES: EDI. If a program specifies INSD, the processor transfers 32 bits from the port to the memory location indicated by ES: EDI. The destination segment register choice (ES) cannot be changed for the INS instruction. Combined with the REP prefix, INS moves a block of information from an input port to a series of consecutive memory locations. OUTS (Output String to Port) transfers a byte, word, or double word string element to an output port from memory. The mnemonics OUTSB, OUTSW, and OUTSD are variants that explicitly specify the size of the operand. If a program specifies OUTSB, the processor transfers 8 bits from the memory location indicated by ES: EDI to the selected port. If a program specifies OUTSW, the processor transfers 16 bits from the memory location indicated by ES: EDI to the selected port. If a program specifies OUTSD, the processor transfers 32 bits from the memory location indicated by ES: EDI to the selected port. Combined with the REP prefix, OUTS moves a block of information from a series of consecutive memory locations indicated by DS: ESI to an output port. 6.6 REGISTER REFERENCE Register-reference instructions are recognized by the control when 07 = 1 and I = 0. These instructions use bits 0 through 11 of the instruction code to specify one of 12 instructions. These 12 bits are available in IR (0-11). They were also transferred to AR during time T2• These instructions are executed with the clock transition associated with timing variable T3• Each control function needs the Boolean relation D7I'T3, which we designate for convenience by the symbol r. The control function is distinguished by one of the bits in IR (0- 11). By assigning the symbol B, to bit i of IR, all control functions can be simply denoted by rB; For example, the instruction CLA has the hexadecimal code 7800, which gives the binary equivalent 011I 1000 0000 0000. The first bit is a zero and is equivalent to I'. The next three bits constitute the operation code and are recognized from decoder output D7• Bit 11 in IR is I and is recognized from 811• The control function that initiates the microoperation for this instruction is D7I'T3B11 = rB11• The execution of a register-reference instruction is completed at time T3• The sequence counter SC is cleared to 0 and the control goes back to fetch the next instruction with timing signal T0• The first seven register-reference instructions perform clear, complement, circular shift, and increment micro operations on the AC or E registers. The next four instructions cause a skip of the next instruction in sequence when a stated condition is satisfied. The skipping of the instruction is achieved by incrementing PC once again (in addition, it is being incremented during the fetch phase at time T1). The condition control statements must be recognized as part of the control conditions. The AC is positive when the sign bit in AC (IS) = 0; it is negative when AC (IS) = I. The content of AC is zero (AC = 0) if all the flip-flops of the 118 CU IDOL SELF LEARNING MATERIAL (SLM)

register are zero. The HLT instruction clears a start-stop flip-flop S and stops the sequence counter from counting. To restore the operation of the computer, the start-stop flip-flop must be set manually. 6.7 SUMMARY  Incomputer science, aninstruction set architecture(ISA), also calledcomputer architecture,is anabstract modelof acomputer. A device that executes instructions described by that ISA, such as acentral processing unit(CPU), is called animplementation.  In general, an ISA defines the supportedinstructionsanddata types, theregisters, the hardware support for managingmain memory, fundamental features (such as thememory consistency,addressing modes,virtual memory), and theinput/output model of a family of implementations of the ISA.  An ISA specifies the behaviour of machine code running on implementations of that ISA in a fashion that does not depend on the characteristics of that implementation, providing binary compatibility between implementations. This enables multiple implementations of an ISA that differ in performance, physical size, and monetary cost (among other things), but that are capable of running the same machine code, so that a lower-performance, lower-cost machine can be replaced with a higher-cost, higher-performance machine without having to replace software. It also enables the evolution of the microarchitectures of the implementations of that ISA, so that a newer, higher-performance implementation of an ISA can run software that runs on previous generations of implementations.  If an operating system maintains a standard and compatible application binary interface (ABI) for a particular ISA, machine code for that ISA and operating system will run on future implementations of that ISA and newer versions of that operating system. However, if an ISA supports running multiple operating systems, it does not guarantee that machine code for one operating system will run on another operating system, unless the first operating system supports running machine code built for the other operating system.  An ISA can be extended by adding instructions or other capabilities, or adding support for larger addresses and data values; an implementation of the extended ISA will still be able to execute machine code for versions of the ISA without those extensions. Machine code using those extensions will only run on implementations that support those extensions.  The binary compatibility that they provide make ISAs one of the most fundamental abstractions in computing. 119 CU IDOL SELF LEARNING MATERIAL (SLM)

 An instruction set architecture is distinguished from a microarchitecture, which is the set of processor design techniques used, in a particular processor, to implement the instruction set. Processors with different microarchitectures can share a common instruction set. For example, theIntelPentiumand theAdvanced Micro DevicesAthlonimplement nearly identical versions of thex86 instruction set, but have radically different internal designs.  The concept of an architecture, distinct from the design of a specific machine, was developed by Fred Brooks at IBM during the design phase of System/360.  Prior to NPL [System/360], the company's computer designers had been free to honour cost objectives not only by selecting technologies but also by fashioning functional and architectural refinements. The SPREAD compatibility objective, in contrast, postulated a single architecture for a series of five processors spanning a wide range of cost and performance. None of the five engineering design teams could count on being able to bring about adjustments in architectural specifications as a way of easing difficulties in achieving cost and performance objectives  Some virtual machines that support byte code as their ISA such as Smalltalk, the Java virtual machine, and Microsoft's Common Language Runtime, implement this by translating the byte code for commonly used code paths into native machine code. In addition, these virtual machines execute less frequently used code paths by interpretation (see: Just-in-time compilation). Trans meta implemented the x86 instruction set atop VLIW processors in this fashion. 6.8 KEYWORDS  RESET – It reset the processor. This may include any or all setting registers to an initial value or setting program counter to standard starting location.  TRAP – It is non-mask able edge and level triggered interrupt. TRAP has the highest priority and vectored interrupt.  INTR – It is level triggered and mask able interrupt. It has the lowest priority. It can be disabled by resetting the processor.  Block I/O Instructions - The block (or string) I/O instructions INS and OUTS move blocks of data between I/O ports and memory space. Block I/O instructions use the DX register to specify the address of a port in the I/O address space.  HALT – It brings the processor to an orderly halt, remaining in an idle state until restarted by interrupt, trace, reset or external action. 120 CU IDOL SELF LEARNING MATERIAL (SLM)

6.9 LEARNING ACTIVITY 1. Conduct a session on types of instructions. ___________________________________________________________________________ ___________________________________________________________________________ 2. Create a survey on memory reference and give feedback on it. ___________________________________________________________________________ ___________________________________________________________________________ 6.10 UNIT END QUESTIONS A. Descriptive Questions Short Questions 1. Define Instruction? 2. Write about types of instructions? 3. What is I/O Reference? 4. What is meant by memory reference? 5. What is data transfer? Long Questions 1. List and Explain types of instructions. 2. Explain the concept of data processing. 3. Discuss about control. 4. Explain I/O Reference. 5. List about memory reference. B. Multiple Choice Questions 1. What is the number of memory operands that are being supported by the typical ALU- instruction may be varying? a. 2 b. 3 c. 4 d. 5 2. What do Virtual memory consists of? 121 a. Static RAM CU IDOL SELF LEARNING MATERIAL (SLM)

b. Dynamic RAM c. Magnetic memory d. None of these 3. In a program using subroutine call instruction, what is necessary? a. Initialize program counter b. Clear the accumulator c. Reset the microprocessor d. Clear the instruction register 4. What do a Stack-organized Computer uses instruction of? a. Indirect addressing b. Two-addressing c. Zero addressing d. Index addressing 5. If the main memory is of 8K bytes and the cache memory is of 2K words. It uses associative mapping. What will be each word of cache memory? a. 11 bits b. 21 bits c. 16 bits d. 20 bits Answers 1-b, 2-a, 3-d, 4-c, 5-c 6.11REFERENCES References Book  Pugh, Emerson W.; Johnson, Lyle R.; Palmer, John H. (1991). IBM's 360 and Early 370 Systems. MIT Press. ISBN 0-262-16123-0.  ^ Crystal Chen; Greg Novick; Kirk Shimano (December 16, 2006). \"RISC Architecture: RISC vs. CISC\". cs.stanford.edu. Retrieved February 21, 2015.  ^ \"Forth Resources: NOSC Mail List Archive\". strangegizmo.com. Archived from the original on 2014-05-20. Retrieved 2014-07-25. 122 CU IDOL SELF LEARNING MATERIAL (SLM)

Textbook References  Bowen, Jonathan P. (July–August 1985). \"Standard Microprocessor Programming Cards\". Microprocessors and Microsystems. 9 (6): 274–290.  The evolution of RISC technology at IBM by John Cocke – IBM Journal of R&D, Volume 44, Numbers 1/2, p.48 (2000)  ^ Page, Daniel (2009). \"11. Compilers\". A Practical Introduction to Computer Architecture. Springer. p. 464. Bibcode: 2009pica.book.....P. ISBN 978-1-84882-255- 9.  ^ Venkat, Ashish; Tullsen, Dean M. (2014). Harnessing ISA Diversity: Design of a Heterogeneous-ISA Chip Multiprocessor. 41st Annual International Symposium on Computer Architecture. Website  https://www.tutorialspoint.com/what-is-data-transfer-instruction-process-in-computer- architecture  https://www.britannica.com/technology/data-processing  https://peda.net/kenya/ass/subjects2/computer-studies/form-3/data-processing 123 CU IDOL SELF LEARNING MATERIAL (SLM)

UNIT – 7: BASIC COMPUTER INSTRUCTIONS PART II STRUCTURE 7.0 Learning Objectives 7.1 Introduction 7.2 Instruction Cycle 7.3Instruction Formats 7.4 Direct and Indirect Address Instructions 7.5Zero Address 7.6 One Address 7.7 Two Address and Three Address Instructions 7.8 Summary 7.9 Keywords 7.10 Learning Activity 7.11 Unit End Questions 7.12 References 7.0 LEARNING OBJECTIVES After studying this unit, you will be able to:  Describe the Instruction Cycle.  Illustrate about Instruction Formats.  Explain the Direct and Indirect Address Instructions. 7.1 INTRODUCTION The instruction cycle is the process a microprocessor goes through to process an instruction. First, the microprocessor fetches or reads the instruction from the memory. Therefore it decodes the instruction, determining which instruction it has fetched. Finally, it implements the operations required to execute the instruction. Each of these functions including fetch, decode and execute contains a sequence of one or more operations. First, the microprocessor locates the address of the instruction on the address bus. The memory subsystem inputs this address and decodes it to access the desired memory locations. 124 CU IDOL SELF LEARNING MATERIAL (SLM)

After the microprocessor enables ample time for memory to decode the address and access the requested memory locations, the microprocessor asserts a READ control signal. The READ signal is ready to read information from the memory or an I/O device. Various processors have a specific name for this signal, but some microprocessors have a signal to implement this function. It relied upon the microprocessor, the READ signal can be active high (asserted=1) or active low (asserted = 0). When the READ signal is asserted, the memory subsystem installs the instruction code to be fetched onto the computer system’s data bus. The microprocessor then inputs this data from the data bus and saves it in one of its internal registers. Next, the microprocessor decodes the instruction. Each instruction can need multiple sequences of operations to perform the instruction. When the microprocessor decodes the instruction, it specifies which instruction it is to choose the right sequence of operations to implement. This is done perfectly within the microprocessor and it does not use the system buses. Finally, the microprocessor executes the instruction. The sequence of operations to execute the instruction change from instruction to instruction. The execute routine can read data from memory, write data to memory, read data from or write data to an I/O device, execute only operations inside the CPU, or perform some sequence of these operations. CLK − CLK stands for the computer system clock. The microprocessor uses the system clock to synchronize its operations. The microprocessor locates the address onto the bus at the starting of a clock cycle, a 0/1 sequence of the system clock. One clock cycle enables time for memory to decode the address and access its information;the microprocessor asserts the READ signal. This generates memory to locate its data onto the system data bus. During this clock cycle, the microprocessor reads the data of the system bus and saves it in one of its registers. At the end of the clock cycle, it eliminates the address from the address bus and desserts the READ signal. 7.2 INSTRUCTION CYCLE A program consisting of the memory unit of the computer includes a series of instructions. The program is implemented on the computer by going through a cycle for each instruction. In the basic computer, each instruction cycle includes the following procedures.  It can fetch instruction from memory.  It is used to decode the instruction.  It can read the effective address from memory if the instruction has an indirect address.  It can execute the instruction. 125 CU IDOL SELF LEARNING MATERIAL (SLM)

After the following four procedures are done, the control switches back to the first step and repeats the similar process for the next instruction. Therefore, the cycle continues until a Halt condition is met. The figure shows the phases contained in the instruction cycle. As display in the figure, the halt condition appears when the device receive turned off, on the circumstance of unrecoverable errors, etc. Figure 7.1: Instruction Cycle Fetch Cycle The address instruction to be implemented is held at the program counter. The processor fetches the instruction from the memory that is pointed by the PC. Next, the PC is incremented to display the address of the next instruction. This instruction is loaded onto the instruction register. The processor reads the instruction and executes the important procedures. Execute Cycle The data transfer for implementation takes place is as follows.  Processor-memory − The data sent from the processor to memory or from memory to processor.  Processor-Input/Output − The data can be transferred to or from a peripheral device by the transfer between a processor and an I/O device. In the execute cycle, the processor implements the important operations on the information, and consistently the control calls for the modification in the sequence of data implementation. These two methods associate and complete the execute cycle. State Diagram for Instruction Cycle The figure provides a large aspect of the instruction cycle of a basic computer, which is in the design of a state diagram. For an instruction cycle, various states can be null, while others can be visited more than once. 126 CU IDOL SELF LEARNING MATERIAL (SLM)

Figure 7.2: Instruction cycle state diagram  Instruction Address Calculation − The address of the next instruction is computed. A permanent number is inserted to the address of the earlier instruction.  Instruction Fetch − The instruction is read from its specific memory location to the processor.  Instruction Operation Decoding − The instruction is interpreted and the type of operation to be implemented and the operand(s) to be used are decided.  Operand Address Calculation − The address of the operand is evaluated if it has a reference to an operand in memory or is applicable through the Input/Output.  Operand Fetch − The operand is read from the memory or the I/O.  Data Operation − The actual operation that the instruction contains is executed.  Store Operands − It can store the result acquired in the memory or transfer it to the I/O. 7.3 INSTRUCTION FORMATS Computer perform task on the basis of instruction provided. A instruction in computer comprises of groups called fields. These field contains different information as for computers everything is in 0 and 1 so each field has different significance on the basis of which a CPU decide what so perform. The most common fields are  Operation field which specifies the operation to be performed like addition.  Address field which contain the location of operand, i.e., register or memory location. 127 CU IDOL SELF LEARNING MATERIAL (SLM)

 Mode field which specifies how operand is to be founded. A instruction is of various length depending upon the number of addresses it contain. Generally CPU organization are of three types on the basis of number of address fields: 1. Single Accumulator organization 2. General register organization 3. Stack organization In first organization operation is done involving a special register called accumulator. In second on multiple registers are used for the computation purpose. In third organization the work on stack basis operation due to which it does not contain any address field. It is not necessary that only a single organization is applied a blend of various organization is mostly what we see generally. On the basis of number of address instruction are classified as Note that we will use X = (A+B)*(C+D) expression to showcase the procedure. 7.4 DIRECT AND INDIRECT ADDRESS INSTRUCTIONS Direct Addressing Direct addressing means the instruction refers directly to the address being accessed. That is, the instruction encoding itself contains the address of the location. Depending on the instruction set, it may also allow computing a small index relative to the address. When used that way, you can think of that as a direct-indexed mode. (Note: Some processors call ‘direct’ mode ‘absolute’, such as the 6502.) Indirect Addressing Indirect addressing uses an address held in a register or other location to determine what memory location to read or write. The idea here is that the instruction itself isn’t directly telling you the address to access, but rather indirectly telling the CPU where to find that address. The processor may also allow you to add a small offset to the indirect address, giving an indirect-indexed addressing mode. 128 CU IDOL SELF LEARNING MATERIAL (SLM)

Figure 7.3: Difference between a direct and an indirect address instruction 7.5 ZERO ADDRESS Figure 7.4: Zero address A stack based computer do not use address field in instruction.To evaluate a expression first it is converted to revere Polish Notation i.e. Post fix Notation. Expression: X = (A+B)*(C+D) Postfixed: X = AB+CD+* TOP means top of stack 129 CU IDOL SELF LEARNING MATERIAL (SLM)

M[X] is any memory location PUSH A TOP = A PUSH B TOP = B ADD TOP = A+B PUSH C TOP = C PUSH D TOP = D ADD TOP = C+D MUL TOP = (C+D)*(A+B) POP X M[X] = TOP 7.6 ONE ADDRESS This use an implied ACCUMULATOR register for data manipulation. One operand is in accumulator and other is in register or memory location. Implied means that the CPU already know that one operand is in accumulator so there is no need to specify it. Figure 7.5: One address instruction Expression: X = (A+B)*(C+D) AC is accumulator M [] is any memory location M [T] is temporary location LOAD A AC = M[A] ADD B AC = AC + M[B] STORE T M[T] = AC LOAD C AC = M[C] ADD D AC = AC + M[D] MUL T AC = AC * M[T] 130 CU IDOL SELF LEARNING MATERIAL (SLM)

STORE X M[X] = AC 7.7 TWO ADDRESS AND THREE ADDRESS INSTRUCTIONS This is common in commercial computers. Here two address can be specified in the instruction. Unlike earlier in one address instruction the result was stored in accumulator here result can be stored at different location rather than just accumulator, but require a greater number of bit to represent address. Figure 7.6: Two address instruction Here destination address can also contain operand. Expression: X = (A+B)*(C+D) R1, R2 are registers M [] is any memory location MOV R1, A R1 = M[A] ADD R1, B R1 = R1 + M[B] MOV R2, C R2 = C ADD R2, D R2 = R2 + D MUL R1, R2 R1 = R1 * R2 MOV X, R1 M[X] = R1 Three Address Instructions This has three address field to specify a register or a memory location. Program created are much short in size but number of bits per instruction increase. These instructions make creation of program much easier but it does not mean that program will run much faster because now instruction only contain more information but each micro operation (changing content of register, loading address in address bus etc.) will be performed in one cycle only. 131 CU IDOL SELF LEARNING MATERIAL (SLM)

Figure 7.7: three address instruction ADD R1, A, B R1 = M[A] + M[B] ADD R2, C, D R2 = M[C] + M[D] MUL X, R1, R2 M[X] = R1 * R2 7.8 SUMMARY  The instruction cycle is the process a microprocessor goes through to process an instruction. First, the microprocessor fetches or reads the instruction from the memory. Therefore it decodes the instruction, determining which instruction it has fetched. Finally, it implements the operations required to execute the instruction. Each of these functions including fetch, decode and execute contains a sequence of one or more operations.  The READ signal is ready to read information from the memory or an I/O device. Various processors have a specific name for this signal, but some microprocessors have a signal to implement this function. It relied upon the microprocessor, the READ signal can be active high (asserted=1) or active low (asserted = 0).  Computer perform task on the basis of instruction provided. A instruction in computer comprises of groups called fields. These field contains different information as for computers everything is in 0 and 1 so each field has different significance on the basis of which a CPU decide what so perform.  Direct addressing means the instruction refers directly to the address being accessed. That is, the instruction encoding itself contains the address of the location. Depending on the instruction set, it may also allow computing a small index relative to the address. When used that way, you can think of that as a direct-indexed mode. (Note: Some processors call ‘direct’ mode ‘absolute’, such as the 6502.)  Indirect addressing uses an address held in a register or other location to determine what memory location to read or write. The idea here is that the instruction itself isn’t directly telling you the address to access, but rather indirectly telling the CPU where to find that address. The processor may also allow you to add a small offset to the indirect address, giving an indirect-indexed addressing mode. 132 CU IDOL SELF LEARNING MATERIAL (SLM)

7.9 KEYWORDS  Instruction cycle - The instruction cycle (also known as the fetch–decode–execute cycle, or simply the fetch-execute cycle) is the cycle that the central processing unit (CPU) follows from boot-up until the computer has shut down in order to process instructions.  Direct Addressing - When using direct addressing mode, the address of the operand is specified in the instruction. The processor will retrieve the data directly from the address specified in the instruction. In this figure, the example shows how the instruction tells the processor where to get the data from in memory.  Zero Address - It may for example enable stack processing: a zero-address instruction implies that the absolute address of the operand is held in a special register that is automatically incremented (or decremented) to point to the location of the top of the stack. A Dictionary of Computing. \"zero-address instruction.”  One Address Instruction - The instruction format in this type of computer uses one address field. For example, the instruction that specifies an arithmetic addition is defined by an assembly language instruction as ADD. Where X is the address of the operand. The ADD instruction in this case results in the operation AC ← AC + M[X].  Two-Address Instruction - Two-address instruction is a format of machine instruction. It has one opcode and two address fields. One address field is common and can be used for either destination or source and other address field for source. Example: X = (A + B) x (C + D) 7.10 LEARNING ACTIVITY 1. Discuss the topic on instruction cycle. ___________________________________________________________________________ __________________________________________________________________________ 2. Conduct a seminar on instruction format. ___________________________________________________________________________ __________________________________________________________________________ 7.11 UNIT END QUESTIONS A. Descriptive Questions 133 Short Questions 1. What is instruction cycle? 2. What is instruction format? CU IDOL SELF LEARNING MATERIAL (SLM)

3. What is zero address? 4. What is one address? 5. What is two address? Long Questions 1. What is instruction cycle? Explain. 2. What is zero address? Explain. 3. What is one address? Explain. 4. Explain the difference between direct and indirect address instruction. 5. Explain two and three address instruction. B. Multiple Choice Questions 1. What is a command given to a computer to perform a specified operation on some given data? a. An instruction b. Command c. Code d. None of these 2. What is an instruction is guided byto perform work? a. PC b. ALU c. Both a and b d. CPU 3. What is the source/destination of operands can be theory one of the general-purpose register? a. Memory b. One c. Both d. None of these 4. What is the sequence of operations performed by CPU in processing an instruction: a. Execute cycle b. Fetch cycle c. Decode 134 CU IDOL SELF LEARNING MATERIAL (SLM)

d. Instruction cycle 5. Select one of the following the instruction fetch operation is initiated by loading the contents of program counter into theand sendsrequest to memory? a. Memory register and read b. Memory register and write c. Data register and read d. Address register and read Answers 1-d, 2-d, 3-b, 4-c, 5-a. 7.12 REFERENCES References  John, P, Hayes. “Computer Architecture and organization”. McGraw Hill.  Dezso, Sima. Terence, Fountain&Peter, Kacsuk.“Advanced Computer Architecture” Pearson Education.  Kai, Hwang. “ Advanced Computer Architecture” TMH Textbooks  Das, Biplab. Paul, Avijit, Kumar&De, Debashis. (2019). \"An unconventional Arithmetic Logic Unit design and computing in Actin Quantum Cellular Automata\". Microsystem Technologies.  Linda, Null&Julia, Lobur. (2014). The Essentials of Computer Organization and Architecture.  Crystal, Chen. Greg, Novick&Kirk, Shimano. (2000). \"Pipelining\". Website  https://www.tutorialspoint.com  https://www.geeksforgeeks.org  https://www.computerscience.gcse.guru 135 CU IDOL SELF LEARNING MATERIAL (SLM)

UNIT – 8: INTERRUPT STRUCTURE 8.0 Learning Objectives 8.1 Introduction 8.2 Introduction to Interrupt 8.3 Types of Interrupts 8.3.1 Hardware Interrupts 8.3.2 Software Interrupts 8.4 Interrupt Cycle 8.5 Summary 8.6 Keywords 8.7 Learning Activity 8.8 Unit End Questions 8.9 References 8.0 LEARNING OBJECTIVES After studying this unit, you will be able to:  Explain the types of Interrupts.  Describe about interrupt cycle.  Elaborate software interrupts. 8.1 INTRODUCTION Normal execution of a given software application is contained within the bounds of one program, or instruction stream. Such execution is provable, as well as traceable. However, system designers and implementers also have to understand how breaks in program flow occur, and how they may affect the running program. Flow breaks fall into two general classes: Exceptions and traps are predictable, synchronous breaks in program flow. They are synchronous because they are caused by the execution of certain instructions (divide by zero; illegal memory access; software interrupt). Exceptions and traps trigger execution of instructions that are not part of the program, but perform work on behalf of it. 136 CU IDOL SELF LEARNING MATERIAL (SLM)

Interrupts are asynchronous breaks in program flow that occur as a result of events outside the running program. They are usually hardware related, stemming from events such as a button press, timer expiration, or completion of a data transfer. We can see from these examples that interrupt conditions are independent of particular instructions; they can happen at any time. Interrupts trigger execution of instructions that perform work on behalf of the system, but not necessarily the current program. This article explains how an interrupt is handled by the processor and software. Why interrupt? As a system's functional requirements and the size of the software grow, it becomes more difficult to ensure that time-critical items (such as capturing incoming data before it is overwritten by the hardware) are performed properly. We can approach this dilemma with a faster processor (more cost, more heat, and more radiated noise), or we can separate the time- critical functions from the others and execute them in a prioritized manner. Interrupts form the basis for this separation. The non-time-critical functions continue to execute as quickly as they can (within the main loop), but time-critical functions are executed on demand-in response to interrupts from the hardware. Hardware When a device asserts its interrupt request signal, it must be processed in an orderly fashion. All CPUs, and many devices, have some mechanism for enabling/disabling interrupt recognition and processing: At the device level, there is usually an interrupt control register with bits to enable or disable the interrupts that device can generate. At the CPU level, a global mechanism functions to inhibit/enable (often called the global interrupt enable) recognition of interrupts. Systems with multiple interrupt inputs provide the ability to mask (inhibit) interrupt requests individually and/or on a priority basis. This capability may be built into the CPU or provided by an external interrupt controller. Typically, there are one or more interrupt mask registers, with individual bits allowing or inhibiting individual interrupt sources. There is often also one non-mask able interrupt input to the CPU that is used to signal important conditions such as pending power fail, reset button pressed, or watchdog timer expiration. Figure shows an interrupt controller, two devices capable of producing interrupts, a processor, and the interrupt-related paths among them. The interrupt controller multiplexes multiple input requests into one output. It shows which inputs are active and allows individual inputs to be masked. Alternatively, it prioritizes the inputs, shows the highest active input, and provides a mask for inputs below a given level. The processor status register 137 CU IDOL SELF LEARNING MATERIAL (SLM)

has a global interrupt enable flag bit. In addition, a watchdog timer is connected to the non- mask able interrupt input. The interrupt software associated with a specific device is known as its interrupt service routine (ISR), or handler. Software Some older CPUs routed all interrupts to a single ISR. Upon recognizing an interrupt, the CPU saved some state information and started execution at a fixed location. The ISR at that location had to poll the devices in priority order to determine which one required service. However, the basic process of interrupt handling is the same as in the more complex case. Most modern CPUs use the same general mechanism for processing exceptions, traps, and interrupts: an interrupt vector table. Some CPU vector tables contain only the address of the code to be executed. In most cases, a specific ISR is responsible for servicing each interrupting device and acknowledging, clearing, and rearming its interrupt; in some cases, servicing the device (for example, reading data from a serial port) automatically clears and rearms the interrupt. Interrupts may occur at any time, but the CPU does not instantly recognize and process them immediately. First, the CPU will not recognize a new interrupt while interrupts are disabled. Second, the CPU must, upon recognition, stop fetching new instructions and complete those still in progress. Because the interrupt is totally unrelated to the running program it interrupts, the CPU and ISR work together to save and restore the full state of the interrupted program (stack, flags, registers, and so on). The running program is not affected by the interruption, although it takes longer to execute. The hardware and software flow for a timer interrupt is shown. Many interrupt controllers provide a means of prioritizing interrupt sources, so that, in the event of multiple interrupts occurring at (approximately) the same time, the more time- critical ones are processed first. These same systems usually also provide for prioritized interrupt handling, a means by which a higher-priority interrupt can interrupt the processing of a lower-priority interrupt. This is called interrupt nesting. In general, the ISR should only take care of the time-critical portion of the processing, then, depending on the complexity of the system, it may set a flag for the main loop, or use an operating system call to awaken a task to perform the non-time-critical portion. Latency The interrupt latency is the interval of time measured from the instant an interrupt is asserted until the corresponding ISR begins to execute. The worst-case latency for any given interrupt is a sum of many things, from longest to shortest: The longest period global interrupt recognition is inhibited 138 CU IDOL SELF LEARNING MATERIAL (SLM)

The time it would take to execute all higher priority interrupts if they occurred simultaneously. The time it takes the specific ISR to service all of its interrupt requests (if multiple are possible). The time it takes to finish the program instructions in progress and save the current program state and begin the ISR. We can see how higher-priority interrupts can have much lower latencies. In simple cases, latency can be calculated from instruction times, but many modern systems with 32-bit CPUs, caches, and multiple interrupt sources, are far too complex for exact latency calculations. Interrupt latency must be considered at design time, whenever responsiveness matters. 8.2 INTRODUCTION TO INTERRUPT An interrupt is the method of processing the microprocessor by peripheral device. An interrupt is used to cause a temporary halt in the execution of program. Microprocessor responds to the interrupt with an interrupt service routine, which is short program or subroutine that instructs the microprocessor on how to handle the interrupt. There are two basic type of interrupt, mask able and non-mask able, no mask able interrupt requires an immediate response by microprocessor, it usually used for serious circumstances like power failure. A mask able interrupt is an interrupt that the microprocessor can ignore depending upon some predetermined upon some predetermined condition defined by status register. Interrupt can divide to five groups: 1. Hardware interrupt 2. Non-mask able interrupts 3. Software interrupt 4. Internal interrupt 5. Reset Hardware, software and internal interrupt are service on priority basis. Each interrupt is given a different priority level by assign it a type number. Type 0 identifies the highest priority and type 255 identifies the lowest- priority interrupts. The 80x86 chips allow up to 256 vectored interrupts. This means that you can have up to 256 different sources for an interrupt and the 80x86 will directly call the service routine for that interrupt without any software processing. This is in contrast to no vectored interrupts that transfer control directly to a single interrupt service routine, regardless of the interrupt source. 139 CU IDOL SELF LEARNING MATERIAL (SLM)

The 80x86 provides a 256-entry interrupt vector table beginning at address 0:0 in memory. This is a 1K table containing 256 4-byte entries. Each entry in this table contains a segmented address that points at the interrupt service routine in memory. The lowest five types are dedicated to specific interrupts such as the divide by zero interrupt and the non-mask able interrupt. The next 27 interrupt types, from 5 to 31 are High priority 3 reserved by Intel for use in future microprocessors. The upper 224 interrupt types, from32 to 255, are available to use for hardware and software interrupts. When an interrupt occurs (shown in figure 8.1), regardless of source, the 80x86 does the following:  The CPU pushes the flags register onto the stack.  The CPU pushes a far return address (segment: offset) onto the stack, segment value first.  The CPU determines the cause of the interrupt (i.e., the interrupt number) and fetches the four byte interrupt vector from address 0: vector*4.  The CPU transfers control to the routine specified by the interrupt vector table entry. Processingofaninterrupt Figure 8.1: Processing of an interrupt 140 CU IDOL SELF LEARNING MATERIAL (SLM)

Figure 8.2: Algorithm 8.3 TYPES OF INTERRUPTS There are two types of interrupts in computer system architecture and they are: 8.3.1 Hardware Interrupts An electronic signal sent from an external device or hardware to communicate with the processor indicating that it requires immediate attention. For example, strokes from a keyboard or an action from a mouse invoke hardware interrupts causing the CPU to read and process it. So it arrives asynchronously and during any point of time while executing an instruction. Hardware interrupts are classified into two types  Mask able Interrupts – Processors have to interrupt mask register that allows enabling and disabling of hardware interrupts. Every signal has a bit placed in the mask register. If this bit is set, an interrupt is enabled & disabled when a bit is not set, or vice versa. Signals that interrupt the processors through these masks are referred to as masked interrupts. 141 CU IDOL SELF LEARNING MATERIAL (SLM)

 Non-mask able Interrupts (NMI) – The NMIs are the highest priority activities that need to be processed immediately and under any situation, such as a timeout signal generated from a watchdog timer. 8.3.2 Software Interrupts The processor itself requests a software interrupt after executing certain instructions or if particular conditions are met. These can be a specific instruction that triggers an interrupt such as subroutine calls and can be triggered unexpectedly because of program execution errors, known as exceptions or traps. Triggering Methods Generally, these signals are designed to trigger using either a logic signal level or a signal edge. These methods are of two types. Level-triggered Interrupt In this type, the input module invokes an interrupt if the service level of this is asserted. If an interrupt source continues to be asserted when the firmware interrupt handler handles it, this module regenerates and triggers the handler to invoke again. The level-triggered inputs are not good if remains asserted for a longer duration. Edge-triggered Interrupt An edge-triggered interrupt input module invokes an interrupt as soon as it identifies an asserting edge – a falling or a rising edge. The edge becomes noticed when the level of source changes. This type of triggering needs immediate action, irrespective of the activity of the source. Figure 8.3: Level-edge-triggering 142 CU IDOL SELF LEARNING MATERIAL (SLM)

System Implementation Interrupts shall be applied to hardware as a different component along with control lines, or integrated into memory subsystems. When implementation is performed in hardware, it needs a Programmable Interrupt Controller (PCI) to connect between the CPU’s input pin and the interrupting device. PCI multiplexes various sources of interrupt to the single or double CPU line. When implemented pertaining to the memory controller, the system’s memory address slot is mapped directly with the interrupts. Shared Interrupt Requests (IRQs) With edge-triggered interrupt, a pull-up or pull-down resistor is used to drive the interrupt line. This line transmits every pulse produced by each device. If interrupt pulses generated from different devices happen close in time, the CPU must invoke a trailing edge of the pulse to not to miss interrupts, following which CPU ensures to inspect every device for service requests. A well-behaved Industry Standard Architecture (ISA) motherboards with pull-up resistors having sharing IRQ lines must work fine. However, multiple devices sharing IRQ line in older systems with poorly designed programming interface makes it difficult to process interrupts. On the other hand, a new system architecture, such as PCI helps in providing considerable relief to this problem. Hybrid A hybrid type of system implementation has a combination of both edge-triggered and level- triggered signalling. The hardware shall look for an edge and also verifies that if a signal is active for a certain period. A hybrid type is commonly used for the non-mask able interrupt (NMI) input, which ensures that false interrupts do not affect the system. Message–Signalled A message-signalled interrupt request for service using device signals by transmitting a message over a communication channel, such as a computer bus. These do not use a physical interrupt line. PCI Express acts as a serial bus and is used exclusively as message-signalled interrupts. Doorbell The doorbell interrupt is commonly used as a mechanism by a software system to signal computer hardware to complete the work. Upon mutual agreement between hardware and software, the software places the data in the well-known memory location and rings the doorbell to notify the hardware that the data is ready and waiting to process. Now, the computer hardware device understands the data is valid and processes it accordingly. Multiprocessor IPI The multiprocessor systems, an interrupt request from a processor is sent to a different processor through inter-processor interrupts (IPI) 143 CU IDOL SELF LEARNING MATERIAL (SLM)

Typical Uses/Applications These are powerful inputs typically used to  Service hardware timers, handle keyboard strokes and mouse actions  Respond quickly to time-sensitive or real-time events  Data transfer to and from peripheral devices  Responds to high-priority tasks such as power-down signals, traps, and watchdog timers  Indicates abnormal events of CPU  Power-off interrupt foresees the loss of power, enabling orderly shut-down of the system  Periodic interrupts to keep track of absolute time 8.4 INTERRUPT CYCLE An instruction cycle (sometimes called fetch-and-execute cycle, fetch-decode-execute cycle, or FDX) is the basic operation cycle of a computer. It is the process by which a computer retrieves a program instruction from its memory, determines what actions the instruction requires, and carries out those actions. This cycle is repeated continuously by the central processing unit (CPU), from boot up to when the computer is shut down. Figure 8.4: Interrupt cycle Block diagram of Interrupt Cycle  After the execute cycle is completed, a test is made to determine if an interrupt was enabled (e.g. so that another process can access the CPU)  If not, instruction cycle returns to the fetch cycle  If so, the interrupt cycle might performs the following tasks: (simplified...) 144 CU IDOL SELF LEARNING MATERIAL (SLM)

 move the current value of PC into MBR  move the PC-save-address into MAR  move the interrupt-routine-address into PC  move the contents of the address in MBR into indicated memory cell  continue the instruction cycle within the interrupt routine  after the interrupt routine finishes, the PC-save-address is used to reset the value of PC and program execution can continue Figure 8.5: Algorithm of Interrupt Cycle 145 CU IDOL SELF LEARNING MATERIAL (SLM)

Dedicated interrupts of 8086 The following are the various types of interrupts:  Type 0 interrupts: This interrupt is also known as the divide by zero interrupt. For cases where the quotient becomes particularly large to be placed / adjusted an error might occur. - Type 1 interrupts: This is also known as the single step interrupt. This type of interrupt is primarily used for debugging purposes in assembly language.  Type 2 interrupts: also known as the non-mask able NMI interrupts. These type of interrupts are used for emergency scenarios such as power failure.  Type 3 interrupts: These type of interrupts are also known as breakpoint interrupts. When this interrupt occurs a program would execute up to its break point.  -Type 4 interrupts: Also known as overflow interrupts is generally existent after an arithmetic operation was performed. Interrupt Priority Structure Bios interrupts BIOSinterruptcalls are a facility that operating systems and application programs use to invoke the facilities of theBasic Input/output SystemonIBM PC compatiblecomputers. Traditionally, BIOS calls are mainly used byMS-DOSprograms and some other software such asboot loaders(including, mostly historically, relatively simple application software that boots directly and runs without an operating system—especially game software.) BIOS only runs in thereal address mode (Real Mode)of the x86 CPU, so programs that call BIOS either must also run in real mode or must switch from protected mode to real mode before calling BIOS and then switch back again. For this reason, modernoperating systemsthat use the CPU inProtected Modegenerally do not use the BIOS to support system functions, although some of them use the BIOS to probe and initialize hardware resources during their early stages ofbooting. In all computers, software instructions control the physical hardware (screen, disk, keyboard, etc.) from the moment the power is switched on. In a PC, the BIOS, preloaded in ROM on the main board, takes control immediately after the processor is reset, including during power-up or when a hardware reset button is pressed. The BIOS initializes the hardware, finds, loads and runs the boot program (usually, but not necessarily, an OS loader), and provides basic hardware control to the operating system running on the machine, which is usually an operating system but may be a directly booting single software application. For IBM's part, they provided all the information needed to use their BIOS fully or to directly utilize the hardware and avoid BIOS completely, when programming the early IBM PC models (prior to the PS/2). From the beginning, programmers had the choice of using BIOS or not, on a per-hardware-peripheral basis. Today, the BIOS in a new PC still supports most, if not all, of the BIOS interrupt function calls defined by IBM for theIBM AT, along with many more newer ones, plus extensions to some of the originals (e.g. expanded parameter 146 CU IDOL SELF LEARNING MATERIAL (SLM)

ranges). This, combined with a similar degree of hardware compatibility, means that most programs written for an IBM AT can still run correctly on a new PC today, assuming that the faster speed of execution is acceptable (which it typically is for all but games that use CPU- based timing). Despite the considerable limitations of the services accessed through the BIOS interrupts, they have proven extremely useful and durable to technological change. 8.5 SUMMARY  Interrupt is a signal emitted by hardware or software when a process or an event needs immediate attention. It alerts the processor to a high-priority process requiring interruption of the current working process. In I/O devices one of the bus control lines is dedicated for this purpose and is called the Interrupt Service Routine (ISR).  When a device raises an interrupt at let’s say process i, the processor first completes the execution of instruction i. Then it loads the Program Counter (PC) with the address of the first instruction of the ISR. Before loading the Program Counter with the address, the address of the interrupted instruction is moved to a temporary location. Therefore, after handling the interrupt the processor can continue with process i+1.  While the processor is handling the interrupts, it must inform the device that its request has been recognized so that it stops sending the interrupt request signal. Also, saving the registers so that the interrupted process can be restored in the future increases the delay between the time an interrupt is received and the start of the execution of the ISR. This is called Interrupt Latency.  In a hardware interrupt, all the devices are connected to the Interrupt Request Line. A single request line is used for all the n devices. To request an interrupt, a device closes its associated switch. When a device requests an interrupt, the value of INTR is the logical OR of the requests from individual devices.  When more than one device raises an interrupt request signal, then additional information is needed to decide which device to be considered first. The following methods are used to decide which device to select: Polling, Vectored Interrupts, and Interrupt Nesting.  Processors priority is encoded in a few bits of PS (Process Status register). It can be changed by program instructions that write into the PS. The processor is in supervised mode only while executing OS routines. It switches to user mode before executing application programs.  In digital computers, an interrupt is a response by the processor to an event that needs attention from the software. An interrupt condition alerts the processor and serves as a request for the processor to interrupt the currently executing code when permitted, so 147 CU IDOL SELF LEARNING MATERIAL (SLM)

that the event can be processed in a timely manner. If the request is accepted, the processor responds by suspending its current activities, saving its state, and executing a function called an interrupt handler (or an interrupt service routine, ISR) to deal with the event. This interruption is temporary, and, unless the interrupt indicates a fatal error, the processor resumes normal activities after the interrupt handler finishes.  Interrupts are commonly used by hardware devices to indicate electronic or physical state changes that require attention. Interrupts are also commonly used to implement computer multitasking, especially in real-time computing. Systems that use interrupts in these ways are said to be interrupt-driven. 8.6 KEYWORDS  Hardware - When a device asserts its interrupt request signal, it must be processed in an orderly fashion.  Software - Some older CPUs routed all interrupts to a single ISR.  Latency - The interrupt latency is the interval of time measured from the instant an interrupt is asserted until the corresponding ISR begins to execute.  Mask able Interrupts – Processors have to interrupt mask register that allows enabling and disabling of hardware interrupts. Every signal has a bit placed in the mask register. If this bit is set, an interrupt is enabled & disabled when a bit is not set, or vice versa. Signals that interrupt the processors through these masks are referred to as masked interrupts.  Non-mask able Interrupts (NMI) – The NMIs are the highest priority activities that need to be processed immediately and under any situation, such as a timeout signal generated from a watchdog timer. 8.7 LEARNING ACTIVITY 1. Conduct a session on types of interrupt. ___________________________________________________________________________ ___________________________________________________________________________ 2. Create a survey on Interrupt Cycle. ___________________________________________________________________________ ___________________________________________________________________________ 8.8 UNIT END QUESTIONS A. Descriptive Questions 148 CU IDOL SELF LEARNING MATERIAL (SLM)

Short Questions 1. Define Interrupt? 2. Write about types of interrupt? 3. What is Hardware Interrupts? 4. What is meant by Software Interrupts? 5. What is introduction on interrupt? Long Questions 1. List and Explain types of Interrupts. 2. Explain the concept of Interrupts. 3. Discuss about Interrupt Cycle. 4. Explain Software Interrupts. 5. List about Hardware Interrupts. B. Multiple Choice Questions 1. What is the interrupt-request line is a part of? a. Data line b. Control line c. Address line d. None of these 2. What is the return address from the interrupt-service routine is stored? a. System heap b. Processor register c. Processor stack d. Memory 3. What is the signal sent to the device from the processor to the device after receiving an interrupt? a. Interrupt-acknowledge b. Return signal c. Service signal d. Permission signal 4. What is the time between the receiver of an interrupt and its service? 149 CU IDOL SELF LEARNING MATERIAL (SLM)

a. Interrupt delay b. Interrupt latency c. Cycle time d. Switching time 5. Select the right option for the statement; Interrupts form an important part of systems. a. Batch processing b. Multitasking c. Real-time processing d. Multi-user Answers 1-b, 2-c, 3-a, 4-b, 5-c 8.9 REFERENCES References Book  Jonathan Corbet; Alessandro Rubini; Greg Kroah-Hartman (2005). \"Linux Device Drivers, Third Edition, Chapter 10. Interrupt Handling\" (PDF). O'Reilly Media.  Rosenthal, Scott (May 1995). \"Basics of Interrupts\". Archived from the original on 2016-04-26. Retrieved 2010-11-11.  \"Interrupt Instructions\". Control Data 3600 Computer System Reference Manual (PDF). Control Data Corporation. July 1964. p. 4-6. Textbook References  Bai, Ying (2017). Microcontroller Engineering with MSP432: Fundamentals and Applications. CRC Press. p. 21. ISBN 978-1-4987-7298-3. LCCN 2016020120  Li, Qing; Yao, Caroline (2003). Real-Time Concepts for Embedded Systems. CRC Press. p. 163. ISBN 1482280825.  Jake Edge (2010). \"Receive flow steering\". LWN.net. Retrieved November 16, 2014. Website  https://en.wikipedia.org/wiki/Interrupt  https://www.geeksforgeeks.org/interrupts/  https://waliamrinal.medium.com/what-are-interrupts-in-computer-organisation- e23a223b3f75 150 CU IDOL SELF LEARNING MATERIAL (SLM)