UNIT – 9: DESIGN OF CONTROL UNIT STRUCTURE 9.0 Learning Objectives 9.1 Introduction 9.2 Introduction to Control Unit 9.3 Types of Control Unit 9.3.1 Hardwired Control Unit 9.3.2 Micro Programmed Control Unit 9.4 Summary 9.5 Keywords 9.6 Learning Activity 9.7 Unit End Questions 9.8 References 9.0 LEARNING OBJECTIVES After studying this unit, you will be able to: Explain the types of Control unit. Describe about Hardwired Control Unit. ElaborateMicro programmed Control Unit. 9.1 INTRODUCTION The control unit (CU) is a component of a computer's central processing unit (CPU) that directs the operation of the processor. A CU typically uses a binary decoder to convert coded instructions into timing and control signals that direct the operation of the other units (memory, arithmetic logic unit and input and output devices, etc.). Most computer resources are managed by the CU. It directs the flow of data between the CPU and the other devices. John von Neumann included the control unit as part of the von Neumann architecture. In modern computer designs, the control unit is typically an internal part of the CPU with its overall role and operation unchanged since its introduction. The simplest computers use a multicycle microarchitecture. These were the earliest designs. They are still popular in the very smallest computers, such as the embedded systems that operate machinery. 151 CU IDOL SELF LEARNING MATERIAL (SLM)
In a multicycle computer, the control unit often steps through the Von Neumann Cycle: Fetch the instruction, Fetch the operands, do the instruction, write the results. When the next instruction is placed in the control unit, it changes the behaviour of the control unit to finish the instruction correctly. So, the bits of the instruction directly control the control unit, which in turn controls the computer. The control unit may include a binary counter to tell the control unit's logic what step it should do. Multicycle control units typically use both the rising and falling edges of their square-wave timing clock. They operate a step of their operation on each edge of the timing clock, so that a four-step operation completes in two clock cycles. Many computers have two different types of unexpected events. An interrupt occurs because some type of input or output needs software attention in order to operate correctly. An exception is caused by the computer's operation. One crucial difference is that the timing of an interrupt cannot be predicted. Another is that some exceptions (e.g. a memory-not- available exception) can be caused by an instruction that needs to be restarted. Control units can be designed to handle interrupts in one of two typical ways. If a quick response is most important, a control unit is designed to abandon work to handle the interrupt. In this case, the work in process will be restarted after the last completed instruction. If the computer is to be very inexpensive, very simple, very reliable, or to get more work done, the control unit will finish the work in process before handling the interrupt. Finishing the work is inexpensive, because it needs no register to record the last finished instruction. It is simple and reliable because it has the fewest states. It also wastes the least amount of work. Exceptions can be made to operate like interrupts in very simple computers. If virtual memory is required, then a memory-not-available exception must retry the failing instruction. It is common for multicycle computers to use more cycles. Sometimes it takes longer to take a conditional jump, because the program counter has to be reloaded. Sometimes they do multiplication or division instructions by a process something like binary long multiplication and division. Very small computers might do arithmetic one or a few bits at a time. Some computers have very complex instructions that take many steps. 9.2 INTRODUCTION TO CONTROL UNIT Control Unit is the part of the computer’s central processing unit (CPU), which directs the operation of the processor. It was included as part of the Von Neumann Architecture by John von Neumann. It is the responsibility of the Control Unit to tell the computer’s memory, arithmetic/logic unit and input and output devices how to respond to the instructions that have been sent to the processor. It fetches internal instructions of the programs from the main 152 CU IDOL SELF LEARNING MATERIAL (SLM)
memory to the processor instruction register, and based on this register contents, the control unit generates a control signal that supervises the execution of these instructions. A control unit works by receiving input information to which it converts into control signals, which are then sent to the central processor. The computer’s processor then tells the attached hardware what operations to perform. The functions that a control unit performs are dependent on the type of CPU because the architecture of CPU varies from manufacturer to manufacturer. Examples of devices that require a CU are: Control Processing Units(CPUs) Graphics Processing Units(GPUs) Figure 9.1: Block Diagram of the control unit Functions of the Control Unit It coordinates the sequence of data movements into, out of, and between a processor’s many sub-units. It interprets instructions. It controls data flow inside the processor. It receives external instructions or commands to which it converts to sequence of control signals. It controls many execution units (i.e. ALU, data buffers and registers) contained within a CPU. It also handles multiple tasks, such as fetching, decoding, execution handling and storing results. 153 CU IDOL SELF LEARNING MATERIAL (SLM)
9.3 TYPES OF CONTROL UNIT There are two types of control units: Hardwired control unit and Micro programmable control unit. 9.3.1 Hardwired Control Unit In the Hardwired control unit, the control signals that are important for instruction execution control are generated by specially designed hardware logical circuits, in which we cannot modify the signal generation method without physical change of the circuit structure. The operation code of an instruction contains the basic data for control signal generation. In the instruction decoder, the operation code is decoded. The instruction decoder constitutes a set of many decoders that decode different fields of the instruction opcode. As a result, few output lines going out from the instruction decoder obtains active signal values. These output lines are connected to the inputs of the matrix that generates control signals for executive units of the computer. This matrix implements logical combinations of the decoded signals from the instruction opcode with the outputs from the matrix that generates signals representing consecutive control unit states and with signals coming from the outside of the processor, e.g. interrupt signals. The matrices are built in a similar way as a programmable logic arrays. Figure 9.2: Block diagram of a hardwired control unit of a computer Control signals for an instruction execution have to be generated not in a single time point but during the entire time interval that corresponds to the instruction execution cycle. Following 154 CU IDOL SELF LEARNING MATERIAL (SLM)
the structure of this cycle, the suitable sequence of internal states is organized in the control unit. A number of signals generated by the control signal generator matrix are sent back to inputs of the next control state generator matrix. This matrix combines these signals with the timing signals, which are generated by the timing unit based on the rectangular patterns usually supplied by the quartz generator. When a new instruction arrives at the control unit, the control units is in the initial state of new instruction fetching. Instruction decoding allows the control unit enters the first state relating execution of the new instruction, which lasts as long as the timing signals and other input signals as flags and state information of the computer remain unaltered. A change of any of the earlier mentioned signals stimulates the change of the control unit state. This causes that a new respective input is generated for the control signal generator matrix. When an external signal appears, (e.g. an interrupt) the control unit takes entry into a next control state that is the state concerned with the reaction to this external signal (e.g. interrupt processing). The values of flags and state variables of the computer are used to select suitable states for the instruction execution cycle. The last states in the cycle are control states that commence fetching the next instruction of the program: sending the program counter content to the main memory address buffer register and next, reading the instruction word to the instruction register of computer. When the on- going instruction is the stop instruction that ends program execution, the control unit enters an operating system state, in which it waits for a next user directive. 9.3.2 Micro Programmed Control Unit The fundamental difference between these unit structures and the structure of the hardwired control unit is the existence of the control store that is used for storing words containing encoded control signals mandatory for instruction execution. In micro programmed control units, subsequent instruction words are fetched into the instruction register in a normal way. However, the operation code of each instruction is not directly decoded to enable immediate control signal generation but it comprises the initial address of a micro program contained in the control store. With a single-level control store In this, the instruction opcode from the instruction register is sent to the control store address register. Based on this address, the first microinstruction of a micro program that interprets execution of this instruction is read to the microinstruction register. This microinstruction contains in its operation part encoded control signals, normally as few bit fields. In a set microinstruction field decoders, the fields are decoded. The microinstruction also contains the address of the next microinstruction of the given instruction micro program and a control field used to control activities of the microinstruction address generator. 155 CU IDOL SELF LEARNING MATERIAL (SLM)
Figure 9.3: Micro programmed control unit with a single level control store The last mentioned field decides the addressing mode (addressing operation) to be applied to the address embedded in the on-going microinstruction. In microinstructions along with conditional addressing mode, this address is refined by using the processor condition flags that represent the status of computations in the current program. The last microinstruction in the instruction of the given micro program is the microinstruction that fetches the next instruction from the main memory to the instruction register. With a two-level control store In this, in a control unit with a two-level control store, besides the control memory for microinstructions, a Nano-instruction memory is included. In such a control unit, microinstructions do not contain encoded control signals. The operation part of microinstructions contains the address of the word in the Nano-instruction memory, which contains encoded control signals. The Nano-instruction memory contains all combinations of control signals that appear in micro programs that interpret the complete instruction set of a given computer, written once in the form of Nano-instructions. 156 CU IDOL SELF LEARNING MATERIAL (SLM)
Figure 9.4: Micro programmed control unit with a two-level store In this way, unnecessary storing of the same operation parts of microinstructions is avoided. In this case, microinstruction word can be much shorter than with the single level control store. It gives a much smaller size in bits of the microinstruction memory and, as a result, a much smaller size of the entire control memory. The microinstruction memory contains the control for selection of consecutive microinstructions, while those control signals are generated at the basis of Nano-instructions. In Nano-instructions, control signals are frequently encoded using 1 bit/ 1 signal method that eliminates decoding. 9.4 SUMMARY Popular variation on microcode is to debug the microcode using a software simulator. Then, the microcode is a table of bits. This is a logical truth table that translates a microcode address into the control unit outputs. This truth table can be fed to a computer program that produces optimized electronic logic. The resulting control unit is almost as easy to design as microprogramming, but it has the fast speed and low number of logic elements of a hard wired control unit. The practical result resembles a Mealy machine or Richards’s controller. Hardwired control units are implemented through use of combinational logic units, featuring a finite number of gates that can generate specific results based on the instructions that were used to invoke those responses. Hardwired control units are generally faster than the micro programmed designs. 157 CU IDOL SELF LEARNING MATERIAL (SLM)
This design uses a fixed architecture—it requires changes in the wiring if the instruction set is modified or changed. It can be convenient for simple, fast computers. A controller that uses this approach can operate at high speed; however, it has little flexibility. A complex instruction set can overwhelm a designer who uses ad hoc logic design. The hardwired approach has become less popular as computers have evolved. Previously, control units for CPUs used ad hoc logic, and they were difficult to design. The idea of microprogramming was introduced by Maurice Wilkes in 1951 as an intermediate level to execute computer program instructions. Micro programs were organized as a sequence of microinstructions and stored in special control memory. The algorithm for the micro program control unit, unlike the hardwired control unit, is usually specified byflowchartdescription. The main advantage of a micro programmed control unit is the simplicity of its structure. Outputs from the controller are by microinstructions. The micro program can be debugged and replaced very like software. A control unit can be designed to finish what it can. If several instructions can be completed at the same time, the control unit will arrange it. So, the fastest computers can process instructions in a sequence that can vary somewhat, depending on when the operands or instruction destinations become available. Most supercomputers and many PC CPUs use this method. The exact organization of this type of control unit depends on the slowest part of the computer. When the execution of calculations is the slowest, instructions flow from memory into pieces of electronics called \"issue units.\" An issue unit holds an instruction until both its operands and an execution unit are available. Then, the instruction and its operands are \"issued\" to an execution unit. The execution unit does the instruction. Then the resulting data is moved into a queue of data to be written back to memory or registers. If the computer has multiple execution units, it can usually do several instructions per clock cycle. It is common to have specialized execution units. For example, a modestly priced computer might have only one floating-point execution unit, because floating point units are expensive. The same computer might have several integer units, because these are relatively inexpensive, and can do the bulk of instructions. One kind of control unit for issuing uses an array of electronic logic, a \"scoreboard\" that detects when an instruction can be issued. The \"height\" of the array is the number of execution units, and the \"length\" and \"width\" are each the number of sources of 158 CU IDOL SELF LEARNING MATERIAL (SLM)
operands. When all the items come together, the signals from the operands and execution unit will cross. The logic at this intersection detects that the instruction can work, so the instruction is \"issued\" to the free execution unit. An alternative style of issuing control unit implements the Tomsula algorithm, which reorders a hardware queue of instructions. In some sense, both styles utilize a queue. The scoreboard is an alternative way to encode and reorder a queue of instructions, and some designers call it a queue table. With some additional logic, a scoreboard can compactly combine execution reordering, register renaming and precise exceptions and interrupts. Further it can do this without the power-hungry, complex content-addressable memory used by the Tomsula algorithm. If the execution is slower than writing the results, the memory write-back queue always has free entries. But what if the memory writes slowly? Or what if the destination register will be used by an \"earlier\" instruction that has not yet issued? Then the write-back step of the instruction might need to be scheduled. This is sometimes called \"retiring\" an instruction. In this case, there must be scheduling logic on the back end of execution units. It schedules access to the registers or memory that will get the results. Retiring logic can also be designed into an issuing scoreboard or a Tomsula queue, by including memory or register access in the issuing logic. Out of order controllers require special design features to handle interrupts. When there are several instructions in progress, it is not clear where in the instruction stream an interrupt occurs. For input and output interrupts, almost any solution works. However, when a computer has virtual memory, an interrupt occurs to indicate that a memory access failed. This memory access must be associated with an exact instruction and an exact processor state, so that the processor's state can be saved and restored by the interrupt. A usual solution preserves copies of registers until a memory access completes. Also, out of order CPUs have even more problems with stalls from branching, because they can complete several instructions per clock cycle, and usually have many instructions in various stages of progress. So, these control units might use all of the solutions used by pipelined processors. 9.5 KEYWORDS Microarchitecture - A microarchitecture is a hardware implementation of an ISA (instruction set architecture). 159 CU IDOL SELF LEARNING MATERIAL (SLM)
Embedded Systems - An embedded system is a microcontroller or microprocessor based system which is designed to perform a specific task. Instruction - When referring to the computer processor, instructions are a segment of code containing steps that need to be executed by the processor. Exceptions - In computer programming, an exception is a special condition encountered during program execution that is unexpected or anomalous. Architecture - Computer architecture is a specification detailing how a set of software and hardware technology standards interact to form a computer system or platform. In short, computer architecture refers to how a computer system is designed and what technologies it is compatible with. 9.6 LEARNING ACTIVITY 1. Conduct a session on types of control units. ___________________________________________________________________________ ___________________________________________________________________________ 2. Create a survey on control unit and give feedback. ___________________________________________________________________________ ___________________________________________________________________________ 9.7 UNIT END QUESTIONS A. Descriptive Questions 160 Short Questions 1. Definesingle-level control store? 2. Write about two-level control store? 3. What is Control Unit? 4. What is meant by Control storage? 5. What is Hardwired control unit? Long Questions 1. List and Explain types of Control Unit. 2. Explain the concept of Micro Programmed Control Unit. 3. Discuss about Introduction to Control Unit. 4. Explain Hardwired control unit. 5. List about design of control unit. CU IDOL SELF LEARNING MATERIAL (SLM)
B. Multiple Choice Questions 1. Which is the raw material used as input and is the processed data obtained as output of data processing? a. Data, Instructions b. Instructions, Program c. Data, Program d. Program, Code 2. Which of the following is not a characteristic of a computer? a. Diligence b. I.Q. c. Accuracy d. Versatility 3. What is the part of a processor which contains hardware necessary to perform all the operations required by a computer? a. Data path b. Controller c. Registers d. Cache 4. What does MAR stand for? a. Main Address Register b. Memory Access Register c. Main Accessible Register d. Memory Address Register 5. Which is the simplest method of implementing hardwired control unit? a. State Table Method b. Delay Element Method c. Sequence Counter Method d. Using Circuits Answers 1-a, 2-b, 3-a, 4-d, 5-a 161 CU IDOL SELF LEARNING MATERIAL (SLM)
9.8 REFERENCES References book Astha Singh (2019). \"Computer Organization - Control Unit and design\". GeeksforGeeks. Asanovic, Krste (2017). The RISC V Instruction Set Manual (PDF) (2.2 ed.). Berkeley: RISC-V Foundation. Power ISA 2017 (tm) (3.0B ed.). Austin: IBM... Retrieved 26 December 2019. Textbook References Alsup, Mitch; Leighton, Luke; Zaruba, Florian; Thornton, James; Kimmitt, Jonathon; Petrisko, Dan; Takano, S.; Falvo, Samuel. \"RISC-V HW Dev, 6600-style out-of-order scoreboard\". Google Groups. RISC-V Foundation. Retrieved 16 January 2020. Celio, Chris. \"BOOM Docs, Rocket ship SOC Generator\". Retrieved 16 January 2020. Introduction to MAXQ Architecture. Dallas: Maxim Integrated Inc. Retrieved 26 December 2019. Website https://www.geeksforgeeks.org/introduction-of-control-unit-and-its-design/ https://en.wikipedia.org/wiki/Control_unit https://www.javatpoint.com/design-of-control-unit 162 CU IDOL SELF LEARNING MATERIAL (SLM)
UNIT – 10: ADDRESSING MODES STRUCTURE 10.0 Learning Objectives 10.1 Introduction 10.2 Introduction to Addressing mode 10.3 Types of Addressing Modes 10.3.1 Immediate Mode 10.3.2 Direct (Absolute) Mode 10.3.3 Indirect Mode 10.3.4 Indexed Mode 10.3.5 Other Modes 10.4 Summary 10.5 Keywords 10.6 Learning Activity 10.7 Unit End Questions 10.8 References 10.0 LEARNING OBJECTIVES After studying this unit, you will be able to: Explain the types of Addressing Modes. Describe about Immediate Mode. Elaborate Indexed Mode. 10.1 INTRODUCTION The term addressing modes refers to the way in which the operand of an instruction is specified. Information contained in the instruction code is the value of the operand or the address of the result/operand. Following are the main addressing modes that are used on various platforms and architectures.Addressing modes are an aspect of the instruction set architecture in most central processing unit (CPU) designs. The various addressing modes that are defined in a given instruction set architecture define how the machine language instructions in that architecture identify the operand(s) of each instruction. An addressing 163 CU IDOL SELF LEARNING MATERIAL (SLM)
mode specifies how to calculate the effective memory address of an operand by using information held in registers and/or constants contained within a machine instruction or elsewhere. In computer programming, addressing modes are primarily of interest to those who write in assembly languages and to compiler writers. For a related concept see orthogonal instruction set which deals with the ability of any instruction to use any addressing mode. Note that there is no generally accepted way of naming the various addressing modes. In particular, different authors and computer manufacturers may give different names to the same addressing mode, or the same names to different addressing modes. Furthermore, an addressing mode which, in one given architecture, is treated as a single addressing mode may represent functionality that, in another architecture, is covered by two or more addressing modes. For example, some complex instruction set computer (CISC) architectures, such as the Digital Equipment Corporation (DEC) VAX, treat registers and literal or immediate constants as just another addressing mode. Others, such as the IBM System/360 and its successors, and most reduced instruction set computer (RISC) designs, encode this information within the instruction. Thus, the latter machines have three distinct instruction codes for copying one register to another, copying a literal constant into a register, and copying the contents of a memory location into a register, while the VAX has only a single \"MOV\" instruction. The term \"addressing mode\" is itself subject to different interpretations: either \"memory addresses calculation mode\" or \"operand accessing mode\". Under the first interpretation, instructions that do not read from memory or write to memory (such as \"add literal to register\") are considered not to have an \"addressing mode\". The second interpretation allows for machines such as VAX which use operand mode bits to allow for a register or for a literal operand. Only the first interpretation applies to instructions such as \"load effective address\". The addressing modes listed below are divided into code addressing and data addressing. Most computer architectures maintain this distinction, but there are (or have been) some architectures which allow (almost) all addressing modes to be used in any context. The instructions shown below are purely representative in order to illustrate the addressing modes, and do not necessarily reflect the mnemonics used by any particular computer. 10.2 INTRODUCTION TO ADDRESSING MODE The term addressing modes refers to the way in which the operand of an instruction is specified. The addressing mode specifies a rule for interpreting or modifying the address field of the instruction before the operand is actually executed. Addressing modes for 8086 instructions are divided into two categories 1. Addressing modes for data 2. Addressing modes for branch 164 CU IDOL SELF LEARNING MATERIAL (SLM)
The 8086 memory addressing modes provide flexible access to memory, allowing you to easily access variables, arrays, records, pointers, and other complex data types. The key to good assembly language programming is the proper use of memory addressing modes. An assembly language program instruction consists of two parts The memory address of an operand consists of two components: Starting address of memory segment. Effective address or Offset: An offset is determined by adding any combination of three address elements: displacement, base and index. Displacement: It is an 8 bit or 16 bit immediate value given in the instruction. Base: Contents of base register, BX or BP. Index: Content of index register SI or DI. According to different ways of specifying an operand by 8086 microprocessor, different addressing modes are used by 8086. 10.3 TYPES OF ADDRESSING MODES Different computer architectures vary greatly as to the number of addressing modes they provide in hardware. There are some benefits to eliminating complex addressing modes and using only one or a few simpler addressing modes, even though it requires a few extra instructions, and perhaps an extra register. It has provenmuch easier to design pipelined CPUs if the only addressing modes available are simple ones. 10.3.1 Immediate Mode In this mode data is present in address field of instruction .Designed like one address instruction format. Note: Limitation in the immediate mode is that the range of constants are restricted by size of address field. Figure 10.1: Immediate mode 165 CU IDOL SELF LEARNING MATERIAL (SLM)
Example: MOV AL, 35H (move the data 35H into AL register) 10.3.2 Direct (Absolute) Mode The operand’s offset is given in the instruction as an 8 bit or 16 bit displacement element. In this addressing mode the 16 bit effective address of the data is the part of the instruction. Here only one memory reference operation is required to access the data. Figure 10.2: Direct mode Example: ADD AL, [0301] //add the contents of offset address 0301 to AL 10.3.3 Indirect Mode In this mode address field of instruction contains the address of effective address.Here two references are required. 1st reference to get effective address. 2nd reference to access the data. Based on the availability of Effective address, Indirect mode is of two kind: Register Indirect: In this mode effective address is in the register, and corresponding register name will be maintained in the address field of an instruction. Here one register reference, one memory reference is required to access the data. Memory Indirect: In this mode effective address is in the memory, and corresponding memory address will be maintained in the address field of an instruction. Here two memory references is required to access the data. 10.3.4 Indexed Mode Auto Indexed (increment mode): Effective address of the operand is the contents of a register specified in the instruction. After accessing the operand, the contents of this register are automatically incremented to point to the next consecutive memory location. (R1)+. Here one register reference,one memory reference and one ALU operation is required to access the data. Example: Add R1, (R2) + // OR R1 = R1 +M [R2] R2 = R2 + d 166 CU IDOL SELF LEARNING MATERIAL (SLM)
Useful for stepping through arrays in a loop. R2 – start of array d – size of an element Auto indexed ( decrement mode): Effective address of the operand is the contents of a register specified in the instruction. Before accessing the operand, the contents of this register are automatically decremented to point to the previous consecutive memory location. –(R1) Here one register reference, one memory reference and one ALU operation is required to access the data. Example: Add R1,-(R2) //OR R2 = R2-d R1 = R1 + M [R2] Auto decrement mode is same as auto increment mode. Both can also be used to implement a stack as push and pop. Auto increment and Auto decrement modes are useful for implementing “Last-In-First-Out” data structures. 10.3.5 Other Modes Indexed addressing mode: The operand’s offset is the sum of the content of an index register SI or DI and an 8 bit or 16-bit displacement. Example AX, [SI +05] Based Indexed Addressing: The operand’s offset is sum of the content of a base register BX or BP and an index register SI or DI. Example: ADD AX, [BX+SI] Based on Transfer of control, addressing modes are PC relative addressing mode: PC relative addressing mode is used to implement intra segment transfer of control, In this mode effective address is obtained by adding displacement to PC. EA= PC + Address field value PC= PC + Relative value. Base register addressing mode: Base register addressing mode is used to implement inter segment transfer of control. In this mode effective address is obtained by adding base register value to address field value. EA= Base register + Address field value. PC= Base register + Relative value. 167 CU IDOL SELF LEARNING MATERIAL (SLM)
1. PC relative and based register both addressing modes are suitable for program relocation at runtime. 2. Based register addressing mode is best suitable to write position independent codes. Implied mode: In implied addressing the operand is specified in the instruction itself. In this mode the data is 8 bits or 16 bits long and data is the part of instruction. Zero address instruction are designed with implied addressing mode. Figure 10.3: Implied mode Example: CLC (used to reset Carry flag to 0) Immediate addressing mode (symbol #): In this mode data is present in address field of instruction. Designed like one address instruction format. Note:Limitation in the immediate mode is that the range of constants are restricted by size of address field. Figure 10.4: Immediate addressing mode Example: MOV AL, 35H (move the data 35H into AL register) Register mode: In register addressing the operand is placed in one of 8 bit or 16-bit general purpose registers. The data is in the register that is specified by the instruction. Here one register reference is required to access the data. Figure 10.5: Register mode 168 Example: MOV AX, CX (move the contents of CX register to AX register) CU IDOL SELF LEARNING MATERIAL (SLM)
Register Indirect mode: In this addressing the operand’s offset is placed in any one of the registers BX,BP,SI,DI as specified in the instruction. The effective address of the data is in the base register or an index register that is specified by the instruction. Here two register referencesare required to access the data. Figure 10.6: RegisterIndirect Mode The 8086 CPUs let you access memory indirectly through a register using the register indirect addressing modes. MOV AX, [BX] (move the contents of memory location s addressed by the register BX to the register AX) 10.4 SUMMARY The operation field of an instruction specifies the operation to be performed. And this operation must be performed on some data. So each instruction needs to specify data on which the operation is to be performed. But the operand (data) may be in accumulator, general purpose register or at some specified memory location. So, appropriate location (address) of data is needed to be specified, and in computer, there are various ways of specifying the address of data. These various ways of specifying the address of data are known as “Addressing Modes” So Addressing Modes can be defined as-“The technique for specifying the address of the operands “ And in computer the address of operand i.e., the address where operand is actually found is known as “Effective Address”. Now, in addition to this, the two most prominent reason of why addressing modes are so important are: First, the way the operand data are chosen during program execution is dependent on the addressing mode of the instruction. Second, the address field(or fields) in a typical instruction format are relatively small and sometimes we would like to be able to reference a large range of locations, so here to achieve this objective i.e., to fit this large range of location in address field, a 169 CU IDOL SELF LEARNING MATERIAL (SLM)
variety of addressing techniques has been employed. As they reduce the number of field in the addressing field of the instruction. Thus, Addressing Modes are very vital in Instruction Set Architecture (ISA). Now, before discussing various addressing modes, I will give her some notations that will use in throughout of this section. Although most Addressing modes need the address field of the instruction, but implied and immediate addressing modes are the only addressing modes that need no address field at all. Now we will discuss each of them in detail one by one. Implied Addressing Mode also known as \"Implicit\" or \"Inherent\" addressing mode is the addressing mode in which, no operand (register or memory location or data) is specified in the instruction. As in this mode the operand are specified implicit in the definition of instruction. 10.5 KEYWORDS Effective address or Offset: An offset is determined by adding any combination of three address elements. Displacement: It is an 8 bit or 16 bit immediate value given in the instruction. Implied mode: In implied addressing the operand is specified in the instruction itself. Immediate addressing mode: In this mode data is present in address field of instruction .Designed like one address instruction format. Register mode: In register addressing the operand is placed in one of 8 bit or 16 bit general purpose registers. The data is in the register that is specified by the instruction. 10.6 LEARNING ACTIVITY 1. Conduct a session on types of addressing modes. ___________________________________________________________________________ ___________________________________________________________________________ 2. Create a survey on indirect mode and give feedback on it. ___________________________________________________________________________ ___________________________________________________________________________ 170 CU IDOL SELF LEARNING MATERIAL (SLM)
10.7 UNIT END QUESTIONS A. Descriptive Questions Short Questions 1. DefineAddressing modes? 2. Write about Addressing modes for data? 3. What is addressing modes for branch? 4. What is meant by Indexed addressing mode? 5. What is implied mode? Long Questions 1. List and Explain Immediate Mode. 2. Explain the concept of Direct (Absolute) Mode. 3. Discuss about Indirect Mode. 4. Explain Indexed Mode. 5. List about Base register addressing mode. B. Multiple Choice Questions 1. How Addressing modes for 8086 instructions are divided into? a. Two categories b. Three categories c. Four categories d. Five categories 2. Which is the mode in which the operand is placed in one of 8 bit or 16-bit general purpose registers? a. Immediate addressing b. Register mode c. Implied addressing d. Register Indirect 3. Which is the mode in which the operand is specified in the instruction itself? 171 a. Immediate addressing b. Register mode c. Implied addressing CU IDOL SELF LEARNING MATERIAL (SLM)
d. Register Indirect 4. What is the addressing mode which makes use of in-direction pointers? a. Indirect addressing mode b. Index addressing mode c. Relative addressing mode d. Offset addressing mode 5. What is the addressing mode/s, which uses the PC instead of a general purpose register? a. Indexed with offset b. Relative c. Direct d. Both Indexed with offset and direct Answers 1-a, 2-b, 3-c, 4-a, 5-b 10.8 REFERENCES References Book John P Hayes “Computer Architecture and organization” McGraw Hill Dezso Sima, Terence Fountain and Peter Kacsuk “ Advanced Computer Architecture” Pearson Education Kai Hwang “ Advanced Computer Architecture” TMH Textbook Reference F. Chow; S. Carrell; M. Himmelstein; E. Killian; L. Weber (1987). \"How many addressing modes are enough?” John L. Hennessy; Mark A. Horowitz (1986). \"An Overview of the MIPS-X-MP Project\" (PDF). MIPS-X uses a single addressing mode: base register plus offset. This simple addressing mode allows the computation of the effective address to begin very early ... Dr. Jon Squire. \"Lecture 19, Pipelining Data Forwarding\". CS411 Selected Lecture Notes. Website https://www.geeksforgeeks.org/addressing-modes/ 172 CU IDOL SELF LEARNING MATERIAL (SLM)
https://www.studytonight.com/computer-architecture/addressingmodes- instructioncycle http://coagarage.blogspot.com/p/coa-addressing-modes.html 173 CU IDOL SELF LEARNING MATERIAL (SLM)
UNIT – 11: I/O ORGANIZATION STRUCTURE 11.0 Learning Objectives 11.1 Introduction 11.2 I/O Interface Units 11.3 Types of Ports 11.3.1 I/O Port 11.3.2 Network Port 11.3.3 USB Port 11.3.4 Serial Port 11.3.5 Parallel Port 11.4 Concept of I/O Bus 11.5 Isolated I/O versus Memory Mapped I/O 11.5.1 Difference Isolated I/O versus Memory Mapped I/O 11.6 Summary 11.7 Keywords 11.8 Learning Activity 11.9 Unit End Questions 11.10 References 11.0 LEARNING OBJECTIVES After studying this unit, you will be able to: Explain the types of ports. Describe about concept of I/O bus. Illustrate Isolated I/O versus Memory Mapped I/O. 11.1 INTRODUCTION The I/O subsystem of a computer provides an efficient mode of communication between the central system and the outside environment. It handles all the input output operations of the computer system. Peripheral Devices Input or output devices that are connected to computer 174 CU IDOL SELF LEARNING MATERIAL (SLM)
are called peripheral devices. These devices are designed to read information into or out of the memory unit upon command from the CPU and are considered to be the part of computer system. These devices are also called peripherals. For example: Keyboards, display units and printers are common peripheral devices. There are three types of peripherals: 1. Input peripherals: Allows user input, from the outside world to the computer. Example: Keyboard, Mouse etc. 2. Output peripherals: Allows information output, from the computer to the outside world. Example: Printer, Monitor etc 3. Input-Output peripherals: Allows both input (from outside world to computer) as well as, output (from computer to the outside world). Example: Touch screen etc. Interfaces Interface is a shared boundary between two separate components of the computer system which can be used to attach two or more components to the system for communication purposes. There are two types of interface: 1. CPU Interface 2. I/O Interface Let's understand the I/O Interface in details, Input-Output Interface Peripherals connected to a computer need special communication links for interfacing with CPU. In computer system, there are special hardware components between the CPU and peripherals to control or manage the input-output transfers. These components are called input-output interface units because they provide communication links between processor bus and peripherals. They provide a method for transferring information between internal system and input-output devices. The Input/output Interface is required because there are exists many differences between the central computer and each peripheral while transferring information. Some major differences are: 1. Peripherals are electromechanical and electromagnetic devices and their manner of operation is different from the operation of CPU and memory, which are electronic device. Therefore, a conversion of signal values may be required. 2. The data transfer rate of peripherals is usually slower than the transfer rate of CPU, and consequently a synchronisation mechanism is needed. 3. Data codes and formats in peripherals differ from the word format in the CPU and Memory. 4. The operating modes of peripherals are differing from each other and each must be controlled so as not to disturb the operation of other peripherals connected to CPU. These differences are resolved through input-output interface. As input-output interface (Interface Unit) contain various components, each of which performs one or more vital function for smooth transforming of information between CPU and Peripherals. Email ThisBlogThis! Share to Twitter Share to Facebook’s hare to Pinterest Input/output Channels a channel is an independent hardware component that co-ordinate all I/O to a set of controllers. Computer systems that use I/O channel have special hardware components that handle all I/O operations. Channels use separate, independent and low cost processors for its functioning which are called Channel Processors. Channel processors are simple, but contain sufficient memory to handle all I/O tasks. When I/O transfer is complete or an error is detected, the channel controller communicates with the CPU using an interrupt, and informs CPU about the error or the task completion. Each channel supports one or more controllers or devices. Channel programs contain list of commands to the channel itself and for various connected controllers or devices. Once the operating system has prepared a list of I/O commands, it executes a single I/O machine 175 CU IDOL SELF LEARNING MATERIAL (SLM)
instruction to initiate the channel program, the channel then assumes control of the I/O operations until they are completed. 11.2 I/O INTERFACE UNIT The method that is used to transfer information between internal storage and external I/O devices is known as I/O interface. The CPU is interfaced using special communication links by the peripherals connected to any computer system. These communication links are used to resolve the differences between CPU and peripheral. There exists special hardware components between CPU and peripherals to supervise and synchronize all the input and output transfers that are called interface units. Mode of Transfer The binary information that is received from an external device is usually stored in the memory unit. The information that is transferred from the CPU to the external device is originated from the memory unit. CPU merely processes the information but the source and target is always the memory unit. Data transfer between CPU and the I/O devices may be done in different modes. Data transfer to and from the peripherals may be done in any of the three possible ways Programmed I/O. Interrupt- initiated I/O. Direct memory access (DMA). Now let’s discuss each mode one by one. Programmed I/O: It is due to the result of the I/O instructions that are written in the computer program. Each data item transfer is initiated by an instruction in the program. Usually the transfer is from a CPU register and memory. In this case it requires constant monitoring by the CPU of the peripheral devices. Example of Programmed I/O: In this case, the I/O device does not have direct access to the memory unit. A transfer from I/O device to memory requires the execution of several instructions by the CPU, including an input instruction to transfer the data from device to the CPU and store instruction to transfer the data from CPU to memory. In programmed I/O, the CPU stays in the program loop until the I/O unit indicates that it is ready for data transfer. This is a time consuming process since it needlessly keeps the CPU busy. This situation can be avoided by using an interrupt facility. This is discussed below. Interrupt- initiated I/O: Since in the above case we saw the CPU is kept busy unnecessarily. This situation can very well be avoided by using an interrupt driven method for data transfer. By using interrupt facility and special commands to inform the interface to issue an interrupt request signal whenever data is available from any 176 CU IDOL SELF LEARNING MATERIAL (SLM)
device. In the meantime the CPU can proceed for any other program execution. The interface meanwhile keeps monitoring the device. Whenever it is determined that the device is ready for data transfer it initiates an interrupt request signal to the computer. Upon detection of an external interrupt signal the CPU stops momentarily the task that it was already performing, branches to the service program to process the I/O transfer, and then return to the task it was originally performing. Note: Both the methods programmed I/O and Interrupt-driven I/O require the active intervention of theprocessor to transfer data between memory and the I/O module, and any data transfer must transversea path through the processor. Thus both these forms of I/O suffer from two inherent drawbacks. The I/O transfer rate is limited by the speed with which the processor can test and service adevice. The processor is tied up in managing an I/O transfer; several instructions must be executedfor each I/O transfer. Direct Memory Access: The data transfer between a fast storage media such as magnetic disk and memory unit is limited by the speed of the CPU. Thus we can allow the peripherals directly communicate with each other using the memory buses, removing the intervention of the CPU. This type of data transfer technique is known as DMA or direct memory access. During DMA the CPU is idle and it has no control over the memory buses. The DMA controller takes over the buses to manage the transfer directly between the I/O devices and the memory unit. Figure 11.1: CPU bus signals for DMA transfer Bus Request: It is used by the DMA controller to request the CPU to relinquish the control of the buses. Bus Grant: It is activated by the CPU to inform the external DMA controller that the buses are in high impedance state and the requesting DMA can take control of the buses. Once the 177 CU IDOL SELF LEARNING MATERIAL (SLM)
DMA has taken the control of the buses it transfers the data. This transfer can take place in many ways. 11.3 TYPES OF PORTS There are 5 different types of ports: 11.3.1 I/O PORT Internal Port It connects the system’s motherboard to internal devices like hard-disk, CD drive, internal Bluetooth etc. External Port It connects the system’s motherboard to internal devices like mouse, printer, USB etc. Figure 11.2: Types of Port 178 CU IDOL SELF LEARNING MATERIAL (SLM)
11.3.2 Network Port A network port is a process-specific or an application-specific software construct serving as a communication endpoint, which is used by the Transport Layer protocols of Internet Protocol suite, such as User Diagram Protocol (UDP) and Transmission Control Protocol (TCP). A specific network port is identified by its number commonly referred to as port number, the IP address in which the port is associated with and the type of transport protocol used for the communication. A port number is a 16-bit unsigned integer that ranges from 0 to 65535. If you could consider all the addresses a computer processor could talk to as the address space, then certain addresses will have specialized purposes. For example, an address could be a memory address or another address could be a port address. A port address could be used to talk to external processes or devices. A port then, is simply a hole in the processor address space where data can be sent and received from. Any networking process or device uses a specific network port to transmit and receive data. This means that it listens for incoming packets whose destination port matches that port number, and/or transmits outgoing packets whose source port is set to that port number. Processes may use multiple network ports to receive and send data. The port numbers that range from 0 to 1023 are known as well-known port numbers. Well- known port numbers are allotted to standard server processes, such as FTP and Telnet. They are referenced by system processes providing widely used types of network services. Specific port numbers are assigned and recorded by the Internet Assigned Numbers Authority (IANA). However, in common practice, there is much unofficial use of both officially assigned numbers and unofficial numbers. Additionally, some network ports are in use for multiple applications and may be designated as either official or unofficial. 11.3.3 USB Port Universal Serial Bus (USB) is an industry standard that establishes specifications for cables and connectors and protocols for connection, communication and power supply (interfacing) between computers, peripherals and other computers. A broad variety of USB hardware exists, including eleven different connectors, of which USB-C is the most recent. Released in 1996, the USB standard is maintained by the USB Implementers Forum (USB- IF). There have been four generations of USB specifications: USB 1.x, USB 2.0, USB 3.x, and USB4. USB was designed to standardize the connection of peripherals to personal computers, both to communicate with and to supply electric power. It has largely replaced interfaces such as serial ports and parallel ports, and has become commonplace on a wide range of devices. 179 CU IDOL SELF LEARNING MATERIAL (SLM)
Examples of peripherals that are connected via USB include computer keyboards and mice, video cameras, printers, portable media players, mobile (portable) digital telephones, disk drives, and network adapters. USB connectors have been increasingly replacing other types as charging cables of portable devices. Objectives The Universal Serial Bus was developed to simplify and improve the interface between personal computers and peripheral devices, when compared with previously existing standard or ad hoc proprietary interfaces. From the computer user's perspective, the USB interface improves ease of use in several ways: The USB interface is self-configuring, eliminating the need for the user to adjust the device's settings for speed or data format, or configure interrupts, input/output addresses, or direct memory access channels. USB connectors are standardized at the host, so any peripheral can use most available receptacles. USB takes full advantage of the additional processing power that can be economically put into peripheral devices so that they can manage themselves. As such, USB devices often do not have user-adjustable interface settings. The USB interface is hot-swappable (devices can be exchanged without rebooting the host computer). Small devices can be powered directly from the USB interface, eliminating the need for additional power supply cables. Because use of the USB logo is only permitted after compliance testing, the user can have confidence that a USB device will work as expected without extensive interaction with settings and configuration. The USB interface defines protocols for recovery from common errors, improving reliability over previous interfaces. Installing a device that relies on the USB standard requires minimal operator action. When a user plugs a device into a port on a running computer, it either entirely automatically configures using existing device drivers, or the system prompts the user to locate a driver, which it then installs and configures automatically. The USB standard also provides multiple benefits for hardware manufacturers and software developers, specifically in the relative ease of implementation: 180 CU IDOL SELF LEARNING MATERIAL (SLM)
The USB standard eliminates the requirement to develop proprietary interfaces to new peripherals. The wide range of transfer speeds available from a USB interface suits devices ranging from keyboards and mice up to streaming video interfaces. A USB interface can be designed to provide the best available latency for time-critical functions or can be set up to do background transfers of bulk data with little impact on system resources. The USB interface is generalized with no signal lines dedicated to only one function of one device. 11.3.4 Serial Port In computing, a serial port is a serial communication interface through which information transfers in or out sequentially one bit at a time. This is in contrast to a parallel port, which communicates multiple bits simultaneously in parallel. Throughout most of the history of personal computers, data has been transferred through serial ports to devices such as modems, terminals, various peripherals, and directly between computers. While interfaces such as Ethernet, FireWire, and USB also send data as a serial stream, the term serial port usually denotes hardware compliant with RS-232 or a related standard, such as RS-485 or RS-422. Modern consumers PCs have largely replaced serial ports with higher-speed standards, primarily USB. However, serial ports are still frequently used in applications demanding simple, low-speed interfaces, such as industrial automation systems, scientific instruments, point of sale systems and some industrial and consumer products. Server computers may use a serial port as a control console for diagnostics, while networking hardware (such as routers and switches) commonly use serial console ports for configuration, diagnostics, and emergency maintenance access. To interface with these and other devices, USB-to-serial converters can quickly and easily add a serial port to a modern PC. Identifying a serial port In the above graphic of a serial port, you can notice the DB9 serial port connection is easy to identify. The connection is in the shape of the letter D, is a male connector, and has 9 pins. What is the serial port used for? Below is a listing of various hardware components that can be purchased and used with your serial port. Mouse - One of the most commonly used devices for serial ports, usually used with computers with no PS/2 or USB ports and specialty mice. 181 CU IDOL SELF LEARNING MATERIAL (SLM)
Modem - Another commonly used device for serial ports. Used commonly with older computers, however, is also commonly used for its ease of use. Network - One of the original uses of the serial port, which allowed two computers to connect together and allow large files to be transferred between the two. Printer - Today, this not a commonly used device for serial ports. However, was frequently used with older printers and plotters. Serial port pin information Below is a listing of each of the pins on the DB9 connector, their purpose, and signal name. Figure 11.3: USB Pin As shown above, pin one is in the top-left portion of the port and pin 9 is in the bottom right. Pin Purpose Signal Name 1 Data Carrier Detect DCD 2 Received Data RxData 3 Transmitted Data TX Data 4 Data Terminal Ready DTR 5 Signal Ground Gnd 6 Data Set Ready DSR 7 Request To Send RTS 182 CU IDOL SELF LEARNING MATERIAL (SLM)
8 Clear To Send CTS 9 Ring Indicator RI Table 11.1: PIN 11.3.5 Parallel Port Less commonly referred to as the Centronics interface, Centronics connector, or Centronics port after the company that originally designed it, the port was later developed by Epson. The parallel port is found on the back of IBM compatible computers and is a 25-pin (type DB-25) computer interface commonly used to connect printers to the computer. The parallel port is found on the back of the computer and is part of the motherboard. Below is an example of the DB25 interface found on the back of the computer? Figure 11.4: Parallel Port (DB25) Identifying a parallel port In the above picture, you can see the DB25 parallel port connection is easy to identify because it's the biggest connection on the back of the computer. The connection is in the shape of the letter D, is a female connector, and has 25 holes. Parallel port modes The computer is capable of having the parallel port run at different modes depending on your needs and available resources. Some of these modes include: IEEE-1284 (Auto), Centronics mode, Nibble Mode, SPP (unidirectional), bidirectional, EPP, and ECP. Parallel port overview The DB25 connector had an 8-bit data bus and a maximum cable length of 15-feet. Although there are 50 foot cables, it is not recommended that these cables be used as it can create poor connection and data signals. Below is additional information about each of the pins on this connector. Pin 1 through 25 identified in the image above. 183 CU IDOL SELF LEARNING MATERIAL (SLM)
Pin Purpose Pin 1 -Strobe Pin 2 +Data Bit 0 Pin 3 +Data Bit 1 Pin 4 +Data Bit 2 Pin 5 +Data Bit 3 Pin 6 +Data Bit 4 Pin 7 +Data Bit 5 Pin 8 +Data Bit 6 Pin 9 +Data Bit 7 Pin 10 -Acknowledge Pin 11 +Busy Pin 12 +Paper End Pin 13 +Select Pin 14 -Auto Feed Pin 15 -Error Pin 16 -Initialize Printer Pin 17 -Select Input Pin 18 -Data Bit 0 Return (GND) Pin 19 -Data Bit 1 Return (GND) Pin 20 -Data Bit 2 Return (GND) 184 CU IDOL SELF LEARNING MATERIAL (SLM)
Pin 21 -Data Bit 3 Return (GND) Pin 22 -Data Bit 4 Return (GND) Pin 23 -Data Bit 5 Return (GND) Pin 24 -Data Bit 6 Return (GND) Pin 25 -Data Bit 7 Return (GND) Table 11.2: Different types of Pins Below is an explanation of each of the above purposes. Pin1 - Data acknowledgement when the signal is low. Pin 2-9 - Data transfer pins. Pin 10 - Acknowledge that the data has finished processing and when the signal is high indicates ready for more. Pin 11 - When the signal goes high indicate that the printer has accepted the data and its being processed. Once this signal goes low and Pin 10 goes high, more data is ready to be accepted. Pin 12 - Printer paper jam when signal is high or no signal if printer jam. Pin 13 - When high signal printer is indicating that it is on-line and ready to print. Pin 14 - When low signal PC has indicated that the printer inset a line feed after each line. Pin 15 - Printer sends data to the computer telling it that an error has occurred. Pin 16 - When low signal PC has requested that the printer initiate an internal reset. Pin 17 - When low signal the PC has selected the printer and should in return prepare for data. Pin 18-25 - Ground. What is the parallel port used for? Today, the parallel port has widely been replaced by the USB port. However, below is a listing of various hardware components that were used with the parallel port. Printer - The most common use for the parallel port. Scanner - Another commonly used parallel device is a parallel port scanner. Parallel port scanners are a popular alternative to SCSI scanners because of how easy they are to install. 185 CU IDOL SELF LEARNING MATERIAL (SLM)
External drives - Parallel ports are popular with external drives such as the Iomega Zip drive, which can be removed from one computer and connected to another. Parallel ports on Apple computers The Apple Macintosh computers use SCSI as its interface, which is parallel, but a lot more flexible compared to the parallel port used with IBM compatible computers. Apple computers have never used a parallel port. 11.4 CONCEPT OF I/O BUS I/O bus networks allow PLCs to communicate with I/O devices in a manner similar to how local area networks let supervisory PLCs communicate with individual PLCs. This configuration decentralizes control in the PLC system, yielding larger and faster control systems. The topology, or physical architecture, of an I/O bus network follows the bus or extended bus (tree) configuration, which lets field devices (e.g., limit, photoelectric, and proximity switches) connect directly to either a PLC or to a local area network bus. Remember that a bus is simply a collection of lines that transmit data and/or power. A typical connection between a PLC, a local area network, and an I/O bus network. The basic function of an I/O bus network is to communicate information with, as well as supply power to, the field devices that are connected to the bus. In an I/O bus network, the PLC drives the field devices directly, without the use of I/O modules; therefore, the PLC connects to and communicates with each field I/O device according to the bus’s protocol. In essence, PLCs connect with I/O bus networks in a manner similar to the way they connect with remote I/O, except that PLCs in an I/O bus use an I/O bus network scanner. An I/O bus network scanner reads and writes to each field device address, as well as decodes the information contained in the network information packet. A large, tree topology bus network (i.e., a network with many branches) may have up to 2048 or more connected discrete field devices. The field devices that connect to I/O bus networks contain intelligence in the form of microprocessors or other circuits. These devices communicate not only the ON/OFF state of input and output controls, but also diagnostic information about their operating states. For example, a photoelectric sensor (switch) can report when its internal gain starts todecrease because of a dirty lens, or a limit switch can report the number of motions it has performed. This type of information can prevent I/O device malfunction and can indicate when a sensor has reached the end of its operating life, thus requiring replacement. 186 CU IDOL SELF LEARNING MATERIAL (SLM)
Figure 11.5: I/O bus network block diagram. 187 CU IDOL SELF LEARNING MATERIAL (SLM)
Figure 11.6: Connection between a PLC, a local area network, and an I/O bus network. To PLC Adapter ( I/O Bus Network Sc)anner I/O Bus Network Intelligent Connection to Photoelectric I/O Field Device Sensor Power Information Status Signal Figure 11.7: Connections for an I/O bus network. 188 CU IDOL SELF LEARNING MATERIAL (SLM)
Sensor’s Input Sensor Micro- Circuit controller/ Network Network Receive/ Chip Transmit Power In To I/O Bus To I/O Bus Network Network Figure 11.8: Intelligent field device. 11.5 ISOLATED I/O VERSUS MEMORY MAPPED I/O As a CPU needs to communicate with the various memory and input-output devices (I/O) as we know data between the processor and these devices flow with the help of the system bus. There are three ways in which system bus can be allotted to them: Separate set of address, control and data bus to I/O and memory. Have common bus (data and address) for I/O and memory but separate control lines. Have common bus (data, address, and control) for I/O and memory. In first case it is simple because both have different set of address space and instruction but require more buses. Isolated I/O Then we have Isolated I/O in which we Have common bus (data and address) for I/O and memory but separate read and write control lines for I/O. So when CPU decode instruction then if data is for I/O then it places the address on the address line and set I/O read or write control line on due to which data transfer occurs between CPU and I/O. As the address space of memory and I/O is isolated and the name is so. The address for I/O here is called ports. Here we have different read-write instruction for both I/O and memory. 189 CU IDOL SELF LEARNING MATERIAL (SLM)
Figure 11.9: Isolated I/O Memory Mapped I/O In this case every bus in common due to which the same set of instructions work for memory and I/O. Hence we manipulate I/O same as memory and both have same address space, due to which addressing capability of memory become less because some part is occupied by the I/O. Figure 11.10: Memory Mapped I/O 190 CU IDOL SELF LEARNING MATERIAL (SLM)
11.5.1 Difference Isolated I/O versus Memory Mapped I/O Isolated I/O Memory Mapped I/O Memory and I/O have separate address space Both have same address space All address can be used by the memory Due to addition of I/O addressable memory become less for memory Separate instruction control read and write Same instructions can control both I/O and operation in I/O and Memory Memory In this I/O address are called ports. Normal memory address is for both More efficient due to separate buses Lesser efficient Larger in size due to more buses Smaller in size It is complex due to separate logic is used to Simpler logic is used as I/O is also treated as control both. memory only. Table 11.3: Difference between Isolated and Memory Mapped I/O 11.6 SUMMARY The I/O subsystem of a computer provides an efficient mode of communication between the central system and the outside environment. It handles all the input- output operations of the computer system. Input or output devices that are connected to computer are called peripheral devices. These devices are designed to read information into or out of the memory unit upon command from the CPU and are considered to be the part of computer system. These devices are also called peripherals. Interface is a shared boundary between two separate components of the computer system which can be used to attach two or more components to the system for communication purposes. Peripherals connected to a computer need special communication links for interfacing with CPU. In computer system, there are special hardware components between the CPU and peripherals to control or manage the input-output transfers. These components are calledinput-output interface unitsbecause they provide 191 CU IDOL SELF LEARNING MATERIAL (SLM)
communication links between processor bus and peripherals. They provide a method for transferring information between internal system and input-output devices. Programmed I/O instructions are the result of I/O instructions written in computer program. Each data item transfer is initiated by the instruction in the program. Usually the program controls data transfer to and from CPU and peripheral. Transferring data under programmed I/O requires constant monitoring of the peripherals by the CPU. In the programmed I/O method the CPU stays in the program loop until the I/O unit indicates that it is ready for data transfer. This is time consuming process because it keeps the processor busy needlessly. This problem can be overcome by usinginterrupt initiated I/O. In this when the interface determines that the peripheral is ready for data transfer, it generates an interrupt. After receiving the interrupt signal, the CPU stops the task which it is processing and service the I/O transfer and then returns back to its previous processing task. Removing the CPU from the path and letting the peripheral device manage the memory buses directly would improve the speed of transfer. This technique is known as DMA. In this, the interface transfer data to and from the memory through memory bus. A DMA controller manages to transfer data between peripherals and memory unit. Many hardware systems use DMA such as disk drive controllers, graphic cards, network cards and sound cards etc. It is also used for intra chip data transfer in multicore processors. In DMA, CPU would initiate the transfer, do other operations while the transfer is in progress and receive an interrupt from the DMA controller when the transfer has been completed. 11.7 KEYWORDS Bus Request: It is used by the DMA controller to request the CPU to relinquish the control of the buses. Bus Grant: It is activated by the CPU to inform the external DMA controller that the buses are in high impedance state and the requesting DMA can take control of the buses. Internal Port: It connects the system’s motherboard to internal devices like hard- disk, CD drive, internal Bluetooth etc. External Port: It connects the system’s motherboard to internal devices like mouse, printer, USB etc. 192 CU IDOL SELF LEARNING MATERIAL (SLM)
Parallel Port Modes: The computer is capable of having the parallel port run at different modes depending on your needs and available resources. 11.8 LEARNING ACTIVITY 1. Conduct a session on I/O Interface Unit. ___________________________________________________________________________ ___________________________________________________________________________ 2. Create a survey on concept of I/O bus. ___________________________________________________________________________ ___________________________________________________________________________ 11.9 UNIT END QUESTIONS A. Descriptive Questions Short Questions 1. DefineInterface? 2. Write about types of ports? 3. What is Mode of Transfer? 4. What is meant by USB Port? 5. What is Parallel Port? Long Questions 1. List and Explain I/O Interface Unit. 2. Explain the concept of I/O bus. 3. Discuss about Isolated I/O versus Memory Mapped I/O. 4. Explain Serial Port. 5. List about Network Port. B. Multiple Choice Questions 1. What is the mode of transmission of data, where one bit is sent for each clock cycle? a. Asynchronous b. Parallel c. Serial d. Isochronous 193 CU IDOL SELF LEARNING MATERIAL (SLM)
2. What is the transformation between the Parallel and serial ports are done with the help of? a. Flip flops b. Logic circuits c. Shift registers d. None of these 3. Select the right option for the statement, the serial port is used to connect basically and processor. a. I/O devices b. Speakers c. Printer d. Monitor 4. What do the double buffer is used for? a. Enabling retrieval of multiple bits of input b. Combining the input and output operations c. Extending the buffer capacity d. None of these 5. How to increase the flexibility of the serial ports? a. The wires used for ports is changed b. The ports are made to allow different clock signals for input and output c. The drivers are modified d. All of these Answers 1-d, 2-c, 3-a, 4-a, 5-b 11.10 REFERENCES References Book Beal, Vangie (September 1996). \"Serial Port Definition & Meaning\". Webopedia. Retrieved 2021-03-08. Serial Cable Connection Guide\". CISCO. 2006-08-01. Retrieved 2016-01-31. 194 CU IDOL SELF LEARNING MATERIAL (SLM)
RS232 - DTE and DCE connectors\". Lantronix. 2006-03-29. Archived from the original on 2015-12-14. Retrieved 2016-01-31. Textbook References SERIAL_COMMPROP structure\". Microsoft. 2018-04-22. Archived from the original on 2019-09-28. Retrieved 2019-09-28. DCB Structure\". Windows Dev Centre. Microsoft. 2018-12-04. Archived from the original on 2019-09-28. Retrieved 2019-09-28. BACnet MS/TP Overview Manual\" (PDF). Neptronic. Archived from the original (PDF) on January 10, 2020. Retrieved September 26, 2019. Website https://www.tutorialspoint.com/basics_of_computers/basics_of_computers_io_ports.h tm https://www.geeksforgeeks.org/input-output-ports/ https://www.techopedia.com/definition/24717/network-port 195 CU IDOL SELF LEARNING MATERIAL (SLM)
UNIT – 12: I/O DATA TRANSFER TECHNIQUES STRUCTURE 12.0 Learning Objectives 12.1 Introduction 12.2 Programmed I/O 12.3Interrupt Initiated I/O 12.4 DMA Controller and IOP 12.4.1 Difference between DMA Controller and IOP 12.5 Summary 12.6 Keywords 12.7 Learning Activity 12.8 Unit End Questions 12.9 References 12.0 LEARNING OBJECTIVES After studying this unit, you will be able to: Explain the Programmed I/O. Describe about DMA Controller. Illustrate Interrupt Initiated I/O. 12.1 INTRODUCTION Data from Peripherals must reach Memory so that the CPU can use it. Similarly, the processed output has to reach peripherals like printer, internet devices, DISK, etc. Thus, I/O data transfer is about how the three subsystems i.e. CPU, Memory and I/O Controller, are involved in achieving the data exchange with peripherals. The word Data Exchange means successful Data in/Data Out with necessary handshake and coordination. Data Exchange with a peripheral involves few steps and not straight forward as devices are mostly electromechanical and/or operate at a different speed than CPU and Memory. The device to be initiated and checked for status whether it is ready for Data Exchange. 196 CU IDOL SELF LEARNING MATERIAL (SLM)
The data transfer has to happen at the acceptable capsule and speed of the device using the applicable protocol. This may happen in more than one sequence, as necessitated. If the device status is an Error status, it is to be suitably handled. I/O Controller's role is to ensure seamless data exchange by ensuring the following Processor/Memory Communication Device Communication Control timing and Status processing – Coordination of the data traffic between CPU, Memory and Io devices Data Buffering – To manage the data transfer speed mismatch Error management ( Transmission errors are corrected other status errors are communicated) 12.2 PROGRAMMED I/O Programmed input–output (also programmed input/output, programmed I/O, PIO) is a method of data transmission, via input/output (I/O), between a central processing unit (CPU) and a peripheral device, such as a network adapter or a Parallel ATA storage device. Each data item transfer is initiated by an instruction in the program, involving the CPU for every transaction. In contrast, in direct memory access (DMA) operations, the CPU is uninvolved in the data transfer. The term can refer to either memory-mapped I/O (MMIO) or port-mapped I/O (PMIO). PMIO refers to transfers using a special address space outside of normal memory, usually accessed with dedicated instructions, such as IN and OUT in x86 architectures. MMIO refers to transfers to I/O devices that are mapped into the normal address space available to the program. PMIO was very useful for early microprocessors with small address spaces, since the valuable resource was not consumed by the I/O devices. The best known example of a PC device that uses programmed I/O is the AT Attachment (ATA) interface; however, this interface can also be operated in any of several DMA modes. Many older devices in a PC also use PIO, including legacy serial ports, legacy parallel ports when not in ECP mode, keyboard and mouse PS/2 ports, legacy Musical Instrument Digital Interface (MIDI) and joystick ports, the interval timer, and older network interfaces. The PIO interface is grouped into different modes that correspond to different transfer rates. The electrical signalling among the different modes is similar — only the cycle time between transactions is reduced in order to achieve a higher transfer rate. All ATA devices support the slowest mode — Mode 0. By accessing the information registers (using Mode 0) on an ATA 197 CU IDOL SELF LEARNING MATERIAL (SLM)
drive, the CPU is able to determine the maximum transfer rate for the device and configure the ATA controller for optimal performance. The PIO modes require a great deal of CPU overhead to configure a data transaction and transfer the data. Because of this inefficiency, the DMA (and eventually Ultra Direct Memory Access (UDMA) interface was created to increase performance. The simple digital logic needed to implement a PIO transfer still makes this transfer method useful today, especially if high transfer rates are unneeded as in embedded systems, or with field-programmable gate array (FPGA) chips, where PIO mode can be used with no significant performance loss. Two additional advanced timing modes have been defined in the CompactFlash specification 2.0. Those are PIO modes 5 and 6. They are specific to CompactFlash. Mode Maximum transfer rate Minimum cycle Standard where spec is defined (MB/s) time Mode 0 3.3 600 ns ATA-1 Mode 1 5.2 383 ns ATA-1 Mode 2 8.3 240 ns ATA-1 Mode 3 11.1 180 ns ATA-2 Mode 4 16.7 120 ns ATA-2 Mode 5 20 100 ns CompactFlash 2.0 Mode 6 25 80 ns CompactFlash 2.0 Table 12.1: PIO modes PIO Mode 5 A PIO Mode 5 was proposedwith operation at 22 MB/s, but was never implemented on hard disks because CPUs of the time would have been crippled waiting for the hard disk at the proposed PIO 5 timings, and the DMA standard ultimately obviated it. While no hard disk drive was ever manufactured to support this mode, some motherboard manufacturers pre- emptively provided BIOS support for it. PIO Mode 5 can be used with CompactFlash cards connected to ATA via CF-to-ATA adapters. 198 CU IDOL SELF LEARNING MATERIAL (SLM)
12.3 INTERRUPT INITIATED I/O interrupt I/O A way of controlling input/output activity in which a peripheral or terminal that needs to make or receive a data transfer sends a signal that causes a program interrupt to be set. At a time, appropriate to the priority level of the I/O interrupt, relative to the total interrupt system, the processor enters an interrupt service routine (ISR). The function of the routine will depend upon the system of interrupt levels and priorities that is implemented in the processor. In a single-level single-priority system there is only a single I/O interrupt – the logical OR of all the connected I/O devices. The associated interrupt service routine polls the peripherals to find the one with the interrupt status set.In a multilevel single-priority system there is a single interrupt signal line and several device identification lines. When a peripheral raises the common interrupt line it also sets its unique code on the identification lines. This system is more expensive to implement but speeds the response.In a single-level multiple-priority system the interrupt lines of the devices are logically connected to a single processor interrupt in such a way that an interrupt from a high-priority device masks that of lower-priority devices. The processor polls the devices, in priority order, to identify the interrupting device. A multilevel multiple-priority system has both the property of masking interrupts according to priority and of immediate identification via identification lines. Programmed I/O In this mode the data transfer is initiated by the instructions written in a computer program. An input instruction is required to store the data from the device to the CPU and a store instruction is required to transfer the data from the CPU to the device. Data transfer through this mode requires constant monitoring of the peripheral device by the CPU and also monitor the possibility of new transfer once the transfer has been initiated. Thus CPU stays in a loop until the I/O device indicates that it is ready for data transfer. Thus programmed I/O is a time consuming process that keeps the processor busy needlessly and leads to wastage of the CPU cycles. This can be overcome by the use of an interrupt facility. This forms the basis for the Interrupt Initiated I/O. Interrupt Initiated I/O This mode uses an interrupt facility and special commands to inform the interface to issue the interrupt command when data becomes available and interface is ready for the data transfer. In the meantime CPU keeps on executing other tasks and need not check for the flag. When the flag is set, the interface is informed and an interrupt is initiated. This interrupt causes the CPU to deviate from what it is doing to respond to the I/O transfer. The CPU responds to the signal by storing the return address from the program counter (PC) into the memory stack and then branches to service that processes the I/O request. After the transfer is complete, CPU 199 CU IDOL SELF LEARNING MATERIAL (SLM)
returns to the previous task it was executing. The branch address of the service can be chosen in two ways known as vectored and non-vectored interrupt. In vectored interrupt, the source that interrupts, supplies the branch information to the CPU while in case of non-vectored interrupt the branch address is assigned to a fixed location in memory. Difference between Programmed and Interrupt Initiated I/O Programmed I/O Interrupt Initiated I/O Data transfer is initiated by the means of The I/O transfer is initiated by the instructions stored in the computer program. interrupt command issued to the CPU. Whenever there is a request for I/O transfer the instructions are executed from the program. The CPU stays in the loop to know if the device There is no need for the CPU to stay is ready for transfer and must continuously in the loop as the interrupt command monitor the peripheral device. interrupts the CPU when the device is ready for data transfer. This leads to the wastage of CPU cycles as CPU The CPU cycles are not wasted as remains busy needlessly and thus the efficiency CPU continues with other work during of system gets reduced. this time and hence this method is more efficient. CPU cannot do any work until the transfer is CPU can do any other work until it is complete as it must stay in the loop to interrupted by the command continuously monitor the peripheral device. indicating the readiness of device for data transfer Its module is treated as a slow module. Its module is faster than programmed I/O module. It is quite easy to program and understand. It can be tricky and complicated to understand if one uses low level language. 200 CU IDOL SELF LEARNING MATERIAL (SLM)
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