เล่มประชุมกรรมการครั้งที่ 2_2564 แก้ไขเพิ่มเติม

บทความวจิ ยั ที่ 1 (วารสาร) 18 4. การใช้รปู ภาพ/กราฟ บทความวจิ ยั ท่ี 2 (วารส 4. การใชร้ ปู ภาพ/กราฟ

89 สาร) คาอธิบายเพ่ิมเติม (ถ้าม)ี ฟ

บทความวจิ ยั ที่ 1 (วารสาร) 19 4. การใช้รปู ภาพ/กราฟ บทความวจิ ยั ท่ี 2 (วารส 4. การใชร้ ปู ภาพ/กราฟ

90 สาร) คาอธิบายเพ่ิมเติม (ถ้าม)ี ฟ

บทความวจิ ยั ที่ 1 (วารสาร) 19 4. การใช้รปู ภาพ/กราฟ บทความวจิ ยั ท่ี 2 (วารส 4. การใชร้ ปู ภาพ/กราฟ

91 สาร) คาอธิบายเพ่ิมเติม (ถ้าม)ี ฟ

บทความวิจยั ที่ 1 (วารสาร) 19 5. การใช้ตาราง บทความวิจัยที่ 2 (วารส 5. การใชต้ าราง

92 สาร) คาอธบิ ายเพ่มิ เตมิ (ถา้ ม)ี

บทความวิจยั ที่ 1 (วารสาร) 19 5. การใช้ตาราง บทความวิจัยที่ 2 (วารส 5. การใชต้ าราง

93 สาร) คาอธบิ ายเพ่มิ เตมิ (ถา้ ม)ี

บทความวิจยั ที่ 1 (วารสาร) 19 5. การใช้ตาราง บทความวิจัยที่ 2 (วารส 5. การใชต้ าราง

94 สาร) คาอธบิ ายเพ่มิ เตมิ (ถา้ ม)ี

บทความวิจยั ที่ 1 (วารสาร) 19 5. การใช้ตาราง บทความวิจัยที่ 2 (วารส 5. การใชต้ าราง

95 สาร) คาอธบิ ายเพ่มิ เตมิ (ถา้ ม)ี

บทความวิจยั ท่ี 1 (วารสาร) 19 5. การใช้ตาราง บทความวิจัยที่ 2 (วารส 5. การใช้ตาราง 6. การอ้างอิง 6. การอ้างองิ [2] Olorunfemi Ojo, The Generalized Discontinuous PWM Modulation [1] Holmes, D.G., Ko Scheme for Three-Phase Voltage Source Inverters, IEEE Transactions of Single and Two P on industrial electronics, (2004), VOL. 51, NO. 6, 1280-1289. Phase Voltage Source Applications. 1993, pp [3] Valentin OLESCHUK, PWM methods providing phase voltage [2] Benedict, E.R., Li symmetry of dualinverter fed drives: Systems modeling and simulation, for a Permanent-Spli PRZEGLĄD ELEKTROTECHNICZNY , ISSN 0033-2097, R. 89 NR Industry Applications. 6/2013. [3] Ba-thunya, A.S., K Phase Induction Moto [6] A. S. Ba-thunya, R. Khopkar, K. Wei and H. A. Toliyat, Single Phase Int. IEEE Internationa Induction Motor Drives-A Literature Survey, (2001), Proceedings of pp. 911-916 IEEE Conference, 911-916.

96 สาร) คาอธบิ ายเพิม่ เตมิ (ถ้ามี) แสดงเฉพำะรำยกำรอ้ำงอิงท่ีไมซ่ ้ำกัน otsopoulos, A.: ‘Variable Speed Control hase Induction Motors Using a Three Inverter’. Proc. Int Conf. IEEE Industry p. 613-619 ipo, T.A.: ‘Improved PWM Modulation it Capacitor Motor’. Proc. Int. IEEE . 2000, pp. 2004-2010 Khopkar, R., Kexin Wei., et al.: ‘Single or Drives – A Literature Survey’. Proc. al Electric Machines and Drives. 2001,

บทความวจิ ยั ท่ี 1 (วารสาร) 19 บทความวิจัยท่ี 2 (วารส [4] Frede, B., Florin, Induction Motor Dr Magazine. , July/Aug, [6] Kinnares, V., Ch Space Vector PWM fo Phase Induction Mo Electronics., 2009, 24, [7] Naser, M.B., A Unsymmetrical Two-P Frequency Control’, Conversion., 2009, 24, [8] Kumsuwan, Y., Pr ‘A Carrier-Base Unb Voltage Source Inve Induction Motor’, electronics., 2013, 60, [9] Tomaselli, L.C., ‘Applicationof the Ve Two-Phase Induction M electronics Specialists. [10] Ameni O., Base Strategies Aimed to Comparison Between IEEE Transactions on 9772-9782 [11] Hava, A.M., K Performance Generali IEEE Transactions on pp.1059–1071

97 คาอธิบายเพมิ่ เตมิ (ถา้ มี) สาร) , L., Kenneth, S., et al.: ‘Two-Phase rives’, IEEE Industry Applications 2004, pp.24-32 harumit, C.: ‘Modulating Functions of or Three-leg VSI-fed Unbalanced Two- otors’, IEEE Transactions on Power , (4), pp. 1135-1139 Abdel-Rahim., Adel, Shaltout.: ‘An Phase Induction Motor Drive with Slip- , IEEE Transactions on Energy , (3), pp. 608-615 remrudeepreechachan, S., Kinnares, V.: balanced PWM Method for Four-Leg erter Fed Unsymmetrical Two-Phase IEEE Transactions on industrial (5), pp. 2031-2041 Lazzarin, T.B., Martins, D.C., et al: ector Modulation in the Symmetrical Machine Drive’. Proc. Int. IEEE Power . 2005, pp. 1253-1258 em E.B., Ahmed, M.: ‘Direct RFOC Symmetrical Two-Phase IM Drives: n B4-and B6-Inverters in the Stator’, power electronics., 2018, 33, (11), pp. Kerkman, R.J., Lipo, T.A.: ‘A High- ized Discontinuous PWM Algorithm’, n Industrial Application., 1998, 34, (5),

บทความวจิ ยั ท่ี 1 (วารสาร) 19 บทความวจิ ัยที่ 2 (วารส [15] Muangthong, K., Based Discontinuous Four-Leg Voltage Elektrotechnicznego., [17] Belbaz, S., Kad Discontinuous PWM S IEEE Computation In 2007, pp. 131-136 [18] Hava, A.M., K Analytical and Graphi VSI Drives’, IEEE Tra 14, (1), pp. 49-61 [19] Bierhoff, Michae Switching Loss Optim PWM Voltage Source Electronics Society. 20 [20] Chaturvedi, P.K switching loss pulse w level diode clamped in (4), pp. 393-399 [21] Pradabane, S., B ‘Space-vector pulse w winding induction mo Electron., 2015, 8, (7),

98 คาอธบิ ายเพ่มิ เติม (ถ้าม)ี สาร) , Charumit, C.: ‘Realization of Carrier- SVPWM Technique of Two-Phase Source Inverter’, Przeglądu 2019, 8, pp. 109-114 djoudj, M., Golea, N.: ‘Analysis of the Strategies Applied to the VSI’. Proc. Int. ntelligence and Intelligent Informatics. Kerman, R.J., Lipo T.A.: ‘Simple ical Methods for Carrier-Based PWM- ansactions on Power electronics., 1999, el, Brandenburg, et al.: ‘An Analysis on mized PWM Strategies for Three Phase Converters’. Proc. Int. IEEE Industrial 007, pp. 1512-1517 K., Jain, S., Agarwal, P.; ‘Reduced width modulation technique for three- nverter’, IET Power Electron., 2006, 4, Beeramangalla, L.N., Nandiraju, V.S.: width modulation scheme for open-end otor drive configuration’, IET Power , pp. 1083-1094 ลงช่ือ นกั ศกึ ษา (นายเกษตร เมอื งทอง)

199 Kaset MUANGTHONG, Chakrapong CHARUMIT Pathumwan Institute of Technology, Thailand   doi:10.15199/48.2019.08.25 Realization of a Carrier-based Discontinuous SVPWM Technique for Two-Phase Four-Leg Voltage Source Inverter Abstract. This paper presents the carrier based discontinuous space vector pulse width modulation (DSVPWM) for two-phase four-leg voltage source inverters (VSI) fed resistive and inductive loads. This proposed technique is focused on the switching losses and output current ripple reduction in each phase-leg of inverter which does not depends on the lagging and leading power factor load. In addition, the carrier based DSVPWM is modified from conventional two-phase four-leg VSI by replacing the zero space vector in each switching sequence. This proposed discontinuous modulation strategy has 180 degrees for unmodulated region. Experimental results provide the performance comparison between the discontinuous SVPWM (DSVPWM) and the traditional continuous SVPWM (CSVPWM) techniques to confirm the reduction of switching losses and output current ripple at high modulation index. The experimental results show that total average values of normalized switching losses of the DSVPWM and the CSVPWM are 7.908 and 11.174, respectively in which the proposed DSVPWM can reduce the switching losses from the conventional CSVPWM up to 29 percent. Streszczenie. W artykkule opisano nieciągła technikę modulacji szerokości impulsu DSVPWM zastosowaną w dwufazowych czterogałęźnym przekształtniku VSI obciążonym indukcyjnością i rezystancją. Projekt zakładał ograniczeniu strat przełączania i zafalowania prądu. Eksperymentalnie porównano zaprojektowany układ z tradycyjnym układem ciągłym. Nieciągła technika modulacji szerokości impulsu DSVPWM zastosowana w dwufazowych czterogałęźnym przekształtniku VSI do Przeglądu Elektrotechnicznego - polski tytuł na końcu streszczenia - Polish tittle at the end). Keywords: Two-phase four-leg inverter, Switching losses, Ripple current, Discontinuous space vector pulse width modulation. Słowa kluczowe: przekształtnik dwufazowy, nieciągła modulacja szerokości impulsu DSVPWM.  Introduction Table 1. Switching state and corresponding active space vector An increase of performance of the three-leg voltage SV0 source inverter can be enhanced by reducing the switching losses and output ripple current when the discontinuous SV1 2Vdc 00 space vector pulse width modulation (DSVPWM) technique for high modulation index has been performed [1-3]. Many SV2 2 2Vdc  450 types of DSVPWM techniques such as DPWMMIN, DPWMMAX, DPWM 0, DPWM 1 and DPWM 2 of three- SV3 2Vdc 900 phase voltage source inverters (VSIs) depend on types of power factor load. For example, DPWM 0 is suitable for a SV4 2 2Vdc  1350 leading power factor load and DPWM 2 is fit for a lagging power factor load [4]. In addition, three-leg voltage source SV5 2Vdc 1800 inverters can be applied to two-phase induction motor of both of the asymmetrical and symmetrical parameter types SV6 2 2Vdc  2250 for industrial application [5]. Especially, the two-phase four- leg voltage source inverter fed two-phase motors drive has SV7 2Vdc 2700 an advantage of a lower DC bus voltage requirement compared to the DC bus voltage of two-leg and three-leg SV8 2 2Vdc  3150 VSI at the same output voltage of inverter [6]. On the other hand, a disadvantage of four-leg VSI is more number of SV9 switching devices than two and three-leg VSI. Therefore, to reduce the switching losses in switching devices in each  Two-phase four-leg SVPWM technique leg, the modulating function of DSVPWM technique for two- A main circuit of the two-phase four-leg voltage source phase four-leg inverter fed balanced R-L load is proposed in this study. The experimental results of a decrease of inverter (VSI) connected to the balanced R-L loads shows switching losses and output current ripples for the proposed in Fig.1. DSVPWM modulation are compared with the conventional CSVPWM. The terminal voltages, vao , vbo , vco and vdo are phase Fig. 1. A proposed two-phase four-leg voltage source inverter voltages and the line terminal voltages, vab and vcd are connected to the balanced R-L loads. The main power circuit has 8 switching devices and 16 switching states which consist of 12 active voltage vectors and 4 null vectors as shown in Table 1. For switching states in Table 1, there are eight possible voltage vectors    SV1, SV2,..., SV8 and two null vectors SV0(0000) and  SV (1111) . In the switching states, upper and lower 9 switches assigned with “1” or “0” mean to turn-on and turn- 108                                                                                    PRZEGLĄD ELEKTROTECHNICZNY, ISSN 0033-2097, R. 95 NR 8/2019 

200  off, respectively. Four active vectors SV1, SV3, SV5, SV7 (4) TSV2  M sin T 2 have the length of 2Vdc and four active vectors 2  SV2, SV4 SV6, SV8 have the length of 2 2Vdc  , unlike the As illustrated in Fig. 2, the maximum possible SVPWM analysis of three-phase VSI which has the same magnitude of the output voltage vector is 2Vdc and the magnitude active voltage vector of each sector [3]. Fig. 2 shows the arbitrary output voltage and the location of active Locus voltage is a circular path; therefore, the output space vectors in a d-q plane which is divided into 8 sectors voltage vector, Vo* can be expressed by with 45 degrees. Due to the similar principle to the conventional two-phase four-leg SVPWM [7], mathematical  (5)Vo*  TSV1 calculation of switching times for the two-phase four-leg T SV1 SVPWM method can be dealt with in the same manner as 2 for the conventional one. The desired output voltage Vo* in Substituting Eq. (3) and SV1  2Vdc into Eq. (5) and vector form which is a rotating vector can be calculated in when   0 degree, the magnitude of output voltage can be terms of the average of a number of these space vectors given by within a switching period in each sector as follows (6) Vo*  MVdc (Peak voltage) (1) V0*  V0  TU1 2 U1  TU 2 2 U2 where M is the modulation index in range of 0  M  2 . T / T / (2) where T  TU1  TU 2  TSV 0  TSV 9 Then, the phase-leg reference voltage or equivalent 2 voltage in average values for four phase-leg reference voltage with respect to the midpoint of DC bus voltage over U1 and U2 are two basic adjacent vectors;  is sampled the time interval T / 2 of sector 1 can be written as angular position; TU1, TU2 are active times for the two basic (7) vao  M sin      1 sin   adjacent vectors; TSV 0 , TSV 9 are times for null vectors; and Vdc 2  4  2  T is a carrier period. Generally, for a symmetrical space (8) vbo  M sin      1 sin  vector pattern, space vector time for each zero switching Vdc 2  4  2  state ( TSV 0 , TSV 9 ) is set to be equal. (9) vco  M 1 sin  sin     Vdc 2  2  4  (10) vdo  M sin      1 sin  Vdc 2  4  2  Table 2. Switching times Fig. 2. Location of active space vectors in d-q plane and arbitrary output voltage. From Eq. (1), an example of the relationship between the space vector active times at different angles between 0 and 180 degrees divided into the equal four sectors (sector 1 to sector 4) can be determined by the equations in Table 2. These equations can be used for deriving the phase-leg reference voltage waveforms for CSVPWM. An example for calculating and drawing the phase-leg reference voltage of sector 1 for angles between 0 and 45 degrees are started from the equation below (3) TSV1  M sin      T 2  4  2 PRZEGLĄD ELEKTROTECHNICZNY, ISSN 0033-2097, R. 95 NR 8/2019  109

201 where TSV 0 , TSV1 , and TSV 2 are the switching time sequencing in a half period of switching for sector 1 and TSV 0  T  TSV1  TSV 2 . 2 After substituting the TSV 0 into Eq. (11) gives (12) vao  2Vdc  TSV1  TSV 2  1   T 2 T 2   2  The other three reference phase-leg voltages can also be calculated as described before and then gives (13) vbo  Vdc (14) vco  2Vdc  TSV 2  1   T 2   2  (15) vdo  Vdc Angle (degrees) Fig. 3. Phase-leg reference voltage waveforms for CSVPWM As described before, the phase-leg reference voltage of Fig. 4. Pulse pattern and phase-leg reference voltage for the sector 8 sectors can also be calculated and the phase-leg 1 reference voltage waveforms as the function of angle for 0 To calculate the phase-leg reference voltage as a to 360 degrees can be drawn as shown in Fig. 3, where va**o function of θ and M for DSVPWM by substituting both of , vb**o , vc*o* and vd**o are fundamental of phase-leg reference Eqs. (3) and (4) into Eq. (12) and Eq. (14) based on the voltage, and va*o , vb*o , vc*o and vd*o are phase-leg reference midpoint of the DC bus voltage, for sector 1 only, the voltage. These phase-leg reference voltage are compared vao Vdc and the vco Vdc can be derived whereas the with the carrier waveform to generate the gate driver signals. vbo Vdc and the vdo Vdc are constant as expressed below  Proposed DSVPWM (16) vao  2M sin      M sin 1 Vdc  4  The principle of carrier based CSVPWM for the two- phase four-leg VSI discussed earlier can be modified as (17) vbo  1 discontinuous pulse or discontinuous modulation. A main Vdc purpose of using the DSVPWM is to reduce the switching losses and output current ripple at high modulation index. (18) vco  M sin 1 This DSVPWM is carried out by alternating the null voltage Vdc vectors SV 0 and SV 9 . In this paper, the modulating (19) vdo  1 Vdc function is calculated using only null voltage vector SV 0 as After calculating like the approach described before, the shown in Fig. 4. According to Fig. 4 which presents the four phase-leg reference voltage of DSVPMW for all 8 pulse pattern and phase-leg reference voltage for the sectors can be plotted as demonstrated in Fig. 5. sector 1 only, an example of calculating the phase-leg reference voltages, vao in average values over the time interval T / 2 of sector 1 can be determined by (11) vao  Vdc  TSV1  TSV 2  TSV 0   T 2 T T   2 2  110                                                                                    PRZEGLĄD ELEKTROTECHNICZNY, ISSN 0033-2097, R. 95 NR 8/2019 

202 The switching power loss during turn-on and turn-off time process is previously proposed [9]. Total average switching loss in a switch period can be expressed as (20) Psw,loss  Pon,avg  Poff ,avg  (21) Vdc Psw,loss  fswIsw ton  toff 3 The power switching loss, Psw,loss depends on the switching frequency, fsw and the load current, Isw . The switching frequency of the proposed DSVPWM method is 1.5 times of the CSVPWM method; therefore, values of the switching frequency of the CSVPWM and the proposed DSVPWM method are 2kHz and 3kHz, respectively. For the normalized switching loss analysis, the normalized switching loss waveform for CSVPWM is similar to the absolute load current Isw while the normalized switching loss for the DSVPWM method is 1.5 times of Isw and zero at the clamping zone resulting in a reduction in switching losses.  Experimental results Figs. 7 and 8 show the proposed system and the experimental setup consisting of a single rectifier providing 300VDC, a four-leg VSI, and the balanced two-phase R-L loads. Each R-L load has resistance of 59  and 50mH. Angle (degrees) Fig. 7. A proposed two-phase four-leg VSI system Fig. 5. Phase-leg reference voltage waveforms for proposed Fig. 8. Experimental setup for two-phase four-leg VSI system DSVPWM The modulated signals for driving all IGBTs are  Switching loss analysis generated by the TMS320F28335 DSP board with The switching losses and output current ripple of both MATLAB/Simulink. An algorithm of MATLAB/Simulink for the proposed DSVPWM is shown in Fig. 9; the fundamental CSVPWM and DSVPWM are compared while the frequency of output voltage and a sampling time are conduction losses is neglected because the conduction defined as 50Hz and 100 s by Ramp generation block losses of both methods are insignificant in term of the set, and the maximum modulation index is set at 2. The modulation index and the switching frequency variation [8]. PWM signals are established by ePWM1- ePWM4 modules Fig. 6(a) shows one-leg voltage source inverter circuit. Fig. at the switching frequency of 2kHz for CSVPWM and of 6(b) shows the gate driver signal, the voltage across 3kHz for DSVPWM. For DAC converters, ePWM5 and terminals of switching device, the current flowing through ePWM6 are applied as DACs by applying PWM signals switching device S1 and the average power switching through low pass filters to be displayed by a digital oscilloscope.. losses for switching device S1.  Fig. 6. Switching loss characteristics (a) one-leg inverter power circuit (b) Linearized switching characteristics (b-1) gate driver signal (b-2) voltage cross switching and load current flowing through switching device S1 (b-3) average switching power loss. PRZEGLĄD ELEKTROTECHNICZNY, ISSN 0033-2097, R. 95 NR 8/2019  111

203 Fig. 9. MATLAB/Simulink for Algorithm development Fig. 12. Output voltage vab and vcd , output current i1 and i2 of Fig. 10. CSVPWM (a) four phase-leg reference voltage of va*o , CSVPWM. vb*o and output phase voltage of vao , vbo . The test conditions are to compare the switching losses and the output load current ripple, i1 and i , of the proposed 2 DSVPWM and the conventional CSVPWM when the modulation index of both methods is fixed at 2. Fig. 10 shows the modulation waveforms of the conventional CSVPWM at which the phase-leg reference voltage of va*o , vb*o and the output phase voltages of vao , vbo are presented Fig. 11 illustrates the modulation waveforms of the proposed DSVPWM and it is noted that the output pulse waveforms of each phase voltage of vao , vbo , vco and vdo does not switch at clamping zone owing to an unmodulated time. This clamping time leads to decrease the switching losses. Figs. 12 and 13 show the output voltages of vab and vcd and the output current waveforms, i1 and i2 with the phase difference of 90 degrees for the conventional CSVPWM and the proposed DSVPWM, respectively. Fig. 11. Proposed DSVPWM (a) phase-leg reference voltage of Fig. 13. Output voltage vab and vcd , output current i1 and i2 of va*o , vb*o and output phase voltage of vao , vbo (b) phase-leg DSVPWM. reference voltage of vc*o , vd*o and output phase voltage of vco , To compare the switching losses, Figs. 14 and 15 vdo . represent an analysis of normalized switching losses of the CSVPWM and the proposed DSVPWM, respectively. The voltages and currents are measured for mathematically calculating using MATLAB/Simulink. Fig. 14 demonstrates the normalized switching losses of the CSVPWM in each phase-leg derived by Eq. (21) when the carrier frequency of CSVPWM is 2 kHz, and absolute load current i1 is representative of the normalized switching losses in switching devices, S1 and S2. The average values of normalized switching losses for CSVPWM of phase-leg a, b, c and d are 2.822, 2.822, 2.735 and 2.735 as shown in Figs. 4 (a) – (d), respectively. Fig. 15 illustrates the normalized switching losses of the proposed DSVPWM in each phase-leg calculated by Eq. (21) when the carrier 112                                                                                    PRZEGLĄD ELEKTROTECHNICZNY, ISSN 0033-2097, R. 95 NR 8/2019 

204 frequency of DSVPWM is fixed at 3 kHz, and 1.5times of Table 3 Normalized switching losses absolute load current i1 is representative of the normalized Method Leg a Leg b Leg c Leg d Total 2.735 11.174 switching losses in switching devices, S1 and S2. The CSVPWM 2.822 2.822 2.735 1.992 average values of normalized switching losses for 27.16% 7.908 DSVPWM of phase-leg a, b, c and d are 1.994, 1.904, DSVPWM 1.994 1.904 2.018 29.22% 2.018 and 1.992 as shown in Fig. 15 (a) – (d), respectively. Table 2 summarizes the average values of the switching Reducing 29.34% 34.93% 26.20% losses of CSVPWM and DSVPWM. A summation of switching losses of four legs of the DSVPWM method is To compare the output current ripple analysis, the load minimum. current ripple waveforms of i1 and i2 for the CSVPWM method and the proposed DSVPWM method are shown in Fig. 16(a) and Fig. 16(b), respectively. The proposed ripple currents are not included the fundamental component using MATLAB/Simulink. The results show that the proposed DSVPWM is lower output current ripple than the conventional CSVPWM. Table 3 shows a comparison of the mean square values of load currents for CSVPWM and DSVPWM methods. It can be concluded that the mean square values of load currents of the proposed DSVPWM is lower than that of the conventional CSVPWM. Fig. 14. Normalized switching losses of CSVPWM in each phase- leg. Fig. 16. Measured load current ripple (a) CSVPWM and (b) proposed DSVPWM Table 4 comparison of mean square value of current ripples Method Load current Mean square value CVPWM i1 3.75e3 i2 5.03e3 DSVPWM i1 3.35e3 i2 4.69e3 Fig. 15. Normalized switching losses of proposed DSVPWM in  Conclusions each phase-leg. The discontinuous SVPWM (DSVPWM) technique compared with conventional CSVPWM for reducing the switching losses and output current ripple at high modulation index is investigated in this study. The experimental results confirm that the DSVPWM technique can reduce the switching losses up to 29% comparing with the CSVPWM. The reduction of switching losses is not depended on lagging or leading power factor. In addition, the proposed DSVPWM technique can be applied to drive the two-phase motor. Authors: Mr. Kaset Muangthong. E-mail: [email protected]; Assoc. Prof. Dr. Chakrapong Charumit , E-mail: [email protected] Department of Electrical Engineering, Pathumwan Institute of Technology, 833 Rama1 Wangmai District, Bangkok, Thailand. PRZEGLĄD ELEKTROTECHNICZNY, ISSN 0033-2097, R. 95 NR 8/2019  113

205 REFERENCES [6] A. S. Ba-thunya, R. Khopkar, K. Wei and H. A. Toliyat, Single Phase Induction Motor Drives-A Literature Survey, (2001), [1] Di Zhao, Member, V. S. S. Pavan Kumar Hari, Gopalaratnam Proceedings of IEEE Conference, 911-916. Narayanan, and Rajapandian Ayyanar, Space Vector Based Hybrid Pulsewidth Modulation Technique for Reduced [7] V. Kremer, Z. Q. Zhu and D. Howe, Indirect and Direct Force Harmonic Distortion and Switching Loss, IEEE Transaction on Control of a Two-Phase Tubular Permanent Magnet Machine, power electronics, (2010), vol. 25, NO. 3, 760-774. IEEE Transactions on power electronics, (2007), VOL. 22, NO. 2, March, 654-662. [2] Olorunfemi Ojo, The Generalized Discontinuous PWM Modulation Scheme for Three-Phase Voltage Source Inverters, [8] Y. Wu, M. A. Shafi, A. M. Knight and R. A. McMahon, IEEE Transactions on industrial electronics, (2004), VOL. 51, Comparison of the Effects of Continuous and Discontinuous NO. 6, 1280-1289. PWM Schemes on Power Losses of Voltage-Sourced Inverters for Induction Motor Drives, IEEE Transactions on power [3] Valentin OLESCHUK, PWM methods providing phase voltage electronics, (2011), VOL. 17, NO. 1, January, 182-191. symmetry of dualinverter fed drives: Systems modeling and simulation, PRZEGLĄD ELEKTROTECHNICZNY , ISSN 0033- [9] C. Charumit and V. Kinnares, Discontinuous SVPWM 2097, R. 89 NR 6/2013. Technique of Three-Leg VSI-Fed Balanced Two-Phase Loads for Reduced Switching Losses and Current Ripple, IEEE [4] D.Grahame Holmes and Thomas A. Lipo, Pulse Width Transactions on power electronics, (2015), VOL. 30, April, Modulation 2191-2204. for Power Converters, (2003), Wiley Interscience, IEEE Press. [5] D. H. Jang, PWM Methods for Two-Phase Inverter, IEEE Industrial Application Magazine, (2007), VOL. 13, April, 50-61. 114                                                                                    PRZEGLĄD ELEKTROTECHNICZNY, ISSN 0033-2097, R. 95 NR 8/2019 

206Author search Sources Create account Sign in Source details Przeglad Elektrotechniczny to Present CiteScore   Open Access  .  Scopus coverage years: from to , from SJR Publisher: Wydawnictwo SIGMA ISSN: - . Subject area: Engineering: Electrical and Electronic Engineering SNIP View all documents ▻ Set document alert  Save to source list Journal Homepage . CiteScore CiteScore rank & trend Scopus content coverage i Improved CiteScore methodology × CiteScore counts the citations received in - to articles, reviews, conference papers, book chapters and data papers published in - , and divides this by the number of publications published in - . Learn more ▻ CiteScore  CiteScoreTracker  ., Citations - . , Citations to date = Documents - = , , Documents to date Calculated on May, Last updated on January, • Updated monthly CiteScore rank  Category Rank Percentile Engineering    st Electrical and / Electronic Engineering View CiteScore methodology ▻ CiteScore FAQ ▻ Add CiteScore to your site ������ About Scopus Language Customer Service What is Scopus 日本語に切り替える Help Content coverage 切换到简体中文 Contact us Scopus blog 切換到繁體中文 Scopus API Русский язык Privacy matters Terms and conditions ↗ Privacy policy ↗ Copyright © Elsevier B.V ↗. All rights reserved. Scopus® is a registered trademark of Elsevier B.V. We use cookies to help provide and enhance our service and tailor content. By continuing, you agree to the use of cookies.

1/22/2021 207Przeglad Elektrotechniczny also developed by scimago: SCIMAGO INSTITUTIONS RANKINGS Scimago Journal & Country Rank Enter Journal Title, ISSN or Publisher Name Home Journal Rankings Country Rankings Viz Tools Help About Us Ads by Send feedback Why this ad? Przeglad Elektrotechniczny Country Poland  -  25 Subject Area and Engineering H Index Category Electrical and Electronic Engineering Publisher Wydawnictwo SIGMA - N O T Sp. z o.o. Publication type Journals ISSN 00332097 Coverage 1969-1984, 2005-2020 Scope \"Przegląd Elektrotechniczny\" exists since 1919 and it is one of the oldest Polish scienti c journals. It is dedicated to electrical engineering. The owner of the tittle is SEP (Society of Polish Electrical and Electronics Engineers). Przeglad Elektrotechniczny is published monthly in average 200 pages per issue (120 - 300 pages). We publish the papers in Polish or English. The Scienti c Level of our Journal is controlled by 44-person Program Editorial Board. Homepage How to publish in this journal Contact Join the conversation about this journal Ads by Send feedback Why this ad? Quartiles 1/5 The set of journals have been ranked according to their SJR and divided into four equal groups, four quartiles. Q1 (green) comprises the quarter of the journals with the highest values, Q2 (yellow) the second highest values, Q3 (orange) the third https://www.scimagojr.com/journalsearch.php?q=18700&tip=sid&clean=0

1/22/2021 208Przeglad Elektrotechniczny highest values and Q4 (red) the lowest values. Category Year Quartile ElEelcetcritcraicl aanl danEdlecEtlreocnticroEnnigcinEenegriinngeering 2006 Q3 Electrical and Electronic Engineering 2007 Q3 Electrical and Electronic Engineering 2008 Q3 Electrical and Electronic Engineering 2009 Q3 SJR Citations per document T0h.3e SJR is a size-independent prestige indicator that 0T.6his indicator counts the number of citations received ranks journals by their 'average prestige per article'. It is by documents from a journal and divides them by the 0b.2a4sed on the idea that 'all citations are not created total number of documents published in that journal. The chart shows the evolution of the average number of 0e.1q8ual'. SJR is a measure of scienti c in uence of 0tt.hi4mreeesadnodcufomuer nytesaprsubhalisvheebdeeinnacjioteudrninaltihnetchuerpreansttytewaor,. journals that accounts for both the number of citations The two years line is equivalent to journal impact factor 0r.e1c2eived by a journal and the importance or prestige of ™ (Thomson Reuters) metric. the journals where such citations come from It meas2u0r0e6s the20s0c8ient2i 0c10in u2e0n1c2e o2f 0th1e4 av2e0ra1g6e a2rt0ic1l8e in a journal it expresses how central to the global Total Cites Self-Cites 0.C2ites per document Year Value 1E.5vkolution of the total number of citations and journal's Cites / Doc. (4 years) 2005 0.000 Cites / Doc. (4 years) 2006 0.074 self-citations received by a journal's published Cites / Doc. (4 years) 2007 0.106 C0ites / Doc. (4 years) 2008 0.130 documents during the three previous years. Cites / Doc. (4 years) 2009 0.186 2017 2019 7J5o0urnal Self-citation is de ned as the number of citation Cite2s00/5Do2c0. 0(47 ye2a0r0s9) 2021011020103.2725015 CitCeiste/s D/ oDcoc. .(4(4yyeeaarrss)) 2011 0.279 from a journal citing article to articles published by the CitCeiste/s D/ oDcoc. .(4(3yyeeaarrss)) 2012 0.370 CitCeiste/s D/ oDcoc. .(4(2yyeeaars)) 2013 0.379 sa0me journal. Cites / Doc. (4 years) 2014 0.319 2005 2007 2009 2011 2013 2015 2017 2019 Cites Year Value S lf Cit 2005 0 External Cites per Doc Cites per Doc % International Collaboration E0v.5olution of the number of total citation per document 8I0nternational Collaboration accounts for the articles that and external citation per document (i.e. journal self- have been produced by researchers from several citations removed) received by a journal's published 0d.2o5cuments during the three previous years. External countries. The chart shows the ratio of a journal's citations are calculated by subtracting the number of 4d0ocuments signed by researchers from more than one se0lf-citations from the total number of citations received by the journal’s documents. country; that is including more than one country a0ddress. 2005 2007 2009 2011 2013 2015 2017 2019 2005 2007 2009 2011 2013 2015 2017 2019 Cit Y Vl Year International Collaboration Citable documents Non-citable documents 2005 5 56 Cited documents Uncited documents 4Nkot every article in a journal is considered primary 4Rkatio of a journal's items, grouped in three years research and therefore \"citable\", this chart shows the windows, that have been cited at least once vs. those ratio of a journal's articles including substantial not cited during the following year. 2rkesearch (research articles, conference papers and 2k reviews) in three year windows vs. those documents op0athpeerrsth. an research articles, reviews and conference Documents Year Value 2017 2019 2005 0 2005 2007 2009 2011 2013 2015 2017 2019 0Uncited documents 22001016 2021301 2015 Un2c0i0te5d d2o0c0u7me2n0t0s9 2007 453 Dt Y Vl Uncited documents 2008 763 Uncited documents ← Show this widget in your own website Just copy the code below and paste within your html code: <a href=\"https://www.scimag https://www.scimagojr.com/journalsearch.php?q=18700&tip=sid&clean=0 2/5

012212320 456ÿ89 2ÿ05 99ÿÿ ÿ ÿ %&'()*+,(-(.* /&+*(&ÿ123ÿ4567()ÿ8+97()* :.6+.(ÿ;<<=3>?@@AB@BC DÿEFE>ÿGH(ÿ;.,*+*I*+5.ÿ5Jÿ/.K+.(()+.KÿL.&ÿG(9H.565K2 ÿ 9Lˆ‰5+Š--ÿŒ,-ÿ*Ž5Iÿ.L+*ÿ9‰*L)‘L*’+95“*.ÿ5,”){ÿ+•}K’–+L.ÿ*+L,(ÿ6.Lÿ)*ÿ(—ÿL,5)(*6L+&9)ÿ69:(H,}ÿÿ}(LL..}ÿ&%(ÿ)9)(9,('{ÿ+,)(,L™ÿ}˜5ÿ+L&I))*.+9L6(6ÿ,*Hÿ+.L* *H(ÿš(6&ÿ5Jÿ}5™()ÿ(6(9*)5.+9,† NOPQRSTU VWXYÿ[\\]\\^Y VWXYÿ_`Y\\a bcd\\^ÿe]]\\XX p_a`W^XfX]kWdf^gYfh`^g\\YpY`Wih`\\p]ÿXggÿj^qÿYrgmsjkWtXv`dVXnÿWÿgXlYXÿXh\\gmÿ`Y^`\\Ya]onp`\\`]^XYÿo`lWWÿj^WhÿÿXpfX^\\WuXYgÿWgjhg^^a]ÿ]\\pahÿhY\\m^WYvÿdh`ndgdXj\\\\ÿÿWlWlÿp]hWv^j\\Yo`^ÿrpqWwpÿxX\\ÿga^a yL,(*ÿzIL.K*H5.K{ÿ|HL7)L}5.Kÿ|HL)I-+* ~+),*ÿ8I16+,H(&3ÿÿEFÿ€L.IL)2ÿEFE> euXYhg]Y xpjjÿY\\Y s‚x [\\l\\h\\^]\\X [\\ƒp\\XYÿd\\hf`XX`W^X bcd\\^ÿe]]\\XX 01\" „XY`fgY`W^ÿWlÿYn\\ÿ]gdg]`YWhÿiWjYgo\\Xÿ`^ÿ…k`^oÿ]gdg]`YWhÿfpjY`vj\\i\\jÿ]W^i\\hY\\hX z+KI(6ÿ~†ÿ/,9L6L.*({ÿ%6(‡ÿ8†ÿ/)&-L.. ~+),*ÿ8I16+,H(&3ÿÿEFÿ€L.IL)2ÿEFE> euXYhg]Y xpjjÿY\\Y s‚x [\\l\\h\\^]\\X [\\ƒp\\XYÿd\\hf`XX`W^X 119    919 10!\"\"#\"#$