Dell 14-3478 17841-1

5 432 1 D D C Vinafix.com C B B Vegas Schematic KBL-R 2017/11/08 REV : A00 DY : None Installed <Core Design> UMA: UMA only installed A OPS: DISCRTE OPTIMUS installed Wistron Corporation A 543 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Cover Page Size Document Number Rev A4 Vegas SKL/KBL-U Date: Wednesday, November 08, 2017 Sheet 1 of A00 105 21

5 432 1 44 Project code: Vegas/Turis MLK KBL-R Block Diagram CHARGER PCB P/N:17841-1 Revision: X02 ISL88739 INPUTS OUTPUTS AD+ DCBATOUT BT+ SYSTEM DC/DC 45 Vinafix.comNEW TPS51225RUKR-GP INPUTS OUTPUTS 2GB = 256Mb x 32 x 2 PCS NEW NEW 3D3V_PWR 3D3V_S5 D DDR4 2400 5V_PWR D 5V_S5 SODIMM A DCBATOUT VRAM(GDDR5) *2 GPU PCIE x 4 Intel CPU DDR4 2400MHz Channel A 12 CPU Core Power GDDR5 DDR4 2400MHz Channel A NCP81208MNTXG 4633~50 2GB (256Mb x 32) AMD Kabylake-U 4+2 DDR4 2400 R17M-M1-30 NCP81382MNTXG x 2 25W 15W (UMA&DIS) SODIMM B 81, 82 NCP81382MNTXG (23e) 76, 77, 78, 79, 80 13 DIS only NCP81253MNTBG INPUTS OUTPUTS DCBATOUT VCC_CORE DCBATOUT +VCCGT DCBATOUT +VCCGT (23e) Vegas 14\"/15\" LCD eDP x2 KBL PCH-LP USB2.0 x1 VEGAS only Fingerprint NEW DCBATOUT+VCCSA Turis 15\" Touch Panel USB2.0 x1 (TURIS only) 55 10 USB 2.0/1.1 ports FM-03331 92 DDR4 SUS 6 USB 3.0 ports RT8231AGQW-GP 51 High Definition Audio APL5930KAI-TRG INPUTS OUTPUTS C Camera USB2.0 x1 3 SATA ports PCIE x1 NGFF WLAN Vegas C Digital MIC 6 PCIE ports Turis 1D2V_S3 LPC I/F 802.11a/b/g/n DCBATOUT 0D6V_S0 BT V4.0 combo 61 3D3V_S5 2D5V_S3 ACPI 5.0 USB2.0 x1 CPU VCCPRIM_CORE 1V LAN 10/100 TURIS only Vegas REALTEK RTL8106E 11 Turis RJ45 Conn. LAN 10/100/1000 PCIE x1 INPUTS OUTPUTS REALTEK RTL8111H 31 VEGAS only 32 1D0V_S5 +VCCPRIM_CORE Vegas HDMI V1.4a 57 DDI1 CPU DCDC-V1D00A Turis AOZ2262QI-10-GP-U 53 INPUTS OUTPUTS SATA (Gen3) x1 HDD DCBATOUT 1D0V_S5 SATA (Gen1) x1 DP/VGA Converter VEGAS only 60 LDO-V1D8V REALTEK RTD2166 eSPI BUS Vegas VGA Conn. DDI2 APL5930KAI-TRG 54 56 Turis 56 Vegas INPUTS OUTPUTS Turis ODD 3D3V_S5 1D8V_S5 Left side 60 Kyloren 15 5V/3V S0 eSPI debug port Vegas USB1(USB3.0) USB2.0 x1 TPS22966DPUR-GP 40 Turis USB3.0 x1 68 B INPUTS OUTPUTS B 36 5V_S5 5V_S0 3D3V_S5 3D3V_S0 Kyloren EOPIO/EDRAM (23e) 15 FAN Control TPS22961DNYT 40 Left side EC Vegas USB2.0 x1 26 INPUTS OUTPUTS Turis USB2(USB3.0) USB3.0 x1 SMSC MEC1416-NU-GP 24 1D0V_S5 +V_EDRAM_VR 36 1D0V_S5 +V_EOPIO_VR 3D3V VGA 86 AO3419L SPI Flash ROM Int. KB Vegas INPUTS OUTPUTS Turis 16MB 3D3V_S0 3D3V_VGA_S0 65 2CH SPEAKER 25 (2CH 2W/4ohm) PS2 Vegas Audio Codec VEGAS only PrecisionTouch pad 26 VGA_CORE Turis 29 HDA 65 ISL62771HRTZ-GP-U 85 ALC3246 TPM 2.0 INPUTS OUTPUTS 27 NPCT650/750 91 DCBATOUT VGA_CORE MIC_IN/GND 1D5V_VGA_S0 86 HP_R/L Y8288RAC-GP I2C Universal Jack INPUTS OUTPUTS A DCBATOUT 1D5V_VGA_S0 A Vegas USB3(USB2.0) USB2.0 x1 <Core Design> Turis USB2.0 x1 Wistron Corporation Vegas SD Card Slot IO BTuoarrids 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. 5 CardReader Title Block Diagram Realtek RTS5170 Size Document Number Vegas SKL/KBL-U Rev C A00 Date: Wednesday, November 08, 2017 Sheet 2 of 105 4 3 21

5 4321 Main Func = CPU #544669 CRB Rev0.52 D +VCCST_CPU [PECI] and [PROCHOT#] Vinafix.com#543016 Rev0.7: Ra = 500 ohm / Rb = 1k ohm 21 R419 +VCCSTG = 1.0 V D Impedance control: 50 ohm 1KR2J-1-GP C #544669 Rev0.52: +VCCSTG [24] H_PECI Ra = 56 ohm (TO BE CHANGED TO 100 OHMS) / Rb = 62 ohm and 150 ohm PCH_THERMTRIP XDP_TMS R421 1 DDYY [24,44,46] H_PROCHOT# XDP_TDI R422 1 2 51R2J-2-GP [24,55] TOUCH_PANEL_INTR# +VCCSTG +VCCSTG = 1.0 V 2 51R2J-2-GP XDP_TDO_CPU 2 51R2J-2-GP [24,65] INT_TP# R423 1 DY 2 51R2J-2-GP PCH_JTAG_TDI 2 51R2J-2-GP C 21Rb R401 4 OF 20 0525 Follow KY15 & SF R408 1 2 51R2J-2-GP 2 1KR2J-1-GP 1KR2J-1-GP CPU1D PCH_JTAG_TDO 2 51R2J-2-GP Ra 1 H_CATERR# D63 R409 1 2 51R2J-2-GP R403 1 H_PECI A54 2 51R2J-2-GP TPAD14-OP-GP TP401 H_PROCHOT#_R C65 CATERR# SKYLAKE_ULT 499R2F-2-GP PCH_THERMTRIP C63 PECI H_PROCHOT# 2 A65 PROCHOT# PCH_JTAG_TMS R416 1 1 SKTOCC# THERMTRIP# TPAD14-OP-GP TP402 SKTOCC# JTAG B61 XDP_TCLK XDP_TCK_JTAGX R417 1 DY 1 XDP_BPM0 D60 XDP_TDI TPAD14-OP-GP TP405 1 XDP_BPM1 C55 CPU MISC PROC_TCK A61 XDP_TDO_CPU XDP_TRST# R402 1 DY TPAD14-OP-GP TP406 1 XDP_BPM2 D55 PROC_TDI C60 XDP_TMS XDP_TCLK TPAD14-OP-GP TP407 1 XDP_BPM3 B54 BPM#[0] PROC_TDO B59 XDP_TRST# PCH_JTAG_TCK R406 1 TPAD14-OP-GP TP408 C56 BPM#[1] PROC_TMS BPM#[2] PROC_TRST# PCH_JTAG_TCK R407 1 DY BPM#[3] PCH_JTAG_TDI PCH_JTAG_TDO A6 GPP_E3/CPU_GP0 PCH_JTAG_TCK B56 PCH_JTAG_TMS TOUCH_PANEL_INTR# A7 GPP_E7/CPU_GP1 PCH_JTAG_TDI D59 XDP_TRST# INT_TP# R410 1 2 TOUCHPAD_INTR# BA5 GPP_B3/CPU_GP2 PCH_JTAG_TDO A56 XDP_TCK_JTAGX 0R0402-PAD TPAD14-OP-GP TP404 GPP_B4/CPU_GP3 PCH_JTAG_TMS C59 1 GPP_B4/CPU_GP3 AY5 C61 R412 1 2 49D9R2F-L1-GP PCH_TRST# A59 R413 1 2 49D9R2F-L1-GP CPU_POPIRCOMP AT16 PROC_POPIRCOMP JTAGX R414 1 2 49D9R2F-L1-GP PCH_OPIRCOMP R415 1 2 49D9R2F-L1-GP PCH_POPIRCOMP AU16 OPCE_RCOMP EDRAM_OPIO_RCOMP H66 OPC_RCOMP EOPIO_RCOMP H65 XDP_TRST# SKYLAKE-U-GP 21DY EC401 SC1KP50V2KX-L-1-GP (#543016) PROCHOT# Routing Guidelines B B A M1,2,3,4,5: <3 inches <Core Design> A 5 M6: 1-11 inches MCPU: 0.3-1.5 inches Wistron Corporation Mt <0.3 mils Main route(M1+M2+M3+M4+M5+M6+MCPU): 1-12 inches 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. 43 Title CPU_(JTAG/CPU SIDE BAND) Size Document Number Rev A3 Vegas SKL/KBL-U A00 Date: W ednesday, November 08, 2017 Sheet 4 of 105 21

5 43 2 1 Main Func = CPU DDR4 ball type: Interleaved Type Vinafix.com DD CPU1B 2 OF 20 CPU1C 3 OF 20 SKYLAKE_ULT [12] M_A_DQ0 M_A_DQ0 AL71 DDR0_DQ[0] DDR0_CKN[0] AU53 M_A_CLK#0 [12] [12] M_A_DQ32 M_A_DQ32 AY39 DDR0_DQ[32]/DDR1_DQ[0] SKYLAKE_ULT DDR1_CKN[0] AN45 M_B_CLK#0 [13] [12] M_A_DQ1 M_A_DQ1 AL68 AT53 M_A_CLK0 [12] M_A_DQ33 AW 39 DDR0_DQ[33]/DDR1_DQ[1] DDR1_CKN[1] AN46 M_B_CLK#1 [13] [12] M_A_DQ2 M_A_DQ2 AN68 DDR0_DQ[1] DDR0_CKP[0] AU55 M_A_CLK#1 [12] [12] M_A_DQ33 M_A_DQ34 AY37 DDR0_DQ[34]/DDR1_DQ[2] DDR1_CKP[0] AP45 M_B_CLK0 [13] [12] M_A_DQ3 M_A_DQ3 AN69 DDR0_DQ[2] DDR0_CKN[1] AT55 M_A_CLK1 [12] [12] M_A_DQ34 M_A_DQ35 AW 37 DDR0_DQ[35]/DDR1_DQ[3] DDR1_CKP[1] AP46 M_B_CLK1 [13] [12] M_A_DQ4 M_A_DQ4 AL70 BA56 [12] M_A_DQ35 M_A_DQ36 BB39 DDR0_DQ[36]/DDR1_DQ[4] AN56 M_B_CKE0 [13] M_A_DQ[0:7] [12] M_A_DQ5 M_A_DQ5 AL69 DDR0_DQ[3] DDR0_CKP[1] BB56 M_A_CKE0 [12] M_A_DQ[32:39] [12] M_A_DQ36 M_A_DQ37 BA39 DDR0_DQ[37]/DDR1_DQ[5] AP55 M_B_CKE1 [13] M_A_DQ[8:15] [12] M_A_DQ6 M_A_DQ6 AN70 DDR0_DQ[4] AW 56 M_A_CKE1 [12] M_A_DQ38 BA37 DDR0_DQ[38]/DDR1_DQ[6] AN55 M_B_DQ[0:7] [12] M_A_DQ7 M_A_DQ7 AN71 DDR0_DQ[5] DDR0_CKE[0] AY56 [12] M_A_DQ37 M_A_DQ39 BB37 DDR0_DQ[39]/DDR1_DQ[7] DDR1_CKE[0] AP53 M_B_DQ[8:15] [12] M_A_DQ8 M_A_DQ8 AR70 DDR0_DQ[6] DDR0_CKE[1] AU45 M_A_CS#0 [12] [12] M_A_DQ38 M_A_DQ40 AY35 DDR0_DQ[40]/DDR1_DQ[8] DDR1_CKE[1] M_A_DQ[16:23] [12] M_A_DQ9 M_A_DQ9 AR68 AU43 M_A_CS#1 [12] [12] M_A_DQ39 M_A_DQ41 AW 35 DDR0_DQ[41]/DDR1_DQ[9] DDR1_CKE[2] M_A_DQ[24:31] [12] M_A_DQ10 M_A_DQ10 AU71 DDR0_DQ[7] DDR0_CKE[2] AT45 M_A_DIMA_ODT0 [12] [12] M_A_DQ40 M_A_DQ42 AY33 DDR0_DQ[42]/DDR1_DQ[10] DDR1_CKE[3] M_B_DQ[16:23] [12] M_A_DQ11 M_A_DQ11 AU68 DDR0_DQ[8] DDR0_CKE[3] AT43 M_A_DIMA_ODT1 [12] M_A_DQ43 AW 33 DDR0_DQ[43]/DDR1_DQ[11] M_B_DQ[24:31] [12] M_A_DQ12 M_A_DQ12 AR71 DDR0_DQ[9] BA51 [12] M_A_DQ41 M_A_DQ44 BB35 DDR0_DQ[44]/DDR1_DQ[12] [12] M_A_DQ13 M_A_DQ13 AR69 BB54 M_A_A5 [12] [12] M_A_DQ42 M_A_DQ45 BA35 DDR0_DQ[45]/DDR1_DQ[13] BB42 M_B_CS#0 [13] [12] M_A_DQ14 M_A_DQ14 AU70 DDR0_DQ[10] DDR0_CS#[0] BA52 M_A_A9 [12] [12] M_A_DQ43 M_A_DQ46 BA33 DDR0_DQ[46]/DDR1_DQ[14] DDR1_CS#[0] AY42 M_B_CS#1 [13] [12] M_A_DQ15 M_A_DQ15 AU69 DDR0_DQ[11] DDR0_CS#[1] AY52 M_A_A6 [12] [12] M_A_DQ44 M_A_DQ47 BB33 DDR0_DQ[47]/DDR1_DQ[15] DDR1_CS#[1] BA42 M_B_DIMB_ODT0 [13] [13] M_B_DQ0 M_B_DQ0 AF65 DDR0_DQ[12] DDR0_ODT[0] AW 52 M_A_A8 [12] M_A_DQ[40:47] M_B_DQ32 AU40 DDR1_DQ[32]/DDR1_DQ[16] DDR1_ODT[0] AW 42 M_B_DIMB_ODT1 [13] [13] M_B_DQ1 M_B_DQ1 AF64 AY55 M_A_A7 [12] M_B_DQ33 AT40 DDR1_DQ[33]/DDR1_DQ[17] DDR1_ODT[1] [13] M_B_DQ2 M_B_DQ2 AK65 DDR0_DQ[13] DDR0_ODT[1] AW 54 M_A_BG0 [12] [12] M_A_DQ45 M_B_DQ34 AT37 DDR1_DQ[34]/DDR1_DQ[18] M_B_A5 [13] [13] M_B_DQ3 M_B_DQ3 AK64 BA54 M_A_A12 [12] [12] M_A_DQ46 M_B_DQ35 AU37 DDR1_DQ[35]/DDR1_DQ[19] M_B_A9 [13] [13] M_B_DQ4 M_B_DQ4 AF66 DDR0_DQ[14] DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] BA55 M_A_A5 M_A_A11 [12] [12] M_A_DQ47 M_B_DQ36 AR40 DDR1_DQ[36]/DDR1_DQ[20] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] AY48 M_B_A5 M_B_A6 [13] [13] M_B_DQ5 M_B_DQ5 AF67 DDR0_DQ[15] AY54 M_A_A9 M_A_ACT_N [12] [13] M_B_DQ32 M_B_DQ37 AP40 DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] AP50 M_B_A9 M_B_A8 [13] [13] M_B_DQ6 M_B_DQ6 AK67 DDR1_DQ[0]/DDR0_DQ[16D]DR0_DQ[16] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] AU46 M_A_A6 M_A_BG1 [12] [13] M_B_DQ33 M_B_DQ38 AP37 DDR1_DQ[38]/DDR1_DQ[22] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] BA48 M_B_A6 M_B_A7 [13] [13] M_B_DQ7 M_B_DQ7 AK66 DDR1_DQ[1]/DDR0_DQ[17D] DR0_DQ[17] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] AU48 M_A_A8 M_B_DQ39 AR37 DDR1_DQ[39]/DDR1_DQ[23] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] BB48 M_B_A8 M_B_BG0 [13] [13] M_B_DQ8 M_B_DQ8 AF70 DDR1_DQ[2]/DDR0_DQ[18]DDR0_DQ[18] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] AT46 M_A_A7 M_A_A13 [12] [13] M_B_DQ34 M_B_DQ40 AT33 DDR1_DQ[40]/DDR1_DQ[24] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] AP48 M_B_A7 M_B_A12 [13] [13] M_B_DQ9 M_B_DQ9 AF68 AU50 M_A_A12 M_A_A15 [12] [13] M_B_DQ35 M_B_DQ41 AU33 DDR1_DQ[41]/DDR1_DQ[25] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] AP52 M_B_A12 M_B_A11 [13] [13] M_B_DQ10 M_B_DQ10 AH71 DDR1_DQ[3]/DDR0_DQ[19]DDR0_DQ[19] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] AU52 M_A_A11 M_A_A14 [12] M_B_DQ[32:39] [13] M_B_DQ36 M_B_DQ42 AU30 DDR1_DQ[42]/DDR1_DQ[26] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] AN50 M_B_A11 M_B_ACT_N [13] [13] M_B_DQ11 M_B_DQ11 AH68 DDR1_DQ[4]/DDR0_DQ[20]DDR0_DQ[20] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] AY51 M_A_A16 [12] M_B_DQ43 AT30 DDR1_DQ[43]/DDR1_DQ[27] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] AN48 M_B_ACT_N M_B_BG1 [13] [13] M_B_DQ12 M_B_DQ12 AF71 DDR1_DQ[5]/DDR0_DQ[21]DDR0_DQ[21]DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] AT48 M_A_A13 M_A_BA0 [12] [13] M_B_DQ37 M_B_DQ44 AR33 DDR1_DQ[44]/DDR1_DQ[28] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# AN53 [13] M_B_DQ13 M_B_DQ13 AF69 AT50 M_A_A15 [13] M_B_DQ38 M_B_DQ45 AP33 DDR1_DQ[45]/DDR1_DQ[29] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] AN52 M_B_A13 [13] [13] M_B_DQ14 M_B_DQ14 AH70 DDR1_DQ[6]/DDR0_DQ[22]DDR0_DQ[22]DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] BB50 M_A_A14 M_A_A2 [12] [13] M_B_DQ39 M_B_DQ46 AR30 DDR1_DQ[46]/DDR1_DQ[30] M_B_A15 [13] [13] M_B_DQ15 M_B_DQ15 AH69 DDR1_DQ[7]/DDR0_DQ[23]DDR0_DQ[23] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# AY50 M_A_A16 M_A_BA1 [12] M_B_DQ47 AP30 DDR1_DQ[47]/DDR1_DQ[31] M_B_A14 [13] [12] M_A_DQ16 M_A_DQ16 BB65 DDR1_DQ[8]/DDR0_DQ[24] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] BA50 M_A_A2 M_A_A10 [12] [13] M_B_DQ40 M_A_DQ48 AY31 DDR0_DQ[48]/DDR1_DQ[32] M_B_A16 [13] [12] M_A_DQ17 M_A_DQ17 AW 65 BB52 M_A_A10 [13] M_B_DQ41 M_A_DQ49 AW 31 DDR0_DQ[49]/DDR1_DQ[33] M_B_BA0 [13] [12] M_A_DQ18 M_A_DQ18 AW 63 DDR1_DQ[9]/DDR0_DQ[25] AM70 M_A_A1 M_A_A1 [12] [13] M_B_DQ42 M_A_DQ50 AY29 DDR0_DQ[50]/DDR1_DQ[34] BA43 M_B_A13 [12] M_A_DQ19 M_A_DQ19 AY63 DDR1_DQ[10]/DDR0_DQ[26] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] AM69 M_A_A0 M_A_A0 [12] M_A_DQ51 AW 29 DDR0_DQ[51]/DDR1_DQ[35] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] AY43 M_B_A15 M_B_A2 [13] [12] M_A_DQ20 M_A_DQ20 BA65 DDR1_DQ[11]/DDR0_DQ[27] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] AT69 M_A_A3 M_A_A3 [12] [13] M_B_DQ43 M_A_DQ52 BB31 DDR0_DQ[52]/DDR1_DQ[36] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] AY44 M_B_A14 M_B_BA1 [13] [12] M_A_DQ21 M_A_DQ21 AY65 DDR1_DQ[12]/DDR0_DQ[28] DDR0_W E#/DDR0_CAB[2]/DDR0_MA[14] AT70 M_A_A4 M_A_A4 [12] M_B_DQ[40:47] [13] M_B_DQ44 M_A_DQ53 BA31 DDR0_DQ[53]/DDR1_DQ[37] DDR1_W E#/DDR1_CAB[2]/DDR1_MA[14] AW 44 M_B_A16 M_B_A10 [13] [12] M_A_DQ22 M_A_DQ22 BA63 AH66 M_A_DQS_DN0 [13] M_B_DQ45 M_A_DQ54 BA29 DDR0_DQ[54]/DDR1_DQ[38] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] BB44 M_B_A2 [12] M_A_DQ23 M_A_DQ23 BB63 DDR1_DQ[13]/DDR0_DQ[29] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] AH65 M_A_DQS_DP0 M_A_DQS0 [13] M_B_DQ46 M_A_DQ55 BB29 DDR0_DQ[55]/DDR1_DQ[39] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] AY47 M_B_A10 M_B_A1 [13] [12] M_A_DQ24 M_A_DQ24 BA61 DDR1_DQ[14]/DDR0_DQ[30] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] AG69 M_A_DQS_DN1 M_A_DQS1 [13] M_B_DQ47 M_A_DQ56 AY27 DDR0_DQ[56]/DDR1_DQ[40] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] BA44 M_B_A1 M_B_A0 [13] [12] M_A_DQ25 M_A_DQ25 AW 61 DDR1_DQ[15]/DDR0_DQ[31] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] AG70 M_A_DQS_DP1 M_B_DQS0 M_A_DQ57 AW 27 DDR0_DQ[57]/DDR1_DQ[41] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] AW 46 M_B_A0 M_B_A3 [13] [12] M_A_DQ26 M_A_DQ26 BB59 DDR0_DQ[16]/DDR0_DQ[32] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] BA64 M_B_DQS_DN0 M_B_DQS1 [12] M_A_DQ48 M_A_DQ58 AY25 DDR0_DQ[58]/DDR1_DQ[42] AY46 M_B_A3 M_B_A4 [13] [12] M_A_DQ27 M_A_DQ27 AW 59 DDR0_DQ[17]/DDR0_DQ[33] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] AY64 M_B_DQS_DP0 M_A_DQS2 [12] M_A_DQ49 M_A_DQ59 AW 25 DDR0_DQ[59]/DDR1_DQ[43] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] BA46 M_B_A4 C [12] M_A_DQ28 M_A_DQ28 BB61 AY60 M_B_DQS_DN1 M_A_DQS3 [12] M_A_DQ50 M_A_DQ60 BB27 DDR0_DQ[60]/DDR1_DQ[44] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] BB46 C [12] M_A_DQ29 M_A_DQ29 AY61 DDR0_DQ[18]/DDR0_DQ[34] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] BA60 M_B_DQS_DP1 M_B_DQS2 [12] M_A_DQ51 M_A_DQ61 BA27 DDR0_DQ[61]/DDR1_DQ[45] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] BA47 DDR4_DRAMRST# [12,13] [12] M_A_DQ30 M_A_DQ30 BA59 DDR0_DQ[19]/DDR0_DQ[35] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] AR66 M_A_DQS_DN2 M_B_DQS3 M_A_DQ[48:55] M_A_DQ62 BA25 DDR0_DQ[62]/DDR1_DQ[46] DDR1_MA[3] [12] M_A_DQ31 M_A_DQ31 AY59 AR65 M_A_DQS_DP2 M_A_DQ63 BB25 DDR0_DQ[63]/DDR1_DQ[47] DDR1_MA[4] [13] M_B_DQ16 M_B_DQ16 AT66 DDR0_DQ[20]/DDR0_DQ[36] DDR0_MA[3] AR61 M_A_DQS_DN3 M_A_ALERT_N [12] [12] M_A_DQ52 M_B_DQ48 AU27 DDR1_DQ[48] [13] M_B_DQ17 M_B_DQ17 AU66 AR60 M_A_DQS_DP3 M_A_PARITY [12] [12] M_A_DQ53 M_B_DQ49 AT27 DDR1_DQ[49] [13] M_B_DQ18 M_B_DQ18 AP65 DDR0_DQ[21]/DDR0_DQ[37] DDR0_MA[4] AW 50 M_B_DQS_DN2 [12] M_A_DQ54 M_B_DQ50 AT25 DDR1_DQ[50] [13] M_B_DQ19 M_B_DQ19 AN65 DDR0_DQ[22]/DDR0_DQ[38] AT52 M_B_DQS_DP2 V_SM_VREF_CNTA [12] M_B_DQ51 AU25 DDR1_DQ[51] [13] M_B_DQ20 M_B_DQ20 AN66 DDR0_DQ[23]/DDR0_DQ[39] DDR0_DQSN[0] AY67 M_B_DQS_DN3 [12] M_A_DQ55 M_B_DQ52 AP27 DDR1_DQ[52] DDR0_DQSN[4]/DDR1_DQSN[0] BA38 M_A_DQS_DN4 [13] M_B_DQ21 M_B_DQ21 AP66 AY68 M_B_DQS_DP3 V_SM_VREF_CNTB [13] [12] M_A_DQ56 M_B_DQ53 AN27 DDR1_DQ[53] DDR0_DQSP[4]/DDR1_DQSP[0] AY38 M_A_DQS_DP4 M_A_DQS4 [13] M_B_DQ22 M_B_DQ22 AT65 DDR0_DQ[24]/DDR0_DQ[40] DDR0_DQSP[0] BA67 [12] M_A_DQ57 M_B_DQ54 AN25 DDR1_DQ[54] DDR0_DQSN[5]/DDR1_DQSN[1] AY34 M_A_DQS_DN5 M_A_DQS5 [13] M_B_DQ23 M_B_DQ23 AU65 DDR0_DQ[25]/DDR0_DQ[41] DDR0_DQSN[1] AW 67 SM_PGCNTL M_B_DQ55 AP25 DDR1_DQ[55] DDR0_DQSP[5]/DDR1_DQSP[1] BA34 M_A_DQS_DP5 M_B_DQS4 [13] M_B_DQ24 M_B_DQ24 AT61 DDR0_DQ[26]/DDR0_DQ[42] DDR0_DQSP[1] [12] M_A_DQ58 M_B_DQ56 AT22 DDR1_DQ[56] DDR1_DQSN[4]/DDR1_DQSN[2] AT38 M_B_DQS_DN4 M_B_DQS5 [13] M_B_DQ25 M_B_DQ25 AU61 DDR0_DQ[27]/DDR0_DQ[43] DDR1_DQSN[0]/DDR0_DQSN[2] M_A_DQ[56:63] [12] M_A_DQ59 M_B_DQ57 AU22 DDR1_DQ[57] DDR1_DQSP[4]/DDR1_DQSP[2] AR38 M_B_DQS_DP4 M_A_DQS6 [13] M_B_DQ26 M_B_DQ26 AP60 M_B_DQ58 AU21 DDR1_DQ[58] DDR1_DQSN[5]/DDR1_DQSN[3] AT32 M_B_DQS_DN5 M_A_DQS7 [13] M_B_DQ27 M_B_DQ27 AN60 DDR0_DQ[28]/DDR0_DQ[44] DDR1_DQSP[0]/DDR0_DQSP[2] [12] M_A_DQ60 M_B_DQ59 AT21 DDR1_DQ[59] DDR1_DQSP[5]/DDR1_DQSP[3] AR32 M_B_DQS_DP5 M_B_DQS6 [13] M_B_DQ28 M_B_DQ28 AN61 [12] M_A_DQ61 M_B_DQ60 AN22 DDR1_DQ[60] DDR0_DQSN[6]/DDR1_DQSN[4] BA30 M_A_DQS_DN6 M_B_DQS7 [13] M_B_DQ29 M_B_DQ29 AP61 DDR0_DQ[29]/DDR0_DQ[45] DDR1_DQSN[1]/DDR0_DQSN[3] [12] M_A_DQ62 M_B_DQ61 AP22 DDR1_DQ[61] DDR0_DQSP[6]/DDR1_DQSP[4] AY30 M_A_DQS_DP6 [13] M_B_DQ30 M_B_DQ30 AT60 DDR0_DQ[30]/DDR0_DQ[46] DDR1_DQSP[1]/DDR0_DQSP[3] [12] M_A_DQ63 M_B_DQ62 AP21 DDR1_DQ[62] DDR0_DQSN[7]/DDR1_DQSN[5] AY26 M_A_DQS_DN7 [13] M_B_DQ31 M_B_DQ31 AU60 DDR0_DQ[31]/DDR0_DQ[47] DDR0_DQSN[2]/DDR0_DQSN[4] [13] M_B_DQ48 M_B_DQ63 AN21 DDR1_DQ[63] DDR0_DQSP[7]/DDR1_DQSP[5] BA26 M_A_DQS_DP7 DDR1_DQ[16]/DDR0_DQ[48] DDR0_DQSP[2]/DDR0_DQSP[4] [13] M_B_DQ49 AR25 M_B_DQS_DN6 DDR1_DQ[17]/DDR0_DQ[49] DDR0_DQSN[3]/DDR0_DQSN[5] DDR1_DQSN[6] AR27 M_B_DQS_DP6 1D2V_S3 DDR1_DQ[18]/DDR0_DQ[50] DDR0_DQSP[3]/DDR0_DQSP[5] [13] M_B_DQ50 DDR1_DQSP[6] AR22 M_B_DQS_DN7 R505 DDR1_DQ[19]/DDR0_DQ[51] DDR1_DQSN[2]/DDR0_DQSN[6] M_B_DQ[48:55] [13] M_B_DQ51 DDR1_DQSN[7] AR21 M_B_DQS_DP7 470R2F-GP [13] M_B_DQ52 DDR1_DQSP[7] 21 DDR1_DQ[20]/DDR0_DQ[52] DDR1_DQSP[2]/DDR0_DQSP[6] [13] M_B_DQ53 DDR1_DQ[21]/DDR0_DQ[53] DDR1_DQSN[3]/DDR0_DQSN[7] DDR1_DQ[22]/DDR0_DQ[54] DDR1_DQSP[3]/DDR0_DQSP[7] [13] M_B_DQ54 [13] M_B_DQ55 DDR1_DQ[23]/DDR0_DQ[55] [13] M_B_DQ56 AN43 DDR1_DQ[24]/DDR0_DQ[56] DDR0_ALERT# DDR1_ALERT# AP43 M_B_ALERT_N [13] DDR1_DQ[25]/DDR0_DQ[57] DDR0_PAR [13] M_B_DQ57 DDR1_PAR AT13 M_B_PARITY [13] DDR1_DQ[26]/DDR0_DQ[58] M_B_DQ[56:63] [13] M_B_DQ58 AR18 SM_DRAMRST# 1 R504 2 [13] M_B_DQ59 DRAM_RESET# AT18 SM_RCOMP_0 R501 1 2 121R2F-GP 0R0402-PAD DDR1_DQ[27]/DDR0_DQ[59] DDR_VREF_CA [13] M_B_DQ60 DDR_RCOMP[0] AU18 SM_RCOMP_1 R502 1 2 80D6R2F-L-GP DDR1_DQ[28]/DDR0_DQ[60] DDR0_VREF_DQ DDR_RCOMP[1] SM_RCOMP_2 R503 1 2 100R2F-L3-GP DDR1_DQ[29]/DDR0_DQ[61] DDR1_VREF_DQ [13] M_B_DQ61 DDR_RCOMP[2] DDR1_DQ[30]/DDR0_DQ[62] [13] M_B_DQ62 [13] M_B_DQ63 DDR CH - B DDR1_DQ[31]/DDR0_DQ[63] DDR CH - A DDR_VTT_CNTL 21 #543016 Layout Note: DY SKYLAKE-U-GP SKYLAKE-U-GP ED502 AZ5725-01FDR7G-GP Design Guideline: 83.05725.0A0 SM_RCOMP keep routing length less than 500 mils. close to CPU DQ Bit Swapping is allowed within the same byte, and Byte Swapping is allowed within the same channel. 3D3V_S5 B Clock (CLK and CLK#) and Strobe (DQS and DQS#) differential signal swapping within a pair is not allowed. Also differential B clock pair to clock pair swapping within a channel is not allowed. R507D2 1 3D3V_S0 10KR2J-L-GP PDG: DDR/ODT Q502 21 R506 Q502_G G 220KR2F-L-GP D SM_PGCNTL_R [51] S SM_PGCNTL G Q501 2N7002K-2-GP DMN5L06K-7-GP 84.2N702.J31 84.05067.031 2ND = 84.2N702.031 S 3rd = 84.07002.I31 ??? Difference with Kyloren A M_A_DQS_DN0 M_A_DQS_DN[7:0] [12] M_B_DQS_DN0 M_B_DQS_DN[7:0] [13] A 5 M_A_DQS_DN1 M_A_DQS_DP[7:0] [12] M_B_DQS_DN1 M_B_DQS_DP[7:0] [13] M_A_DQS_DN2 M_B_DQS_DN2 M_A_DQS_DN3 M_B_DQS_DN3 <Core Design> M_A_DQS_DN4 M_B_DQS_DN4 M_A_DQS_DN5 M_B_DQS_DN5 Wistron Corporation M_A_DQS_DN6 M_B_DQS_DN6 M_A_DQS_DN7 M_B_DQS_DN7 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, M_A_DQS_DP0 Taipei Hsien 221, Taiwan, R.O.C. M_A_DQS_DP1 M_B_DQS_DP0 M_A_DQS_DP2 M_B_DQS_DP1 M_A_DQS_DP3 M_B_DQS_DP2 M_A_DQS_DP4 M_B_DQS_DP3 M_A_DQS_DP5 M_B_DQS_DP4 M_A_DQS_DP6 M_B_DQS_DP5 M_A_DQS_DP7 M_B_DQS_DP6 M_B_DQS_DP7 Title Rev CPU_(DDR) A00 Size Document Number 105 A2 Vegas SKL/KBL-U Date: Wednesday, November 08, 2017 Sheet 5 of 1 43 2

5 4 3 2 1 CPU1S D Main Func = CPU 19 OF 20 C B RESERVED SIGNALS-1 0607 Delete TP TPAD14-OP-GP TP618 1 CFG0 E68 CFG[0] SKYLAKE_ULT RSVD_TP#BB68 BB68 TPAD14-OP-GP TP619 1 CFG1 B67 CFG[1] RSVD_TP#BB69 BB69 Vinafix.comD TPAD14-OP-GP TP620 1 CFG2 D65 CFG[2] RSVD_TP#AK13 AK13 TPAD14-OP-GP TP621 1 CFG3 D67 CFG[3] RSVD_TP#AK12 AK12 TPAD14-OP-GP TP622 1 CFG4 E70 CFG[4] BB2 TPAD14-OP-GP TP623 1 CFG5 C68 CFG[5] RSVD#BB2 BA3 TPAD14-OP-GP TP624 1 CFG6 D68 CFG[6] RSVD#BA3 TPAD14-OP-GP TP625 1 CFG7 C67 CFG[7] TPAD14-OP-GP TP626 1 CFG8 F71 CFG[8] TP5 AU5 TPAD14-OP-GP TP627 1 CFG9 G69 CFG[9] TP6 AT5 TPAD14-OP-GP TP628 1 CFG10 F70 CFG[10] TPAD14-OP-GP TP629 1 CFG11 G68 CFG[11] RSVD#D5 D5 TPAD14-OP-GP TP630 1 CFG12 H70 CFG[12] RSVD#D4 D4 TPAD14-OP-GP TP631 1 CFG13 G71 CFG[13] RSVD#B2 B2 TPAD14-OP-GP TP632 1 CFG14 H69 CFG[14] RSVD#C2 C2 TPAD14-OP-GP TP633 1 CFG15 G70 CFG[15] RSVD#B3 B3 RSVD#A3 A3 TPAD14-OP-GP TP634 1 CFG16 E63 CFG[16] RSVD#AW1 AW1 TPAD14-OP-GP TP635 1 CFG17 F63 CFG[17] RSVD#E1 E1 RSVD#E2 E2 TPAD14-OP-GP TP636 1 CFG18 E66 CFG[18] RSVD#BA4 BA4 TPAD14-OP-GP TP637 1 CFG19 F66 CFG[19] RSVD#BB4 BB4 RSVD#A4 A4 R601 1 2 CFG_RCOMP E60 CFG_RCOMP RSVD#C4 C4 ITP_PMODE E8 ITP_PMODE BB5 49D9R2F-L1-GP 1 TP4 A69 RSVD#A69 B69 TPAD14-OP-GP TP638 RSVD#B69 AY3 RSVD#AY3 D71 AY2 RSVD#AY2 RSVD#D71 C70 AY1 RSVD#AY1 RSVD#C70 C54 RSVD#C54 D54 D1 RSVD#D1 RSVD#D54 AY4 D3 RSVD#D3 BB3 TP1 AY71 K46 RSVD#K46 TP2 AR56 K45 RSVD#K45 VSS AW71 ZVM# AW70 C AL25 RSVD#AL25 RSVD_TP_AW71RSVD_TP#AW71 AP56 AL27 RSVD#AL27 RSVD_TP_AW70RSVD_TP#AW70 C64 MSM# C71 RSVD#C71 PROC_SELECT# B70 RSVD#B70 F60 RSVD#F60 A52 RSVD#A52 TPAD14-OP-GP TP601 1 RSVD_TP_BA70 BA70 RSVD_TP#BA70 TP1_AY4 1 TP610 TPAD14-OP-GP TPAD14-OP-GP TP602 1 RSVD_TP_BA68 BA68 RSVD_TP#BA68 TP2_BB3 1 TP611 TPAD14-OP-GP RSVD#J71 J71 RSVD#J68 VSS_AY71 1 R602 1 2 0R0402-PAD #54469 CRB. J68 ZVM# 1 1 TP616 TPAD14-OP-GP RSVD_TP_AW 71 1 TPAD14-OP-GP TP612 1 RSVD_F65 F65 VSS RSVD_TP_AW 70 TP614 TPAD14-OP-GP TPAD14-OP-GP TP613 1 RSVD_G65 G65 VSS TP615 TPAD14-OP-GP MSM# F61 PROC_SELECT# TP617 TPAD14-OP-GP +VCCST_CPU E61 RSVD#F61 R603 1 DY 2 100KR2J-1-GP RSVD#E61 0515 DY SKYLAKE-U-GP PCH strap pin: CFG3 B [BDW Only]PHYSICAL_DEBUG_ENABLED (DFX PRIVACY)21 R604 0 : ENABLED DY 1KR2J-1-GP CFG[3] SET DFX ENABLED BIT IN DEBUG INTERFACE MSR 1 : DISABLED CFG4 (#543016) 21 R605 DISPLAY PORT PRESENCE STRAP 1KR2J-1-GP 0 : ENABLED CFG[4] An external Display Port device is connected to the Embedded Display Port. 1 : DISABLED (Default) No Physical Display Port attached to Embedded DisplayPort*. No connect for disable. CFG TERMINATIONS #544669 Rev0.52 (CRB) 20140807 david A <Core Design> A SKL(#543016): Wistron Corporation Processor strap CFG[4] should be pulled low to enable embedded DisplayPort* 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Rev CPU_(RESERVED) A00 Size Document Number 105 A3 Vegas SKL/KBL-U Date: W ednesday, November 08, 2017 Sheet 6 of 1 5432

5 4321 Main Func = CPU 20170427 CPU1M 13 OF 20 +VCCGT For U22 & U42 D CPU1L 12 OF 20 CPU POWER 2 OF 4 [46] VCC_SENSE [46] VSS_SENSE VCC_CORE CPU POWER 1 OF 4 VCC_CORE VCCGT N70 +VDDQ_CPU_CLK VCCGT N71 [46] VSSSA_SENSE A30 VCC VCC G32 VCC_SENSE GT_CORE A48 VCCGT SKYLAKE_ULT VCCGT R63 [46] VCCSA_SENSE A34 VCC VCC G33 VSS_SENSE +VCCGT A53 VCCGT VCCGT R64 [46] VCCGT_SENSE A39 VCC Vinafix.comSKYLAKE_ULTVCC G35 H_CPU_SVIDALRT# A58 VCCGT VCCGT R65 21 1D2V_S3 [46] VSSGT_SENSE A44 VCC VCC G37 H_CPU_SVIDCLK A62 VCCGT VCCGT R66 21 AK33 VCC VCC G38 H_CPU_SVIDDAT A66 VCCGT VCCGT R67 DY C722 C AK35 VCC VCC G40 +VCCFUSEPRGR703 1 AA63 VCCGT VCCGT R68 AK37 VCC VCC G42 AA64 VCCGT VCCGT R69 SC1U10V2KX-1GP AK38 VCC VCC J30 0R0402-PAD AA66 VCCGT VCCGT R70 AK40 VCC VCC J33 AA67 VCCGT VCCGT R71 DY SC1U10V2KX-1GP CPU1N +VCCIO(ICCMAX.=2.73A AL33 VCC VCC J37 AA69 VCCGT VCCGT T62 C719 CPU POWER 3 OF 4 14 OF 20 AL37 VCC VCC J40 AA70 VCCGT VCCGT U65 AL40 VCC VCC K33 AA71 VCCGT VCCGT U68 +VCCIO AM32 VCC VCC K35 AC64 VCCGT VCCGT U71 AM33 VCC VCC K37 AC65 VCCGT VCCGT W 63 AU23 VDDQ SKYLAKE_ULT VCCIO AK28 D AM35 VCC VCC K38 AC66 VCCGT VCCGT W 64 AU28 VDDQ VCCIO AK30 C AM37 VCC VCC K40 AC67 VCCGT VCCGT W 65 1D2V_S3 +VDDQ_CPU_CLK AU35 VDDQ VCCIO AL30 B AM38 VCC VCC K42 AC68 VCCGT VCCGT W 66 AU42 VDDQ VCCIO AL42 G30 VCC VCC K43 AC69 VCCGT VCCGT W 67 R705 1 2 BB23 VDDQ VCCIO AM28 +VCCSA AC70 VCCGT VCCGT W 68 0R0603-PAD BB32 VDDQ VCCIO AM30 AC71 VCCGT VCCGT W 69 BB41 VDDQ VCCIO AM42 ??? J43 VCCGT VCCGT W 70 BB47 VDDQ AK23 20170508 20170427 K32 RSVD#K32RSVD_K32 VCC_SENSE E32 GT_CORE J45 VCCGT VCCGT W 71 SC10U6D3V3MX-G2P DY1 C715 BB51 VDDQ VCCSA AK25 待確認 FOR KBL U22 U42 AK32 RSVD#AK3R2SVD_AK32 VSS_SENSE E33 J46 VCCGT VCCGT Y62 VCCSA G23 KYLOREN AB62 VCCOPC VIDALERT# B63 J48 VCCGT +VCCST_CPU AM40 VDDQC VCCSA G25 +V_EDRAM_VR VCCOPC A63 J50 VCCGT 0.04 A A18 VCCST VCCSA G27 VSSSA_SENSE 3A P62 VCCOPC VIDSCK D64 +VCCSTG J52 VCCGT GTX_CORE SC1U10V2KX-1GP2 DY1 C716 VCCSTG VCCSA G28 VCCSA_SENSE V62 VIDSOUT G20 2 J53 VCCGT A22 VCCPLL_OC VCCSA J22 VCCSTG J55 VCCGT AK42 +VCCSTG AL23 VCCPLL VCCSA J23 J56 VCCGT AK43 VCCPLL VCCSA J27 +VCCGT J58 VCCGT VCCGTX AK45 SC1U10V2KX-1GP2 DY1 C717 K20 VCCSA K23 J60 VCCGT VCCGTX AK46 K21 VCCSA K25 +14V10m.A8S_ESyDmbRoAl Merror for H63 NCVCC_OPC_1P8 K48 VCCGT VCCGTX AK48 1D2V_S3 VCCSA K27 layout VCC_OPC_1P8 K50 VCCGT VCCGTX AK50 VCCSA K28 +VCCGT K52 VCCGT VCCGTX AK52 SCD1U16V2KX-3G2P DY1 C718 VCCSA K30 G61 K53 VCCGT VCCGTX AK53 VCCSA AM23 R721 1 DY K55 VCCGT VCCGTX AK55 AM22 AC63 VCCOPC_SENSE GT_CORE K56 VCCGT VCCGTX AK56 H21 AE63 VSSOPC_SENSE 0R2J-L-GP 2 U22_POWER_K52 K58 VCCGT VCCGTX AK58 H20 K60 VCCGT VCCGTX AK60 +V_EOPIO_VR AE62 +VCCGT L62 VCCGT VCCGTX AK70 +V1.00U_CPU VCCIO_SENSE 3A AG62 L63 VCCGT VCCGTX AL43 0.12 A VSSIO_SENSE AL63 VCCEOPIO follow INTEL suggestion L64 VCCGT VCCGTX AL46 AJ62 VCCEOPIO L65 VCCGT VCCGTX AL50 GTX_CORE C720 DY C721 VCCEOPIO_SENSE L66 VCCGT VCCGTX AL53 GTX_CORE 21 VSSSA_SENSE VSSEOPIO_SENSE L67 VCCGT VCCGTX AL56 21 VCCSA_SENSE L68 VCCGT VCCGTX AL60 For U42 L69 VCCGT VCCGTX AM48 SCD1U16V2KX-3GP SKYLAKE-U-GP L70 VCCGT VCCGTX AM50 SCD1U16V2KX-3GP SKYLAKE-U-GP L71 VCCGT VCCGTX AM52 M62 VCCGT VCCGTX AM53 VCC_CORE N63 VCCGT VCCGTX AM56 N64 VCCGT VCCGTX AM58 R710 1 2 100R2F-L3-GP VCC_SENSE N66 VCCGT VCCGTX AU58 only VCC_CORE GT_CORE +VCCGT R711 1 2 100R2F-L3-GP VSS_SENSE N67 VCCGT VCCGTX AU63 N69 VCCGT VCCGTX BB57 Layout Note: VCCGTX BB66 R718 1U42 2 R719 1U22 2 VCCGTX 1. Place close to CPU VCCGT_SENSEJ70 VCCGT_SENSE VCCGTX AK62 D0002R5J-GP-U D0002R5J-GP-U 2. VCC_SENSE/ VSS_SENSE VSSGT_SENSE J69 VSSGT_SENSE VCCGTX_SENSE AL61 VSSGTX_SENSE impedance=50 ohm 3. Length match<25mil SKYLAKE-U-GP +VCCGT VCC_CORE GTX_CORE R712 1 2 100R2F-L3-GP VCCGT_SENSE R720 1U42 2 R713 1 2 100R2F-L3-GP VSSGT_SENSE D0002R5J-GP-U Layout Note: VCCSA_SENSE R716 1 +VCCSA VSSSA_SENSE R717 1 2 100R2F-L3-GP 1. Place close to CPU 2 100R2F-L3-GP 2. VCC_SENSE/ VSS_SENSE impedance=50 ohm 3. Length match<25mil Layout Note: 1. Place close to CPU 2. VCC_SENSE/ VSS_SENSE impedance=50 ohm 3. Length match<25mil Layout Note: The total Length of Data and Clock (from CPU to each VR) must be equal (±0.1 inch). Route the Alert signal between the Clock and the Data signals. B SVID DATA +VCCST_CPU 21 CLOSE TO CPU #544669 R726 100R2F-L3-GP H_CPU_SVIDDAT R709 1 2 VR_SVID_DATA [46] 0R0402-PAD +VCCST_CPU SVID CLOCK 21 #544669 SVID_543016: CLOSE TO VR DY R723 54D9R2F-L1-GP H_CPU_SVIDCLK 1 R732 2 VR_SVID_CLK [46] 0R0402-PAD A A +VCCST_CPU 21 R727 #544669 <Core Design> 56R2J-4-GP CLOSE TO CPU Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. H_CPU_SVIDALRT# R728 1 2 VR_SVID_ALERT# [46] Title 220R2J-L2-GP 4 CPU(VCC_CORE) Size Document Number Rev A2 Turis/Vegas KBL-R A00 Date: Wednesday, November 08, 2017 Sheet 7 of 105 5 3 21

54321 Main Func = CPU CPU1A 1 OF 20 HDMI Vinafix.comD E55 SKYLAKE_ULT C47 eDP_TX_CPU_N0 [55] [57] HDMI_DATA2# F55 DDI1_TXN[0] EDP_TXN[0] C46 eDP_TX_CPU_P0 [55] [57] HDMI_DATA2 E58 DDI1_TXP[0] EDP_TXP[0] D46 eDP_TX_CPU_N1 [55] D [57] HDMI_DATA1# F58 DDI1_TXN[1] EDP_TXN[1] C45 eDP_TX_CPU_P1 [55] C [57] HDMI_DATA1 F53 DDI1_TXP[1] EDP_TXP[1] A45 B [57] HDMI_DATA0# G53 DDI1_TXN[2] EDP_TXN[2] B45 [57] HDMI_DATA0 F56 DDI1_TXP[2] EDP_TXP[2] A47 [57] HDMI_CLK# G56 DDI1_TXN[3] EDP_TXN[3] B47 [57] HDMI_CLK DDI1_TXP[3] EDP_TXP[3] [56] PCH_DPC_N0 C50 DDI2_TXN[0] DDI EDP EDP_AUXN E45 eDP_AUX_CPU_N [55] [56] PCH_DPC_P0 D50 DDI2_TXP[0] EDP_AUXP F45 eDP_AUX_CPU_P [55] DPHtDoMVIGAC [56] PCH_DPC_N1 C52 DDI2_TXN[1] [56] PCH_DPC_P1 D52 DDI2_TXP[1] EDP_DISP_UTIL B52 EDP_DISP_UTIL 1 A50 DDI2_TXN[2] DDI1_AUXN G50 B50 DDI2_TXP[2] DDI1_AUXP F50 TP801 TPAD14-OP-GP D51 DDI2_TXN[3] DDI2_AUXN E48 PCH_DPC_AUXN [56] C51 DDI2_TXP[3] DDI2_AUXP F48 PCH_DPC_AUXP [56] RSVD#G46 G46 DISPLAY SIDEBANDS RSVD#F46 F46 [57] CPU_DP1_CTRL_CLK L13 GPP_E18/DDPB_CTRLCLK Strap GPP_E13/DDPB_HPD0 L9 CPU_DP1_HPD [57] [57] CPU_DP1_CTRL_DATA L12 GPP_E19/DDPB_CTRLDATA Strap GPP_E14/DDPC_HPD1 L7 CPU_DP2_HPD [56] GPP_E15/DDPD_HPD2 L6 EDP_HPD [55] CPU_DP2_CTRL_CLK N7 SKYLAKE-U-GP GPP_E16/DDPE_HPD3 N9 SIO_EXT_SMI#_R CPU_DP2_CTRL_DATA N8 GPP_E20/DDPC_CTRLCLK L10 GPP_E21/DDPC_CTRLDATA GPP_E17/EDP_HPD +VCCIO TPAD14-OP-GP N11 GPP_E22 TP802 1 DDPD_CTRLDATA N12 GPP_E23 Strap R12 EDP_BKLTEN R11 L_BKLT_EN [24] R801 2 EDP_COMP E52 EDP_RCOMP EDP_BKLTCTL U13 L_BKLT_CTRL [55] 1 EDP_VDD_EN [55] EDP_VDDEN 24D9R2F-L-GP (#543016) The Skylake U/Y processor supports only two DDI ports - Port 1 and Port 2. 3D3V_S0 Design Guideline: Skylake processor signal eDP_RCOMP should be connected to the VCCIO rail via a single 24.9 ±1% Ω resistor. RN801 2 3 CPU_DP1_CTRL_CLK 3D3V_S0 1 4 CPU_DP1_CTRL_DATA SIO_EXT_SMI#_R R802 1 2 10KR2J-L-GP SRN2K2J-1-GP CPU_DP2_HPD R806 1Vegas 2 100KR2J-1-GP B RN803 Strap pin: 2 3 CPU_DP2_CTRL_DATA 1 Vegas 4 CPU_DP2_CTRL_CLK Port B / Port C Detected Sampled at rising edge of PCH_PWROK SRN2K2J-1-GP (#543016) eDP_RCOMP Guideline DDPB_CTRLDATA 0 = Port B is not detected. DDPC_CTRLDATA Signal Trace Isolation Resistor Length * 1 = Port B is detected. Width Spacing Value Max = 100 mils 24.9 Ω ±1% 0 = Port C is not detected. eDP_RCOMP 20 mils 25 mils * 1 = Port C is detected. (#543016) DDI Disabling and Termination Guidelines These two signals have weak internal pull-down. Port Strap Enable Port Disable Port <Core Design> Port 1 DDPB_CTRLDATA PU to 3.3 V with 2.2-k NC Wistron Corporation ±5% resistor 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, A PU to 3.3 V with 2.2-k Taipei Hsien 221, Taiwan, R.O.C. A Port 2 DDPC_CTRLDATA ±5% resistor NC Title Size Document Number CPU_(DISPLAY) Rev A4 Vegas SKL/KBL-U A00 Date: Wednesday, November 08, 2017 Sheet 8 of 105 54 321

5 4 3 2 1 D Main Func = CPU 1D2V_S3 10U 0603 x 4 C B VCC_CORE CORE U-line 23e 28W (#543016 PDG) IccMax current-10ms max = 34 A PC1001 PC1002 PC1003 PC1004 PC1005 PC1006 PC1007 PC1008 PC1009 PC1010 PC1011 PC1012 PC1013 PC1014 PC1015 PC1055 PC1057 PC1058 PC1056 PC1059 PC1060 PC1061 PC1062 PC1063 PC1064 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 Vinafix.com DY DY DY DY DY DY DY DY D SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC10U6D3V3MX-GP SC4D7P50V2BN-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC10U6D3V3MX-GP SC4D7P50V2BN-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC10U6D3V3MX-GP SC4D7P50V2BN-GP SC22U6D3V3MX-1-GP SC4D7P50V2BN-GP 22U 0603 x 22 PC1016 PC1017 PC1018 PC1019 PC1020 PC1021 PC1022 PC1023 PC1024 PC1025 PC1026 PC1027 PC1028 PC1029 PC1030 VCCSA+VCCSA DY DY 21 22U 0603 x 8 21 21 PC1045 PC1046 PC1047 PC1048 PC1049 PC1050 PC1051 PC1052 PC1054 PC1098 21 21 DY DY 21 21 21 21 21 21 21 21 21 21 SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP 21 SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP 21 SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP 21 21 21 21 21 21 21 21 PC1040 PC1066 PC1067 PC1068 PC1097 PC1099 +VCCIO 1D0V_S5 SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP 21 SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP 21 SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP 21 SC22U6D3V3MX-1-GP 21 21 21 21 21 21 21 21 +VCCIO(ICCMAX.=2.73A) U42 U42 U42 DY U42 U42 PC1035 PC1036 PC1037 PC1038 PC1039 C DY SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP 20170810 SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP New Common Part SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-DL-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-DL-GP SC22U6D3V3MX-1-GP +VCCGT SLICED GT U-line 23e 28W IccMax current-10ms max[A] = 67 A 22U 0603 x28 PC1031 PC1032 PC1033 PC1034 PC1041 PC1042 PC1043 PC1044 PC1069 PC1070 PC1071 PC1072 PC1073 PC1074 PC1075 DY DY 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP B PC1076 PC1077 PC1078 PC1079 PC1080 PC1081 PC1082 PC1083 PC1084 PC1085 PC1086 PC1087 PC1088 PC1089 PC1090 DY DY 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP PC1091 PC1092 PC1093 PC1094 PC1095 PC1096 PC1053 PC1065 DY DY DY DY U42 U42 21 21 SC22U6D3V3MX-1-GP 21 SC22U6D3V3MX-1-GP 21 21 21 21 21 SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP A <Core Design> A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Rev CPU_(Power CAP1) A00 Size Document Number A3 Vegas SKL/KBL-U Date: W ednesday, November 08, 2017 Sheet 10 of 105 54 3 21

5 4 3 2 1 D Main Func = CPU VCCIO C PCH DERIVED RAILS UNSLICED GT +VCCIO 1D0V_S5 +VCCPRIM_CORE Vinafix.com+VCCGT +VCCIO(ICCMAX.=2.73A) D 1U 0402 x 6 DY R1101 1 2 SC1U10V2KX-1GP SC1U10V2KX-1GP 0R1206-PAD SC1U10V2KX-1GP SC1U10V2KX-1GP C1154 C1153 C1152 C1151 C1150 C1149 C1148 C1147 C1138 C1136 21 DY 21 21 21 21 21 21 21 21 21 +V1.00A_SIP DY DY DY R1117 1 2 0R0603-PAD-2-GP-U 21 C1108 SC22U6D3V3MX-1-GP SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP +VCCMPHYGTAON_1P0(ICCMAX.=2.12A) 3D3V_S5_PCH +V3.3A_SIP C +VCCMPHYGTAON_1P0_LS_SIP +VCCMPHYGTAON_1P0_LS_SIP +VCCMPHYGTAON_1P0_LS_SIP +VCCMPHYGTAON_1P0_LS_SIP R1110 1 2 0R0603-PAD-2-GP-U 21 SC22U6D3V3MX-1-GP C1104 SC1U10V2KX-1GP C1175 SC10U6D3V3MX-GP C1176 SC1U10V2KX-1GP C1172 SC22U6D3V3MX-1-GP C1184 C1180 C1173 SC1U10V2KX-1GP C1174 SC22U6D3V3MX-1-GP C1182 21 21 21 21 21 21 21 21 1D8V_S5 +V1.8A_SIP SC1U10V2KX-1GP SC1U10V2KX-1GP R1139 1 2 Layout Note: 1uF: 0R0603-PAD-2-GP-U 21 SC22U6D3V3MX-1-GP C1174 near N15 C1106 C1180 near K15 B C1173 near AF20 B C1172 near N18 C1175 near AB19 22uF : C1182 C1184 near N15 10uF: C1176 near N15 VCC_CORE 1U 0402 x 5 +VCCPRIM_CORE +V3.3A_SIP U-line 23e 28W IccMax current-10ms max = 34 A SC10U6D3V3MX-GP C1183 PC1106 PC1105 C1117 C1116 C1103 C1102 C1101 21 21 21 21 21 21 21 21 <Core Design> A SC1U10V2KX-1GP SC1U10V2KX-1GP SC22U6D3V3MX-1-GP Wistron Corporation A SC1U10V2KX-1GP SC1U10V2KX-1GP SC22U6D3V3MX-1-GP SC1U10V2KX-1GP 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Rev CPU_(Power CAP2) A00 Size Document Number Custom 105 Vegas SKL/KBL-U Date: Wednesday, November 08, 2017 Sheet 11 of 543 2 1

5 4 3 2 1 Main Func = DDR4 SODIMM 20170502 DM1 062.10011.00U1> DM1A 1 OF 4 062.10011.01C1 144 8 DM1D 4 OF 4 133 7 [5] M_A_A0 132 A0 DQ0 20 M_A_DQ0 [5] DM1B 2 OF 4 1 VSS VSS 99 131 A1 DQ1 21 2 VSS VSS 102 Vinafix.comD [5] M_A_A1 128 A2 DQ2 4 M_A_DQ1 [5] DQS0_C 11 M_A_DQS_DN0 5 VSS VSS 103 D [5] M_A_A2 126 A3 DQ3 3 M_A_DQ2 [5] DQS0_T 13 M_A_DQS_DP0 6 VSS VSS 106 C 127 A4 DQ4 16 DQS1_C 32 M_A_DQS_DN1 9 VSS VSS 107 [5] M_A_A3 122 A5 DQ5 17 M_A_DQ3 [5] DQS1_T 34 M_A_DQS_DP1 10 VSS VSS 167 [5] M_A_A4 125 A6 DQ6 28 M_A_DQ4 [5] DQS2_C 53 M_A_DQS_DN2 14 VSS VSS 168 121 A7 DQ7 29 DQS2_T 55 M_A_DQS_DP2 15 VSS VSS 171 [5] M_A_A5 146 A8 DQ8 41 M_A_DQ5 [5] DQS3_C 74 M_A_DQS_DN3 18 VSS VSS 172 120 A9 DQ9 42 DQS3_T 76 M_A_DQS_DP3 19 VSS VSS 175 [5] M_A_A6 119 A10/AP DQ10 24 M_A_DQ6 [5] DQS4_C 177 M_A_DQS_DN4 22 VSS VSS 176 [5] M_A_A7 158 A11 DQ11 25 M_A_DQ7 [5] DQS4_T 179 M_A_DQS_DP4 23 VSS VSS 180 151 A12 DQ12 38 DQS5_C 198 M_A_DQS_DN5 26 VSS VSS 181 [5] M_A_A8 156 A13 DQ13 37 M_A_DQ8 [5] DQS5_T 200 M_A_DQS_DP5 27 VSS VSS 184 [5] M_A_A9 152 WE#/A14 DQ14 50 M_A_DQ9 [5] DQS6_C 219 M_A_DQS_DN6 30 VSS VSS 185 CAS#/A15 DQ15 49 DQS6_T 221 M_A_DQS_DP6 31 VSS VSS 188 [5] M_A_A10 RAS#/A16 DQ16 62 M_A_DQ10 [5] DQS7_C 240 M_A_DQS_DN7 35 VSS VSS 189 DQ17 63 DQS7_T 242 M_A_DQS_DP7 36 VSS VSS 192 [5] M_A_A11 DQ18 46 M_A_DQ11 [5] DQS8_C 95 39 VSS VSS 193 [5] M_A_A12 DQ19 45 M_A_DQ12 [5] DQS8_T 97 40 VSS VSS 196 DQ20 58 43 VSS VSS 197 [5] M_A_A13 DQ21 59 M_A_DQ13 [5] DM0#/DBI0# 12 44 VSS VSS 201 [5] M_A_A14 DQ22 70 M_A_DQ14 [5] DM1#/DBI# 33 47 VSS VSS 202 DQ23 71 54 48 VSS VSS 205 [5] M_A_A15 DQ24 83 M_A_DQ15 [5] DM2#/DBI2# 75 51 VSS VSS 206 DQ25 84 DM3#/DBI3# 178 52 VSS VSS 209 [5] M_A_A16 DQ26 66 M_A_DQ16 [5] DM4#/DBI4# 199 56 VSS VSS 210 DQ27 67 M_A_DQ17 [5] DM5#/DBI5# 220 1D2V_S3 57 VSS VSS 213 [5] M_A_BA0 150 BA0 DQ28 79 DM6#/DBI6# 241 60 VSS VSS 214 [5] M_A_BA1 145 BA1 DQ29 80 M_A_DQ18 [5] DM7#/DBI7# 96 61 VSS VSS 217 115 BG0 DQ30 174 M_A_DQ19 [5] DM8#/DBI#/NC 64 VSS VSS 218 [5] M_A_BG0 113 BG1 DQ31 173 65 VSS VSS 222 DQ32 187 M_A_DQ20 [5] 68 VSS VSS 223 [5] M_A_BG1 DQ33 186 69 VSS VSS 226 DQ34 170 M_A_DQ21 [5] 72 VSS VSS 227 92 CB0/NC DQ35 169 M_A_DQ22 [5] 73 VSS VSS 230 91 CB1/NC DQ36 183 77 VSS VSS 231 101 CB2/NC DQ37 182 M_A_DQ23 [5] 78 VSS VSS 234 105 CB3/NC DQ38 195 M_A_DQ24 [5] 81 VSS VSS 235 88 CB4/NC DQ39 194 82 VSS VSS 238 87 CB5/NC DQ40 207 M_A_DQ25 [5] 85 VSS VSS 239 100 CB6/NC DQ41 208 86 VSS VSS 243 104 CB7/NC DQ42 191 M_A_DQ26 [5] 89 VSS VSS 244 DQ43 190 M_A_DQ27 [5] 90 VSS VSS 247 [5] M_A_CLK0 137 CK0_T DQ44 203 DDR4-260P-65-GP 93 VSS VSS 248 139 CK0_C DQ45 204 M_A_DQ28 [5] 94 VSS VSS 251 [5] M_A_CLK#0 138 CK1_T/NF DQ46 216 M_A_DQ29 [5] 1D2V_S3 3D3V_S0 98 VSS VSS 252 [5] M_A_CLK1 140 CK1_C/NF DQ47 215 DQ48 228 M_A_DQ30 [5] DY [5] M_A_CLK#1 DQ49 229 DM1C 3 OF 4 DQ50 211 M_A_DQ31 [5] VDDSPD 255 [5] M_A_CKE0 109 CKE0 DQ51 212 M_A_DQ32 [5] 111 VDD [5] M_A_CKE1 110 CKE1 DQ52 224 112 VDD DQ53 225 M_A_DQ33 [5] 117 VDD [5] M_A_CS#0 149 CS0# DQ54 237 M_A_DQ34 [5] 118 VDD VPP 257 2D5V_S3 DY21 SC2D2U10V3KX-L-GP [5] M_A_CS#1 157 CS1# DQ55 236 123 VDD VPP 259 21 C1201 162 C0/CS2#/NC DQ56 249 M_A_DQ35 [5] 124 VDD VTT 258 C 165 C1/CS3#/NC DQ57 250 129 VDD SCD1U16V2KX-3GP DQ58 232 M_A_DQ36 [5] 130 VDD C1228 155 DQ59 233 M_A_DQ37 [5] 135 VDD 0D6V_S0 161 DQ60 245 136 VDD [5] M_A_DIMA_ODT0 ODT0 DQ61 246 M_A_DQ38 [5] 141 VDD [5] M_A_DIMA_ODT1 ODT1 DQ62 M_A_DQ39 [5] 142 VDD DQ63 147 VDD SA0_CHA_DIM0 256 SA0 M_A_DQ40 [5] 148 VDD 261 261 DDR4-260P-65-GP 260 SA1 153 VDD 262 262 SA1_CHA_DIM0 166 SA2 M_A_DQ41 [5] 154 VDD SA2_CHA_DIM0 M_A_DQ42 [5] 159 VDD 160 VDD [13,18,56,65,67] PCH_SMBDATA 254 SDA M_A_DQ43 [5] 163 VDD [13,18,56,65,67] PCH_SMBCLK 253 SCL M_A_DQ44 [5] M_A_DQ45 [5] NP1 NP1 NP2 NP2 M_A_DQ46 [5] 1D2V_S3 [5,13] DDR4_DRAMRST# TS#_DIMM0_1 108 RESET# M_A_DQ47 [5] DDR4-260P-65-GP [5] M_A_ACT_N 114 ACT# R1215 1 DY 116 ALERT# M_A_DQ48 [5] 2 [5] M_A_ALERT_N 134 EVENT#/NF M_A_DQ49 [5] 240R2F-1-GP [5] M_A_PARITY 143 PARITY M_A_DQ50 [5] M_VREF_CA_DIMMA164 VREFCA M_A_DQ51 [5] UN 0225 M_A_DQ52 [5] M_A_DQ53 [5] M_A_DQ54 [5] M_A_DQ55 [5] M_A_DQ56 [5] M_A_DQ57 [5] M_A_DQ58 [5] M_A_DQ59 [5] M_A_DQ60 [5] M_A_DQ61 [5] M_A_DQ62 [5] M_A_DQ63 [5] DDR4_DRAMRST# 21 C1229 DDR4-260P-65-GP SCD1U16V2KX-3GP 21 062.10011.01C1 1D2V_S3 0D6V_S0 0D6V_S0 0D6V_S0 AZ5725-01FDR7G-GP ???跟sw確認 DDR4 SWAP 0212 C1226 ED1217 C1225 C1227 C1224 C1230 C1223 C1210 C1209 C1208 C1206 C1205 C1204 C1203 C1202 21 21 21 21 21 21 21 21 21 21 21 21 21 21 DY DY DY DY DY DY DY 3D3V_S0 B R1204 1 DY 2 10KR2F-L1-GP SA0_CHA_DIM0 B 2 0R0402-PAD Layout note: closed to Dimm R1205 1 SC10U6D3V3MX-GP SC10U6D3V3MX-GP SC4D7U6D3V2MX-1-GP SC4D7U6D3V2MX-1-GP SC1U10V2KX-1GP SC10U6D3V3MX-GP SC10U6D3V3MX-GP SC4D7U6D3V2MX-1-GP SC4D7U6D3V2MX-1-GP SC1U10V2KX-1GP 1D2V_S3 SC10U6D3V3MX-GP SC10U6D3V3MX-GP for placement modify 2015/10/19 RN1201 SC10U6D3V3MX-GP SC10U6D3V3MX-GP 1 4 R1206 3D3V_S0 2 3 2R2F-GP R1208 1 DY C1213 C1207 R1210 1 C1232 C1231 C1212 C1211 C1221 C1220 C1219 C1218 C1217 C1216 C1215 C1214 M_VREF_CA_DIMMA1 2 V_SM_VREF_CNTA [5] 21 2D5V_S3 C1222 21 SCD022U16V2KX-3GP 2 10KR2F-L1-GP SA1_CHA_DIM0 21 2 0R0402-PAD 21 +V_VREF_PATH1 21 21 R1209 21 24D9R2F-L-GP 21 21 21 21 21 21 21 SRN1KJ-7-GP 12 1 DY DY DY DY DY DY DY DY DY 2 3D3V_S0 2 10KR2F-L1-GP SA2_CHA_DIM0 SC1U10V2KX-1GP SC1U10V2KX-1GP 2 0R0402-PAD SC1U10V2KX-1GP SC1U10V2KX-1GP R1211 1 DY SC1U10V2KX-1GP SC1U10V2KX-1GP R1212 1 SC1U10V2KX-1GP SC1U10V2KX-1GP SC4D7U6D3V2MX-1-GP SC1U10V2KX-1GP SC4D7U6D3V2MX-1-GP SC1U10V2KX-1GP SC4D7U6D3V2MX-1-GP M_A_DQS_DN[7:0] [5] SC4D7U6D3V2MX-1-GP A M_A_DQS_DN0 M_A_DQS_DP0 M_A_DQS_DP[7:0] [5] A M_A_DQS_DN1 M_A_DQS_DP1 2 <Core Design> M_A_DQS_DN2 M_A_DQS_DP2 Wistron Corporation M_A_DQS_DN3 M_A_DQS_DP3 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, M_A_DQS_DN4 M_A_DQS_DP4 Taipei Hsien 221, Taiwan, R.O.C. M_A_DQS_DN5 M_A_DQS_DP5 M_A_DQS_DN6 M_A_DQS_DP6 M_A_DQS_DN7 M_A_DQS_DP7 Title DDR4-SODIMM1 Rev Size Document Number A00 Custom Vegas SKL/KBL-U Date: Wednesday, November 08, 2017 Sheet 12 of 106 54 3 1

5 4 3 21 Main Func = DDR4 SODIMM 20170502 DM1 062.10011.00T1> DM2A 1 OF 4 1D2V_S3 062.10011.01B1 [5] M_B_A0 144 A0 DQ0 8 M_B_DQ8 [5] DM2C 3 OF 4 3D3V_S0 D [5] M_B_A1 133 A1 DQ1 7 M_B_DQ9 [5] VDDSPD 255 [5] M_B_A2 132 A2 DQ2 20 M_B_DQ10 [5] 111 DM2D 4 OF 4 C [5] M_B_A3 131 A3 DQ3 21 M_B_DQ11 [5] 112 Vinafix.comD [5] M_B_A4 128 A4 DQ4 4 M_B_DQ12 [5] 117 VDD VPP 257 2D5V_S3 DY 21 SCD1U16V2KX-3GPDY 1 VSS VSS 99 [5] M_B_A5 126 A5 DQ5 3 M_B_DQ13 [5] 118 VDD VPP 259 21C1328 2 VSS VSS 102 C [5] M_B_A6 127 A6 DQ6 16 M_B_DQ14 [5] 123 VDD 0D6V_S0 5 VSS VSS 103 [5] M_B_A7 122 A7 DQ7 17 M_B_DQ15 [5] 124 VDD VTT 258 SC2D2U10V3KX-L-GP 6 VSS VSS 106 [5] M_B_A8 125 A8 DQ8 28 M_B_DQ0 [5] 129 VDD C1329 9 VSS VSS 107 [5] M_B_A9 121 A9 DQ9 29 M_B_DQ1 [5] 130 VDD 10 VSS VSS 167 [5] M_B_A10 146 A10/AP DQ10 41 M_B_DQ2 [5] 135 VDD 261 261 14 VSS VSS 168 [5] M_B_A11 120 A11 DQ11 42 M_B_DQ3 [5] 136 VDD 262 262 15 VSS VSS 171 [5] M_B_A12 119 A12 DQ12 24 M_B_DQ4 [5] 141 VDD 18 VSS VSS 172 [5] M_B_A13 158 A13 DQ13 25 M_B_DQ5 [5] 142 VDD NP1 NP1 19 VSS VSS 175 [5] M_B_A14 151 WE#/A14 DQ14 38 M_B_DQ6 [5] 147 VDD NP2 NP2 22 VSS VSS 176 [5] M_B_A15 156 CAS#/A15 DQ15 37 M_B_DQ7 [5] 148 VDD 23 VSS VSS 180 [5] M_B_A16 152 RAS#/A16 DQ16 50 M_B_DQ16 [5] 153 VDD 26 VSS VSS 181 DQ17 49 M_B_DQ17 [5] 154 VDD 27 VSS VSS 184 [5] M_B_BA0 150 BA0 DQ18 62 M_B_DQ18 [5] 159 VDD 30 VSS VSS 185 [5] M_B_BA1 145 BA1 DQ19 63 M_B_DQ19 [5] 160 VDD 31 VSS VSS 188 [5] M_B_BG0 115 BG0 DQ20 46 M_B_DQ20 [5] 163 VDD 35 VSS VSS 189 [5] M_B_BG1 113 BG1 DQ21 45 M_B_DQ21 [5] VDD 36 VSS VSS 192 DQ22 58 M_B_DQ22 [5] VDD 39 VSS VSS 193 [5] M_B_CLK0 92 CB0/NC DQ23 59 M_B_DQ23 [5] 40 VSS VSS 196 [5] M_B_CLK#0 91 CB1/NC DQ24 70 M_B_DQ24 [5] DDR4-260P-64-GP 43 VSS VSS 197 [5] M_B_CLK1 101 CB2/NC DQ25 71 M_B_DQ25 [5] 44 VSS VSS 201 [5] M_B_CLK#1 105 CB3/NC DQ26 83 M_B_DQ26 [5] DM2B 2 OF 4 47 VSS VSS 202 88 CB4/NC DQ27 84 M_B_DQ27 [5] 48 VSS VSS 205 [5] M_B_CKE0 87 CB5/NC DQ28 66 M_B_DQ28 [5] DQS0_C 11 M_B_DQS_DN1 M_B_DQS_DN1 [5] 51 VSS VSS 206 [5] M_B_CKE1 100 CB6/NC DQ29 67 M_B_DQ29 [5] DQS0_T 13 M_B_DQS_DP1 M_B_DQS_DP1 [5] 52 VSS VSS 209 104 CB7/NC DQ30 79 M_B_DQ30 [5] DQS1_C 32 M_B_DQS_DN0 M_B_DQS_DN0 [5] 56 VSS VSS 210 [5] M_B_CS#0 DQ31 80 M_B_DQ31 [5] DQS1_T 34 M_B_DQS_DP0 M_B_DQS_DP0 [5] 57 VSS VSS 213 [5] M_B_CS#1 137 CK0_T DQ32 174 M_B_DQ32 [5] DQS2_C 53 M_B_DQS_DN2 M_B_DQS_DN2 [5] 60 VSS VSS 214 139 CK0_C DQ33 173 M_B_DQ33 [5] DQS2_T 55 M_B_DQS_DP2 M_B_DQS_DP2 [5] 61 VSS VSS 217 [5] M_B_DIMB_ODT0 138 CK1_T/NF DQ34 187 M_B_DQ34 [5] DQS3_C 74 M_B_DQS_DN3 M_B_DQS_DN3 [5] 64 VSS VSS 218 [5] M_B_DIMB_ODT1 140 CK1_C/NF DQ35 186 M_B_DQ35 [5] DQS3_T 76 M_B_DQS_DP3 M_B_DQS_DP3 [5] 65 VSS VSS 222 DQ36 170 M_B_DQ36 [5] DQS4_C 177 M_B_DQS_DN4 M_B_DQS_DN4 [5] 68 VSS VSS 223 [12,18,56,65,67] PCH_SMBDATA 109 CKE0 DQ37 169 M_B_DQ37 [5] DQS4_T 179 M_B_DQS_DP4 M_B_DQS_DP4 [5] 69 VSS VSS 226 [12,18,56,65,67] PCH_SMBCLK 110 CKE1 DQ38 183 M_B_DQ38 [5] DQS5_C 198 M_B_DQS_DN5 M_B_DQS_DN5 [5] 72 VSS VSS 227 DQ39 182 M_B_DQ39 [5] DQS5_T 200 M_B_DQS_DP5 M_B_DQS_DP5 [5] 73 VSS VSS 230 149 CS0# DQ40 195 M_B_DQ40 [5] DQS6_C 219 M_B_DQS_DN6 M_B_DQS_DN6 [5] 77 VSS VSS 231 157 CS1# DQ41 194 M_B_DQ41 [5] DQS6_T 221 M_B_DQS_DP6 M_B_DQS_DP6 [5] 78 VSS VSS 234 162 C0/CS2#/NC DQ42 207 M_B_DQ42 [5] DQS7_C 240 M_B_DQS_DN7 M_B_DQS_DN7 [5] 81 VSS VSS 235 165 C1/CS3#/NC DQ43 208 M_B_DQ43 [5] DQS7_T 242 M_B_DQS_DP7 M_B_DQS_DP7 [5] 82 VSS VSS 238 DQ44 191 M_B_DQ44 [5] DQS8_C 95 85 VSS VSS 239 155 ODT0 DQ45 190 M_B_DQ45 [5] DQS8_T 97 1D2V_S3 86 VSS VSS 243 161 ODT1 DQ46 203 M_B_DQ46 [5] 89 VSS VSS 244 DQ47 204 M_B_DQ47 [5] 90 VSS VSS 247 SA0_CHB_DIM0 256 SA0 DQ48 216 M_B_DQ48 [5] 93 VSS VSS 248 SA1_CHB_DIM0 260 SA1 DQ49 215 M_B_DQ49 [5] 94 VSS VSS 251 SA2_CHB_DIM0 166 SA2 DQ50 228 M_B_DQ50 [5] 98 VSS VSS 252 DQ51 229 M_B_DQ51 [5] 254 SDA DQ52 211 M_B_DQ52 [5] DM0#/DBI0# 12 DDR4-260P-64-GP 253 SCL DQ53 212 M_B_DQ53 [5] DM1#/DBI# 33 DQ54 224 M_B_DQ54 [5] 54 1D2V_S3 [5,12,13] DDR4_DRAMRST# 108 RESET# DQ55 225 M_B_DQ55 [5] DM2#/DBI2# 75 [5] M_B_ACT_N 114 ACT# DQ56 237 M_B_DQ56 [5] DM3#/DBI3# 178 116 ALERT# DQ57 236 M_B_DQ57 [5] DM4#/DBI4# 199 2 [5] M_B_ALERT_N TS#_DIMM1_1 134 EVENT#/NF DQ58 249 M_B_DQ58 [5] DM5#/DBI5# 220 DQ59 250 M_B_DQ59 [5] DM6#/DBI6# 241 143 PARITY DQ60 232 M_B_DQ60 [5] DM7#/DBI7# 96 DQ61 233 M_B_DQ61 [5] DM8#/DBI#/NC R1312 1 DY VREFCA DQ62 245 M_B_DQ62 [5] DQ63 246 M_B_DQ63 [5] 240R2F-1-GP [5] M_B_PARITY DDR4-260P-64-GP M_VREF_CA_DIMMB 164 21 C1301 0D6V_S0 0D6V_S0 0D6V_S0 2D5V_S3 21 SCD1U16V2KX-3GP DDR4_DRAMRST# DDR4-260P-64-GP DY DY DY DY 062.10011.01B1 1D2V_S3 C1314 C1313 C1331 C1330 C1312 C1311 C1327 C1326 SC10U6D3V3MX-GP C1325 SC10U6D3V3MX-GP C1324 C1310 C1309 C1308 C1307 C1306 C1305 C1304 C1303 AZ5725-01FDR7G-GP 跟sw確認 DDR4 SWAP 0212 21 DY ED1302 21 3D3V_S0 2 10KR2F-L1-GP SA0_CHB_DIM0 21 2 0R0402-PAD 21 R1302 1 DY 21 21 R1303 1 21 21 21 21 21 21 21 21 21 21 21 21 B DY DY DY DY DY SC1U10V2KX-1GP SC4D7U6D3V2MX-1-GP SC1U10V2KX-1GP B SC1U10V2KX-1GP SC4D7U6D3V2MX-1-GP SC1U10V2KX-1GP Layout note: closed to Dimm SC4D7U6D3V2MX-1-GP 0921 Install UN 0225 SC4D7U6D3V2MX-1-GP 1D2V_S3 3D3V_S0 SC10U6D3V3MX-GP SC10U6D3V3MX-GP M_B_DQS_DN[7:0] [5] R1306 1 SC10U6D3V3MX-GP SC10U6D3V3MX-GP M_B_DQS_DP[7:0] [5] RN1301 4 M_VREF_CA_DIMMB 1 R1305 2 2 10KR2F-L1-GP SA1_CHB_DIM0 SC10U6D3V3MX-GP SC10U6D3V3MX-GP M_B_DQS_DN0 1 3 R1307 1 DY 2 0R2J-L-GP SC10U6D3V3MX-GP SC10U6D3V3MX-GP M_B_DQS_DN1 2 M_B_DQS_DN2 V_SM_VREF_CNTB [5] DY DY DY DY M_B_DQS_DN3 C1322 M_B_DQS_DN4 C1323 C1321 M_B_DQS_DN5 SCD022U16V2KX-3GP C1320 M_B_DQS_DN6 C1319 M_B_DQS_DN7 +V_VREF_PATH2 C1318 C1317 M_B_DQS_DP0 R1309 C1316 M_B_DQS_DP1 24D9R2F-L-GP C1315 M_B_DQS_DP2 SRN1KJ-7-GP 2R2F-GP 12 1 21 M_B_DQS_DP3 21 M_B_DQS_DP4 3D3V_S0 21 M_B_DQS_DP5 21 M_B_DQS_DP6 R1310 1 DY 21 M_B_DQS_DP7 21 R1311 1 21 21 2 10KR2F-L1-GP SA2_CHB_DIM0 2 0R0402-PAD 2 SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP AA <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title DDR4-SODIMM1 Size Document Number Rev Custom Vegas SKL/KBL-U A00 Date: Wednesday, November 08, 2017 Sheet 13 of 106 54321

5 4 3 21 D Main Func = PCH 3D3V_S0 CPU1I 9 OF 20 CSI-2 SKYLAKE_ULT Vinafix.comD A36 C37 W IFI_RF_EN R101K5R032J1D-LY-GP 2 B36 D37 C38 CSI2_DN0 CSI2_CLKN0 C32 DC resistance < 0.5ohm. D38 CSI2_DP0 CSI2_CLKP0 D32 C36 CSI2_DN1 CSI2_CLKN1 C29 D36 CSI2_DP1 CSI2_CLKP1 D29 A38 CSI2_DN2 CSI2_CLKN2 B26 B38 CSI2_DP2 CSI2_CLKP2 A26 CSI2_DN3 CSI2_CLKN3 CSI2_DP3 CSI2_CLKP3 C31 CSI2_DN4 CSI2_COMP E13 CSI2_COMP R1501 1 2 100R2F-L3-GP D31 CSI2_DP4 GPP_D4/FLASHTRIG B7 W IFI_RF_EN C33 CSI2_DN5 D33 CSI2_DP5 EMMC AP2 EMMC_D0 [63] [#545659 Rev0.7] A31 CSI2_DN6 AP1 EMMC_D1 [63] B31 CSI2_DP6 GPP_F13/EMMC_DATA0 AP3 EMMC_D2 [63] A33 CSI2_DN7 GPP_F14/EMMC_DATA1 AN3 EMMC_D3 [63] B33 CSI2_DP7 GPP_F15/EMMC_DATA2 AN1 EMMC_D4 [63] GPP_F16/EMMC_DATA3 AN2 EMMC_D5 [63] A29 CSI2_DN8 GPP_F17/EMMC_DATA4 AM4 EMMC_D6 [63] B29 CSI2_DP8 GPP_F18/EMMC_DATA5 AM1 EMMC_D7 [63] C28 CSI2_DN9 GPP_F19/EMMC_DATA6 AM2 D28 CSI2_DP9 GPP_F20/EMMC_DATA7 AM3 EMMC_RCLK [63] A27 CSI2_DN10 AP4 B27 CSI2_DP10 GPP_F21/EMMC_RCLK AT1 EMMC_CLK [63] C27 CSI2_DN11 GPP_F22/EMMC_CLK D27 CSI2_DP11 GPP_F12/EMMC_CMD EMMC_CMD [63] EMMC_RCOMP EMMC_RCOMP R1502 1 2 200R2F-L-GP SKYLAKE-U-GP C C GPP_F: VCCPGPPF = 1.8V Only [61] W IFI_RF_EN B B A <Core Design> A 543 Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Rev CPU_(CS-2/EMMC) A00 Size Document Number A3 Vegas SKL/KBL-U Date: W ednesday, November 08, 2017 Sheet 15 of 105 21

54321 Main Func = PCH #543016: CPU1H 8 OF 20 220 nF nominal capacitors are recommended for Gen 3. 100 nF nominal capacitors are recommended for Gen 2. GLWAPLNUAN Vinafix.com UUUSSSBBB132UU(((SSUUIBBOSS12BBB((D33UU../00SSUBBSPp33Boo..rr200tt.120PP))ooPrrottr12t))3)D SKYLAKE_ULT PCIE/USB3/SATA SSIC / USB3 USB3_1_RXN H8 USB30_RX_CPU_N1 [36] (#545659) The xHCI controller supports USB Debug port on all USB3.0 capable ports. USB3_1_RXP G8 USB30_RX_CPU_P1 [36] [76] PEG_RX_CPU_N0 C1606 11OOPPSS22 SCD22U10V2KX-L1-GP PEG_TX_CPU_N0 H13 PCIE1_RXN/USB3_5_RXN USB3_1_TXN C13 USB30_TX_CPU_N1 [36] [76] PEG_RX_CPU_P0 C1605 SCD22U10V2KX-L1-GP PEG_TX_CPU_P0 G13 PCIE1_RXP/USB3_5_RXP USB3_1_TXP D13 USB30_TX_CPU_P1 [36] [76] PEG_TX_GPU_N0 B17 PCIE1_TXN/USB3_5_TXN USB3_2_RXN/SSIC_RXN J6 [76] PEG_TX_GPU_P0 A17 PCIE1_TXP/USB3_5_TXP USB3_2_RXP/SSIC_RXP H6 USB30_RX_CPU_N2 [36] D PCIE2_RXN/USB3_6_RXN USB3_2_TXN/SSIC_TXN B13 USB30_RX_CPU_P2 [36] C [76] PEG_RX_CPU_N1 C1608 11OOPPSS22 SCD22U10V2KX-L1-GP PEG_TX_CPU_N1 G11 PCIE2_RXP/USB3_6_RXP USB3_2_TXP/SSIC_TXP A13 USB30_TX_CPU_N2 [36] B [76] PEG_RX_CPU_P1 C1607 SCD22U10V2KX-L1-GP PEG_TX_CPU_P1 F11 PCIE2_TXN/USB3_6_TXN USB3_3_RXN J10 USB30_TX_CPU_P2 [36] [76] PEG_TX_GPU_N1 D16 PCIE2_TXP/USB3_6_TXP USB3_3_RXP H10 [76] PEG_TX_GPU_P1 C16 PCIE3_RXN USB3_3_TXN B15 PCIE3_RXP USB3_3_TXP A15 [76] PEG_RX_CPU_N2 C1610 11OOPPSS22 SCD22U10V2KX-L1-GP PEG_TX_CPU_N2 H16 PCIE3_TXN USB3_4_RXN E10 [76] PEG_RX_CPU_P2 C1609 SCD22U10V2KX-L1-GP PEG_TX_CPU_P2 G16 PCIE3_TXP USB3_4_RXP F10 [76] PEG_TX_GPU_N2 D17 PCIE4_RXN USB3_4_TXN C15 [76] PEG_TX_GPU_P2 C17 PCIE4_RXP USB3_4_TXP D15 PCIE4_TXN AB9 [76] PEG_RX_CPU_N3 C1612 11OOPPSS22 SCD22U10V2KX-L1-GP PEG_TX_CPU_N3 G15 PCIE4_TXP USB2N_1 AB10 USB_CPU_PN0 [36] [76] PEG_RX_CPU_P3 C1611 SCD22U10V2KX-L1-GP PEG_TX_CPU_P3 F15 PCIE5_RXN USB2P_1 AD6 USB_CPU_PP0 [36] [76] PEG_TX_GPU_N3 B19 PCIE5_RXP USB2N_2 AD7 [76] PEG_TX_GPU_P3 A19 PCIE5_TXN USB2P_2 AH3 USB_CPU_PN1 [36] PCIE5_TXP USB2N_3 AJ3 USB_CPU_PP1 [36] 0516 Swap [31] PCIE_RX_CPU_N5 F16 PCIE6_RXN USB2P_3 AD9 [31] PCIE_RX_CPU_P5 E16 PCIE6_RXP USB2N_4 AD10 USB_CPU_PN2 [37] [31] PCIE_TX_CON_N5 C1601 1 2 SCD1U16V2KX-3GP PCIE_TX_CPU_N5 C19 PCIE6_TXN USB2P_4 USB_CPU_PP2 [37] [31] PCIE_TX_CON_P5 C1602 1 2 SCD1U16V2KX-3GP PCIE_TX_CPU_P5 D19 PCIE6_TXP [61] PCIE_RX_CPU_N6 C1603 1 2 SCD1U16V2KX-3GP PCIE_TX_CPU_N6 G18 [61] PCIE_RX_CPU_P6 C1604 1 2 SCD1U16V2KX-3GP PCIE_TX_CPU_P6 F18 [61] PCIE_TX_CON_N6 D20 [61] PCIE_TX_CON_P6 C20 HDD1 [60] SATA_RX_CPU_N0 F20 PCIE7_RXN/SATA0_RXN USB2N_5 AJ1 USB_CPU_PN4 [55] CAMERA (USB2.0 Port5) ODD [60] SATA_RX_CPU_P0 E20 PCIE7_RXP/SATA0_RXP USB2P_5 AJ2 USB_CPU_PP4 [55] [60] SATA_TX_CPU_N0 B21 PCIE7_TXN/SATA0_TXN [60] SATA_TX_CPU_P0 A21 PCIE7_TXP/SATA0_TXP USB2 AF6 AF7 [60] SATA_RX_CPU_N1 G21 USB2N_6 USB_CPU_PN5 [33] Card Reader (USB2.0 Port6) [60] SATA_RX_CPU_P1 F21 USB2P_6 USB_CPU_PP5 [33] [60] SATA_TX_CPU_N1 D21 [60] SATA_TX_CPU_P1 C21 PCIE8_RXN/SATA1A_RXN USB2N_7 AH1 USB_CPU_PN6 [61] WLAN (USB2.0 Port7) PCIE8_RXP/SATA1A_RXP USB2P_7 AH2 USB_CPU_PP6 [61] PCIE8_TXN/SATA1A_TXN PCIE8_TXP/SATA1A_TXP USB2N_8 AF8 USB_CPU_PN7 [55] Touch Screen (USB2.0 Port8) USB2P_8 AF9 USB_CPU_PP7 [55] E22 PCIE9_RXN E23 PCIE9_RXP USB2N_9 AG1 USB_CPU_PN8 [92] Finger Print (USB2.0 Port9) B23 PCIE9_TXN USB2P_9 AG2 USB_CPU_PP8 [92] A23 PCIE9_TXP 0511 Remove SSD F25 PCIE10_RXN USB2N_10 AH7 E25 PCIE10_RXP USB2P_10 AH8 D23 PCIE10_TXN USB2_COMP AB6 DC resistance < 0.5ohm. C23 PCIE10_TXP AG3 +V1.8A_SIP PCIE_RCOMPN USB2_ID AG4 USBCOMP R1603 1 2 113R2F-GP F5 PCIE_RCOMPP USB2_VBUSSENSE A9 USB2_ID R1601 1 2 0R0402-PAD 21 PCIE_RCOMPN E5 PROC_PRDY# GPP_E9/USB2_OC0# C9 USB2_VBUSSENSE R1602 1 2 0R0402-PAD 2 PCIE_RCOMPP D56 PROC_PREQ# GPP_E10/USB2_OC1# D9 R1607 R1604 1 D61 GPP_A7/PIRQA# GPP_E11/USB2_OC2# B9 USB_OC1# USB_OC0# [35] Unused SATA[3:0]GP pins must be terminated to either 10KR2J-L-GP 100R2F-L3-GP 1 XDP_PRDY# BB11 GPP_E12/USB2_OC3# USB_OC2# USB_OC2# [35] 3.3V rail or GND using 8.2K  to 10K  on the 1 XDP_PREQ# USB_OC3# motherboard. Either pull-up or pull-down is acceptable. 0620 Connect to TPM TPAD14-OP-GP TP1601 (#543016) When used as DEVSLP, no external pull-up or pull-down [91] PIRQA# TPAD14-OP-GP TP1602 PIRQA# E28 PCIE11_RXN/SATA1B_RXN GPP_E4/DEVSLP0 J1 SIO_EXT_SCI# HDD_DEVSLP [60] termination required from SATA Host DEVSLP. E27 PCIE11_RXP/SATA1B_RXP GPP_E5/DEVSLP1 J2 GPP_E0/SATAXPCIE0/SATAGP0 C D24 PCIE11_TXN/SATA1B_TXN GPP_E6/DEVSLP2 J3 TP1603 TPAD14-OP-GP C24 PCIE11_TXP/SATA1B_TXP GPP_E0/SATAXPCIE0/SATAGP0 H2 1 0511 Remove SSD E30 PCIE12_RXN/SATA2_RXN GPP_E1/SATAXPCIE1/SATAGP1 H3 F30 PCIE12_RXP/SATA2_RXP GPP_E2/SATAXPCIE2/SATAGP2 G4 SATA_ODD_PRSNT# [60] A25 PCIE12_TXN/SATA2_TXN GPP_E8/SATALED# H1 B25 PCIE12_TXP/SATA2_TXP SATA_LED#_R [64] 3D3V_S0 SKYLAKE-U-GP 3D3V_S5_PCH 3D3V_S0 SIO_EXT_SCI# R1610 1 1 10KR2J-L-GP Layout Note: 3D3V_S0 USB_OC2# RN802 2 2 8 3 1. Trace Width: 4 mils min (breakout) 12-15 mils (trace) USB_OC3# 7 4 Note: Must maintain low DC resistance routing (<0.1 ohm). 6 2. Isolation Spacing: At least 12 mils to any adjacent USB_OC0# 5 SATA_LED#_R R1606 1 2 high speed I/O. 10KR2J-L-GP SATA_ODD_PRSNT# R1608 1 2 USB_OC1# 10KR2J-L-GP SRN10KJ-6-GP (#543016) Unused SATAGP[2:0]/GPP_E[2:0] pins must be terminated to either 3.3 V rail or GND (#543611) using 8.2 KΩ to 10 KΩ on the motherboard. The SATALED# signal is open-collector and requires a weak external pull-up (8.2 kΩ to 10 kΩ) to Vcc3_3. Do not use both pull-up and pull-down. Either pull-up or pull-down is acceptable. PCIE Table USB 2.0 Table Pair Device Port Device Share BUS 1 N/A USB3.0_3 0 USB3.0 port1 2 N/A USB3.0_4 1 USB3.0 Port2 3 WLAN 2 USB2.0 Port3 (IOBD) B 4 LAN 3 Finger Print 5(L0~L3) GPU 4 CAMERA 6(L3) HDD SATA0 5 Card Reader 6(L2) ODD SATA1 6 Touch Panel 6(L0~L1) N/A 7 WLAN #545659 (SKL_PCH_U_Y_EDS Rev0.7) AA <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Rev CPU_(PCIE/SATA/USB) A00 Size Document Number A1 Turis/Vegas KBL-R Date: Wednesday, November 08, 2017 Sheet 16 of 105 54321

54321 Main Func = PCH +V3.3A_SIP 3D3V_S5 21 CPU1K 11 OF 20 RN1704 21 8 AC_PRESENT R1701 SYSTEM POWER MANAGEMENT 1 7 PCH_W AKE# 10KR2J-L-GP 2 6 PCH_BATLOW # AT11 SIO_SLP_S0# 1 3 5 GPP_B12/SLP_S0# AP15 SIO_SLP_S3# 1 TP1701 TPAD14-OP-GP 4 GPD11/LANPHYPC GPD4/SLP_S3# BA16 SIO_SLP_S4# GPD11 pull high SKYLAKE_ULT GPD5/SLP_S4# AY16 SIO_SLP_S5# SIO_SLP_S3# [24,27,40,51] by Intel PDG1.3 request SIO_SLP_S4# [40,44,51] Vinafix.com PCH_PLTRST# AN10 GPP_B13/PLTRST# GPD10/SLP_S5# SRN10KJ-6-GP XDP_DBRESET# B5 SYS_RESET# SLP_SUS# TP1703 TPAD14-OP-GP PM_RSMRST# RSMRST# SLP_LAN# TP1702 TPAD14-OP-GP AY17 TP1704 TPAD14-OP-GP GPD9/SLP_WLAN# AN15 SLP_SUS# 1 TP1705 TPAD14-OP-GP GPD6/SLP_A# AW15 TP1706 TPAD14-OP-GP D BATLOW#: R1720 1 DY 2 10KR2J-L-GP H_CPUPW RGD A68 PROCPWRGD BB17 SLP_LAN# 1 D Pull-up required even if not implemented. R1734 1 2 60D4R2F-GP H_VCCST_PW RGD B65 VCCST_PWRGD GPD3/PWRBTN# AN16 C H_VCCST_PW RGD_R 2 0R0402-PAD GPD1/ACPRESENT GPD9/SLP_W LAN# 1 B 2 0R0402-PAD GPD0/BATLOW# SIO_SLP_A# 1 3D3V_S5 +VCCPDSW _3P3 SYS_PW ROK R1706 1 SYS_PW ROK B6 SYS_PWROK BA15 SIO_PW RBTN# SIO_PW RBTN# [24] RESET_OUT# R1704 1 PM_PCH_PW ROK BA20 PCH_PWROK AY15 AC_PRESENT PM_RSMRST# PCH_DPW ROK BB20 DSW_PWROK AU13 PCH_BATLOW # R1711 1 2 ME_SUS_PWR_ACK_R AR13 GPP_A13/SUSWARN#/SUSPWRDNACK DY EC1707 SUSACK#_R AP11 GPP_A15/SUSACK# SCD1U16V2KX-3GP 0R0603-PAD-2-GP-U DY for OBFF disable AU11 1 PCH_W AKE# GPP_A11/PME# AP16 PME# TP1707 Layout note: 3 PAD SHARING GPD2/LAN_W AKE# BB15 INTRUDER# AM10 SM_INTRUDER# TPAD14-OP-GP AM15 WAKE# AM11 +VCCPDSW _3P3 R1707 1 2 10KR2J-L-GP GPD11/LANPHYPC AW17 GPD2/LAN_WAKE# GPP_B11/EXT_PWR_GATE# EXT_PW R_GATE# [24] LANW AKE# AT15 GPD11/LANPHYPC GPP_B2/VRALERT# RTC_AUX_S5 R1710 1 2 0R0402-PAD GPD7/RSVD#AT15 #544669 (CRB): 330k. 2 330KR2J-L1-GP SM_INTRUDER# R1730 1 3D3V_S5_PCH (PDG#543016) SKYLAKE-U-GP [#543016 Rev0.7] WAKE#: Ensure that WAKE# signal Trise (Maximum) is <100 ns. EXT_PWR_GATE#: Due to a bug on A0, a temporary pull-up resistor will be required to overcome the internal 20k 0516 Follow Taos DY 071.SKYLA.000U pull-down that is active during the early portion of the power up sequence R1731 1 DY 2 20KR2J-L2-GP EXT_PW R_GATE# RN1701 4 PM_PCH_PW ROK 1 3 PM_RSMRST# 2 SRN10KJ-5-GP R1713 1 2 PCH_PLTRST# 0R0402-PAD C R1717 1DY 2 SYS_PW ROK [31,55,61,63,76,91] PLT_RST# 10KR2J-L-GP 21 21 100KR2RJ1-17-1G5PDY DY C1701 SC220P50V2KX-3GP +VCCMPHYGTAON_1P0 +VCCSTG D1702 AK 1D0V_S5 +VCCMPHYGTAON_1P0_LS_SIP ACOK_IN [24,44] R1724 1 2 (ICCMAX.=3.5A) 21 DY R1722 Q1702 RB751V-40H-GP AC_PRESENT 21 100KR2J-1-GP PM_RSMRST# 0R0805-PAD-2-GP-U C1704 3D3V_AUX_S5 S4 3D 83.R2004.G8F SC10U6D3V3MX-GP 21 2 1 21 R1735 1 2 R1716 1 2 H_VCCST_PW RGD_R 5 2G 21 6NON DS13 S 0R0805-PAD-2-GP-U [24,40] ALL_SYS_PW RGD G R1737 1NON DS23 PM_RSMRST#_M D 2N7002KDW -GP 100KR2F-L3-GP 100KR2J-1-GP 84.2N702.A3F DY EC1709 R1719 DY EC1708 SCD1U16V2KX-3GP 47KR2F-GP SCD01U50V2KX-L-GP 3D3V_AUX_S5 2nd = 84.2N702.E3F 3rd = 75.00601.07C B R1727 1NON DS23 XDP_DBRESET# 0516 Follow Taos DY SYS_PW ROK +V1.8A_SIP 100KR2J-1-GP PLT_RST# RESET_OUT# R1726 Q1701 3D PM_RSMRST# R1702 1 2 1KR2J-1-GP PCH_RSMRST# 3V_5V_POK 21 10KR2J-L-GP 2G 3V_5V_POK_C R1728 1 S4 1S DY S1 D1 PCH_RSMRST# [24] DY R1718 G1 G2 10KR2J-L-GP 3V_5V_POK# G 5 D2 S2 2 0R0402-PAD 3V_5V_POK [21,40,45,53,54] 21 21 21 21 21 21 D6 DY EC1712 SC1KP50V2KX-L-1-GP SCD1U16V2KX-3GP EC1705 EU1701 AZ5325-01FDR7G-GP SC1KP50V2KX-L-1-GP EC1703 SC1KP50V2KX-L-1-GP EC1702 SC1KP50V2KX-L-1-GP EC1706 DY DY DY ME_SUS_PW R_ACK_R PJT138KA-GP R1708 1 2 SUSACK#_R 0R0402-PAD 075.00138.0A7C [24] SYS_PW ROK [24,26,79] RESET_OUT# A <Core Design> A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title CPU_(POWER MANAGEMENT) Size Document Number Rev A3 Turis/Vegas KBL-R A00 Date: W ednesday, November 08, 2017 Sheet 17 of 105 54321

5 432 1 Main Func = PCH PCH strap pin: PCH Prim PCH strap pin: PCH Prim 3D3V_S5_PCH 3D3V_S5_PCH eSPI or LPC Sampled at rising edge of RSMRST# BOOT HALT 3D3V_S0 3D3V_S5_PCH R1835 and R1834 merge to RN1802 SML0ALERT# / This signal has a weak internal pull-down. SPI0_MOSI 0 = ENABLED Q1801 R1834 1 2 10KR2J-L-GP 3D3V_S0 Follow Starlord GPP_C5 0 = LPC Is selected for EC. 1 = DISABLED 61 R1835 1 2 10KR2J-L-GP 1 = eSPI Is selected for EC. WEAK INTERNAL PU 52 R1827 1 2 SPI_HOLD_ROM 2 12 1R1822 DY R1824 43 1KR2J-1-GP 2 SPI_WP_ROM 2 12 11KR2J-1-GP1KR2J-1-GP R1828 1 MEM_SMBDATA 2N7002KDW-GP 1KR2J-1-GP This signal has a weak internal pull-down. This signal has a weak internal pull-up. 84.2N702.A3F PCH_SMBDATA [12,13,56,65,67] SPI_SI_CPU Vinafix.com GPP_C5/SML0ALERT# 2nd = 84.2N702.E3F 3rd = 75.00601.07C 0511 Follow KY15. DY R1823 DY R1825 D 1KR2J-1-GP 1KR2J-1-GP D C +V1.8A_SIP PCH_SMBCLK [12,13,56,65,67] R1816 1 2 SIO_RCIN# MEM_SMBCLK 10KR2J-L-GP 3D3V_S5_PCH SML1_SMBDATA RN1807 1 SML1_SMBCLK 8 2 SML0_SMBDATA 7 3 SML0_SMBCLK 6 4 5 CPU1E 5 OF 20 SRN2K2J-4-GP Resister value will check later SPI - FLASH SMBUS, SMLINK 0516 Check with SW(Internal PH?) [25,91] SPI_CLK_ROM R1806 1 2 0R0402-PAD SPI_CLK_CPU AV2 SPI0_CLK SKYLAKE_ULT GPP_C0/SMBCLK R7 MEM_SMBCLK GPP_B23/SML1ALERT# R1820 1 2 150KR2J-GP [25,91] SPI_SO_ROM SPI_SO_CPU AW3 SPI0_MISO LPC GPP_C1/SMBDATA R8 MEM_SMBDATA R1807 1 2 0R0402-PAD SPI_SI_CPU SPI0_MOSI GPP_C2/SMBALERT# R10 GPP_C2/SMBALERT# GPP_C2/SMBALERT# R1821 1 [25,91] SPI_SI_ROM R1808 1 2 0R0402-PAD AV3 SPI0_IO2 2 2K2R2J-L1-GP [25] SPI_WP_ROM SPI_WP_CPU AW2 SPI0_IO3 Strap R9 SML0_SMBCLK [25] SPI_HOLD_ROM R1809 1 2 0R0402-PAD SPI0_CS0# W2 SML0_SMBDATA [25] SPI_CS_ROM_N0 R1811 1 2 0R0402-PAD SPI_HOLD_CPU AU4 SPI0_CS1# W1 GPP_C5/SML0ALERT# SPI_CS_CPU_N0 AU3 SPI0_CS2# GPP_C3/SML0CLK [91] SPI_CS_ROM_N2 R1812 1 2 0R0402-PAD GPP_C4/SML0DATA W3 SML1_SMBCLK AU2 GPP_C5/SML0ALERT# V3 SML1_SMBDATA SPI_CS_CPU_N2 AU1 Strap AM7 GPP_B23/SML1ALERT# MEM_SMBCLK R1814 1 2 0R0402-PAD MEM_SMBDATA R1805 1 2 2K2R2J-L1-GP R1832 1 2 2K2R2J-L1-GP GPP_C6/SML1CLK SML1_SMBCLK [24,79] 0511 Follow KY15. SPI - TOUCH GPP_C7/SML1DATA SML1_SMBDATA [24,79] GPP_B23/SML1ALERT#/PCHHOT# 0620 NC M2 C eSPI [67] HDD_FALL_INT TPAD14-OP-GP TP1803 1 CPU_D3_TP M3 GPP_D1/SPI1_CLK For eSPI 0512 Modify +V1.8A_SIP DVT1 add FFS 2/18 TPAD14-OP-GP TP1804 1 CPU_D4_TP J4 GPP_D2/SPI1_MISO CLKRUN#_R TPAD14-OP-GP TP1805 1 CPU_D5_TP V1 GPP_D3/SPI1_MOSI 20170504 R1818 TPAD14-OP-GP TP1806 1 CPU_D6_TP V2 GPP_D21/SPI1_IO2 8K2R2F-1-GP M1 GPP_D22/SPI1_IO3 GPP_A1/LAD0/ESPI_IO0 AY13 ESPI_IO0_CPU R1829 1 2 15R2F-2-GP ESPI_IO0 GPP_D0/SPI1_CS# GPP_A2/LAD1/ESPI_IO1 BA13 2 15R2F-2-GP ESPI_IO1 1 DY 2 GPP_A3/LAD2/ESPI_IO2 BB13 ESPI_IO1_CPU R1830 1 2 15R2F-2-GP ESPI_IO2 ESPI_IO[3..0] GPP_A4/LAD3/ESPI_IO3 AY12 2 15R2F-2-GP ESPI_IO3 [24] ESPI_IO[3..0] GPP_A5/LFRAME#/ESPI_CS# BA12 ESPI_IO2_CPU R1831 1 2 0R0402-PAD ESPI_CS# C LINK GPP_A14/SUS_STAT#/ESPI_RESET# BA11 2 0R0402-PAD ESPI_RESET# ESPI_IO3_CPU R1833 1 ESPI_IO0 [61] CL_CLK G3 CL_CLK ESPI_CS#_CPU R1801 1 ESPI_IO1 [61] CL_DATA G2 CL_DATA ESPI_IO2 [61] CL_RST# G1 CL_RST# ESPI_RESET#_CPU R1826 1 ESPI_IO3 ??? PH only? AW9 ESPI_CLK_CPU R1804 1 2 15R2F-2-GP ESPI_CLK SIO_RCIN# AW13 GPP_A9/CLKOUT_LPC0/ESPI_CLK AY9 [24] ESPI_CS# 21 SCD1U16V2KX-3GP GPP_A0/RCIN# RCIN#: GPP_A10/CLKOUT_LPC1 AW11 CLKRUN#_R R1819 1 DY [24] ESPI_RESET# DY EC1805 Frequency to Avoid: 33 MHz GPP_A8/CLKRUN# 2 0R2J-L-GP PWR_SEClET [24] [24] ESPI_ALERT# ESPI_ALERT# AY11 0512 DY GPP_A6/SERIRQ 21 DY EC1802 SC10P50V2JN-L1-GP SKYLAKE-U-GP [24] ESPI_CLK CPU1J 10 OF 20 3D3V_S0 RN1812 8 CLKREQ_PCIE#5 GPU [76] PEG_CLK_CPU# D42 CLKOUT_PCIE_N0 CLOCK SIGNALS 20170428 U22 1 7 CLKREQ_PEG#0 [76] PEG_CLK_CPU C42 CLKOUT_PCIE_P0 SKYLAKE_ULT 2 6 CLKREQ_PCIE#1 [79] CLKREQ_PEG#0 CLKREQ_PEG#0 AR10 GPP_B5/SRCCLKREQ0# 3 5 CLKREQ_PCIE#2 XTAL24_IN XTAL24_IN_R 4 CLKOUT_PCIE_N1 1 R1810 2 C1801 1 2 SC15P50V2JN-2-GP CLKOUT_PCIE_P1 0R0402-PAD WLAN [61] PEG_CLK1_CPU# B42 GPP_B6/SRCCLKREQ1# F43 PCIE_CLK_XDP_N 1 TP1807 TPAD14-OP-GP SRN10KJ-6-GP [61] PEG_CLK1_CPU CLKREQ_PCIE#1 A42 CLKOUT_ITPXDP_N E43 PCIE_CLK_XDP_P 1 TP1808 TPAD14-OP-GP 21 B [61] CLKREQ_PCIE#1 AT7 CLKOUT_PCIE_N2 CLKOUT_ITPXDP_P 32 B CLKOUT_PCIE_P2 BA17 41 RN1813 [31] PEG_CLK2_CPU# D41 GPP_B7/SRCCLKREQ2# GPD8/SUSCLK SUSCLK_R 0517 DY 2 SUS_CLK [24] U22 1MR2J-1-GP X1801 [31] PEG_CLK2_CPU C41 E37 XTAL24_IN R1802 XTAL-24MHZ-81-GP 1 4 CLKREQ_PCIE#3 LAN [31] CLKREQ_PCIE#2 AT8 CLKOUT_PCIE_N3 XTAL24_IN E35 0RR1821J-3L1-GPDY XTAL24_OUT U22 2 3 CLKREQ_PCIE#4 CLKOUT_PCIE_P3 XTAL24_OUT 82.30004.841 GPP_B8/SRCCLKREQ3# E42 XTAL24_OUT XCLK_BIASREF SRN10KJ-5-GP 0511 Remove SSD D40 CLKOUT_PCIE_N4 AM18 XCLK_BIASREF Intel recommend: 2.71k ohm 5% CLKOUT_PCIE_P4 RTCX1 AM20 RTC_X1 C40 GPP_B9/SRCCLKREQ4# RTCX2 R1803 1 2 +V1.00A_SIP CLKREQ_PCIE#3 AT10 AN18 2K7R2F-GP CLKOUT_PCIE_N5 SRTCRST# AM16 U22C1802 1 B40 CLKOUT_PCIE_P5 RTCRST# RTC_X2 2 SC15P50V2JN-2-GP A40 GPP_B10/SRCCLKREQ5# CLKREQ_PCIE#4 AU8 SRTC_RST# RTC_RST# E40 E38 CLKREQ_PCIE#5 AU7 RTC_X1 R1815 1 2 RTC_X2 10MR2J-L-GP 4 SKYLAKE-U-GP X1802 RTC_AUX_S5 1 RN1901 4 SRTC_RST# SC3D9P50V2CN-1GP 1 3 C1803 2 SC3D9P50V2CN-1GP C1804 21 21 23 SRN20KJ-1-GP 21 C1902 21DY EC1806 SC1U10V2KX-1GP SCD1U16V2KX-3GP [21,24] RTCRST_ON Q1901 A G DY 21 10KR2J-L-GP D RTC_RST# X-32D768KHZ-65-GP A 21 R1817 5 82.30001.A41 SCD1U16V2KX-3GP EC1808 S 2 <Core Design> 2N7002K-2-GP 21 C1901 G1901 21DY EC1807 SC1U10V2KX-1GP GAP-OPEN SCD1U16V2KX-3GP 84.2N702.J31 Wistron Corporation 1 2ND = 84.2N702.031 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, 3rd = 84.07002.I31 Taipei Hsien 221, Taiwan, R.O.C. (#514849) Title Layout: Place at the open door area. CPU_(LPC/SPI/SMBUS/CL/CLK) Size Document Number Rev Custom Turis/Vegas KBL-R A00 Date: Wednesday, November 08, 2017 Sheet 18 of 105 4 321

5 4 3 2 1 Main Func = PCH 7 OF 20 PCH strap pin: CPU1G Flash Descriptor Security Overide/ Vinafix.com AUDIO SKYLAKE_ULT Intel ME Debug Mode HDA_SYNC BA22 HDA_SYNC/I2S0_SFRM D HDA_BITCLK AY22 HDA_BLK/I2S0_SCLK C D HDA_SDOUT BB22 HDA_SDO/I2S0_TXD B HDA_SDIN0 BA21 HDA_SDI0/I2S0_RXD HDA_SDOUT Low = Default * AY21 HDA_SDI1/I2S1_RXD SDIO/SDXC High = Enable DY AW22 HDA_RST#/I2S1_SCLK GPP_D23/I2S_MCLK GPP_G0/SD_CMD AB11 The internal pull-down is disabled after SC2P50V2CN-GP J5 I2S1_SFRM GPP_G1/SD_DATA0 AB13 PLTRST# deasserts FC1902 AY20 I2S1_TXD GPP_G2/SD_DATA1 AB12 AW20 GPP_F1/I2S2_SFRM GPP_G3/SD_DATA2 W12 GPP_F0/I2S2_SCLK GPP_G4/SD_DATA3 W11 AK7 GPP_F2/I2S2_TXD W10 AK6 GPP_F3/I2S2_RXD GPP_G5/SD_CD# W8 AK9 GPP_G6/SD_CLK W7 AK10 GPP_G7/SD_WP BA9 GPP_A17/SD_PWR_EN#/ISH_GP7 BB9 GPP_A16/SD_1P8_SEL AB7 SD_RCOMP [24,79,85] DGPU_PWROK 21 H5 GPP_D19/DMIC_CLK0 CPU_A16_TP 1 TP1902 21D7GPP_D20/DMIC_DATA0SD_RCOMPR1901 1TPAD14-OP-GP [27] HDA_CODEC_BITCLK GPP_D17/DMIC_CLK1 200R2F-L-GP 2 [27] HDA_CODEC_SDOUT GPP_D18/DMIC_DATA1 [27] HDA_CODEC_SYNC D8 GPP_B14/SPKR GPP_F23 AF13 [27] HDA_SDIN0 DGPU_PWROK C8 C [24] ME_FWP SPKR AW5 [27] SPKR SKYLAKE-U-GP PCH strap pin: 3D3V_S0 HDA_CODEC_BITCLK R1907 1 2 0R0402-PAD HDA_BITCLK HDA_CODEC_SYNC R1908 1 2 0R0402-PAD HDA_SYNC NO REBOOT R2006 1DY 2 1KR2J-1-GP SPKR HDA_SPKR * Low = Enable (Default) High = Disable R1904 1UMA 2 100KR2J-1-GP DGPU_PWROK The internal pull-down is disabled after EC1901 1DY 2 SC10P50V2JN-L1-GP HDA_CODEC_BITCLK HDA_CODEC_SDOUT R1912 1 2 0R0402-PAD HDA_SDOUT PLTRST# deasserts ME_FWP R1909 1 EC1903 1DY 2 SC1KP50V2KX-L-1-GP DGPU_PWROK 2 1KR2J-1-GP FC1901 B DY SC2P50V2CN-GP <Core Design> A Wistron Corporation A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title CPU_(AUDIO/SDIO/SDXC) Size Document Number Rev A4 Vegas SKL/KBL-U A00 Date: Wednesday, November 08, 2017 Sheet 19 of 105 54321

5 4 321 Main Func = PCH 3D3V_S0 CPU1F 6 OF 20 RN2007 SRN10KJ-5-GP [68] UART_2_CRXD_DTXD LPSS ISH I2C0_SCL 14 [68] UART_2_CTXD_DRXD I2C0_SDA SKYLAKE_ULT GPP_D9 2 DY 3 GPP_D10 I2C1_SCL EC2002 1DY 2 SC1KP50V2KX-L-1-GP DGPU_HOLD_RST# [76] VRAM_ID1 AN8 GPP_B15/GSPI0_CS# GPP_D11 P2 USB_UART_SEL_D9 1 TP2006 TPAD14-OP-GP I2C1_SDA RN2008 GPP_B18/GSPI0_MOSI AP7 GPP_B16/GSPI0_CLK GPP_D12 P3 DGPU_HOLD_RST# RTC_DET# [25] AP8 GPP_B17/GSPI0_MISO P4 1 DY 4 RN2009 AR7 GPP_B18/GSPI0_MOSI Strap GPP_D5/ISH_I2C0_SDA P1 RTC_DET# 2 3 14 DGPU_HOLD_RST# GPP_D6/ISH_I2C0_SCL DGPU_PWR_EN Vinafix.com[55] DBC_PANEL_EN AM5 GPP_B19/GSPI1_CS# M4 I2C0_SDA SRN2K2J-1-GP 2 OPS 3 AN7 GPP_B20/GSPI1_CLK GPP_D7/ISH_I2C1_SDA N3 I2C0_SCL TPAD14-OP-GP 1 GPP_B22 AP5 GPP_B21/GSPI1_MISO GPP_D8/ISH_I2C1_SCL SRN10KJ-5-GP TP2008 AN5 GPP_B22/GSPI1_MOSI N1 I2C1_SDA GPP_F10/I2C5_SDA/ISH_I2C2_SDA N2 I2C1_SCL D AB1 GPP_C8/UART0_RXD GPP_F11/I2C5_SCL/ISH_I2C2_SCL (PDG#543016) Ensure that all I2C interface on-board terminations are pulled up D AB2 GPP_C9/UART0_TXD AD11 1.8V Only to the same voltage rail as the device/end point. C (PDG#543016) If the UART/GPIO functionality is also not used, [61] BLUETOOTH_EN W4 GPP_C10/UART0_RTS# AD12 the signals can be left as no-connect. [24] SIO_EXT_WAKE# BOARD_ID2 AB3 GPP_C11/UART0_CTS# 3D3V_S0 UART_2_CRXD_DTXD AD1 GPP_C20/UART2_RXD UART_2_CTXD_DRXD AD2 GPP_C21/UART2_TXD R2048 1 DDDeeebbbuuu222ggg555111KKKRRR222JJJ---111---GGGPPP UART_2_CRXD_DTXD AD3 GPP_C22/UART2_RTS# GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA U1 DGPU_PWR_EN 1 TP2007 TPAD14-OP-GP DGPU_PWR_EN [85,86] R2049 1 UART_2_CTXD_DRXD LPSS_UART2_CTS# AD4 GPP_C23/UART2_CTS# GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL U2 UART0_TXD 1 TP2010 TPAD14-OP-GP R2046 1 LPSS_UART2_CTS# GPP_D15/ISH_UART0_RTS# U3 UART0_RTS# 1 TP2011 TPAD14-OP-GP GPP_D16/ISH_UART0_CTS#/SML0BALERT# U4 UART0_CTS# R2002 1 DY 2 10KR2J-L-GP BLUETOOTH_EN 1 TP2012 TPAD14-OP-GP GPP_C12/UART1_RXD/ISH_UART1_RXD AC1 UART1_RXD FFS_INT2 [67] 2 10KR2J-L-GP DBC_PANEL_EN PTP [65] I2C0_SDA_TCH_PAD U7 GPP_C16/I2C0_SDA GPP_C13/UART1_TXD/ISH_UART1_TXD AC2 1 +V1.8A_SIP [65] I2C0_SCL_TCH_PAD U6 GPP_C17/I2C0_SCL GPP_C14/UART1_RTS#/ISH_UART1_RTS# AC3 UART1_CTS# DVT1 add FFS 2/18 R2003 1 GPP_C15/UART1_CTS#/ISH_UART1_CTS# AB4 TP2015TPAD14-OP-GP 0517 Change PH power rate PCH Prim U8 GPP_C18/I2C1_SDA PROJECT_ID1 3D3V_S5_PCH U9 GPP_C19/I2C1_SCL GPP_A18/ISH_GP0 AY8 PROJECT_ID2 KB_DET# R2001 1 2 10KR2J-L-GP DY R2007 GPP_A19/ISH_GP1 BA8 KB_DET# 2 10KR2J-L-GP RN2010 4 I2C0_SDA_TCH_PAD 1KR2J-1-GP AH9 GPP_F4/I2C2_SDA GPP_A20/ISH_GP2 BB7 CAMERA_DET# KB_DET# [65] CAMERA_DET# R2004 1 1 3 I2C0_SCL_TCH_PAD AH10 GPP_F5/I2C2_SCL GPP_A21/ISH_GP3 BA7 TPM_SELECT CAMERA_DET# [55] GPP_A22/ISH_GP4 AY7 ??? Ask SW in PH necessary 2 DY AH11 GPP_F6/I2C3_SDA GPP_A23/ISH_GP5 AW7 PANEL_SIZE_ID [55] AH12 GPP_F7/I2C3_SCL SX_EXIT_HOLDOFF#/GPP_A12/BM_BUSY#/ISH_GP6 AP13 SRN2K2J-1-GP AF11 GPP_F8/I2C4_SDA 2 12 1 AF12 GPP_F9/I2C4_SCL 3D3V_S5_PCH SKYLAKE-U-GP RN2011 SIO_EXT_WAKE# SRN10KJ-5-GP RTC_DET# 14 23 GPP_B18/GSPI0_MOSI DY R2019 +V1.8A_SIP +V1.8A_SIP BIOS strap pin: GPP_A19 GPP_A18 C 1KR2J-1-GP 0517 Change PH power rate PROJECT Strap pin PCH strap pin: PROJECT_ID2 PROJECT_ID1 No Reboot Sampled at rising edge of PCH_PWROK R2015 2 12 1 R20172 12 1 Turis X0 GSPI0_MOSI / 0 = Disable “No Reboot” mode. 10KR2J-L-GP Vegas X1 GPP_B18 1 = Enable “No Reboot” mode (PCH will disable the TCO DY_SKL10KR2J-L-GP 0X Timer system reboot feature). This function is useful Vegas KBL 1X when running ITP/XDP. 0511 Remove DB2 PROJECT_ID2 SKL PROJECT_ID1 The signal has a weak internal pull-down. R2018 R2016 KBL 10KR2J-L-GP Turis10KR2J-L-GP 0517 Change PH power rate +V1.8A_SIP 3D3V_S0 2 12 1 R2005 BIOS strap pin: GPP_C11 R20222 12 1 BIOS strap pin: GPP_A22 BOARD_ID2 10KR2J-L-GP OPS 10KR2J-L-GP BIOS UMA/DIS Strap pin TPM BIOS UMA/DIS Strap pin TPM_SELECT BOARD_ID2 B UMA 0 TPM_SELECT TPM 1 B R2008 DIS 1 R2020 NON_TPM 0 10KR2J-L-GP UMA 10KR2J-L-GP NON_TPM 3D3V_S0 VRAM_ID1 R2023 2 12 1 BIOS strap pin: GPP_B17 10KR2J-L-GP VRAM_ID1 BIOS VRAM Size Strap pin VRAM_2G 4G 0 2G 1 R2024 10KR2J-L-GP VRAM_4G AA <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title CPU_(LPSS/ISH) Size Document Number Rev Custom Vegas SKL/KBL-U A00 Date: Wednesday, November 08, 2017 Sheet 20 of 105 54321

5432 1 Main Func = PCH RTC_AUX_S5 RTC_AUX_S5 +VCCPRTC_3P3 CPU1O 15 OF 20 DY +V1.00A_SIP CPU POWER 4 OF 4 SCD1U16V2KX-3GP R2107 1 2 SCD1U16V2KX-3GP AB19 0511 Follow KY15. 0R0402-PAD-2-GP AB20 +V1.8A_SIP CAP need close to VCCRTC VCCPRIM_1P0 SC1U10V2KX-1GP P18 VCCPRIM_1P0 +V3.3A_SIP C2117 2.57A AF18 VCCPRIM_1P0 +V1.8A_SIP VCCPRIM_CORE C2118 AF19 VCCPRIM_CORE +V3.3A_SIP C2119 +VCCPRIM_CORE V20 VCCPRIM_CORE SKYLAKE_ULT VCCPGPPA AK15 21 +VCCMPHYGTAON_1P0_LS_SIP +VCCAMPHYPLL_1P0 V21 VCCPRIM_CORE VCCPGPPB AG15 21 DY AL1 DCPDSW_1P0 1.8V Only VCCPGPPC Y16 21 VCCPGPPD Y15 +VCCDSW _1P0 VCCPGPPE T16 Vinafix.comD VCCPGPPF AF16 R2112 1 2 VCCPGPPG AD15 VCCPRIM_3P3 V19 0R0603-PAD-2-GP-U 21 SC1U10V2KX-1GP +V1.00A_SIP +VCCAPLL_1P0 D 21C2120 C K17 T1 SCD1U25V2KX-GP L1 AA1 +V1.00A_SIP EC2101 AK17 +V1.8A_SIP +V1.00A_SIP VCCMPHYAON_1P0 VCCPRIM_1P0 AK19 +V3.3A_SIP R2108 1 2 +VCCMPHYGTAON_1P0_LS_SIP VCCMPHYAON_1P0 VCCATS_1P8 BB14 +VCCPRTC_3P3 0R0603-PAD-2-GP-U N15 VCCRTCPRIM_3P3 N16 VCCMPHYGT_1P0 VCCRTC N17 VCCMPHYGT_1P0 VCCRTC P15 VCCMPHYGT_1P0 P16 VCCMPHYGT_1P0 VCCMPHYGT_1P0 K15 VCCAMPHYPLL_1P0 DCPRTC BB10 VCCRTCEXT C2112 1 2 SCD1U16V2KX-3GP L15 VCCAMPHYPLL_1P0 VCCCLK1 A14 +V1.00A_SIP +VCCAMPHYPLL_1P0 VCCCLK2 K19 RTC_3D3V R2113 1 2 0R0402-PAD RTC_AUX_S5 VCCCLK3 L21 +VCCAPLL_1P0 V15 VCCAPLL_1P0 VCCCLK4 N20 Q2107 R2104 VCCCLK5 L19 +V1.00A_SIP AB17 VCCPRIM_1P0 VCCCLK6 A10 S RTC_RST 4K7R2J-2-GP Y18 VCCPRIM_1P0 GPP_B0/CORE_VID0 AN11 GPP_B1/CORE_VID1 AN13 RTC_RSTD RTC_3P3_EN_D +VCCPDSW _3P3 AD17 SCD022U16V2KX-3GP AD18 VCCDSW_3P3 C2123 D2 1 AJ17 VCCDSW_3P3 21 G DMP2130L-7-GP VCCDSW_3P3 RTC_RST 84.02130.031 +V3.3A_SIP R2101 1 2 +VCCPAZIO AJ19 VCCHDA D 100KR2J-1-GP 0R0402-PAD AJ16 VCCSPI R2118 2nd = 84.00102.031 Symbol error for layout NC 3rd = 84.03413.B31 +V3.3A_SIP G C +VCCMPHYGTAON_1P0_LS_SIP AF20 VCCSRAM_1P0 0512 Follow SF RTC_RST AF21 VCCSRAM_1P0 VCCSRAM_1P0 +V1.8A_SIP +VCCDSW _1P0 Q2110 T19 VCCSRAM_1P0 2N7002K-2-GP T20 R84T.C2N_R70S2T.J31 +V3.3A_SIP AJ21 VCCPRIM_3P3 D2102 2ND = 84.2N702.031 +V1.00A_SIP AK20 VCCPRIM_1P0 SC1U10V2KX-1GP SC1U10V2KX-1GP RKTC_RSTA 3rd = 84.07002.I31 C2108 C2103 4th = 84.2N702.W31 +VCCMPHYGTAON_1P0_LS_SIP N18 VCCAPLLEBB_1P0 21 RB751VM-40TE-17-GP G 21 S 83.R2004.J8F [18,24] RTCRST_ON 1RM21R022J1-1-GRPTC_R2ST RTC_3P3_EN_G SKYLAKE-U-GP +V3.3A_SIP Layout Note: +V1.00A_SIP Layout Note: 21 1uF: DY DY DY DY C2111 C2105 near V19 DY 1uF: C2110 C2106 near AK17 SC22U6D3V3MX-1-GP C2101 near AB19 SC1U10V2KX-1GP C2107 near AG15 C2122 C2104 near K17 B SC1U10V2KX-1GP C2109 C2109 near Y16 C2107 0.1uF: C2121 SC1U10V2KX-1GPC2106 C2110 near T16 C2116 SC1U10V2KX-1GPC2105 C2111 near AJ19 C2104 +VCCAMPHYPLL_1P0 C2101 21 21 DY DY 21 21 21 21 C2116 near A10 21 21 C2121 near AL1 21 21 21 22uF: C2122 near L19 SCD1U16V2KX-3GP SC1U10V2KX-1GP SCD1U16V2KX-3GP SC1U10V2KX-1GP B SC1U10V2KX-1GP SC1U10V2KX-1GP 3D3V_S5 3D3V_S5 +VCCAPLL_1P0 0512 Follow SF R2114 1 DY 2 21 21 2 1 0R2J-L-GP Layout Note: Layout Note: 100KR2J-1-GP R2115 DY 22uF: DY 22uF: R2120 10KR2J-L-GP C2113 near K15 C2114 near V15 RTC_RST RTC_RST SC22U6D3V3MX-1-GP D2101 C2114 1 SC22U6D3V3MX-1-GP C2113 21 [17,40,45,53,54] 3V_5V_POK 3V_5V_POK 21 RTC_RST 3 3V_5V_DSW _OK [24] VCCDSW _EN# VCCDSW_EN# 2 BAT54A-11-GP DY C2125 SC1U10V2KX-1GP 3D3V_S5 U2101 3D3V_S5_PCH 5 RTC_RST 1 2 3D3V_S5_PCH_Gen9 R2116 1RTC_RS2T VIN#5 EN 3 GND 0R3J-L1-GP 4 VIN#4 VOUT RT9724GB-GP 74.09724.09F A <Core Design> A 5 Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Rev CPU_(POWER1) A00 Size Document Number 105 A3 Vegas SKL/KBL-U Date: W ednesday, November 08, 2017 Sheet 21 of 1 4 3 2

5 432 1 D D C Vinafix.com C B B CPU1T 20 OF 20 SKYLAKE_ULT SPARE AW69 RSVD#AW69 RSVD#F6 F6 XTAL24_IN_U42 AW68 RSVD#AW68 RSVD#E3 E3 XTAL24_OUT_U42 AU56 RSVD#AU56 RSVD#C11 C11 AW48 RSVD#AW48 RSVD#B11 B11 RSVD#C7 RSVD#A11 A11 C7 RSVD#U12 RSVD#D12 D12 U12 RSVD#U11 RSVD#C12 C12 U11 RSVD#H11 RSVD#F52 F52 H11 SKYLAKE-U-GP XTAL24_IN_U42 R0R2220J-121-UGP42 2 XTAL24_IN_U42_R C2201 1U42 2 SC15P50V2JN-2-GP U4221 1MR2J-1-GP U42 X2201 32R2203 XTAL-24MHZ-86-GP 41 82.30004.891 XTAL24_OUT_U42 R0R222J0-221-UGP42 2 XTAL24_OUT_R_U42 C2202 1U42 2 SC15P50V2JN-2-GP <Core Design> A Wistron Corporation A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title CPU_(RSVD) Rev Size Document Number A4 Vegas SKL/KBL-U A00 Date: Wednesday, November 08, 2017 Sheet 22 of 105 54321

5432 1 Main Func = PCH CPU1Q 17 OF 20 CPU1R 18 OF 20 0517 Follow KY15. CPU1P 16 OF 20 GND 2 OF 3 F8 GND 3 OF 3 L18 G10 L2 GND 1 OF 3 Vinafix.comVSS AT63 VSS SKYLAKE_ULT VSS BA49 G22 VSS VSS L20 AT68 VSS VSS BA53 G43 VSS VSS L4 VSS AT71 VSS VSS BA57 G45 VSS SKYLAKE_ULT VSS L8 VSS AU10 VSS VSS BA6 G48 VSS VSS N10 Symbol error for layout NC A5 VSS SKYLAKE_ULT VSS AL65 AU15 VSS VSS BA62 VSS VSS N13 VSS VSS AL66 AU20 VSS VSS BA66 G5 VSS VSS N19 TPAD14-OP-GP TP2311 1 A67_TP A67 VSS VSS AM13 AU32 VSS VSS BA71 G52 VSS VSS N21 1 A70_TP A70 VSS VSS AM21 0517 Follow KY15. AU38 VSS VSS BB18 G55 VSS VSS N6 D TPAD14-OP-GP TP2301 AA2 VSS VSS AM25 AV1 VSS VSS BB26 G58 VSS VSS N65 D C VSS VSS AM27 AV68 VSS VSS BB30 VSS VSS N68 C B AA4 VSS VSS AM43 AV69 VSS VSS BB34 Symbol error for layout NC G6 VSS VSS P17 B VSS VSS AM45 AV70 VSS VSS BB38 G60 VSS VSS P19 AA65 VSS VSS AM46 1 AV1_TP AV71 VSS VSS BB43 G63 VSS VSS P20 AA68 VSS VSS AM55 AW10 VSS VSS BB55 G66 VSS VSS P21 AB15 VSS VSS AM60 TPAD14-OP-GP TP2310 AW12 VSS VSS BB6 H15 VSS VSS R13 VSS VSS AM61 AW14 VSS VSS BB60 H18 VSS VSS R6 AB16 VSS VSS AM68 AW16 VSS VSS BB64 H71 VSS VSS T15 AB18 VSS VSS AM71 AW18 VSS VSS BB67 J11 VSS VSS T17 AB21 VSS VSS AM8 1 AV71_TP AW21 VSS VSS BB70 0517 Follow KY15. J13 VSS VSS T18 AB8 VSS VSS AN20 TPAD14-OP-GP TP2304 AW23 VSS VSS C1 J25 VSS VSS T2 VSS VSS AN23 AW26 VSS VSS C25 J28 VSS VSS T21 AD13 VSS VSS AN28 AW28 VSS VSS C5 J32 VSS VSS T4 AD16 VSS VSS AN30 AW30 VSS VSS D10 J35 VSS VSS U10 AD19 VSS VSS AN32 AW32 VSS VSS D11 J38 VSS VSS U63 AD20 VSS VSS AN33 AW34 VSS VSS D14 Symbol error for layout NC J42 VSS VSS U64 VSS VSS AN35 AW36 VSS VSS D18 BB70_TP 1 VSS VSS U66 AD21 VSS VSS AN37 AW38 VSS VSS D22 TP2307 TPAD14-OP-GP J8 VSS VSS U67 AD62 VSS VSS AN38 AW41 VSS VSS D25 K16 VSS VSS U69 AD8 VSS VSS AN40 AW43 VSS VSS D26 K18 VSS VSS U70 AE64 VSS VSS AN42 AW45 VSS VSS D30 K22 VSS VSS V16 AE65 VSS VSS AN58 AW47 VSS VSS D34 K61 VSS VSS V17 AE66 VSS VSS AN63 AW49 VSS VSS D39 K63 VSS VSS V18 AE67 VSS VSS AP10 AW51 VSS VSS D44 K64 VSS VSS W13 AE68 VSS VSS AP18 AW53 VSS VSS D45 K65 VSS VSS W6 AE69 VSS VSS AP20 AW55 VSS VSS D47 K66 VSS VSS W9 AF1 VSS VSS AP23 AW57 VSS VSS D48 K67 VSS VSS Y17 AF10 VSS VSS AP28 AW6 VSS VSS D53 K68 VSS VSS Y19 AF15 VSS VSS AP32 AW60 VSS VSS D58 K70 VSS VSS Y20 AF17 VSS VSS AP35 AW62 VSS VSS D6 K71 VSS VSS Y21 AF2 VSS VSS AP38 AW64 VSS VSS D62 L11 VSS VSS AF4 VSS VSS AP42 AW66 VSS VSS D66 L16 VSS VSS AF63 VSS VSS AP58 AW8 VSS VSS D69 L17 AG16 VSS VSS AP63 AY66 VSS VSS E11 AG17 VSS VSS AP68 VSS VSS E15 AG18 VSS VSS AP70 B10 VSS VSS E18 AG19 VSS VSS AR11 B14 VSS VSS E21 AG20 VSS VSS AR15 B18 VSS VSS E46 AG21 VSS VSS AR16 B22 VSS VSS E50 AG71 VSS VSS AR20 B30 VSS VSS E53 AH13 VSS VSS AR23 B34 VSS VSS E56 AH6 VSS VSS AR28 B39 VSS VSS E6 AH63 VSS VSS AR35 B44 VSS VSS E65 AH64 VSS VSS AR42 B48 VSS VSS E71 VSS VSS AR43 B53 VSS VSS F1 SKYLAKE-U-GP VSS VSS AR45 B58 VSS VSS F13 AH67 VSS VSS AR46 B62 VSS VSS F2 AJ15 VSS VSS AR48 B66 VSS VSS F22 AJ18 VSS VSS AR5 B71 VSS VSS F23 [#543016 Rev0.9] AJ20 VSS VSS AR50 BA1 VSS VSS F27 AJ4 VSS VSS AR52 BA10 VSS VSS F28 Symbol error for layout NC AK11 VSS VSS AR53 BA14 VSS VSS F32 AK16 VSS VSS AR55 BA18 VSS VSS F33 AK18 VSS VSS AR58 BA2 VSS VSS F35 AK21 VSS VSS AR63 BA23 VSS VSS F37 AK22 VSS VSS AR8 0517 Follow KY15. BA28 VSS VSS F38 AK27 VSS VSS AT2 BA32 VSS VSS F4 AK63 VSS VSS AT20 TPAD14-OP-GP TP2312 BA36 VSS VSS F40 AK68 VSS VSS AT23 TPAD14-OP-GP TP2305 1 B71_TP F68 VSS VSS F42 AK69 VSS VSS AT28 1 BA1_TP BA45 VSS BA41 AK8 VSS VSS AT35 AL2 VSS VSS AT4 AL28 VSS AT42 AL32 VSS AT56 Symbol error for layout NC VSS AT58 AL35 AL38 AL4 AL45 AL48 AL52 AL55 AL58 AL64 SKYLAKE-U-GP SKYLAKE-U-GP A <Core Design> A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Rev CPU_(VSS) A00 Size Document Number A3 Vegas SKL/KBL-U Date: W ednesday, November 08, 2017 Sheet 23 of 105 54321

54321 Main Func = KBC Layout Note: 3D3V_S5 3D3V_S5_KBC 3D3V_S5 Need very close to EC R2446 1 2 LID_CL_SIO# RN2405 TP_EN# 18 0R0603-PAD-2-GP-U 27 36 SCD1U16V2KX-3GP Q2412 45 C2423 16 0R0402-PAD 25 R2472 0R2J-2-GP R2473 SC2D2U10V3KX-L-GP C2417 SCD1U16V2KX-3GP C2413 SCD1U16V2KX-3GP C2414 SCD1U16V2KX-3GP C2410 SCD1U16V2KX-3GP C2411 SCD1U16V2KX-3GP C2412 SCD1U16V2KX-3GP C2420 SC2D2U10V3KX-L-GP C2415 SCD1U16V2KX-3GP C2416 SCD1U16V2KX-3GP C2421 1D0V_S5 R2402 1 2 0R0402-PAD VREF_CPU 21 DY BAT2_LED# 21 C240621 21 3D3V_S5_KBC BATT_WHITE_LED# [64] SRN100KJ-5-GP SCD1U16V2KX-3GP 21 3D3V_S5 21 3D3V_S5 21 21 DY If don't need RTC alarm wake up, [64] CHG_AMBER_LED# 34 BAT1_LED# 21 can change to 3D3V_AUX_S5 2N7002KDW-GP 21 Q2412 and Q2413 merge 21 Vinafix.com 0511 Follow KY15. 1D8V_S5 1D8V_S5_KBC 0517 Change to digital GND 84.2N702.A3F D 3D3V_AUX_S5 RTC_3D3V R2462 1 2 2nd = 84.2N702.E3F D 3rd = 75.00601.07C C 0R0402-PAD-2-GP 3D3V_S0 B A 3D3V_S5_KBC 0519 Install 21 VBAT 122 2 1 TOUCH_PANEL_INTR# 1R02K4R292J1D-L-YGP 2 DY Touch Panel PH internally. 3D3V_S5_KBC 2 12 1 21 R2450 3D3V_S5_KBC 100KR2J-1-GP RN2408 +RTC_CELL_VBAT 0516 Follow CY17. SRN100KJ-5-GP BKLT_IN_EC 18 21 [8] L_BKLT_EN R2435 1 2 0R0402-PAD KSO8 C2428 14 21 23 2 7 KSO3 KSO9 SCD1U16V2KX-3GP 43 82 3 6 KSO1 103 RN2402 R2436 5 45 KSO2 KBC24 19 SRN4K7J-8-GP 100KR2J-1-GP RN2409 65 DY R2449 VTR VTR_33_18 54 100KR2J-1-GP VTR [65] KSO[0..16] VTR 3D3V_S0 VTR VTR VTR SRN100KJ-5-GP KSO5 KSO0 2 GPIO027/KSO00/PVT_IO1 GPIO007/SMB01_DATA/SMB01_DATA18 8 PBAT_CHG_SMBDAT R2438 1 2 0R0402-PAD SML1_SMBDATA 21 R2430 18 KSO4 KSO1 14 GPIO015/KSO01/PVT_CS# GPIO010/SMB01_CLK/SMB01_CLK18 9 PBAT_CHG_SMBCLK R2439 1 2 0R0402-PAD SML1_SMBCLK 10KR2J-L-GP 27 KSO7 KSO2 15 GPIO016/KSO02/PVT_SCLK 11 GPU_THM_SMBDAT 36 KSO6 KSO3 16 GPIO017/KSO03/PVT_IO0 GPIO012/SMB02_DATA/SMB02_DATA18 12 GPU_THM_SMBCLK 45 KSO4 37 GPIO045/BCM_INT1#/KSO04 GPIO013/SMB02_CLK/SMB02_CLK18 89 KSO0 3D3V_S5_KBC KSO5 38 GPIO046/BCM_DAT1/KSO05 91 0516 NC 41, 89, 91, 97 pin RN2406 KSO12 KSO6 39 GPIO047/BCM_CLK1/KSO06 GPIO130/SMB03_DATA/SMB03_DATA18 96 NB_MODE# 1 TP2401 TPAD14-OP-GP 0RR224J6-12-1GPDY 2 SRN100KJ-5-GP KSO16 RN2403 KSO7 50 GPIO025/KSO07/PVT_IO2 GPIO131/SMB03_CLK/SMB03_CLK18 97 18 KSO15 SRN10KJ-12-GP KSI7 KSO8 46 GPIO055/PWM2/KSO08/PVT_IO3 FAN1_TACH AK FAN_TACH1 [26] 27 18 KSI6 KSO9 68 GPIO102/KSO09/CR_STRAP GPIO141/SMB04_DATA/SMB04_DATA18 40 3D3V_S0 36 KSO13 27 KSI4 KSO10 72 GPIO106/KSO10 GPIO142/SMB04_CLK/SMB04_CLK18 41 0518(CY15) D2403 45 KSO14 36 KSI2 KSO11 74 GPIO110/KSO11 KB_LED_PWM 1 RB751V-40H-GP KSO11 45 KSO12 75 GPIO111/KSO12 GPIO050/TACH0 44 BEEP RN2407 KSO10 KSO13 76 GPIO112/PS2_CLK1A/KSO13 GPIO051/TACH1 45 0517 Follow Taos. 83.R2004.G8F SRN100KJ-5-GP KSO14 77 GPIO113/PS2_DAT1A/KSO14 FAN1_PWM TP2407 TPAD14-OP-GP 18 KSO15 86 GPIO125/KSO15 GPIO053/PWM0 47 FAN2_PWMVOL_LP# C2401 27 RN2404 KSI5 KSO16 92 GPIO132/KSO16 GPIO054/PWM1 34 R2403 1 2 10KR2J-L-GP FAN1_DAC_1 21 SC10U6D3V3MX-GP 36 SRN10KJ-12-GP KSI1 CAP_LED# 93 GPIO140/KSO17 35 LANWAKE# 2 0R2J-2-GP SIO_SLP_S3# 45 18 KSI3 GPIO056/PWM3 36 PS_ID R2486 1 DY 27 KSI0 [65] KSI[0..7] KSI0 GPIO030/BCM_INT0#/PWM4 4 PCIE_WAKE# 20170504 ESPI 36 KSI1 98 GPIO031/BCM_DAT0/PWM5 [18] ESPI_IO[3..0] 45 KSI2 99 GPIO143/KSI0/DTR# GPIO032/BCM_CLK0/PWM6 1 KSI3 GPIO144/KSI1/DCD# 106 [18] ESPI_CS# KSI4 6 GPIO005/SMB00_DATA/SMB00_DATA18/KSI2 GPIO002/PWM7 70 BAT2_LED# 0518(KY15) [18] ESPI_CLK KSI5 7 GPIO006/SMB00_CLK/SMB00_CLK18/KSI3 BAT1_LED# 0518(KY15) Q2414 [18] ESPI_ALERT# KSI6 104 GPIO147/KSI4/DSR# GPIO157/LED0/TST_CLK_OUT 80 BREATH_LED# 1 TP2402 TPAD14-OP-GP 21 2N7002K-2-GP [18] ESPI_RESET# KSI7 105 GPIO150/KSI5/RI# GPIO156/LED1 81 0516(CY17 GPIO) G 107 GPIO151/KSI6/RTS# GPIO104/LED2 ME_FWP 100KR2J-1-GP [43,44] AC_DIS 108 GPIO152/KSI7/CTS# 90 HOST_DEBUG_TX R2489 D GPIO116/TFDP_DATA/UART_RX 94 [17,44] ACOK_IN GPIO117/TFDP_CLK/UART_TX S CAP_LED#_S [65] 95 [17,40] ALL_SYS_PWRGD GPIO035/SB-TSI_CLK 84.2N702.J31 GPIO033/PECI_DAT/SB_TSI_DAT 101 [40] ALWON 102 2ND = 84.2N702.031 VREF_CPU 87 3rd = 84.07002.I31 ESPI ??? Check function with KevinC[27] BEEP ESPI_IO0 CLK_TP_SIO 78 GPIO114/PS2_CLK0 PTP_DIS# Need very close to EC CAP_LED# ESPI_IO1 DAT_TP_SIO 79 GPIO115/PS2_DAT0 GPIO145/ICSP_CLOCK 119 H_PECI_R [55] BLON_OUT ESPI_IO2 SIO_PWRBTN# 52 GPIO026/PS2_CLK1B GPIO146/ICSP_DATA 120 0518(CY17 GPIO) R2437 1 2 43R2J-GP H_PECI [4] ESPI_IO3 0512(SF) VCCDSW_EN# R0R2241J-1L-1GPDY VCCDSW_ON 88 GPIO127/PS2_DAT1B ICSP_MCLR 121 [26] CMP_VIN0_R 2 126 21 [26] CMP_VOUT0 ESPI_IO0 BGPO/GPIO004 127 VREF_CPU ESPI_IO1 59 SYSPWR_PRES/GPIO003 128 0517(CY17 GPIO) DY C2405 [18] PWR_SEClET ESPI_IO2 60 ICSP_CLK SC100P50V2JN-3GP ESPI_IO3 61 GPIO040/LAD0/ESPI_IO0 VCI_OUT/GPIO036 23 ICSP_DAT [65] CLK_TP_SIO 1D8V_S5_KBC ESPI_CS# 62 GPIO041/LAD1/ESPI_IO1 VCI_IN1#/GPIO162 24 ICSP_CLR [65] DAT_TP_SIO MASK_SATA_LED# 58 GPIO042/LAD2/ESPI_IO2 VCI_IN0#/GPIO163 22 R2410 1 2 ESPI_ALERT# 0511(KY15) ESPI_CLK 56 GPIO043/LAD3/ESPI_IO3 VCI_OVRD_IN/GPIO164 NB_MUTE# +RTC_CELL_VBAT [19,79,85] DGPU_PWROK 10KR2J-L-GP 2 PBAT_PRES# PWR_SEClET 57 GPIO044/LFRAME#/ESPI_CS# 85 SYSPWR_PRES 2 100KR2J-1-GP 21 0515(KY15) ESPI_ALERT# 63 GPIO064/LRESET# GPIO160/DAC_0 20 R2452 1 2 0R0402-PAD ACOK_IN 0519 Follow Vendor [27] NB_MUTE# 3D3V_S5_KBC 21 GPU_PWR_LEVEL 55 GPIO034/PCI_CLK/ESPI_CLK GPIO161/DAC_1 25 ALWON R2469 1 3D3V_S5_KBC 0511(KY15) TP_EN# 10 GPIO067/CLKRUN# VCI_IN1# [26] FAN1_DAC_1 R2415 1 DY R2401 1 ESPI_RESET# 49 GPIO063/SER_IRQ/ESPI_ALERT# DAC_VREF 83 POWER_SW_IN# 3D3V_AUX_S5 10KR2J-L-GP 10KR2F-L1-GP LID_CL_SIO# 53 GPIO011/SMI#/EMI_INT# 21 HW_ACAV_IN [79] GPU_PWR_LEVEL 66 GPIO060/KBRST GPIO124/CMP_VOUT0 26 CCG4_I2C_INT# GPIO061/LPCPD#/ESPI_RESET# GPIO020/CMP_VIN0 DGPU_PWROK_EC R2427 1 2 0R0402-PAD DGPU_PWROK 2 12 1 2 12 1 [4,44,46] H_PROCHOT# TP2406 SYS_PWROK GPIO100/EC_SCI# 118 HW_ACAVIN_NB 1 TP2405 21R2424 R2453 TPAD14-OP-GP PBAT_PRES# GPIO165/CMP_VREF0 117 TPAD14-OP-GP 20KR2F-L3-GP [61,68] HOST_DEBUG_TX PRIM_PWRGD 32 GPIO126/SHD_SCLK 116 CMP_VOUT0 C2429 1 3D3V_S5_KBC DY 1KR2J-1-GP RTCRST_ON 28 GPIO133/SHD_IO0 GPIO120/CMP_VOUT1 109 CMP_VIN0 2 SCD1U16V2KX-3GP Vref = 1.117 PCH_RSMRST# 29 GPIO134/SHD_IO1 GPIO021/CMP_VIN1 110 VCREF0 R2470 1 CMP_VOUT0 temp around 85 SYSPWR_PRES 30 GPIO135/SHD_IO2 111 0516(CY17) 31 GPIO136/SHD_IO3 GPIO166/CMP_VREF1/UART_CLK 113 2 0R0402-PAD CMP_VIN0_R 0511(KY15) 27 GPIO123/SHD_CS# 114 GPIO024/ADC7 115 0519 DY if not enable the RTC/WeekTimer GPIO023/ADC6/A20M 3D3V_S5 PROCHOT 0517(CY17 GPIO) SCD01U50V2KX-L-GP R2455 GPIO022/ADC5 CMP_VIN1 C2409 100KR2J-1-GP 3D3V_S5_KBC 0516(CY17) BKLT_IN_EC 67 GPIO101/SPI_CLK GPIO153/ADC4 LCD_TST 1 TP2404 TPAD14-OP-GP 0516(KY15) AC_DIS 69 GPIO154/ADC3 3D3V_S5_KBC 10KR2F-L1-GP TP2403 71 GPIO103/SPI_IO0 GPIO155/ADC2 R2448 1 USB_POWERSHARE_VBUS_EN 42 GPIO122/ADC1 2 10KR2F-L1-GP TPAD14-OP-GP 10KR2J-L-GP FPR_SCAN# 33 GPIO105/SPI_IO1 GPIO121/ADC0 USB_PWR_SHR_EN_L# 2 0R0402-PAD BLON_OUT 0516(CY17 GPIO) 0R0402-PAD TP_WAKE_KBC# GPIO052/SPI_IO2 PANEL_BKEN_EC 2 0R2J-L-GP CMP_VIN0_R R2434 0511(KY15) R2412 1 2 0R0402-PAD AUX_ON 0518(CY17) 3 0516 Follow KY15. ADC_VREF SIO_EXT_WAKE# R2493 1 100KR2J-1-GP INT_TP# MODEL_ID R2497 1 PM_LAN_ENABLE R2431 1 2 GPIO062/SPI_IO3 I_ADP BOARD_ID R2471 1 DY R2491 1 2 GPIO001/SPI_CS#/32KHZ_OUT LCD_VCC_TEST_EN_R I_BATT R2495 1 USB_PWR_EN# R2479 1 2 0R0402-PAD USB_EN# 13 RESET_IN#/GPIO014 0R0402-PAD R2421 1 2 AD_IA [44] 1108 Install ALL_SYS_PWRGD R2481 1 2 0R0402-PAD RUNPWROK 48 GPIO057/VCC_PWRGD 330R2J-3-GP RESET_OUT# 73 GPIO107/RESET_OUT# VSS_VBAT 2 LCD_VCC_TEST_EN ALL_SYS_PWRGD assert, 2 0R2J-L-GP VSS 0516(CY17 GPIO) 21 SC2200P50V2KX-2GP delay 10ms; RESET_OUT# assert. MEC_XTAL2 VSS C2435 SUS_CLK MEC_XTAL1_R VSS R2428 1 DY 125 XTAL2 VSS 3D3V_S5_KBC 123 XTAL1 VSS R0R242J8-7L-1GPDY 2 SIO_SLP_S3# D2402 AVSS LID_CL_SIO# KA 0517 DY VR_CAP TOUCH_PANEL_INTR# [4,55] RB751V-40H-GP MEC1416-NU-D0-GP 124 21 SCD1U16V2KX-3GP EC_AGND 84 C2422 83.R2004.G8F 071.01416.000G 51 17 64 100 112 18 B [4,65] INT_TP# 21 R2458 VR_CAP PTP_DIS# D2405 [17] LANWAKE# 0R0402-PAD EC_AGND [55] LCD_VCC_TEST_EN PKTP A TP_LOCK# [65] XTAL_KBC_2 X2401 R2445 21 C2418 EC_AGND RB751V-40H-GP 12 12 SC1U10V2KX-1GP 83.R2004.G8F 0R0402-PAD [64] LID_CL_SIO# XTAL-32D768KHZ-91-GP Power Switch Logic(PSL) [64] MASK_SATA_LED# [19] ME_FWP 082.30003.0221 +RTC_CELL_VBAT [43,44] PBAT_PRES# SC18P50V2JN-1-GP [17] PCH_RSMRST# 21 C242421 EC_AGND Layout Note: I_BATT SC18P50V2JN-1-GP Connect GND and AGND planes via either R2423 1 2 boost_mon [44] C2425 0R resistor or connect directly. 330R2J-3-GP SC2200P50V2KX-2GP 1 C2441 [31] PCIE_WAKE# Microchip: Use CL=9p Xtal，C = 10p EC LCD test R2456 1 2 0R0402-PAD 21 Layout Note: R2432 R2451 [31] PM_LAN_ENABLE R2419 1 2 0R0402-PAD LCD_TST 1KR2J-1-GP 100KR2J-1-GP [40,54] PRIM_PWRGD [55] EC_BRIGHTNESS Need very close to EC [64] KBC_PWRBTN# 12 12 [43] PS_ID POWER_SW_IN# [55] LCD_TST_R EC_AGND C2426 SC2D2U10V3KX-L-GP [17,26,79] RESET_OUT# 2 0522 Follow KY15 [18,21] RTCRST_ON EC_GPIO47 High Active R0R2421J-8L-1GPDY 2 3D3V_S5_KBC 3D3V_S5_KBC [20] SIO_EXT_WAKE# [17] SIO_PWRBTN# PROCHOT R2420 1 2 CMP_VOUT1_R Q2408 R241421 R2478 R2476 1 E2C_DEBUG 0R2J-L-GP 3D3V_AUX_KBC_R DB3 0R0402-PAD G 10KR2J-L-GP 21 100KR2J-1-GP ICSP_CLK R2463 1 7 [17,27,40,51] SIO_SLP_S3# DY DY ICSP_DAT R2464 1 ICSP_CLK_R 1 21 D H_PROCHOT#_EC R2416 1 2 H_PROCHOT# EC_DEBUG ICSP_DATA_R [17,40,44,51] SIO_SLP_S4# 21 100KR2J-1-GP 0R0402-PAD R2417 S EE22CC__DDEEBBUUGG 0R2J-L-GP E51_TXD_R 2 [43,44] PBAT_CHG_SMBCLK 0R2J-L-GP ICSP_MCLR_R [43,44] PBAT_CHG_SMBDAT SCD01U50V2KX-L-GP 2N7002K-2-GP 21 3 C2419 [18,79] SML1_SMBCLK 84.2N702.J31 DY C2403 HOST_DEBUG_TX R2466 1 EE22CC__DDEEBBUUGG 0R2J-L-GP 4 EC_DEBUG [18,79] SML1_SMBDATA SC47P50V2JN-3GP 0R2J-L-GP 5 2ND = 84.2N702.031 ICSP_CLR [18] SUS_CLK 3rd = 84.07002.I31 R2465 1 6 1108 Install 8 20.K0691.006 ACES-CON6-58-GP [17] SYS_PWROK 3D3V_S5 A 3D3V_S5 [65] TP_EN# MODEL_ID [35] USB_PWR_EN# 21 PCB_REV 21 R2442 64K9R2F-1-GP 100KR2F-L3-GP 2 12 1 2 12 1 [21] VCCDSW_EN# R2443 10KR2F-L1-GP 100KR2F-L3-GP BOARD_ID R2474 1 2 BOARD_ID_R MODEL_ID <Core Design> 0R0402-PAD EC_AGND SCD1U16V2KX-3GP SCD1U16V2KX-3GP R2444 3 C2407 R2441 Wistron Corporation C2408 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title KBC SMSC 1416 EC_AGND Size Document Number Rev 5 Custom Turis/Vegas KBL-R A00 Date: Friday, November 10, 2017 Sheet 24 of 105 4 21

54321 Main Func = SPI Flash Vinafix.com SPI Flash ROM1(16M) for PCH 3D3V_S5_PCH 3D3V_S5_PCH D D C 0519 Follow KY15. 3D3V_S5_PCH 21 SPI_CS_ROM_N0 8 14 SPI_SO_ROM_R 7 SPI_HOLD_ROM_R 23 SPI_WP_ROM_R 6 SPI_CLK_ROM_R 5 SPI_SI_ROM_R 21 21 SKT251 C2501 DY C2502 SC10U6D3V3MX-GP SCD1U16V2KX-3GP 1 2 3 4K7R2J-2-GP RN2501 4 EVT R2501 DY SRN4K7J-8-GP SKT-G6179HT0321-001-GP SPI25 3D3V_S5_PCH Layout Note : 62.10089.011 Co-lay with SPI25 [18] SPI_CS_ROM_N0 SPI_CS_ROM_N0 1 CS# VCC 8 SPI_HOLD_ROM_R RN2503 [18,91] SPI_SO_ROM 2 SPI_SO_ROM_R 2 SO IO3 7 SPI_CLK_ROM_R SRN0J-6-GP R2507 1 SPI_WP_ROM_R 3 IO2 6 SPI_SI_ROM_R 14 10R2F-L1-GP 4 VSS SCLK 5 SPI_WP_ROM_R 23 SI SPI_CLK_ROM [18,91] 14 SPI_SI_ROM [18,91] C 23 SPI_HOLD_ROM [18] SPI_WP_ROM [18] GD25B128CSIGR-GP RN2502 SRN0J-6-GP 072.25128.0H01 Main Func = RTC 3D3V_AUX_S5 2 12 1 R2503 0511 Follow KY15. 1K6R2F-GP 3D3V_RTC_SYS B B +RTC_VCC AFTP2502 1 +RTC_VCC R2505 47KR2F-GP D2501 RTC_3D3V 1 RTC1 3 PWR 1 R2502 1 2 RTC_PWR 2 21 C2503 GND 2 1KR2J-1-GP SCD47U10V2KX-GP NP1 NP1 BAT54C-12-GP NP2 NP2 75.00054.A7D BAT-AAA-BAT-054-P06-GP-U 1 AFTP2501 62.70001.061 Q2505 <Core Design> G Wistron Corporation A 21 R2504 D RTC_DET# [20] A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, 10MR2J-L-GP S Taipei Hsien 221, Taiwan, R.O.C. 2N7002K-2-GP Title 84.2N702.J31 Flash/RTC Size Document Number Rev 2ND = 84.2N702.031 A4 Turis/Vegas KBL-R A00 Date: Wednesday, November 08, 2017 Sheet 25 of 105 543 21

54 3 21 D Main Func = Thermal Sensor PURE_HW_SHUTDOWN# [40,79] 3D3V_S5_KBC KBC T8 Vinafix.com 21 Q2602 21G SCD1U16V2KX-3GP C2610 10KR2J-L-GP R2607 D DY [24] CMP_VOUT0 [17,24,79] RESET_OUT# R2602 DY D 1 DY 2 THERM_SYS_SHDN# S DY 0R2J-2-GP 2N7002K-2-GP 84.2N702.J31 2ND = 84.2N702.031 R2612 1 2 0R0402-PAD Close to Thermal sensor 3D3V_AUX_S5 3D3V_S5_KBC C DY2 12 1R2609 R2608 Close to KBC C 21 2 124K9R2F-L-GP25K5R2F-GP 21 VD_IN1 for system thermal sensor thermistor CMP_VIN0_R [24] R2610 C2612 C2613 NTC-100K-8-GP SCD1U16V2KX-3GP SC100P50V2JN-3GP VD_IN1_C 1 R2611 2 0R0402-PAD Fan controller1 5V_S0 AFTP2602 1FAN_TACH1_C R2605 FAN261 1FAN_VCC1 B AFTP2603 0R2J-2-GP B 1 DY 2 FON# 1 8 2 FSM# GND 7 5V_S0 FAN_VCC1 3 VIN GND 6 FAN_VCC1 4 VOUT GND 5 [24] FAN1_DAC_1 VSET GND SC4D7U6D3V3KX-GPFAN_TACH121 C261121 SCD1U16V2KX-3GPFAN_VCC1 C2605 APL5606AKI-TRG-GP SCD1U16V2KX-3GP SC10P50V2JN-L1-GP 74.05606.A71 EC2602 DY21 DY EC2601 Layout Note: 2rd = 74.02113.0E1 21 3rd = 74.03940.A71 Need 10 mil trace width. FAN1 5 1 R2606 2 FAN_TACH1_C 3 0R0402-PAD [24] FAN_TACH1 2 FAN_VCC1 FAN_VCC1 1 4 <Core Design> D2601 21 ETY-CON3-11-GP AK A Layout Note: C2604 RB551V30-GPDY DY 020.F0283.0003 Wistron Corporation A Signal Routing Guideline: SC4D7U6D3V3KX-GPDY 21 2nd = 20.F1621.003 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, C2603 Taipei Hsien 221, Taiwan, R.O.C. Trace width = 15mil 1 SC2200P50V2KX-2GP AFTP2601 83.R5003.H8H Title change the fan define & connect P/N 020.F0283.0003 by Andy 1/27 THERMAL NCT7718W/Fan Rev Size Document Number Custom Turis/Vegas KBL-R A00 Date: Wednesday, November 08, 2017 Sheet 26 of 105 543 21

5 4 32 1 D Main Func = Audio Audio Codec Chip ALC3204 [29] AUD_HP1_JACK_L LINE1_VREFO [29] +5V_AVDD moat 5V_S0 VinafixCP.VcDD om [29] AUD_HP1_JACK_R MIC2_VREFO [29] 5V_S0 +5V_PVDD AUD_AGND R2703 1 2 LDO1_CAP 0R0603-PAD-2-GP-U SC10U6D3V3MX-GP R2701 1 2 C2708 21 21 C2707 21 21 SCD1U16V2KX-3GP 0R0805-PAD-2-GP-U 21 21 SC2D2U10V2KX-GP VREF 22 AUD_VREF 2 1 SC2D2U10V2KX-GP SC2D2U10V2KX-GP C2706 R2707 1 2 C2709 C2702 C2703 0R0805-PAD-2-GP-U SC2D2U10V2KX-GP 100KR2J-1-GP C2705 R2702 D 1D8V_S0 CPVDD 21 SCD1U16V2KX-3GP SC2D2U10V3KX-L-GP LINE1-VREFO-L 24 LINE1_VREFO MIC2-VREFO 23 MIC2_VREFO LDO1-CAP 21 LDO1_CAP Layout Note: 21C2704 Analog Place close to Pin 20 R2709 1 2 CPVEE 27 CPVEE moat CBP 30 CBP CBN 28 CBN AUD_AGND 0R0402-PAD-2-GP 2 SCD1U25V2KX-GP AUD_AGND EC2701 11111DDDDDYYYYY 2 SCD1U25V2KX-GP Digital EC2702 2 SCD1U25V2KX-GP 1.8V power rail should be supplied by CPVDD 29 HP-OUT-R 26 HP-OUT-L 25 EC2703 2 SCD1U25V2KX-GP linear regulator, not awitching HDA27 EC2704 2 SCD1U25V2KX-GP regulator.if switch regulator is EC2705 unavilable, please make sure that switch frequency operates at out-band(over 20KHz) 1D8V_S0 R2719 1 2 +5V_AVDD 0R0402-PAD-2-GP 21 C2710 31 AVSS2 AUD_AGND SC10U6D3V3MX-GP 32 LDO2-CAP AUD_AGND C2711 2 1 LDO2_CAP AVDD1 20 AUD_AGND AVSS1 19 LINE1-L 18 AUD_AGND >2A moat AUD_AGND SC10U6D3V3MX-GP +3V_1D8V_AVDD 33 AVDD2 LINE1-R 17 LINE1_L AUD_AGND R2704 1 2 0R0603-PAD VD33STB 16 LINE1_R R2705 1 2 0R0603-PAD +5V_PVDD R2713 1 2 0R0805-PAD-2-GP-U +5V_PVDD1 34 PVDD1 ALC3204 MIC2-CAP 15 V3D3_STB LINE1_L [29] R2706 1 2 0R0603-PAD R2714 1 2 0R0805-PAD-2-GP-U AUD_SPK_L+ 35 SPK-L+ SLEEV/MIC2-R 14 MIC_CAP C2715 1 LINE1_R [29] 21 C2713 C2714 QFN40 (5X5) RING2/MIC2-L 13 SLEEVE 21 [29] AUD_SPK_L+ HP/LINE1-JD_JD1 12 RING2 2 SC10U6D3V3MX-GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP PCBEEP 11 AUD_SENSE_A SLEEVE [29] AUD_AGND Layout Note: SC10U6D3V3MX-GP SC10U6D3V3MX-GP [29] AUD_SPK_L- AUD_SPK_L- 36 SPK-L- AUD_PC_BEEP RING2 [29] Tied at point only under SC2D2U10V2KX-GP [29] AUD_SPK_R- AUD_SPK_R- 37 SPK-R- Codec or near the Codec C2740 SCD1U16V2KX-3GP [29] AUD_SPK_R+ AUD_SPK_R+ 38 SPK-R+ C2741 21 C2717 C2718 Layout Note: +5V_PVDD1 39 PVDD2 DVDD 21 PDB_R 40 PDB GPIO0/DMIC-DATA12 Speaker trace 41 GND GPIO1/DMIC-CLK DVDD must >= DVDD_IO width >40mil @ SDATA-OUT 2W4ohm speaker BIT-CLK 3D3V_S0 +3V_1D8V_DVDD power LDO3-CAP SDATA-IN DVDD-IO SYNC DC_DET R2715 1 2 ALC3204-CG-GP-U 1 +3V_1D8V_DVDD Analog +3V_1D8V_DVDD DMIC_DATA_R 2 Digital 0R0603-PAD-2-GP-U DMIC_CLK_R 3 place close to pin8 moat HDA_SDOUT_CODEC_R 4 C 21 HDA_BITCLK_CODEC_R 5 C 21 LDO3_CAP 6 HDA_CODEC_SDIN0 7 8 HDA_CODEC_SYNC 9 DVSS 10 +3V_1D8V_DVDD SC4D7U6D3V3KX-GP 21 C2723 21DY R2717 21 21 Open drain output. SCD1U16V2KX-3GP pull up to DVDD or 100KR2J-1-GP C2721 max. 5V SC10U6D3V3MX-GP R2712 1 2 PDB_R C2720 R2708 1 2 0R0402-PAD-2-GP V3D3_STB [24] NB_MUTE# 0R0402-PAD place close to pin1 RTC_AUX_S5 2 100KR2J-1-GP DVSS 21 C2722 3D3V_S0 R2716 1 DY SC10U6D3V3MX-GP [55] DMIC_DATA R2718 1 2 0R0402-PADDMIC_DATA_R [29] AUD_SENSE AUD_SENSE R2711 1 2 AUD_SENSE_A [55] DMIC_CLK R2720 1 2 22R2J-2-GP DMIC_CLK_R 200KR2F-L-GP 2 R2710 1 21 [19] HDA_SDIN0 DY C2725 +3V_1D8V_DVDD 100KR2J-1-GP 21 [19] HDA_CODEC_SYNC 21 [19] HDA_CODEC_SDOUT SC10P50V2JN-L1-GP [19] HDA_CODEC_BITCLK 0602 DY 21 Close pin3 Azalia I/F EMI [19] SPKR R2741 1 2 D2703 HDA_CODEC_SDOUT [24] BEEP HDA_SPKR_R 1 HDA_CODEC_BITCLK DMIC_DATA R2724 1 2 22R2J-2-GP HDA_CODEC_SDIN0 0R0402-PAD-2-GP 3 AUD_PC_BEEP_C C2735 AUD_PC_BEEP 12 DY EC2709 EC2710DY EC2711 HDA_CODEC_SYNC R2734 1 2 KBC_BEEP_R 2 SCD1U16V2KX-3GP SC100P50V3JN-2GPR2722 12HDA_SDOUT_CODEC_R0R0402-PAD-2-GP BAT54C-12-GP 21 C2739HDA_BITCLK_CODEC_R 21 0R0402-PAD-2-GP 75.00054.A7D DY 1KR2J-1-GPR2723 12 22R2J-2-GP R2735 B B D G0602 Delete C2727 SCD1U16V2KX-3GP1D8V_S5 Q2704 1D8V_S0 C2737 DMP2130L-7-GP 150mA SC22P50V2JN-4GP S SC22P50V2JN-4GP D SC22P50V2JN-4GP 0602 Delete R2739 213D3V_S0 R2736 C2738 21 10KR2J-L-GP SCD22U10V2KX-L1-GP DY C2736 1D8V_EN# 2 1 21 SCD1U16V2KX-3GP G DY R2737 21 0R2J-2-GP R2738 1 2 1D8V_EN_R# 4K7R2J-2-GP 84.02130.031 [17,24,40,51] SIO_SLP_S3# R2740 1 2 Q4009_G Q2705 2nd = 84.00102.031 G 3rd = 84.03413.B31 0R0402-PAD-2-GP D S 2N7002K-2-GP A A <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Rev Audio Codec ALC3204 X00 Size Document Number 105 A2 Turis/Vegas KBL-R Date: Wednesday, November 08, 2017 Sheet 27 of 1 5432

5 4 3 2 1 D Main Func = Audio C Layout NoteV:inafix.com Speaker Speaker trace width >40mil @ 2W4ohm speaker power SPK1 D5 2 0R0603-PAD-2-GP-U AUD_SPK_R+_C CONN Pin Net name [27] AUD_SPK_R+ R2904 1 1 Pin1 SPK_R+ Pin2 SPK_R- [27] AUD_SPK_R- R2903 1 2 0R0603-PAD-2-GP-U AUD_SPK_R-_C 2 Pin3 SPK_L+ [27] AUD_SPK_L+ R2902 1 2 0R0603-PAD-2-GP-U AUD_SPK_L+_C 3 Pin4 SPK_L- [27] AUD_SPK_L- R2901 1 2 0R0603-PAD-2-GP-U AUD_SPK_L-_C 4 6 SC1KP50V2KX-L-1-GP ACES-CON4-29-GP EC2904 20.F1639.004 SC1KP50V2KX-L-1-GP EC2903 2nd = 020.F0700.0004 3rd = 20.F1804.004 SC1KP50V2KX-L-1-GP EC2902 SC1KP50V2KX-L-1-GP EC2901 21 21 21 21 AUD_SPK_L-_C 1 AFTP2901 AUD_SPK_L+_C 1 AFTP2902 AUD_SPK_R-_C 1 AFTP2903 AUD_SPK_R+_C 1 AFTP2904 C RN2901 Universal Jack (Moved to I/O Board) 2 [27] MIC2_VREFO 1 3 4 [27] RING2 C2907 1 2 LINE1-L_C R2922 1 SRN2K2J-1-GP R2908 1 2 10R2F-L1-GP R2906 1 2 0R0603-PAD-2-GP-U RING2_R RING2_R [66] [27] AUD_HP1_JACK_L C2908 1 R2910 1 2 10R2F-L1-GP AUD_HP1_JACK_L1 R2907 1 2 0R0603-PAD-2-GP-U AUD_PORTA_L_R_B AUD_PORTA_L_R_B [66] SC10U6D3V3MX-L-GP 2 1KR2J-1-GP AUD_HP1_JACK_R1 R2909 1 [27] LINE1_L 2 LINE1-L_R R2921 1 2 1KR2J-1-GP JACK_PLUG JACK_PLUG [66] R2911 1 2 0R0603-PAD-2-GP-U AUD_PORTA_R_R_B AUD_PORTA_R_R_B [66] [27] LINE1_R SC10U6D3V3MX-L-GP 2 0R0603-PAD-2-GP-U SLEEVE_R [27] AUD_HP1_JACK_R SLEEVE_R [66] [27] SLEEVE D2901 1 LINE1_VREFO_D1 R2912 121 2 SC100P50V2JN-3GP 21 EC2905 B 4K7R2J-2-GP SC100P50V2JN-3GPDY DYDY DYDY DY B 21 EC2906 [27] LINE1_VREFO 3 21 10KR2J-L-GP 2 LINE1_VREFO_D2 R2913 1 212R2919 4K7R2J-2-GP 21SC100P50V2JN-3GP 21EC2907 BAT54A-11-GP 10KR2J-L-GP R2920 SC100P50V2JN-3GP EC2908 AUD_AGND AUD_AGND AUD_AGND Delay circuit (JACK_PLUG_DET: on IO Board) JACK_PLUG 10 mils 10 mils R2923 1 2 AUD_SENSE [27] 0R0603-PAD-2-GP-U DY C2902 SC10U6D3V3MX-GP <Core Design> A AUD_AGND Wistron Corporation A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Audio IO Size Document Number Rev Custom Turis/Vegas KBL-R Date: Wednesday, November 08, 2017 A00 Sheet 29 of 105 54 321

54321 Main Func = LAN Layout: Ca: colse to Pin8 LAN CHIP (10/100/1000M & 10/100M co-lay) For RTL8111G(S) Cb close to Pin30 * Place Ca~Cd close to each VDD10 pin-- 8, 30, 3, 22 For RTL8106E Vinafix.comCc: close to Pin3 * Place Ca,Cb close to each VDD10 pin-- 8, 30 Cd: close to Pin22 Ra LAN power Noise 1V_LAN_VDD10 < 100mV Vpeak to Vpeak. D REGOUT R3101 1 2 VDD10 D C C3101,R3101: 0R0603-PAD-2-GP-U B Only for SCD1U16V2KX-3GP RTL8111 LDO mode. 21 L2AN_1SW L2AN_1SW 21 21 8111G2/LA 1N_SW 8111G2/LA 1N_SW Ci Cj Ca Cb Cc Cd R3102 C3102 C3118 1 L3101 La 2 SCD1U16V2KX-3GP RTL8111GUS-CG RTL8111G-CGT RTL8106EUS-CG RTL8106E-CG 2K49R2F-2-L-GP PCIE_RX_CON_P5 1 2 SCD1U16V2KX-3GP PCIE_RX_CPU_P5 [16] C3122 71.08111.W03 71.08111.U03 71.08106.003 071.08106.0003 12 PCIE_RX_CON_N5 1 2 SCD1U16V2KX-3GP PCIE_RX_CPU_N5 [16] SCD1U16V2KX-3GP PCIE_TX_CON_P5 C3107 PCIE_TX_CON_P5 [16] 8111G IND-4D7UH-242-GP C3123 PCIE_TX_CON_N5 PCIE_TX_CON_N5 [16] Ch SCD1U16V2KX-3GP LAN_SW C3119 SCD1U16V2KX-3GP 68.4R71E.10G C3112 SCD1U16V2KX-3GP C3115 SWR mode LDO mode SWR mode LDO mode PEG_CLK2_CPU [18] SC4D7U6D3V3KX-GP PEG_CLK2_CPU# [18] C3108 3D3V_LAN_S5 10/100/1000M 10/100/1000M 10/100M 10/100M RSET LED0 1 VDD10 LED1 1 Layout: LANXOUT LED2 1 TP3103 TPAD14-OP-GP For RTL8111G(S) LANXIN TP3102 TPAD14-OP-GP * Place Ce and Cf close to each VDD33 pin-- 11, 32 TP3101 TPAD14-OP-GP For RTL8106E * Place Cg and Cf close to each VDD33 pin-- 23, 32 LOM31 32 3D3V_LAN_S5 33 GND 31 30 29 28 27 26 25 AVDD33 3D3V_S5 RSET VDDREG 21 AVDD10 21 40 mils R3104 1 2 0R0603-PAD 1 CKXTAL2 24 1 2 C3104 R3103 2 CKXTAL1 23 SC1U10V2KX-1GP 10KR2J-L-GP 8111G/LAN_SW [32] LAN_MDI0P 3 MDIP0 (NC) REGOUT 22 REGOUT C3114 1 3D3V_S0 [32] LAN_MDI0N 4 LED0 21 VDDREG 2 SCD1U16V2KX-3GP 21 [32] LAN_MDI1P 5 (GPO) LED1/GPO 20 VDD10 21 [32] LAN_MDI1N 6 19 PCIE_W AKE# [32] LAN_MDI2P 7 (LED1) LED2 18 8106E [32] LAN_MDI2N 8 17 C3113 C3117 C3103 LAN_SW VDD10 MDIN0 (DVDD33) VDDREG 21 C3124 Ck VDD10 AVDD10 (NC)71.08111.U03 (NC) DVDD10 SCD1U16V2KX-3GP LAN_SW MDIP1 LANW AKE# ISOLATE# R3109 1 2 PCIE_WAKE# [24] Cl C3110 PLT_RST#_LAN 1KR2J-1-GP 21 R3113 21 SC4D7U6D3V3KX-GP 15KR2J-1-GP Ce Cf Cf: close to Pin32 MDIN1 ISOLATE# Cg Ce: close to Pin11 X5R MDIP2 (NC) (071.08106.0003) PERST# MDIN2 (NC) HSON PCIE_RX_CON_N5 Cg: close to Pin23 PCIE_RX_CON_P5 AVDD10 HSOP SCD1U16V2KX-3GP MDIP3 (NC) SCD1U16V2KX-3GP MDIN3 (NC) SCD1U16V2KX-3GP AVDD33 (NC) CLKREQ# C HSIP HSIN REFCLK_P Manual: :071.08106.0003 RTL8107E-CG PN:071.08106.0003 REFCLK_N RTL8111G-CGT-1-GP-U2 9 10 11 12 13 14 15 16 3D3V_LAN_S5 RTL8111G-CGT (71.08111.U03/LDO Mode): 10/100/1000M < 252 mW. RTL8106E-CG (071.8107E.0A03): 10/100M <70mW. 21 SC4D7U6D3V3KX-GP [32] LAN_MDI3P 21 C3111 [32] LAN_MDI3N DY DY SC4D7U6D3V3KX-GP C3116 Layout: C3109 3D3V_LAN_S5 LANXOUT 12 C3109 : close to Pin32 LAN_CLKREQ_LAN# [17,55,61,63,76,91] PLT_RST# R3110 1 2 PLT_RST#_LAN C3111 : close to Pin11 PCIE_TX_CON_P5 SC15P50V2JN-2-GP 0R0402-PAD PCIE_TX_CON_N5 PEG_CLK2_CPU X3101 PEG_CLK2_CPU# XTAL-25MHZ-260-GP 0512 Deleted DY part R3105 1 2 LAN_CLKREQ_LAN# 14 082.30005.0041 0R0402-PAD 23 [18] CLKREQ_PCIE#2 0512 Deleted DY part 3D3V_LAN_S5 rise time must be controlled LANXIN C3125 between 0.5 mS and 100 mS. 12 LAN power Noise 3D3V_LAN_VDD33 < 200mV Vpeak to Vpeak. SC15P50V2JN-2-GP 3D3V_S5 Q3101 3D3V_LAN_S5 DMP2130L-7-GP 85mA S D 21 SCD1U16V2KX-3GP SCD1U16V2KX-3GP 21C3121 D LAN_ENABLE_R_C 2 1100KR2J-1-GP G 21R3107 G 21 B C3120 R3106 DY 10KR2J-L-GP C3105 SC1U10V2KX-1GP R3111 1 2 PM_LAN_ENABLE_C 20KR2J-L2-GP 84.02130.031 2nd = 84.00102.031 Q3102 3rd = 84.03413.B31 G [24] PM_LAN_ENABLE D S 2N7002K-2-GP BOM Option 1.0V Ra Ch Cc Cd Ce La Ci Cj Ck Cl Cg Source RTL8111G-CGT 8111G LDO O O O OO X XX XXX (71.08111.U03) SWR LDO A RTL8111GUS-CG A 5 (71.08111.W03)/ RTL8106EUS-CG LAN_SW X XO OO O O O O O X (71.08106.003) 8106E RTL8106E-CG <Core Design> (071.08106.0003) XX X X X X X X X X O Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Rev LAN RTL8106 A00 Size Document Number 105 A2 Vegas SKL/KBL-U Date: Wednesday, November 08, 2017 Sheet 31 of 1 432

54321 Main Func = LAN LAN TransFormer (10/100/1000M & 10/100M co-lay) 9 RJ45 1 Vinafix.com Layout: MDO0+ CHASSIS#9 XF3201 XFORM-12P-48-GP Place near RJ45 MDO0- MDO0+ 12 1CT:1CT 1 MDO1+ [31] LAN_MDI3N MDO3- 1 MDO0+ MDO2+ 2 MDO0- D [31] LAN_MDI3P MDO3+ AFTE14P-GP AFTP3204 1 MDO0- MDO2- 3 MDO1+ D [31] LAN_MDI2N MDO2- AFTE14P-GP AFTP3201 1 MDO1+ MDO1- 4 MDO2+ C 3 MCT0 AFTE14P-GP AFTP3202 1 MDO2+ MDO3+ 5 MDO2- B AFTE14P-GP AFTP3205 1 MDO2- MDO3- 6 MDO1- 11 2 AFTE14P-GP AFTP3203 1 MDO1- 7 MDO3+ AFTE14P-GP AFTP3208 1 MDO3+ 8 MDO3- 10 5 AFTE14P-GP AFTP3207 1 MDO3- 10 CHASSIS#10 AFTE14P-GP AFTP3206 8 1CT:11CT0/100/1000 RJ45 4 MCT1 RJ45-8P-186-GP [31] LAN_MDI2P 7 6 MDO2+ 022.10001.00C1 9 2nd = 022.10001.0D41 3rd = 022.10001.0C41 68.68167.30D XF3202 XFORM-12P-48-GP MCT3 9 MCT2 MCT1 C 7 6 MDO1- MCT0 [31] LAN_MDI1N 4 MCT2 21 5 4 63 [31] LAN_MDI1P 8 5 MDO1+ 72 RN3201 10 81 SRN75J-1-GP 1CT:1CT LOM_TCT [31] LAN_MDI0N 11 1CT:1CT 2 MDO0- 3 MCT3 [31] LAN_MDI0P 12 1 MDO0+ MCT C3202 68.68167.30D SC56P3KV8JN-1-GP Layout note:21 Layout note: 30 mil spacing between MDI differential pairs. 30 mil spacing between MDI differential pairs. C3201 B SCD01U50V2KX-L-GP Follow Reference Schematic 0.01uF~0.4uF ED3202 ED3201 LAN_MDI0P 1 IN1 NC#10 10 LAN_MDI0P LAN_MDI2P 1 IN1 NC#10 10 LAN_MDI2P LAN_MDI0N 2 IN2 NC#9 9 LAN_MDI0N LAN_MDI2N 2 IN2 NC#9 9 LAN_MDI2N LAN_MDI1P 3 GND GND 8 LAN_MDI1P LAN_MDI3P 3 GND GND 8 LAN_MDI3P LAN_MDI1N 4 IN3 NC#7 7 LAN_MDI1N LAN_MDI3N 4 IN3 NC#7 7 LAN_MDI3N 5 IN4 DY NC#6 6 5 IN4 DY NC#6 6 <Core Design> TVWDF1004AD0-1-GP TVWDF1004AD0-1-GP Wistron Corporation 75.01004.073 75.01004.073 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. A A Title Size Document Number XFOM&RJ45 Rev A4 Vegas SKL/KBL-U A00 Date: Wednesday, November 08, 2017 Sheet 32 of 105 54 3 2 1

54321 Main Func = Card Reader Vinafix.com D D C [16] USB_CPU_PN5 R3301 1 2 0R0402-PAD-2-GP USB_PN5_C [66] C [16] USB_CPU_PP5 R3302 1 2 0R0402-PAD-2-GP USB_PP5_C [66] B Layout Note: A Close to CON1 5 B <Core Design> Wistron Corporation A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Card Reader-RTS5170 Rev Document Number A4 Vegas SKL/KBL-U A00 Date: Wednesday, November 08, 2017 Sheet 33 of 105 4321

54 3 21 Main Func = USB3.0 Port1 USB_OC0# [16] Vinafix.com USB3.0 Port1 D USB30_VCCC 2A D C 5V_S5 Layout Note: Close USB1 B [24,35] USB_PWR_EN# U3501 USB30_VCCC SC22U6D3V3MX-1-DL-GP C3513 SC22U6D3V3MX-1-DL-GP C3512 SC1U10V2KX-1GP C3508 SCD1U16V2KX-3GP C3507 5 IN OUT 1 21 DY TC3501 2 21 SC100U6D3V6MX-GP SC1U10V2KX-1GP 4 EN# GND 3 21 21 C3510 OC# 21 78.10710.52L 21 Active Low SY6288DAAC-GP 074.06288.009B 0817 Change Cap Size C Main Func = USB2.0 Port3 USB2.0 Port3 (IO Board) USB20_VCCA 5V_S5 Support 2A USB20_VCCA 2A U3503 SC22U6D3V5MX-L3-GP C3515 5 IN OUT 1 21 SC1U10V2KX-1GP DY 4 EN# GND 2 21C3518 [24,35] USB_PWR_EN# OC# 3 USB_OC2# [16] 21SCD1U16V2KX-3GP C3517 B Active Low 21 C3504 SY6288DAAC-GP SCD1U16V2KX-3GP 074.06288.009B Layout Note: Close CON1 <Core Design> A Wistron Corporation A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Document Number USB switch Rev Turis/Vegas KBL-R A00 Date: Wednesday, November 08, 2017 Sheet 35 of 105 54321

54 32 1 Main Func = USB3.0 Port1 USB3.0 Port1 1 AFTP3601 1 AFTP3602 USB30_VCCC USB1 1 AFTP3603 USB_PN0_C [16] USB_CPU_PP0 EL3601 USB_PP0_C USB_PP0_C 1 VBUS CHASSIS#10 10 USB30_VCCC [16] USB_CPU_PN0 12 USB3_PRX_CTX_N1_C CHASSIS#11 11 USB_PN0_C USB3_PRX_CTX_P1_C CHASSIS#12 12 USB_PP0_C 4 Vina3fix.com USB_PN0_C USB3_PTX_CRX_N1_C 2 D- CHASSIS#13 13 USB3_PTX_CRX_P1_C 3 D+ FILTER-4P-137-GP-U USB3_PRX_CTX_N1_C 5 SSRX- D USB3_PRX_CTX_P1_C 6 SSRX+ C D 68.01012.20B USB3_PTX_CRX_N1_C USB3_PTX_CRX_P1_C 8 PGND 4 1 AFTP3604 9 GND 7 C3602 SSTX- SCD1U16V2KX-3GP SSTX+ [16] USB30_TX_CPU_N1 1 2 USB3_PTX_CRX_N1_R R3605 1 2 USB3_PTX_CRX_N1_C USB3.0 [16] USB30_TX_CPU_P1 USB3_PTX_CRX_P1_C 0R0402-PAD-2-GP SKT-USB13-179-GP C3601 022.10005.00B1 SCD1U16V2KX-3GP R3606 1 2 2nd = 022.10005.0831 1 2 USB3_PTX_CRX_P1_R 3rd = 022.10005.00A1 0R0402-PAD-2-GP Stuff for ESD R2 spec ED3602 [16] USB30_RX_CPU_N1 R3607 1 2 0R0402-PAD-2-GP USB3_PRX_CTX_N1_C 1 LINE_1 NC#10 10 USB3_PRX_CTX_N1_C [16] USB30_RX_CPU_P1 R3608 1 2 0R0402-PAD-2-GP USB3_PRX_CTX_P1_C 2 LINE_2 NC#9 9 USB3_PRX_CTX_P1_C 3 GND GND 8 4 LINE_3 NC#7 7 USB3_PTX_CRX_N1_C 5 LINE_4 NC#6 6 USB3_PTX_CRX_P1_C C AZ1045-04F-R7G-GP 75.01045.073 Main Func = USB3.0 Port2 USB3.0 Port2 USB2 USB30_VCCC 1 VBUS CHASSIS#10 10 USB_PN1_C CHASSIS#11 11 EL3602 USB_PP1_C 2 D- CHASSIS#12 12 43 3 D+ CHASSIS#13 13 USB3_PRX_CTX_N2_C [16] USB_CPU_PN1 12 USB_PN1_C USB3_PRX_CTX_P2_C 5 SSRX- [16] USB_CPU_PP1 USB_PP1_C 6 SSRX+ FILTER-4P-137-GP-U USB3_PTX_CRX_N2_C USB3_PTX_CRX_P2_C 8 PGND 4 1 AFTP3608 68.01012.20B 9 GND 7 SSTX- SSTX+ USB3.0 C3605 SKT-USB13-179-GP SCD1U16V2KX-3GP B R3609 1 2 USB3_PTX_CRX_N2_C 022.10005.00B1 B 1 2 USB3_PTX_CRX_N2_R USB3_PTX_CRX_P2_C [16] USB30_TX_CPU_N2 0R0402-PAD-2-GP 2nd = 022.10005.0831 [16] USB30_TX_CPU_P2 C3604 3rd = 022.10005.00A1 SCD1U16V2KX-3GP R3610 1 2 Stuff for ESD R2 spec 1 2 USB3_PTX_CRX_P2_R ED3603 0R0402-PAD-2-GP [16] USB30_RX_CPU_N2 R3611 1 2 0R0402-PAD-2-GP USB3_PRX_CTX_N2_C USB3_PRX_CTX_N2_C 1 LINE_1 NC#10 10 USB3_PRX_CTX_N2_C [16] USB30_RX_CPU_P2 R3612 1 2 0R0402-PAD-2-GP USB3_PRX_CTX_P2_C USB3_PRX_CTX_P2_C 2 LINE_2 NC#9 9 USB3_PRX_CTX_P2_C USB3_PTX_CRX_N2_C 3 GND GND 8 USB3_PTX_CRX_P2_C 4 LINE_3 NC#7 7 USB3_PTX_CRX_N2_C 5 LINE_4 NC#6 6 USB3_PTX_CRX_P2_C USB30_VCCC USB_PN1_C AZ1045-04F-R7G-GP USB_PP1_C 75.01045.073 3 2nd = 75.00107.073 StuEffD3f6o0r4 ESD R2 spec <Core Design> A USB_PN1_C 1 I/O1 I/O4 6 USB_PP1_C USB30_VCCC Wistron Corporation A 2 GND VDD 5 1 AFTP3605 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, 1 AFTP3606 Taipei Hsien 221, Taiwan, R.O.C. USB_PN0_C 3 I/O2 I/O3 4 USB_PP0_C 21DY C3618 1 AFTP3607 SCD1U16V2KX-3GP Title AZC099-04S-2-GP USB30 075.09904.0A7C Size Document Number Rev Custom Vegas SKL/KBL-U A00 Date: Wednesday, November 08, 2017 Sheet 36 of 105 54 2 1

54 3 2 1 D Main Func = USB2.0 Port3 C Vinafix.com D USB port 3 (USB2.0 only) CMC 0RR372J0-1L1-GPDY 2 [16] USB_CPU_PN2 EL3706 Layout Note: USB_PN2_C [66] [16] USB_CPU_PP2 12 Close to CON1 USB_PP2_C [66] C 43 USB_PN2_C USB_PP2_C FILTER-4P-137-GP-U 68.01012.20B R0R327J0-2L1-GPDY 2 USB ESD Diode USB20_VCCA Stuff for ESD R2 spec ED3704 B USB_PP2_C 1 I/O1 I/O4 6 USB_PN2_C B A 2 GND DYVDD 5 Layout Note: 21 5 3 4 Close to CON1 I/O2 I/O3 DY C3706 SCD1U16V2KX-3GP AZC099-04S-2-GP 075.09904.0A7C <Core Design> Wistron Corporation A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title USB20 Size Document Number Rev A4 Turis/Vegas KBL-R A00 Date: Wednesday, November 08, 2017 Sheet 37 of 105 2 1 43

54 3 2 3D3V_S0 1 Main Func = Power Plane & Sequence 5V_S0 Power Good R4005 ALL_SYS_PWRGD [17,24] 1KR2J-1-GP VR_EN [46] ROSA Run Power 5V_S0 21 0519 Follow KY15 to delete DY part U4001 5V_S0 Comsumption R4011 1 2 Peak current 5A 0R0402-PAD 5V_S5 Vinafix.com1 13 [51] PWR_VDDQ_PG 14 3D3V_S03D3V_S0 3D3V_S5 2 D VIN1#1 VOUT1#13 8 3D3V_S0 Comsumption R4002 1 2 VIN1#2 VOUT1#14 9 Peak current 2.5A 0R0402-PAD 5V_S5 6 VIN2#6 VOUT2#8 RSMRST_PWRGD# D4002 1 7 VIN2#7 VOUT2#9 3 2 SC10U6D3V3MX-GP DY C4005 SC10U6D3V3MX-GP C4004 SC470P50V2KX-3GP C4001 SC470P50V2KX-3GP C4002 SC10U6D3V3MX-GP C4009 20KR2J-L2-GP R4006 21 4 VBIAS SS1 12 3V5V_CT1 LBAS16LT1G-GP D 21 SS2 10 3V5V_CT2 C 21 B [17,24,27,40,51] SIO_SLP_S3# R4010 1 2 213V5V_S0_ON 3EN1GND11 83.00016.P11 0R0402-PAD 215EN2GND15 21 3D3V_S5 3D3V_S5_KBC AP22966DC8-7-GP [#543016] Optional, Added for addition system robustness 21 21 074.22966.0093 [53] 1D0V_S5_PWRGD R4029 1 2 0R0402-PAD R4031 DY R4032 100KR2J-1-GP 100KR2J-1-GP 0522 Follow EC vendor Marc suggest. 0511 Follow KY15. [24,54] PRIM_PWRGD R4030 1 2 0R0402-PAD RSMRST_PWRGD# 0RR4021J-2L1-GPDY 2 [17,21,45,53,54] 3V_5V_POK R4033 1 DY 2 0R2J-2-GP D4001 NON DS3: PH 3V_5V_POK to 3D3V_AUX_S5 at page17 2 [45] 3V_5V_EN 1 3 PURE_HW_SHUTDOWN# [26,79] ALWON [24] LBAS16LT1G-GP 5V_S5 83.00016.P11 VCCSTG and VCCIO R4009 1 2 10KR2J-L-GP 21 SC10U6D3V3MX-GP C4007 DY SC10U6D3V3MX-GP C4016U4002+VCCIO(ICCMAX = 2.73A)+VCCIO +VCCSTG 0519 Follow KY15 to change cap value SC1U10V2KX-1GP 1 VIN VOUT#8 8 R4048 1 2 C C4029 2 VIN VOUT#7 7 3 VBIAS VOUT#6 6 0R0805-PAD-2-GP-U 4 EN 5 [17,24,27,40,51] SIO_SLP_S3# R4034 1 2 VCCSTG_EN_R GND 1D0V_S5 0R0402-PAD 9 VIN 21 21DY C4017 21 VIL > 0.7 V, VIH < 2 V SCD1U16V2KX-3GP Rds(on) = 11 mΩ @ VDD = 4 V Ids(max) 10 A APE8939GN3-GP 074.08939.0093 VCCSTG should only ramp up equal to or after VCCST. U4002 U4006 change to 074.08939.0093 +VCCSTG(ICCMAX.=0.16A) for quality issue change 2/26 Trise=10US < TR < 65US MANAGEMENT RAIL POWER GENERATION EOPIO and EDRAM 5V_S5 20170428 21 VIL > 0.7 V, VIH < 2 V V1.8S Rds(on) = 11 mΩ @ VDD = 4 V C4028 DY Ids(max) 10 A +V1.00U_CPU 20170428 SC1U10V2KX-1GP B VCCSTU4006 1 8 +V1.00U_CPU_LS R4025 1 2 2 VIN VOUT#8 7 3 VIN VOUT#7 6 0R0805-PAD-2-GP-U 4 VBIAS VOUT#6 5 EN GND SC10U6D3V3MX-GP C4012 SC10U6D3V3MX-GP C4013 SCD1U16V2KX-3GP C4018 [17,44,51] SIO_SLP_S4# R4024 1 2 VCCSTU_EN_R 21 0R0402-PAD 21 VIN 9 1D0V_S5 21DY APE8939GN3-GP 074.08939.0093 U4002 U4006 change to 074.08939.0093 +V1.00U_CPU +VCCST_CPU for quality issue change 2/26 VCCST, VCCSTG, and VCCPLL can remain powered during S4 and S5 power states for board VR optimization. R4036 1 2 0.04 A 0R0402-PAD-2-GP AA <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Rev Power Plane Enable A00 Size Document Number Custom Vegas SKL/KBL-U Date: Wednesday, November 08, 2017 Sheet 40 of 105 54321

54 3 2 1 D Main Func = Power & Sequence C Vinafix.com D 3D3V_S5 3D3V_S5_PCH R4101 1 2 0R0805-PAD-2-GP-U C BB <Core Design> A Wistron Corporation A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Connected_Standby(1/2)+DS3 Size Document Number Rev A4 Vegas SKL/KBL-U A00 Date: Wednesday, November 08, 2017 Sheet 41 of 105 54321

5 4 3 2 1 3D3V_S5 Main Func = ADT Input 3D3V_S5 3P3RR423J0-62-G1 P DY 2 2 S 3 PQ4301 DMN5L06K-7-GP 1 21 Layout Note: D 75.00099.O7D PR4304 PSID Layout width > 25mil 2nd = 75.00099.K7D 2K2R2J-L1-GP 20170502 remove DCIN2 3rd = 75.00099.Q7D Vinafix.comPR4317 1 PD4302 2 PS_ID_R2 PS_ID_R1 PR4305 1 LBAV99LT1G-1-GP 33R2J-2-GP 2 PS_ID [24] 0R0603-PAD 1 D 84.05067.031 3 2 12 1 D C EL4303 1 2 2 PR4309 E CG 5V_S5 PD4303 100KR2J-1-GP 2 PESD24VS2UT-GP 0R0805-PAD-2-GP-U PSID_DISABLE#_R_C EL4304 1 2 PR4303 1 10KR2J-L-GP 0R0805-PAD-2-GP-U JGND PQ3802_1 B PQ4302 LMBT3904LT1G-GP DCIN1 8 PR4302 6 15KR2F-GP 84.T3904.H11 5 4 PS_ID_R 1 AFTP4301 20170810 Id=-9.6A 3 1 AFTP4315 ESD 600W TVS 2 Qg=-25nC Rdson=18~30mohm +DC_IN AD+ 1 0921 Install PU4301 7 +DC_IN 1S D8 AK 2S D7 3S D6 21 SCD1U50V3KX-GP21 21 SC10U25V5KX-L-GP 21 PC4302 12 1 PC4306 P6SMBJ24A-H-GP PD4301 PC4305 PC4304 SCD1U25V2KX-GP PC4303 ACES-CON6-63-GP DY EC4302 SC1U50V3KX-GP 4G D5 21 SC10U25V5KX-L-GP PC4301 21 20.F2132.006 EC4301 21 21 2nd = 20.F2505.006 21 21 240KR3-GP DY DY PR4307 PR4312 PR4314 AC_DIS [24,44] PQ4305 2 AON7403-GP-U 3K3R6J-GP 1 3 DY 100KR2J-1-GP PQ4304 84.07403.037 C AD_OFF_L R1 JGND JGND R2 AD_OFF_R B R1 C PQ4306 E LTA024EUB-FS8-GP SCD01U50V2KX-L-GP SCD01U50V2KX-L-GP PQ3809_D 3 4 R2 84.00024.01K SCD01U50V2KX-L-GP LMUN5212T1G-GP AC_IN#_G 2 5 47KR3J-L-GP 84.05212.B11 PR4308 1 +DC_IN 21 1 6 AC_IN_KBC# 1 TP4301 2 1 PS_ID_R TPAD14-OP-GP AFTP4313 1 +DC_IN 2N7002KDW -GP AFTP4312 PR4313 AFTP4314 0R0402-PAD 84.2N702.A3F 2nd = 84.2N702.E3F 3rd = 75.00601.07C Main Func = M-BAT Input 20170502 remove BATT2 Placement: Close to Batt Connector BT+ B PBAT_SMBCLK1 B PBAT_SMBDAT1 21 DY EC4308 EC4307 PBAT_PRES1# 21 AK SCD1U25V2KX-GP DY PD4304 SCD1U50V3KX-GP SMF18A-GP Batt Connecter 1 D4306 3 LBAV99LT1G-1-GP 2 75.00099.O7D 1 3 2 1 3 2 0921 Install BATT1 D4304 D4305 9 LBAV99LT1G-1-GP LBAV99LT1G-1-GP 1 75.00099.O7D 75.00099.O7D [24,44] PBAT_CHG_SMBCLK PBAT_CHG_SMBCLK RN4302 2 3 SRN100J-3-GP PBAT_SMBCLK1 2 3D3V_S5_KBC [24,44] PBAT_CHG_SMBDAT PBAT_CHG_SMBDAT 1 4 PBAT_SMBDAT1 3 PBAT_PRES# 2 PBAT_PRES1# 4 [24,44] PBAT_PRES# R4302 1 SYS_PRES1# 5 DY 100R2J-L-GP 6 7 DY 8 EC4306 10 2nd = 75.00099.K7D 2nd = 75.00099.K7D 2nd = 75.00099.K7D EC4310 3rd = 75.00099.Q7D 3rd = 75.00099.Q7D 3rd = 75.00099.Q7D EC4309 ALP-CON8-17-GP-U1 21 DY R4301 21 0R0402-PAD 20.82003.008 21 21 2nd = 20.81775.008 3rd = 020.80842.0008 PBAT_PRES1# 1 AFTP4303 1 AFTP4311 PBAT_SMBDAT1 1 AFTP4308 SC10P50V2JN-L1-GP 1 AFTP4309 PBAT_SMBCLK1 1 SC10P50V2JN-L1-GP Layout note: 1 AFTP4310 AFTP4304 SC10P50V2JN-L1-GP SYS_PRES1# >40 mil 1 AFTP4307 A BT+ 1 AFTP4306 <Core Design> A BT+ BT+ 1 AFTP4302 SYS_PRES1# 1 Wistron Corporation AFTP4305 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title DCIN Rev Size Document Number A00 A3 Vegas SKL/KBL-U Date: W ednesday, November 08, 2017 Sheet 43 of 105 543 21

54321 Main Func = Charger AD+ +SDC_IN DCBATOUT +VCHGR PQ4410 PR4426 1S PQ4401 8D S 1 D01R3721F-GP-U 2S D8 7D S 2 3S D7 6D S 3 12 4G D6 5D G 4 D5 21 Vinafix.comAON7403-GP-U PR4441 1PG_1 1 2 PG4429 1PG_2 1 2 PG4407 AON7403-GP-U 84.07403.037 100KR2J-1-GP GAP-CLOSE-PW R-3-GP GAP-CLOSE-PW R-3-GP 84.07403.037 AD+ D 21 PR4440 D 20KR3J-1-GP PR4420 AD+_G_2 12 AD+_R 10KR2F-L1-GP 21 21 PR4422 PR4467 PR4468 PR4445 10KR2F-L1-GP 0R0402-PAD-1-GP 2R2F-GP 470KR2J-L1-GP AD+_G_1 PC4466 DY PC4468 PQ4412 G AC_DIS_R PR4444 1 2 DC_IN_D SCD1U25V2KX-GP 1KR2J-1-GP 21 2 SC2K2P50V2KX-L-GP AC_DIS [24,43] 2 12 21 D 21 2N7002KDW -GP PWR_CHG_ACN S PC4471 34 PWR_CHG_ACP SCD22U10V2KX-L1-GP 25 DY 16 SC2K2P50V2KX-L-GP 2N7002K-2-GP ACOK_IN PC4467 PQ4405 84.2N702.J31 84.2N702.A3F 2nd = 84.2N702.E3F 2ND = 84.2N702.031 4th = 84.DMN66.03F 3rd = 84.07002.I31 3rd = 75.00601.07C DCBATOUT 21 PR4477 DCBATOUT 1KR2F-L1-GP PW R_CHG_REGN SC1KP50V2KX-L-1-GP PC4418 PC4427 PC4438 PC4459 PR4417 PC4407 100KR2J-1-GP SC1KP50V2KX-L-1-GP DY PC4409 SCD1U25V2KX-GP symbol name change by Andy 1/19 SC1KP50V2KX-L-1-GP PC4456 BT+ SC10U25V5KX-L-GP SC10U25V5KX-L-GP SC10U25V5KX-L-GP SC10U25V5KX-L-GP DS DS DS D G 2 12 1 21 PR4454 BT+ 21 21 100R5F-2-GP 21 21 12 21 21 21 21 VAC DET AD+ 21 BGATE 25 PWR_CHG_BATDRV2 1 Greater than 2.633 V C [17,24] ACOK_IN Less than 3.5 V PC4408 C PR4418 191KR2F-1-GP AC_IN:3.35~3.75V 21 PR4452 CSIP 32 PWR_CHG_ACP CSIN 31 PWR_CHG_ACN ASGATE 30 PWR_CHG_ASGATE CMSRC 29 PWR_CHG_CMSRC 5 21 SC10U25V5KX-L-GP 21 150KR2F-L-GP 36 21 PC4410 3D3V_AUX_S5 VDD 27 SC10U25V5KX-L-GP 2 12 1 PW R_CHG_ACDET QPCN 28 PWR_OPCN QPCP 27 PWR_OPCP VBAT 26 PWR_VBAT PU4411 18 PC4401 21 SM4378NSKPC-TRG-GP 65 BOM 4 SCD01U50V2KX-L-GP 084.04378.0037 +VCHGR BT+ PC4419 18K7R2F-GP PU4401 PL4401 PR4443 PC4452 PC4453 PR4416 1 DY 100KR2F-L3-GP PR4451 PG4426 300KR2F-L-GP PR4434 100KR2F-L3-GP PR4450 10KR2F-L1-GP PR4449 10KR2F-L1-GP PR4435 DY DY DY DY DY PWR_CHG_PHASE 1 2 2 COIL-4D7UH-33-GP SCD1U25V2KX-GP PR4428 PC4431 68.4R71A.20H D01R3721F-GP-U PC4464 SC10U25V5KX-L-GP SC10U25V5KX-L-GP GAP-CLOSE-PWR-3-GP 0R0603-PAD-1-GP-U SCD22U25V3KX-GP 1 PWR_CHG_SRP_R 1 2 1 PWR_CHG_SRN_R 1 2 PWR_CHG_BTST 1 2PWR_CHG_BTST1 1 21 PR4474 1 ACIN BOOT 24 2 5 21 36 21 0R0402-PAD 27 GAP-CLOSE-PWR-3-GP PG4428 ACOK_IN 1 2 PW R_CHG_ACOK 2 ACOK UGATE 23 PW R_CHG_HIDRV PU4412 18 DS BT+ PR4470 PW R_CHG_SDA SM4378NSKPC-TRG-GP DS [24,43] PBAT_CHG_SMBDAT 0R0402-PAD PW R_CHG_SCL 3 SDA PHASE 22 PW R_CHG_PHASE DS [24,43] PBAT_CHG_SMBCLK 12 65 BOM D 12 PW R_CHG_AMON 4 SCL LGATE 21 PW R_CHG_LODRV 0R0402-PAD PW R_CHG_BMON 5 PROCHOT# VDDP 20 4 G PR4471 H_PROCHOT# ISL95521AHRZ-T-GP PW R_CHG_REGN VDD PW R_CHG_REGN 084.04378.0037 VDD [24] AD_IA 074.95521.0A73 PW R_CHG_DCIN PR4438 PR4481 [24] boost_mon PW R_CHG_NTC 12 0R2J-2-GP [46] P_SYS PR4475 1 2 0R0402-PAD 6 AMON VDD 19 4D7R3F-L-GP PR4476 1 2 0R0402-PAD 2 DY 1 7 BMON U(Ps/eNb:o0m7c4.h8an87ge39.to007I3SL)8873D9CIN 18 21 21 8 PSYS 17 PC4446 PC4445 NTC SC1U10V2KX-1GP SC1U10V2KX-1GP 21 PC4402 PC4403 PC4404 PROG 12 1 21 COMP 21 CCLIM 21 FSET 1KR2F-L1-GPDY DY 33 GND BATGONE DY PR4410 AD+ 3 PR4456 PR4457 PR4411 CSON 1 R1 2R2F-GP 0R0402-PAD-1-GP SC2K2P50V2KX-L-GP CSOP 7K15R2F-L-GP PD4410 SC2K2P50V2KX-L-GP ACLIM 1 2 SC2K2P50V2KX-L-GP PR4437 R2 PQ4416 PC4463 B 2R2F-GP 12 SCD1U25V2KX-GP 2 B 9 1 LTA024EUB-FS8-GP 2 12 12 10 PW R_CHG_NTC_1 2PWR_CHG_DCIN_R 3 11 84.00024.01K 12 13 14 15 16 PWR_CHG_PROG 21 PC4435 2 PWR_CHG_DCIN_D DY DY PWR_CHG_COMP VDD PWR_CHG_FSET SC1U50V3KX-GP PQ4415 PC4461 PC4462 PWR_CHG_BATGONE DY PR4412 BAT54C-12-GP LMUN5212T1G-GP SC2K2P50V2KX-L-GP SC2K2P50V2KX-L-GP NTC-220K-1-GP-U 75.00054.A7D 84.05212.B11 21 PR4402 PR4401 2 [17,40,51] SIO_SLP_S4# B R1 C PQ4416_1 21 R2 E 200KR2F-L-GP 200KR2F-L-GP PW R_CHG_SRP CCLIM PW R_CHG_SRN ACLIM 21 PR4407100R2F-L3-GP SCD022U25V2KX-DLGP 3D3V_AUX_S5 AD+ CPU PROCHOT# Circuit 21 21 PR4431 PR4404 PR4403 21 PR4406 0R0402-PAD 1 100KR2J-1-GP 95K3R2F-GP 82K5R2F-GP 21 2 1 DY DY 12SC470P50V2KX-L-GP DY PR4409 PC4406 147KR2F-GP 21 100KR2F-L3-GP PR4405 21 PR_2PC4405 2 PR4439 1 2 PBAT_PRES# PBAT_PRES# [24,43,44] 21 100KR2F-L3-GP Need fine tune DY 1MR2J-1-GP PR4414 Battery PROCHOT# Circuit 3D3V_S5 PC4436 PD4404 E PQ4409_E SC10P50V2JN-L1-GP K A PD4404_A B DY RB551V30-GP 21 Change net name from BAT_IN# to PBAT_PRES# PD4404_K 12 H_PROCHOT# [4,24,44,46] by power team Edward 1/30 PR4459 0R0402-PAD 100KR2F-L3-GP PQ4409 PR4458 84.2N702.A3F PR4472 MMBT3906-7F-GP 0R0402-PAD 2nd = 84.DM601.03F 3rd = 84.2N702.E3F 84.03906.P11 PQ4406 4th = 84.2N702.F3F C PQ4406_3 3 4 A [24,43,44] PBAT_PRES# 12 A PQ4409_C 2 1 PQ4406_2 2 5 PQ4406_5 PC443321 PR4462 16 PC4439 SC1U10V2KX-1GP 10KR2F-L1-GP SCD47U25V3KX-1GP 0R0402-PAD BP_G 21 PR4478 21 PR4455 21DY PR4408 2N7002KDW -GP <Core Design> 100KR2J-1-GP 680KR2F-GP PQ4402 G DCBATOUT 0R2J-2-GP PQ4406_6 21 100KR2F-L3-GP D PR4413 [4,24,44,46] H_PROCHOT# PR4415 21 PWR_CHG_ACOK 1 Wistron Corporation 1 2 BP_D 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, 0R0402-PAD S PR4453 Taipei Hsien 221, Taiwan, R.O.C. 3D3V_S5 Title 2N7002K-2-GP 2 Charger 84.2N702.J31 2ND = 84.2N702.031 Size Document Number Rev 3rd = 84.07002.I31 A2 Vegas SKL/KBL-U A00 Date: Wednesday, November 08, 2017 Sheet 44 of 105 1 5 4 32

ABCDE Main Func = 3D3V_5V Vinafix.com 3D3V_AUX_S5 PR450121 4 4 0R2J-2-GP DY PR4530 PW R_5V_EN1_R PR4502 PW R_5V_EN1 DCBATOUT PW R_DCBATOUT_5V 0R0402-PAD PG4520 2 DY 1 12 21 GAP-CLOSE-PW R 0R2J-2-GP 21 PG4536 21 PR4504 GAP-CLOSE-PW R 0R0402-PAD PG4518 21 [40] 3V_5V_EN PR4503 GAP-CLOSE-PW R 0R0402-PAD PG4534 1 2 PWR_3D3V_EN2 21 GAP-CLOSE-PW R DCBATOUT PW R_DCBATOUT_3D3V PG4542 PG4525 21 21 Change PU4503 from 074.06575.0A to GAP-CLOSE-PW R 74.51225.073 by power change 2/26 PG4543 GAP-CLOSE-PW R 21 PG4521 DCBATOUT GAP-CLOSE-PW R 21 GAP-CLOSE-PW R PG4524 21 GAP-CLOSE-PW R PG4531 21 GAP-CLOSE-PW R PW R_DCBATOUT_3D3V 3 PW R_DCBATOUT_5V 3 Design Current=3.5A SC4D7U25V5KX-L2-GP SCD01U50V2KX-L-GP 5.25A<OCP>6.3A PC4509 PC4531 SC10U25V5KX-L-GP SC10U25V5KX-L-GP PC4528 PC4519 SCD1U50V3KX-GP PC4525 21 DY 21 21 21 21 1 S D8 SC10U25V5KX-L-GP 2 S D7 PC4527 3 S D6 SC4D7U25V5KX-L2-GP 4 G D5 PC4529 SCD1U50V3KX-GP PC4530 DS DS DS DG PU4504 PU4501 5 21 5V_PW R 5V_S5 6 AON7410-GP VIN 12 AON7410-GP 7 PG4527 8 21 21 GAP-CLOSE-PW R 21 PG4519 65 BOM 84.07410.A37 PU4503 84.07410.A37 65 BOM 21 PC4535 PR4528 PU4502 Design Current=6.85A GAP-CLOSE-PW R AON7506-GP 10.275A<OCP>12.33A PG4538 3D3V_S5 3D3V_PW R 2 1PWR_3D3V_VBST2_11 2 PWR_3D3V_VBST2 PC4516 2 65 BOM 5V_PW R 21 1D5R3-GP 9 VBST2 17 PW R_5V_VBST1 PR4524 PWR_5V_VBST1_1 1 2 4 GAP-CLOSE-PW R 2 16 PW R_5V_DRVH1 12 43 PG4537 PG4526 18 PW R_5V_LL1 2 1 15 PW R_5V_DRVL1 1D5R3-GP 1 21 GAP-CLOSE-PW R SCD1U50V3KX-GP VBST1 PG4533 DRVH1 3D3V_PW R PL4502 PWR_3D3V_DRVH2 10 DRVH2 SCD1U50V3KX-GP PL4501 21 SW 1 12 GAP-CLOSE-PW R GAP-CLOSE-PW R 12 PW R_3D3V_LL2 8 SW2 DRVL1 IND-2D2UH-46-GP-U1 PG4517 21 PWR_3D3V_DRVL2 11 DRVL2 68.2R210.20B 1 D8 D7 PR4529 IND-3D3UH-57-GP-U D6 1 68.3R310.20A D5 DY 2D2R5F-2-GP GAP-CLOSE-PW R DY 5 PG4532 PC4518 PG4528 PR4533 14 PW R_5V_VO1 36 GAP-CLOSE-PWR-3-GP 21 PC4517 PT4502 PG4535 2D2R5F-2-GP 2 PW R_5V_FB1 27 DS DY 21 3V_FEEDBACK 2 1 VO1 18 DS 21 21 SCD1U16V2KX-3GP PU4505 PW R_3D3V_FB2 4 VFB2 VFB1 DS SCD1U16V2KX-3GP D 21 65 BOM 21 GAP-CLOSE-PW R DY AON7410-GP G 1PWR_5V_SNUB 2 PT4501 PG4522 SC330P50V2KX-3GP 21 PC4520 79.22710.3KLSE220U6D3VM-38-GP GAP-CLOSE-PW R PWR_3D3V_SNUB21 PR4517 change to 127K PWR_3D3V_EN2 6 EN2 EN1 20 PWR_5V_EN1 84.07506.037 PG4523 PG4529 1S by PWR team Jerry 21 GAP-CLOSE-PWR-3-GP 2S 21 SE220U6D3VM-38-GP 3S PWR_3D3V_CS2 5 CS2 CS1 1 PW R_5V_CS1 GAP-CLOSE-PW R GAP-CLOSE-PW R 4G PG4541 21 TP4501 21 21 79.22710.3KL DY 84.07410.A37 PR4517 TPS51225RUKR-GP TPAD14-OP-GP PR4531 GAP-CLOSE-PW R 127KR2F-L-GP PWR_5V_VCLK 1 127KR2F-L-GP PG4540 74.51225.07V3CLK 19 21 DY PC4536 SC560P50V-GP 7 PGOOD GND 21 2 2 3 VREG3 GAP-CLOSE-PW R 2 13 VREG5 PG4545 21 PR4512 21 2 12 1 PR4535 3D3V_PW R_2 PR4531 change to 127K PR45252 12 1 GAP-CLOSE-PW R 6K65R2F-GP PC4526 by PWR team Jerry 12 1 PG4544 DY0R2J-2-GP 0R2J-2-GP DY 21 100KR2J-1-GP3D3V_S5 SC4D7U6D3V3KX-GP 5V_PW R_2 PR4527 GAP-CLOSE-PW R PW R_3D3V_FB2_R 21PR4534 PC4524 PW R_5V_FB1_R 15K4R2F-GP PC4523 21 SC1U50V3KX-GP DY 21 PC4522 DY 20170810 DYSC18P50V2JN-1-GP 5V output voltage modify SC18P50V2JN-1-GP 21 PR4523 [17,21,40,53,54] 3V_5V_POK PR4526 10KR2F-L1-GP 10KR2F-2-GP PH at Page17 3D3V_PW R_2 3D3V_AUX_S5 2 12 Close to VFB Pin (pin2) PR4505 Close to VFB Pin (pin5) 0R0402-PAD I/P cap: CHIP CAP C 10U 25V K0805 X5R/ 78.10622.51L I/P cap: CHIP CAP C 10U 25V K0805 X5R/ 78.10622.51L 1 Inductor: CHIP IND 3.3UH PCMC063T-3R3MN Cyntec 28mohm/30mohm Isat =13.5Arms 68.3R310.20A Inductor: CHIP CHOKE 2.2U PCMC063T-2R2MN 18mohm/20mohm Isat =14Arms 68.2R210.20B O/P capCHIP CAP EL 220U 6.3V M6.3*4.4 /Chemi-con/ 18mOhm / 79.22710.3KL O/P capCHIP CAP EL 220U 6.3V M6.3*4.4 /Chemi-con/ 18mOhm / 79.22710.3KL 1 H/S:SIS412 / 24mOhm/[email protected] / 84.00412.037 H/S:SIS412 / 24mOhm/[email protected] / 84.00412.037 L/S:SIS412 / 24mOhm/[email protected] / 84.00412.037 L/S:SIS780 / 14.5mOhm/[email protected] / 84.00780.037 AB <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title DCDC-3D3V&5V Size Document Number Rev A2 Vegas SKL/KBL-U A00 Date: Wednesday, November 08, 2017 Sheet 45 of 105 C DE

54321 Main Func = CPU_CORE +VCCST_CPU https://shop62935598.taobao.com +VCCST_CPU 1 PR4604 PC4602 1PR4605 SCD1U25V2KX-GP 20170427 PR4603 1PR4606 DY Vinafix.com DY 1KR2F-L1-GP 21 VR_SVID_CLK [7] D PR460721 2 VR_SVID_ALERT# [7] D 100R2F-L3-GP 2 VR_SVID_DATA [7] C 12 2 B PR4608 [4,24,44] H_PROCHOT# 90K9R2F-GP 100R2F-L3-GP 21 PC4603 1 U42 2 75R2F-2-GP 1SCD1U25V2KX-GP 45D3R2F-L-GP PR4672 DCBATOUT 5V_S5 PWR_VCCSA_ISUMN [50] 88K7R2F-GP 1 U22 2 PC4604 21 0R0402-PAD-1-GP 1R2J-GP 21 21DY PR4613 PR4611 SC330P50V2KX-3-DL-GP 3D3V_S0 21PR4612 PR4610 PR4615 NTC-10K-29-GP-U 12 0R2J-L-GP DY 1KR2F-L1-GP 20170810 PBl=a3c9e4n0eKar high side MOSFET of Phase1 20170810 21 PR4622 12 BPl=a3c3e7n0eKar Phase1 choke New Common Part IA VRHot 21 PR4623 PR4620 21 PR4624 392R2F-GP PR4616 21 5K76R2F-2-GP PR4609 PR4618 22 21 11KR2F-L-GP PW R_VCCGT_NTC1 DY 10KR2F-L1-GP PWR_VCCSA_ISUMN_RC 21 PC4605 PW R_VCCSA_ISUMN_P_1 PW R_VCCSA_ISUMN_P_2 SCD068U25V2KX-GP PR4617 1 2 NTC-470K-9-GP-U AFTP4601 1 VR_RDY 21 PR4621 1 2 27K4R2F-GP 21 SCD22U25V3KX-GP SC1U10V2KX-1GP 12DY PC4608 PR4625 21PC4606 PC4607 SCD033U25V2KX-GP 2K61R2F-1-GP PC4610 1 2 SC33P50V2JN-3GP [40] VR_EN 10R2F-L1-GP 0R0402-PAD-1-GP PC4651 2 1 SC1KP50V2KX-L-1-GP PR4626 49D9R2F-L1-GP 1 PC4612 2 1 SC2K2P50V2KX-L-GP 3K3R2F-2-GP PW R_VCCGT_COMP1 12 PC4613 PWR_VCCSA_ISUMP [50] 12 SCD01U50V2KX-L-GP DY PC4611 12 0707 Modify by PWR Jerry PWR_VCORE_VRHOT# SC2K2P50V2KX-L-GP PWR_VCORE_SCLK PC4661 2U42 1 SC470P50V2KX-3GP PWR_VCORE_ALERT# 21 PR4628 PR4629 PR4627 1 DY 2 PC4614 2U22 1 SC330P50V2KX-3GP PR4630 PWR_VCORE_SDIO 21 88K7R2F-GP 2 0R0402-PAD-1-GP PW R_VCCGT_FB1 2KR2F-L1-GP 0517 Modify PWR_VCORE_VCC 9K31R2F-GP 100R2F-L3-GP VSSSA_SENSE [7] 12 [44] P_SYS PWR_VCORE_VIN PR4602 1 VCCSA_SENSE [7] PWR_VCORE_PROG1 C 21DY PC4615 PR4671 1U22 2 1K54R2F-GP PWR_VCORE_PROG2 20170811 21DY PC4616 SA compensation SCD01U50V2KX-L-GP SC1KP50V2KX-L-1-GP PR4614 PR4632 PC4617 PR4601 1 PR4633 1U42 2 3K01R2F-3-GP 1 DY 2 1KR2F-3-GP SC1KP50V2KX-L-1-GP PR4631 1 DY 2 PR4636 2 1 PWR_VCCSA_FB_RC 1 2 PWR_VCCSA_FB2 2 0R0402-PAD-1-GP VCC_CORE 0R2J-L-GP 40 100R2F-L3-GP PU4601 39 38 37 36 35 34 33 32 31 PR4665 PW R_VCCGT_FB2 499R2F-2-GP VR_ENABLE 21 12 PC4618 1U22 2 PWR_VCCGT_FB_RC 1 2 VR_READY PR4637 DY PC4620 [7] VCC_SENSE 1K69R2F-2-GP SC1KP50V2KX-L-1-GP VR_HOT# 12 SCD01U50V2KX-L-GP 0R0402-PAD-1-GP 1 SCLK 30 PR4666 21DY PC4619 PC4662 1U42 2 PW R_VCCGT_IMON 2 PSYS PW M_C 29 PW R_VCCSA_ISUMNB PWR_VCCSA_PWM [50] 0R0402-PAD-1-GP PW R_VCCGT_NTC 3 IMON_B ALERT# FCCM_C 28 PW R_VCCSA_ISUMP PWR_VCCSA_FCCM [50] 12 SC1KP50V2KX-L-1-GP SC220P50V2KX-3GP PW R_VCCGT_COMP 4 NTC_B SDA ISUMN_C 27 PW R_VCCSA_RTN 0707 Modify by PWR Jerry PW R_VCCGT_FB 5 COMP_B VCC ISUMP_C 26 PW R_VCCSA_FB PWR_VCORE_PWM [47] PW R_VCCGT_RTN 6 FB_B VIN 25 PW R_VCCSA_COMP PWR_VCORE_FCCM# [47] PW R_VCCGT_ISUMP 7 RTN_B RTN_C 24 PW R_VCCSA_IMON PW R_VCCGT_ISUMNB 8 ISUMP_B PROG1 FB_C 23 PW R_VCCGT_ISEN1 9 ISUMN_B PROG2 22 PW R_VCCGT_ISEN2 10 ISEN1_B COMP_C 21 [7] VSS_SENSE ISEN2_B IMON_C PR4638 PW R_VCCSA_FB1 PC4621 PW M_A 2KR2F-L1-GP SC680P50V2KX-2GP FCCM_A 2 DY 1 2 D1Y PR4639 1 DY 2 PR4669 1 DY 2 0R2J-L-GP 100R2F-L3-GP PR4640 PC4601 2K49R2F-2-L-GP SC2200P50V2KX-2DLGP PC4622 2 1 1 2 PWR_VCCSA_COMP_RC 1 2 12 FCCM_B SCD01U50V2KX-L-GP 21PC4623 20170810 5V_S5 PWM1_B 21SC2K2P50V2KX-L-GP IA OCP 41 GND PWM2_B 20170811 21 IMON_A SA compensation PC4624 20170810 SCD022U25V2KX-DLGP NTC_A 20170811 IA RC time constant PC4626 COMP_A SC33P50V2JN-3GP SA compensation SCD022U25V2KX-DLGP FB_A 12 U22 U42 PC4625 RTN_A ISUMP_A ISUMN_A [48] PWR_VCCGT_ISUMP PWR_VCCGT_ISUMN_RC PR4642 PR4670 PR4635 21 11 ISL95859AHRTZ-T-GP PR4641 324R2F-GP 267R2F-1-GP 1KR2F-L1-GP U42 21 U42 12 13 074.95859.0B33 2K61R2F-1-GP 14 15 16 17 18 19 20 12 1 SCD01U50V2KX-L-GP2121 21 SCD047U25V2KX-GP U42 U22 U22 PC4629 PC4609 PC4653 SC330P50V2KX-3-DL-GP SCD033U25V2KX-GP PWR_VCORE_IMON 11KR2F-L-GP PC4628 PWR_VCORE_NTC 21 PR4643 PWR_VCORE_COMP PW R_VCCGT_ISUMN_P_2 21 21 SCD1U25V2KX-GP PWR_VCORE_FB 20170810 PC4630 PWR_VCORE_RTN PR4644 New Common Part PWR_VCORE_ISUMP 12 PWR_VCORE_ISUMNA PR4646 2 PW R_VCCGT_ISUMN_P_1 21 PR4645 1KR2F-L1-GP 20170810 113KR2F-1-GP GT OCP PWR_VCORE_ISUMN [47] NTC-10K-29-GP-U PR4647 2 274R2F-GP PR4648 1 PR4650 NTC-10K-29-GP-U BPl=a3c3e7n0eKar Phase1 choke 0R0402-PAD-1-GP 12 PR4649 1 BPl=a3c3e7n0eKar Phase1 choke B 2 11KR2F-L-GP21PC463112 21 SCD022U25V2KX-DLGPSCD1U25V2KX-GP PW R_VCORE_ISUMN_P_2 PC4632 PR4651 PC4635 PR4652 [48] PWR_VCCGT_ISUMN 1 SC2K2P50V2KX-L-GP 1KR2F-L1-GP 2 1PWR_VCORE_ISUMN_RC 12 0R0402-PAD-1-GP [48] PWR_VCCGT_FCCM# SCD022U25V2KX-DLGP PC4633 [48] PWR_VCCGT_PWMA PW R_VCORE_ISUMN_P_1 PC4652 22 SCD1U25V2KX-GP [48] PWR_VCCGT_PWMB SCD1U25V2KX-GP PC4634 20170810 20170810 21 21DY 21 PR4653 GT VRHot GT compensation 2K61R2F-1-GP [48] PWR_VCCGT_ISEN1 21 PR4662 PR4656 21 PWR_VCORE_ISUMP [47] 214K75R2F-1-GP 2K87R2F-1-GP 1 PR4658 PWR_VCORE_COMP1 499R2F-2-GP 1 21 21 PWR_VCORE_FB_RC [48] PWR_VCCGT_ISEN2 PR4657 PC4637 2KR2F-L1-GP SCD01U50V2KX-L-GP 20170810 12 GT RC time constant PC4639 SC33P50V2JN-3GP U22 U42 PWR_VCORE_FB1 20170810 PR4659 1 DY 2 GT load line PC4625 DY PC4625 0.022u(78.22321.2FL) PW R_VCORE_NTC1 100R2F-L3-GP PR4668 PR4660 0R0402-PAD-1-GP 20170810 1K91R2F-1-GP 21 New Common Part PWR_VCORE_FB2 VSSGT_SENSE [7] PC4626 DY PC4626 0.022u(78.22321.2FL) 21 PR466121 21 VCCGT_SENSE [7] PC4638 20170810 21 GT IMON 12 21 SC330P50V2KX-3-DL-GP 27K4R2F-GP 21PC4641 DY PC4642 PR4669 DY PR4669 DY NTC-470K-9-GP-U PC4640 2SC330P50V2KX-3-DL-GP PC4643 PR4667 PR4654 SC1KP50V2KX-L-1-GP 0R0402-PAD-1-GP 88K7R2F-GP 21 21 PR4655 SC4700P50V2KX-1DLGP SC1KP50V2KX-L-1-GP PR4635 1K(64.10015.6DL) PR4635 DY 20170811 20170810 GT compensation New Common Part PR4663 1 DY 2 +VCCGT PR4670 267(64.26705.6DL) PR4642 316(64.31605.6DL) 100R2F-L3-GP PC4630 0.1u(78.10422.5FL) PC4630 0.1u(78.10422.5FL) PC4644 1 D2Y SCD01U50V2KX-L-GP A PC4609 0.01u(78.10324.L0L) PC4628 0.022u(78.22322.2FL) BPl=a3c9e4n0eKar high side MOSFET of Phase1 A PC4653 DY PC4653 47n(78.47322.2FL) PR4671 1.54K(64.15415.6DL) PR4633 3.01K(64.30115.6DL) <Core Design> PR4672 88.7K(64.88725.6DL) PR4608 90.9K(64.90925.6DL) Wistron Corporation PC4614 330p(78.33124.2FL) PC4661 470p(78.47124.2FL) 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. PC4618 1000p(78.10224.2FL) PC4662 220p(78.22124.2FL) Title NCP81208MN_CPU_VCORE(1/3) Size DocumentVNuemgbear s SKL/KBL-R Rev A2 A00 Date: Wednesday, November 08, 2017 Sheet 46 of 105 1 5432

54 3 2 1 D Main Func = CPU_CORE 20170427 DCBATOUT PW R_DCBATOUT_VCORE PG4701 Vinafix.com 12 PW R_DCBATOUT_VCORE GAP-CLOSE-PW R-3-GP D PG4702 12 GAP-CLOSE-PW R-3-GP PC4704 PG4703 PC4703 12 PC4702 PC4701 21 21 21 21 DY DY GAP-CLOSE-PW R-3-GP PG4704 12 GAP-CLOSE-PW R-3-GP SC10U25V5KX-L-GP PG4705 SC10U25V5KX-L-GP 12 SC10U25V5KX-L-GP SC10U25V5KX-L-GP GAP-CLOSE-PW R-3-GP PG4706 12 GAP-CLOSE-PW R-3-GP PR4706 PR4702 PW R_VCORE_PW M [46] 12 12 PW R_VCORE_BOOT_RC 0R0402-PAD [46] PW R_VCORE_FCCM# 0R0402-PAD 21 C 5V_S5 21 C PR4704 21 2D2R2F-GP PR4712 PR4705 PC4707 12 5K11R2F-L1-GP 2D2R3F-L-GP SCD22U25V3KX-GP 21 SC1U10V2KX-1GP PU4701 PC4708 PW R_VCORE_FCCM#_R 1 SKIP# PWM 8 PW R_VCORE_PW M_R SKL_U22_15W PW R_VCORE_VCC_R 2 VDD BOOT 7 PW R_VCORE_BOOT Icc(max)=29A 3 PGND BOOT_R 6 PW R_VCORE_BOOTR TDC=21A PW R_VCORE_SW 4 VSW 5 VIN 9 PW R_DCBATOUT_VCORE PGND Confirm with EE CSD97396Q4M-GP 22uF/0805 total 33pcs (78.22610.L2L) 074.97396.0043 PL4701 Cyntec. 6.8mm x6.4mmx4.0mm+VCCGT COIL-D15UH-2-GP DCR: 0.66m Ohm +/-7% PW R_VCORE_SW 1 2 Idc : 26A , Isat : 52A 68.R1510.20A 21 2 1DY PR4703 12 12 21 PT4701 2D2R6J-3-GP SE330U2VDM-4-GP PANASONIC B PG4707 PG4708 ESR: 9 mohm B GAP-CLOSE-PW R-3-GP GAP-CLOSE-PW R-3-GP PW R_VCORE_SNB DY PC4706 PW R_VCORE_ISUMP_G PW R_VCORE_ISUMN_G SC1KP50V2KX-L-1-GP 21 21 PR4701 0R0402-PAD PR4708 3K65R2F-1-GP [46] PW R_VCORE_ISUMP [46] PW R_VCORE_ISUMN A <Core Design> A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title NCP81382MN_CPU_VCORE(2/3) Size Document VNuembgeras SKL/KBL-R Rev A3 A00 Date: W ednesday, November 08, 2017 Sheet 47 of 105 1 5432

54321 Main Func = CPU_CORE 20170427 DCBATOUT PW R_DCBATOUT_VCCGTA PW R_DCBATOUT_VCCGTA PG4802 GAP-CLOSE-PW R-3-GP 2 VDYinafiDxY .com 1 PC4805 PG4803 PC4804 2 GAP-CLOSE-PW R-3-GP PC4803 1 PC4802 21 DCBATOUT 21 21 21 D PG4804 GAP-CLOSE-PW R-3-GP 21 D 21 SC10U25V5KX-L-GP 21PT4805PT4806 C SC10U25V5KX-L-GP SC10U25V5KX-L-GP SKL_U22_15W ST100U25VDM-1-GP SE33U25VM-11-GP SC10U25V5KX-L-GP Icc(max)=31A PG4805 GAP-CLOSE-PW R-3-GP TDC=18A 2 1 Confirm with EE 22uF/0805 total 36pcs PG4806 GAP-CLOSE-PW R-3-GP (78.22610.L2L) 0920 Change acoustic solution 2 1 1101 Change acoustic solution PR4802 PWR_VCCGT_PWMA [46] For acoustic noice 12 PW R_VCCGT_BOOTA_RC 0R0402-PAD PR4806 PWR_VCCGT_PWMA_RA [46,48] PWR_VCCGT_FCCM# 12 21 0R0402-PAD 21 5V_S5 212D2R3F-L-GP PR4804 21 2 1 21 2 15K11R2F-L1-GPPC4808 Cyntec. 6.8mm x6.4mmx4.0mm VCC_CORE 21PR4817SCD22U25V3KX-GPDCR: 0.66m Ohm +/-7% PR4803 Idc : 26A , Isat : 52A 2D2R2F-GP PU4801 PL4801 PWR_VCCGT_FCCM#_RA 1 SKIP# PW M 8 COIL-D15UH-2-GP PWR_VCCGT_VCCDA 2 VDD BOOT 7 PW R_VCCGT_BOOTA 12 3 PGND BOOT_R 6 PW R_VCCGT_BOOTRA SC1U10V2KX-1GP PW R_VCCGT_SW A 4 VSW 5 68.R1510.20A PC4809 VIN 9 PW R_DCBATOUT_VCCGTA PGND CSD97396Q4M-GP DY PR4805 PG4808 21 PT4801 GAP-CLOSE-PW R-3-GP 21 SE330U2VDM-4-GP 074.97396.0043 2D2R6J-3-GP PG4809 PW R_VCCGT_SNB1 GAP-CLOSE-PW R-3-GP PANASONIC ESR: 9 mohm C DY PC4810 SC1KP50V2KX-L-1-GP PW R_VCCGT_ISUMP_GA PW R_VCCGT_ISUMN_GA [46,48] PWR_VCCGT_ISEN1 PR4821 1U42 2 [46,48] PWR_VCCGT_ISUMP [46,48] PWR_VCCGT_ISUMN 100KR2F-L3-GP 21 21 PR4808 1 2 PR4809 DY PR4822 3K65R2F-1-GP 10R2F-L1-GP 100KR2F-L3-GP DCBATOUT PW R_DCBATOUT_VCCGTB [46,48] PWR_VCCGT_ISEN2 PG4810 GAP-CLOSE-PW R-3-GP 2 PW R_DCBATOUT_VCCGTB 1 PG4816 21 2 GAP-CLOSE-PW R-3-GP 21 1 21 21 PC4816 PC4817 PC4814 PC4815 U42 U42 U42 U42 SC10U25V5KX-L-GP PG4811 GAP-CLOSE-PW R-3-GP SC10U25V5KX-L-GP 2 1 SC10U25V5KX-L-GP SC10U25V5KX-L-GP PG4812 GAP-CLOSE-PW R-3-GP 2 1 PG4814 GAP-CLOSE-PW R-3-GP B 21 B PR4811 PWR_VCCGT_PWMB [46] 12 PW R_VCCGT_BOOTB_RC 0R0402-PAD PR4812 PWR_VCCGT_PWMB_RA [46,48] PWR_VCCGT_FCCM# 1 2 0R0402-PAD 21 21 5V_S521 2 1 21PR4818PR4810U42 PC4811 Cyntec. 6.8mm x6.4mmx4.0mm VCC_CORE 5K11R2F-L1-GP 2D2R3F-L-GP DCR: 0.66m Ohm +/-7% U42 PR48132D2R2F-GP SC1U10V2KX-1GP 21 2 1SCD22U25V3KX-GP Idc : 26A , Isat : 52A U42 21U42U42 PL4802 PU4802 COIL-D15UH-2-GP PWR_VCCGT_FCCM#_RB 1 SKIP# PW M 8 1 U42 2 PWR_VCCGT_VCCDB 2 VDD 7 PW R_VCCGT_BOOTB 3 PGND BOOT 6 PW R_VCCGT_BOOTRB 4 VSW BOOT_R 5 PC4812 PW R_VCCGT_SW B U42 VIN 9 PW R_DCBATOUT_VCCGTB PGND CSD97396Q4M-GP DY PR4814 21 U42 21 074.97396.0043 2D2R6J-3-GP PT4803 PW R_VCCGT_SNB2 SE330U2VDM-4-GP PG4813 PG4815 GAP-CLOSE-PW R-3-GP GAP-CLOSE-PW R-3-GP DY PC4813 SC1KP50V2KX-L-1-GP PW R_VCCGT_ISUMP_GB PW R_VCCGT_ISUMN_GB [46,48] PWR_VCCGT_ISEN2 PR4823 1U42 2 [46,48] PWR_VCCGT_ISUMP 100KR2F-L3-GP A A 5 PR4816 1U42 2 21 21 3K65R2F-1-GP U42 PR4815 DY PR4824 10R2F-L1-GP 100KR2F-L3-GP <Core Design> [46,48] PWR_VCCGT_ISUMN Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. [46,48] PWR_VCCGT_ISEN1 Title NCP81382MN_CPU_VCCGT(3/3) Size DocumentVNuemgbear s SKL/KBL-R Rev A2 A00 Date: Wednesday, November 08, 2017 Sheet 48 of 105 4321

5 4 32 1 Main Func = CPU_CORE Vinafix.com DCBATOUT PW R_DCBATOUT_VCCSA 20170427 PG5002 D GAP-CLOSE-PW R-3-GP C D 21 B PG5003 GAP-CLOSE-PW R-3-GP 21 PW R_DCBATOUT_VCCSA SKL_U22_15W Icc(max)=4.5A 45 PC5002 DY PC5003 PC5004 TDC=3.7A 36 Confirm with EE 27 22uF/0805 total 6pcs 18 (78.22610.L2L) 21 21 21 SCD1U25V2KX-GPPU5002 SC10U25V5KX-L-GPAON7410-GP SC10U25V5KX-L-GP PW R_VCCSA_BST_RC C DS DS DS Cyntec. 7.3mm x6.8mm x3.0mm DG DCR: 4.0~4.2 mohm Idc : 17.5A , Isat : 26A 21 PR5001 21 PC5005 2D2R3F-L-GP SCD22U25V3KX-GP PU5001 PL5001 +VCCSA PW R_VCCSA_DRVH 1 UGATE PHASE 8 PW R_VCCSA_SW 12 PW R_VCCSA_BST 2 BOOT FCCM 7 PW R_VCCSA_FCCM [46] IND-D47UH-22-GP-U 3 PWM 6 [46] PW R_VCCSA_PW M 4 GND VCC 5 5V_S5 LGATE 9 21 45 PU5003 GND 36 AON7410-GP PC5001 27 PWR_VCCSA_ISUMP_R SC2D2U10V3KX-L-GP 18 12 12 DS ISL95808HRZ-T-1-GP DS PG5011 PG5001 DS GAP-CLOSE-PW R-3-GP GAP-CLOSE-PW R-3-GP 074.95808.0B73 DG If no need support PS4 mode PW R_VCCSA_DRVL PWR_VCCSA_ISUMN_R please change to ISL6208C 74.06208.B73 B 21 PR5003 21 PR5004 3K65R2F-1-GP 0R0402-PAD [46] PW R_VCCSA_ISUMP [46] PW R_VCCSA_ISUMN A <Core Design> A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title NCP81253MN_CPU_VCCSA Size Document Number Rev A3 Vegas SKL/KBL-R A00 Date: W ednesday, November 08, 2017 Sheet 50 of 105 54321

54321 SSID = PWR.Plane.Regulator_1p2v& 2D5V DCBATOUT PW R_DCBATOUT_VDDQ Vinafix.com VID PG5117 Logic-High = 0.75V GAP-CLOSE-PW R-3-GP Logic-Low = 0.6V 12 D PG5118 PW R_VDDQ_VID PR5107 5V_S5 D GAP-CLOSE-PW R-3-GP 5D1R2F-GP C 12 12 21 PC5102 PW R_DCBATOUT_VDDQ PW R_1D2V 1D2V_S3 SC1U10V2KX-1GP PG5119 GAP-CLOSE-PW R-3-GP 12 0620 Change Res value PR5109 5 PG5120 by PWR team Jerry 0R0402-PAD-1-GP 6 GAP-CLOSE-PW R-3-GP 1 2 5V_S5 7 12 OCP setting 8 PW R_VDDQ_CS 21 21 21 PW R_VDDQ_VDD DY PC5103 PC5104 PC5105 SCD1U25V2KX-GP 3D3V_S521 21 PR5114 CS 13 PC5107 SC4D7U25V5KX-L2-GP PG5121 PR5111 255KR2F-GP VID 11 SC1U10V2KX-1GP SC4D7U25V5KX-L2-GP GAP-CLOSE-PW R-3-GP VDD 12 12 DY 10KR2F-L1-GP PU5102 DS 21 AON7410-GP DS DS PG5122 84.07410.A37 65 BOM DG GAP-CLOSE-PW R-3-GP 12 PU5101 RT8231AGQW -GP [40] PWR_VDDQ_PG 4 074.08231.0073 3 2 BOOT 18 PWR_VDDQ_BOOT 1 UGATE 17 PWR_VDDQ_HG Freq. setting PW R_DCBATOUT_VDDQ PW R_VDDQ_PG PR5112 PW R_VDDQ_BOOT_A PC5108 PG5123 750K -> 350K Hz PR5113 PW R_VDDQ_TON PHASE 16 PWR_VDDQ_PH 2D2R3F-L-GP SCD1U50V3KX-GP GAP-CLOSE-PW R-3-GP 750KR2F-L-GP PW R_VDDQ_EN 12 12 12 PW R_VTT_EN LGATE 15 PWR_VDDQ_LG 12 PW R_VDDQ_VLDOIN PC5109 10 PGOOD DCR=5~5.5mohm Design Current=6.9A PW R_1D2V PG5124 SC10U6D3V3MX-GP 9 TON IDC=15.5A, Isat=25A 10.4A<OCP>13.8A GAP-CLOSE-PW R-3-GP 8 S5 12 7 S3 PL5101 PG5115 COIL-D68UH-5-GP-U GAP-CLOSE-PW R-3-GP 19 VLDOIN 12 12 PG5116 1D2V_S3 GAP-CLOSE-PW R-3-GP 5 PC5110 PC5111 PC5112 PC5113 PC5114 PG5127 12 36 GAP-CLOSE-PW R-3-GP 21 27 DY 12 18 Close to output cap pin1, not 21 2 1PR5120 PG5125 inside of the output cap GAP-CLOSE-PW R-3-GP 21DY 2D2R5F-2-GP 12 21 1 VTTGND PGND 14 PU5105 DS 21 AON7506-GP DS 21 C DS 21 D PW R_VDDQ_SNUB PG5101 PW R_VDDQ_VTT G PW R_VDDQ_VDDQ GAP-CLOSE-PW R-3-GP 4 65 BOM VDDQ 5 12 DY PC5120 PG5126 2D5V_PWROK PR5128 1 2 0R0402-PAD PWR_VDDQ_EN PW R_1D2V GAP-CLOSE-PW R-3-GP SC2200P50V2KX-2GP SC22U6D3V3MX-1-DL-GP 20170810 12 20 VTT FB 6 PW R_VDDQ_FB 84.07506.037 SC22U6D3V3MX-1-DL-GP New Common Part 21 2 VTTSNS SC22U6D3V3MX-1-DL-GP DY PC5106 4 VTTREF R1 DY SC22U6D3V3MX-1-DL-GP PG5128 SC22U6D3V3MX-1-DL-GP GAP-CLOSE-PW R-3-GP SCD1U16V2KX-3GP 12 GND GND S5 PC5115 21 21 PR5116 SC18P50V2JN-1-GP 15K8R2F-GP 21 PG5129 3 GAP-CLOSE-PW R-3-GP 12 1 PWR_VDDQ_VTTREF [17,24,27,40] SIO_SLP_S3# PR5126 1 DY 2 0R2J-2-GP PW R_VTT_EN PR5116 from 12.1Kohm change to 15.8Kohm(64.15825.6DL) to setting VDDQ =1.2V PG5130 [5] SM_PGCNTL_R PR5127 1 Due to pin 11 VID is pull high, Vref. should be 0.675V GAP-CLOSE-PW R-3-GP 2 0R0402-PAD S3 by power team Edward 1/30 12 21 R2 PC5116 PR5117 20KR2F-L3-GP 2 Vout Setting Vout = Vref * ( 1 + R1/R2 ) = 0.675 * ( 1 + 12.1K / 20K) = 1.2V Vout = 0.6V VID vs Vref Table Iomax = 1.2A VID Logic-High => Vref = 0.675 V VID Logic-Low => Vref = 0.75 V note. Vref can only be changed form 0.675v to 0.75v after power-on B B PW R_VDDQ_VTT PG5113 0D6V_S0 GAP-CLOSE-PW R-3-GP 21 PG5114 GAP-CLOSE-PW R-3-GP DY 2 1 21 SC10U6D3V3MX-GP 21 PC5117 SC10U6D3V3MX-GP PC5118 APL5930 for VPP_2D5V 5V_S5 3D3V_S5 3D3V_S5 Design Current = 700mA 21 21 SC10U6D3V3MX-GP 21 PC5152 PR5155 PC5156 2D5V_PW R 10KR2F-L1-GP SC1U50V3KX-GP 20170810 EE needs check sequence control PU5151 DY New Common Part 2D5V_PW R 2D5V_S3 2D5V_PWROK PR5158 1 2 0R0402-PAD PW R_2D5V_POK 6 VCNTL VIN#5 5 12 1 PG5151 1 2 GAP-CLOSE-PWR PR5153 1 2 0R0402-PAD PW R_2D5V_EN 7 POK VOUT#4 4 21 SC22U6D3V3MX-1-DL-GP PG5152 1 2 GAP-CLOSE-PWR 8 EN VOUT#3 3 21 PC5154 [17,40,44] SIO_SLP_S4# 9 VIN#9 2 PWR_2D5V_FB SC68P50V2JN-1GP FB 1 PC5153 GND 43K2R2F-L-GP A DY21 DY APL5930KAI-TRG-GP PR5151 A PR5152 PC5155 74.05930.03D 47KR2J-2-GP 2ND = 74.G9731.03D SC4700P50V2KX-1GP 21 PR5154 <Core Design> 20KR2F-L3-GP SCD047U25V2KX-GP Vout=0.8V*(R1+R2)/R2 2 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title RT8231_VDDQ/VTT Size DocumentVNuemgbear s SKL/KBL-U Rev A2 A00 Date: Wednesday, November 08, 2017 Sheet 51 of 105 54321

54321 SSID = PWR.Plane.Regulator_1p0v Vinafix.com D D DCBATOUT PW R_DCBATOUT_1D0V PG5301 AOZ2262 for 1D0V GAP-CLOSE-PW R-3-GP 12 PG5302 PW R_1D0V 1D0V_S5 GAP-CLOSE-PW R-3-GP 5V_S5 PG5304 12 PG5303 GAP-CLOSE-PW R-3-GP GAP-CLOSE-PW R-3-GP 12 12 DCR=5~5.5mohm IDC=15.5A, Isat=25A C PW R_DCBATOUT_1D0V PL5301 SC4D7U25V5KX-L2-GP21 PU5301 COIL-1UH-34-GP-U1 PW R_1D0V PG5305 PC5302 21 VCC GAP-CLOSE-PW R-3-GP 18 PW R_1D0V_PH 12 design current : 8.92A C SC10U25V5KX-L-GP 17 12 PC5310 LX#18 16 PC5304 68.1R01A.20B SC10U25V5KX-L-GP LX#17 11 SCD1U25V2KX-GP PG5306 PC5309 LX#16 10 21 GAP-CLOSE-PW R-3-GP SCD1U25V2KX-GP LX#11 20 21 2 1 PC5308 LX#10 5 12 BST PC5306 FB PC5307 PC5305 PC5303 PC5301 7 12 21 DY PG5307 8 21 GAP-CLOSE-PW R-3-GP 9 IN#7 21 12 6 IN#8 PW R_1D0V_BT DY PR5309 PG5310 21 IN#9 PW R_1D0V_VFB 2D2R5F-2-GP GAP-CLOSE-PW R-3-GP 21 21 PR5301 TON PW R_1D0V_SNUB PW R_1D0V_VFB_A SC22U6D3V3MX-1-DL-GP 20170810 PG5308 21 95K3R2F-GP PGOOD SC22U6D3V3MX-1-DL-GP New Common Part GAP-CLOSE-PW R-3-GP 21 1 2 PWR_1D0V_TON EN SC22U6D3V3MX-1-DL-GP PFM# SC22U6D3V3MX-1-DL-GP 12 PWR_1D0V_PG 1 SS AGND 4 SC22U6D3V3MX-1-DL-GP PGND 19 PG5309 PW R_1D0V_EN 2 PGND 14 DY PC5315 12 1 2K55R2F-GP SC220P50V2KX-3GP GAP-CLOSE-PW R-3-GP PGND 13 SC2200P50V2KX-2GP 21PR5302 PC5312 PGND 12 12 PWR_1D0V_PFM 3 PGND 15 R1 DY PG5311 PW R_1D0V_SS 22 GAP-CLOSE-PW R-3-GP 12 PR530321 AOZ2262QI-10-GP-U Vo=0.8x(1+R1/R2) R2 10KR2F-L1-GP PG5312 100KR2F-L3-GP 21 =0.8x(1+7.5/30) PR5304 GAP-CLOSE-PW R-3-GP PC5313 074.02262.0043 =1.00 SCD01U50V2KX-L-GP 12 2 PG5313 GAP-CLOSE-PW R-3-GP 5V_S5 12 B 21 PG5314 B GAP-CLOSE-PW R-3-GP DY PR5308 12 100KR2J-1-GP [40] 1D0V_S5_PW RGD PR5305 1 2 PW R_1D0V_PG 0R0402-PAD [17,21,40,45,54] 3V_5V_POK PR5306 1 2 PWR_1D0V_EN 0R0402-PAD 21 PC5314 SC1KP50V2KX-L-1-GP A <Core Design> A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title AOZ2262QI_1D0V Size Document VNuembgeras SKL/KBL-U Rev Custom A00 Date: W ednesday, November 08, 2017 Sheet 53 of 105 54321

5 4 3 21 Main Func = 1D8V APL5930 for 1D8V_S5 Vinafix.com D C D 1D8V_PWR 1D8V_S5 PG5405 12 GAP-CLOSE-PWR PG5406 12 GAP-CLOSE-PWR PG5407 12 5V_S5 3D3V_S5 GAP-CLOSE-PWR PC5401 C 3D3V_S521 SC1U10V2KX-1GP 21 SC10U6D3V3MX-GP 100KR2F-L3-GP 21 PC5403 0511 Follow KY15. DY PR5402 PU5401 1D8V_PWR [24,40] PRIM_PWRGD PH at Page40 [17,21,40,45,53] 3V_5V_POK 6 VIN#5 5 Design Current = 1.1A B 7 VOUT#4 4 PR5408 1 2 0R0402-PAD PWR_1D8V_POK 8 VCNTL VOUT#3 3 PWR_1D8V_EN 9 POK 2 EN FB 1 1.8V_RUN_FB 12 1 SC68P50V2JN-1GP PC5404 DY DY VIN#9 GND 21 PC5405 PC5402 16K5R2F-2-GPDY 21 DY 20170810 1 PR5406 2 SC4700P50V2KX-1GP PR5403 21 New Common Part 0R0402-PAD 21 PC5406 47KR2J-2-GP 21 APL5930KAI-TRG-GP [#544669 Rev0.53] PR5401 74.05930.03D 2ND = 74.G9731.03D SC22U6D3V3MX-1-DL-GP B SC22U6D3V3MX-1-DL-GP PR5404 13KR2F-GP 2 Vout=0.8V*(R1+R2)/R2 <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, A Taipei Hsien 221, Taiwan, R.O.C. A Title LDO-V1D5V&V1D8V Size Document VNuembgeras SKL/KBL-U Rev A4 A00 Date: Wednesday, November 08, 2017 Sheet 54 of 105 54321

5 4 3 2 1 LCDVDD Main Func = LCD LCDVDD_LCD INVERTER POWER Main Func = CAMERA LCD1 R5523 DCBATOUT DCBATOUT_LCD 43 12 0R5J-5-GP F5503 800mA EE note: Never change R5229 to short pad after MP 41 12 Reserved for one time fuse: 69.43001.201 EE note: Never change R5211 to short pad after MP 1 DCBATOUT_LCD SC1KP50V2KX-L-1-GPPOLYSW -1D1A24V-GP-U3D3V_S0 3D3V_CAMERA_S0 2 C5515 2 3 Trace width = 80mil SCD1U50V3KX-GP69.50007.A31 4 C5535 DY 5 DBC_EN_R 0517 Change PH power rate D6 EDP_HPD_CONN SC1U10V2KX-1GP 1D8V_S5 7 LCD_TST_C C5536 8 eDP_AUX_CON_P SC10U6D3V3MX-GP 9 eDP_AUX_CON_N C5538 10 eDP_TX_CON_N0 LCDVDD_LCD DBC_EN_R R5518 1 2 DBC_PANEL_EN [20] 2 12 1 DY 11 eDP_TX_CON_P0 CAMERA_DET# [20] 21 12 eDP_TX_CON_N1 100R2J-L-GP 21 R5532 1 13 eDP_TX_CON_P1 0R5J-5-GP 14 LCD_BRIGHTNESS Vinafix.com SC4D7U6D3V3KX-GP 15 BLON_OUT_C 21 CAMERA_DET#_R R5501 1 2 21 C5539 D 16 PANEL_SIZE_ID_CONN 21 21 C 17 0R0402-PAD-2-GP SC33P50V2JN-3GP B 18 EC5503 19 LCD add for camera detect pin 1/25 20 21 R5521 22 10KR2J-L-GP 23 24 For ESD 0RR5253J-3L1-GPDY 2 25 26 PANEL_SIZE_ID_CONN R5525 1 DY 2 PANEL_SIZE_ID PANEL_SIZE_ID [20] 27 28 100R2J-L-GP For AUDIO Grade B or C selection. EL5507 29 1 30 USB_CAMERA_PN4 2 USB_CPU_PN4 [16] 31 USB_CAMERA_PP4 USB_CPU_PP4 [16] 32 PU/PD FOR AUX CHANNEL DY R5526 43 33 0R2J-2-GP DMIC_DATA [27] 34 DMIC_CLK [27] 35 SKL PDG (#543016): COIL-90OHM-100MHZ-5-GP 36 Recommends having a pull-up resistor of 100 kΩ for AUXN 37 and a pull-down resistor of 100 kΩ for AUXP 68.00396.001 38 between the AC capacitor and the connector, 39 DMIC_CLK_EDP MIC_GND to assist source detection by the sink device. R5534 1 DY 2 C 40 DMIC_DATA_EDP Camera 0R2J-L-GP 42 Touch Panel USB_CAMERA_PN4 3D3V_CAMERA_S0 eDP_AUX_CON_P R5528 1 DY 2 100KR2J-1-GP DMIC_DATA_EDP R5502 1 2 100R2J-L-GP 44 USB_CAMERA_PP4 eDP_AUX_CON_N R5529 1 DY 2 100KR2J-1-GP DMIC_CLK_EDP R5503 1 2 100R2J-L-GP IPEX-CON40-3-GP CAMERA_DET#_R DY USB_CON_PN7 3D3V_S0 21 SC22P50V2JN-4GP 20.F2406.040 USB_CON_PP7 21 EC5502 SC22P50V2JN-4GP 2nd = 20.F1407.040 TP_RS EC5501 TP_RESET TPAN_VDD RN5502 BKLT_CTRL 18 BLON_OUT_C 27 EDP_HPD 36 45 R5524 1 DY 2 0R2J-2-GP Layout Note: SRN100KJ-5-GP D5503 1 eDP_BKLT_CTRL Colse to LCD1. LCD_TST_C RN5501 LCD_TST_R [24] 3 R5531 LCD_BRIGHTNESS SRN100J-3-GP 12 14 BLON_OUT [24] 2 EC_BRIGHTNESS [24] BLON_OUT_C 2 3 BKLT_CTRL EDP_HPD [8] 0R0402-PAD EDP_HPD_CONN MIC_GND 14 23 BAT54C-12-GP EC (BIST MODE) RN5503 SRN100J-3-GP 75.00054.A7D LCD_BRIGHTNESS [8] eDP_TX_CPU_N0 C5508 1 2 SCD1U16V2KX-3GP eDP_TX_CON_N0 3D3V_S0 5V_S0 Main Func = Touch panel [8] eDP_TX_CPU_P0 C5532 1 2 SCD1U16V2KX-3GP eDP_TX_CON_P0 R5527 DY 0R0603-PAD-2-GP-U Touch Panel 21 0R3J-L1-GP TPAN_VDD ED5501 21R5522 [8] eDP_TX_CPU_N1 C5534 1 2 SCD1U16V2KX-3GP eDP_TX_CON_N1 69.50007.A31 USB_CON_PN7 1 I/O1 I/O4 6 USB_CON_PP7 [8] eDP_TX_CPU_P1 C5537 1 2 SCD1U16V2KX-3GP eDP_TX_CON_P1 F5502 1 DY 2 POLYSW-1D1A24V-GP-U 21 TP_RS DY EC5504 R5537 1 2 TOUCH_PANEL_INTR# [4,24] 2 GND DYVDD 5 TPAN_VDD SC22P50V2JN-4GP TPAN_VDD_F R5520 1 2 0R0603-PAD-2-GP-U 21 0R0402-PAD-2-GP 3 I/O2 I/O3 4 DY C5541 [8] eDP_AUX_CPU_N C5533 1 2 SCD1U16V2KX-3GP eDP_AUX_CON_N 21DY SC2D2U10V3KX-L-GP 21DY C5501 [8] eDP_AUX_CPU_P C5531 1 2 SCD1U16V2KX-3GP eDP_AUX_CON_P C5543 SC10P50V2JN-L1-GP SCD1U16V2KX-3GP B EE note: Never change R5232 to short pad after MP AZC099-04S-2-GP Brightness Reserved for one time fuse: 69.43001.201 075.09904.0A7C [8] L_BKLT_CTRL R5530 1 2 0R0402-PAD eDP_BKLT_CTRL TP_RESET R5538 1 2 PLT_RST# [17,31,61,63,76,91] 21 0R0402-PAD-2-GP DY C5540 SC10P50V2JN-L1-GP LCDVDD D5502 1 [8] EDP_VDD_EN 3 LCDVDD_EN [24] LCD_VCC_TEST_EN 2 21 R5506 USB_CON_PN7 R5535 1 2 0R0402-PAD-2-GP USB_CPU_PN7 [16] 100KR2J-1-GP USB_CON_PP7 R5536 1 2 0R0402-PAD-2-GP USB_CPU_PP7 [16] BAT54C-12-GP U5501 3D3V_S0 75.00054.A7D LCDVDD 1 EN VIN#5 5 2 GND VIN#4 4 3 VOUT Layout Note: 21 SC4D7U6D3V3KX-GPRT9724GB-GP21 C550574.09724.09F Trace width = 80mil SC22U6D3V3MX-1-GP C5506 AA <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title LCD&CAM&DMC&Touch Size Document Number Rev Custom Vegas SKL/KBL-U A00 Date: Wednesday, November 08, 2017 Sheet 55 of 105 54321

5 4 3 2 1 Main Func = CRT 5V_CRT_S0_R For EMI R2 SPEC Reserved 5V_HDMI_S0 D5604 5V_CRT_S0_R DY ED5603 DY ED5602 DY ED5601 5V_CRT_S0_R CRT Connector VAegas K 14 23 C5623 VGA1 RB551V30-GP CRT_G CRT_R CRT_B Vinafix.comD SCD01U16V2KX-3GP 9 VCC_CRT 4 83.R5003.H8H RN5601 Vegas 1DY 2 11 SRN2K2J-1-GP NC#4 NC#11 21 D 21 C CRT_DDCDATA_CON 12 DDCDATA_ID1 CRT_DDCDATA_CON 21 CRT_DDCCLK_CON 15 DDCCLK_ID3 5 CRT_DDCCLK_CON AZ5725-01FDR7G-GP AZ5725-01FDR7G-GP AZ5725-01FDR7G-GP GND 6 CRT_R 1 CRT_RED Vegas GND 7 CRT_DDCCLK_CON_R R5602 1 2 0R0402-PAD CRT_DDCCLK_CON CRT_G 2 GND 8 CRT_DDCDATA_CON_R R5603 1 2 0R0402-PAD CRT_DDCDATA_CON CRT_B 3 CRT_GREEN GND 10 CRT_BLUE GND 16 GND 17 CRT_VSYNC_CON 14 VSYNC GND DP_CRT_HSYNC_CON R5612 VV11eeggaass 2 47R2J-2-GP CRT_HSYNC_CON CRT_HSYNC_CON 13 HSYNC DP_CRT_VSYNC_CON R5611 2 47R2J-2-GP CRT_VSYNC_CON CRT_PCH_HPD R5605 1 2 0R0402-PAD CPU_DP2_HPD [8] 83.05725.0A0 83.05725.0A0 D-SUB-15-297-GP 83.05725.0A0 020.20067.0015 2nd = 20.20975.015 DP_CRT_R BELLM561081BB1V47e0SgNa1sD-GP 2 CRT_R CRT_HSYNC_CON CRT_VSYNC_CON CRT_DDCDATA_CON CRT_DDCCLK_CON DP_CRT_G BELL5M61083BB1V47e0SgNa1sD-GP 2 CRT_G EBLLM561082BB1V47e0SgNa1sD-GP 2 CRT_B C C5607 3D3V_S0 VDD_DAC_33 C5622 DP_CRT_B C5616 C5617 C5618 C5614 C5619 C5613 C5611 C5612 R5606 R5608 R5607 21 DY DY DY DY 21 21 R5609 1 2 21 21 0R0603-PAD-2-GP-U 21 21 21 Vegas C5615 21 SC10U6D3V3MX-GP 21 21 21 21 21 VegaVsegaVsegas Vegas Vegas Vegas Vegas Vegas Vegas SC18P50V2JN-1-GP SC100P50V2JN-3GP SC18P50V2JN-1-GP SC100P50V2JN-3GP 3D3V_S0 AVCC33 75R2F-2-GP SC15P50V2JN-2-GP SC15P50V2JN-2-GP 5V_CRT_S0_R 1 AFTP5604 AFTE14P-GP R5610 1 2 CRT_VSYNC_CON 1 AFTP5602 AFTE14P-GP 75R2F-2-GP SC15P50V2JN-2-GP SC15P50V2JN-2-GP CRT_HSYNC_CON 1 AFTP5603 AFTE14P-GP 0R0603-PAD-2-GP-U 12 75R2F-2-GP SC15P50V2JN-2-GP SC15P50V2JN-2-GP AFTP5609 AFTE14P-GP C5621 Layout note: Layout note: CRT_DDCDATA_CON 1 AFTP5608 AFTE14P-GP Vegas SC10U6D3V3MX-GP AFTP5605 AFTE14P-GP R5607, R5608, R5606 need to close U5601 C5611 & C5612 & C5613 & C5614 & C5618 & C5619 & L5601 & L5602 & L5603 CRT_DDCCLK_CON 1 AFTP5607 AFTE14P-GP Trace length not over 300 mil need to close connect AFTP5606 AFTE14P-GP CRT_R 1 CRT_G CRT_B 1 1 3D3V_S0 U5601 5V_S0 B SCD1U16V2KX-3VGPeg2as 1 C5620 VCCK_12 4 AVCC_12 Vegas AUX_P 2 PCH_DPC_AUXP_U SCD1U16V2KX-3GP 22VVeeggaa11ssCC55662254 PCH_DPC_AUXP [8] B 25 VCCK_12 AUX_N 3 PCH_DPC_AUXN_U SCD1U16V2KX-3GP 2222VVVVeeeeggggaaaa1111ssssCCCC5555666600001354 PCH_DPC_AUXN [8] DY 1 AVCC_33 LANE0_P 5 PCH_DPC_P0_U SCD1U16V2KX-3GP 14 VCC_33 LANE0_N 6 PCH_DPC_N0_U SCD1U16V2KX-3GP LANE1_P 7 PCH_DPC_P1_U SCD1U16V2KX-3GP LANE1_N 8 PCH_DPC_N1_U SCD1U16V2KX-3GP 21 SSSCCCDD2D11UU2U116160VVV22KK3KXXX--33-VVVGLG-PPGeeePggg222aaasss 1 C5609 VCCK_12 211C5608 1 C5606 AVCC33 SCD1U16V2KX-3GPPCH_DPC_P0[8]21 C5602SCD1U16V2KX-3VGPeg2as 1 C5626 3D3V_S0PCH_DPC_N0[8]21 PCH_DPC_P1 [8] Vegas PCH_DPC_N1 [8] SC4D7P50V2BN-GPSSSCCC1DD011UUU611D663VVV223KKMXX--X33-VVVGGGPPeeeP ggg222 aaasss1C5627 VDD_DAC_33 20VDD_DAC_33HVSYNC_PWR17DP_CRT_HSYNC_CON5V_S0 C56291PVCC_33HSYNC19DP_CRT_VSYNC_CON0523 Follow vendor suggest. 1 C5628 VSYNC 18 VegasC5610 3D3V_S026 4K7R2J-2-GPCRT_DDCCLK_CON_R 15VGA_SCLBLUE_P21DP_CRT_B Layout note: R5616CRT_DDCDATA_CON_R 16VGA_SDAGREEN_P22DP_CRT_G close to pin17 23 DP_CRT_R 4K7R2J-2-GP RED_P R5613 30 27 SPI_CLK_CRT 29 28 [12,13,18,65,67] PCH_SMBCLK SMB_SCL LDO_RSTB 31 EXT_CLK_IN_CRT [12,13,18,65,67] PCH_SMBDATA SMB_SDA EXT_CLK_IN 32 CRT_PCH_HPD EXT1.2V_CTRL RN5603 SPI_CLK_CRT 11 GPI1/SPI_CLK 14 SPI_SI_CRT 12 GPI2/SPI_SI HPD 3D3V_S0 SPI_SO_CRT 13 GPI3/SPI_SO 2 DY 3 POL1/SPI_CEB 24 DY <Core Design> POL2 GND 33 23 10 POL1/SPI_CEB GND 1 4 9 POL2 A 3D3V_S0 RN5602 Vegas Wistron Corporation A SRN4K7J-8-GP 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. SRN4K7J-8-GP RTD2166-CGT-GP 071.02166.0003 Title CRT 543 Size Document Number Rev Custom Vegas SKL/KBL-U A00 Date: Wednesday, November 08, 2017 Sheet 56 of 105 2 1

54321 Main Func = HDMI HDMI_CLK_R ER5706 1 2 HDMI_CLK_R_C HDMI_DATA1_R ER5705 1 2 HDMI_DATA1_R_C [8] HDMI_CLK# C5701 1 Vinafix.com2 SCD1U16V2KX-3GP HDMI_CLK#_R 0R0402-PAD-2-GP 21 R5702 0R0402-PAD-2-GP 21 R5708 [8] HDMI_CLK C5704 1 HDMI_CLK_R 150R2J-L1-GP-U 150R2J-L1-GP-U 2 SCD1U16V2KX-3GP C5705 1 2 SCD1U16V2KX-3GP HDMI_DATA0#_R HDMI_CLK#_R_C HDMI_DATA1#_R_C D [8] HDMI_DATA0# C5703 1 2 SCD1U16V2KX-3GP HDMI_DATA0_R D [8] HDMI_DATA0 HDMI_CLK#_R ER5714 1 2 HDMI_DATA1#_R ER5704 1 2 0R0402-PAD-2-GP 0R0402-PAD-2-GP [8] HDMI_DATA1# C5707 1 2 SCD1U16V2KX-3GP HDMI_DATA1#_R HDMI_DATA0_R ER5713 1 2 HDMI_DATA0_R_C HDMI_DATA2_R ER5717 1 2 HDMI_DATA2_R_C [8] HDMI_DATA1 C5706 1 2 SCD1U16V2KX-3GP HDMI_DATA1_R C5708 1 2 SCD1U16V2KX-3GP [8] HDMI_DATA2# C5709 1 2 SCD1U16V2KX-3GP HDMI_DATA2#_R [8] HDMI_DATA2 HDMI_DATA2_R 0R0402-PAD-2-GP 21 0R0402-PAD-2-GP 21 18 R5701 R5703 27 150R2J-L1-GP-U 150R2J-L1-GP-U 36 5V_S0 Q5701 RN5703 45 RN5701 HDMI_DATA0#_R ER5715 1 2 HDMI_DATA0#_R_C HDMI_DATA2#_R ER5716 1 2 HDMI_DATA2#_R_C G SRN470J-3-GP 21 SRN470J-3-GP 18 27 0R0402-PAD-2-GP 0R0402-PAD-2-GP 36 D HDMI_PLL_GND 45 1R0507K1R9 21J-1D-GYP 2 S 2N7002K-2-GP DY R5707 5V_S0 0R2J-2-GP 84.2N702.J31 2ND = 84.2N702.031 5V_HDMI_S0 HDMI CONN C 3rd = 84.07002.I31 C5702 HDMI1 3 C D5701 18 +5V_POWER SCL 15 DDC_CLK_HDMI LBAW 56LT1G-GP SDA 16 DDC_DATA_HDMI 69.50007.691: 83.00056.Y11 21 HDMI_DATA0_R_C 7 TMDS_DATA0+ 13 OBS REASON: Please transfer to down size item 69.48001.081 for cost reduction and good cost down trend HDMI_DATA0#_R_C 9 TMDS_DATA0- 17 HDMI_DATA1_R_C 4 TMDS_DATA1+ 19 HDMI_DATA1#_R_C 6 TMDS_DATA1- 14 HDMI_DATA2_R_C 1 TMDS_DATA2+ HDMI_DATA2#_R_C 3 TMDS_DATA2- 5V_S0 5V_HDMI_S0 DDC_CLK_PH1 2 2 DDC_DATA_PH2 1 HPD_HDMI_CONCEC SCD1U16V2KX-3GPHDMI_CLK_R_C DDC/CEC_GROUNG F5701 HDMI_CLK#_R_C HOT_PLUG_DETECT 1 RESERVED#14 2 8 TMDS_DATA0_SHIELD 5 TMDS_DATA1_SHIELD POLYSW -1D1A6V-9-GP-U 2 TMDS_DATA2_SHIELD 20 21 69.48001.081 3D3V_S0 41 11 TMDS_CLOCK_SHIELD GND 22 10 TMDS_CLOCK+ GND 23 R0R5371J-8L11-GDPY 2 2ND = 69.50011.081 Q5702 RN5702 12 TMDS_CLOCK- HDMI GND 3RD = 69.50013.061 43 SRN2K2J-1-GP (A_Type) GND 52 3 DDC_CLK_HDMI SKT-HDMI23-168-GP [8] CPU_DP1_CTRL_CLK 022.10025.0161 2nd = 022.10025.0181 3rd = 022.10025.0051 61 3D3V_S0 B 2N7002KDW-GP B [8] CPU_DP1_CTRL_DATA DDC_DATA_HDMI 84.T3904.H11 1E C R5710 84.2N702.A3F Q5703 B HDMI_HPD_B 2 150KR2F-L-GP 2nd = 84.2N702.E3F 1 3rd = 75.00601.07C R5712 1 LMBT3904LT1G-GP 21 R5711 [8] CPU_DP1_HPD 0R0402-PAD 2 HDMI_HPD_E 200KR2F-L-GP EMI Request: HDMI_DATA1#_R_C HDMI_DATA0#_R_C DDC_CLK_HDMI R57092 HDMI_DATA1_R_C HDMI_DATA0_R_C DDC_DATA_HDMI 10KR2J-L-GP HDMI_DATA2#_R_C HDMI_CLK_R_C HPD_HDMI_CON HDMI_DATA2_R_C HDMI_CLK#_R_C <Core Design> ED5701 10 1 ED5702 10 ED5703 10 1 9 1 9 29 2 7 2 7 6 6 3 3 3 8 8 8 4 DY 4 DY 7 4 DY A 56 5 5 A RCLAMP0524P-2-GP RCLAMP0524P-2-GP RCLAMP0524P-2-GP Wistron Corporation 75.00524.A73 75.00524.A73 75.00524.A73 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. 5 4 3 Title Rev HDMI A00 Size Document Number A3 Vegas SKL/KBL-U Date: W ednesday, November 08, 2017 Sheet 57 of 105 21

5 43 21 E Main Func = HDD SATA HDD Connector 5V_HDD_S0 ED6001 5V_S0 E 80 mils R6001 Vinafix.com SATA_TX_CON_P0 1 LINE_1 NC#10 10 SATA_TX_CON_P0 12 SATA_TX_CON_N0 2 GLINNDE_2DY NC#9 9 SATA_TX_CON_N0 3 GND 8 0R0805-PAD-2-GP-U SATA_RX_CON_N0 4 LINE_3 NC#7 7 SATA_RX_CON_N0 SATA_RX_CON_P0 5 6 SATA_RX_CON_P0 SCD1U16V2KX-3GP LINE_4 NC#6 C6007 SC10U6D3V3MX-GP C6008 SCD1U16V2KX-3GP C6001 SC10U6D3V3MX-GP C6002 21 21 21 21 DY DY AZ1045-04F-R7G-GP Swap ba7s5e.d0o1n04th5e.0s7wa3p report. Close to HDD1 Layout Note: Place near HDD1 [16] SATA_TX_CPU_P0 C6005 1 2 SCD22U10V2KX-L1-GP SATA_TX_CON_P0 [16] SATA_TX_CPU_N0 C6006 1 2 SCD22U10V2KX-L1-GP SATA_TX_CON_N0 HDD1 C6004 1 14 D C6003 1 2 SCD22U10V2KX-L1-GP SATA_RX_CON_N0 12 D R6002 1 2 SCD22U10V2KX-L1-GP SATA_RX_CON_P0 11 [16] SATA_RX_CPU_N0 10 [16] SATA_RX_CPU_P0 2 0R0402-PAD HDD_DEVSLP_R 9 [16] HDD_DEVSLP 8 7 5V_HDD_S0 6 5 4 3 2 [67] FFS_INT2_Q 1 13 5V_HDD_S0 1 AFTP6001 AFTE14P-GP STAR-CON12-1-GP 020.K0049.0012 2nd = 020.K0125.0012 3rd = 020.K0190.0012 C Main Func = ODD ODD Connector ODD1 C B 20 22 19 18 5V_S0 ODD_PWR_5V 1 SATA_ODD_DA#_C TP6001 17 TPAD14-OP-GP 16 R6003 1 2 15 14 0R0805-PAD-2-GP-U 13 SCD1U16V2KX-3GP21 ODD_PWR_5V 12 C601821 ODD ODD 11 SC10U6D3V3MX-GP C6009 10 9 [16] SATA_ODD_PRSNT# R6004 1 2 0R0402-PAD-2-GP SATA_ODD_PRSNT#_R 8 ODD 2 SCD01U50V2KX-L-GP SATA_RX_CON_P1 7 OODD11DD 2 SCD01U50V2KX-L-GP SATA_RX_CON_N1 6 [16] SATA_RX_CPU_P1 C6011 5 B [16] SATA_RX_CPU_N1 C6010 4 [16] SATA_TX_CPU_N1 C6013 OODD11DD 2 SCD01U50V2KX-L-GP SATA_TX_CON_N1 3 [16] SATA_TX_CPU_P1 C6014 2 SCD01U50V2KX-L-GP SATA_TX_CON_P1 2 1 21 ACES-CON20-30-GP-U1 20.K0708.020 2nd = 020.K0050.0020 <Core Design> A Wistron Corporation A 543 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title INT IO (HDD/ODD) Size Document Number Rev Custom Vegas SKL/KBL-U A00 Date: Wednesday, November 08, 2017 Sheet 60 of 105 21

5 4 3 2 1 Main Func = WLAN 3D3V_S0 R6117 3D3V_WLAN_S0 USB_CON_PP6 R6111 1 2 0R0402-PAD-2-GP USB_CPU_PP6 12 USB_CON_PN6 R6110 1 2 0R0402-PAD-2-GP USB_CPU_PN6 1.1A 0R0805-PAD-2-GP-U Vinafix.DcYom DY DY DY SCD1U16V2KX-3GP C6103 SCD1U16V2KX-3GP C6104 SC10U6D3V3MX-GP C6106 SCD1U16V2KX-3GP C6102 SCD1U16V2KX-3GP C6101 SC10U6D3V3MX-GP C6105 D [18] PEG_CLK1_CPU# 21 D [18] PEG_CLK1_CPU 21 21 21 21 21 [16] PCIE_RX_CPU_N6 [16] PCIE_RX_CPU_P6 [16] PCIE_TX_CON_N6 [16] PCIE_TX_CON_P6 [18] CLKREQ_PCIE#1 WLAN1 77 [15] WIFI_RF_EN 3D3V_WLAN_S0 75 73 [20] BLUETOOTH_EN 74 NP 71 72 NP 69 70 67 [24,68] HOST_DEBUG_TX 68 65 63 66 61 64 59 [17,31,55,63,76,91] PLT_RST# 62 57 55 1 TPAD14-OP-GP E51_RX2 60 53 WLAN_DISABLE#1 58 51 C [18] CL_RST# TP6103 R6114 1 2 BLUETOOTH_EN_NGFF 56 49 C [18] CL_CLK WIFI_RF_EN PLT_RST_NGFF# 54 47 [18] CL_DATA BLUETOOTH_EN R6113 1 2 0R0402-PAD 52 45 WLAN_WAKE 1 TP6101 PLT_RST# 0R0402-PAD 50 43 TPAD14-OP-GP R6116 1 2 0R0402-PAD 41 WLAN_CLKREQ_WLAN# R6112 1 2 CLKREQ_PCIE#1 39 48 37 PEG_CLK1_CPU# 0R0402-PAD 46 35 PEG_CLK1_CPU [16] USB_CPU_PN6 TP6102 1 E51_RX1 44 33 [16] USB_CPU_PP6 E51_TX1 42 31 TPAD14-OP-GP CL_CLK_R 40 29 CL_CLK R6109 1 2 0R2J-L-GP CL_DATA_R 38 27 PCIE_RX_CPU_N6 CL_DATA R6119 1 DDDYYY 2 0R2J-L-GP CL_RST#_R 36 25 PCIE_RX_CPU_P6 CL_RST# R6108 1 2 0R2J-L-GP 23 21 PCIE_TX_CON_N6 3160 does not support C-Link 34 19 PCIE_TX_CON_P6 17 32 15 30 13 Reserved for NGFF Debug Card 28 11 9 3D3V_S5 Ra 3D3V_WLAN_S0 24 7 26 5 2 22 3 0RR6211J-8L1-GPDY 20 1 B 18 B 16 HOST_DEBUG_TX 0RR621J1-5L1-GPDY 2 E51_TX1 14 12 10 EE Note: Rb 3D3V_WLAN_S0 8 6 For NFGG Debug Card: 4 USB_CON_PN6 Stuff Ra, Rb; DY Rc. USB_CON_PP6 Note:pin 76 and pin 77 need contact to GND 2 76 Support: Intel Dual Band Wireless-AC 3160 PAD-SKT-NGFF75P-GP 1 3D3V_WLAN_S0 062.10003.0621 Wistron Corporation 1 WLAN_CLKREQ_WLAN# 1 WLAN_DISABLE#1 <Core Design> 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, 1 BLUETOOTH_EN_NGFF 2nd = 062.10007.0081 Taipei Hsien 221, Taiwan, R.O.C. 1 PLT_RST_NGFF# 3rd = 062.10007.0391 1 USB_CON_PN6 A AFTE14P-GP AFTP6101 1 USB_CON_PP6 A AFTE14P-GP AFTP6105 AFTE14P-GP AFTP6106 Title AFTE14P-GP AFTP6107 AFTE14P-GP AFTP6108 NGFF_WLAN CONN AFTE14P-GP AFTP6109 AFTE14P-GP AFTP6110 Size Document Number Rev A4 Vegas SKL/KBL-U A00 Date: Wednesday, November 08, 2017 Sheet 61 of 105 54 321

5 43 21 Main Func = eMMC 1D8V_S5 EMMC Vinafix.com eMMC21 R6311 3D3V_S5 0R3J-L1-GP [15] EMMC_D7 1 OF 2 [15] EMMC_D6 U6301A D [15] EMMC_D5 [15] EMMC_D4 EMMC_VCCQ C6 VDD DAT0 A3 EMMC_D0_R R6312 1 eeeeeeeeMMMMMMMMMMMMMMMM22222222CCCCCCCC 10R2F-L1-GP EMMC_D0 D [15] EMMC_D3 M4 VDD DAT1 A4 EMMC_D1_R R6313 1 10R2F-L1-GP EMMC_D1 [15] EMMC_D2 1 C631621 C6317 N4 VDD DAT2 A5 EMMC_D2_R R6314 1 10R2F-L1-GP EMMC_D2 [15] EMMC_D1 SCD1U16V2KX-3GP 21 SC4D7U6D3V3KX-GP P3 VDD DAT3 B2 EMMC_D3_R R6316 1 10R2F-L1-GP EMMC_D3 [15] EMMC_D0 eMMC R6325 P5 VDD DAT4 B3 EMMC_D4_R R6317 1 10R2F-L1-GP EMMC_D4 [15] EMMC_CLK 0R3J-L1-GP eMMC eMMC DAT5 B4 EMMC_D5_R R6318 1 10R2F-L1-GP EMMC_D5 [15] EMMC_CMD DAT6 B5 EMMC_D6_R R6319 1 10R2F-L1-GP EMMC_D6 12 EMMC_VCC E6 VDDF DAT7 B6 EMMC_D7_R R6315 1 10R2F-L1-GP EMMC_D7 [15] EMMC_RCLK F5 VDDF eMMC CSC6311U810V2KeX-M1GMP C 21 C6319 C6320 J10 VDDF A6 Change 10 ohm follow PDG [17,31,55,61,76,91] PLT_RST# SCD1U16V2KX-3GP SC1U10V2KX-1GP K9 VDDF C4 modify date 4/17 E7 2 1 EMMC_VDDI C2 VDDI eMMC VSS G5 VSS H10 2 eMMC VSS J5 VSS K8 EMMC_CLK R6320 11eeMMMMCC 2 0R2J-2-GP EMMC_CLK_R M6 CLK VSS N2 EMMC_CMD R6321 2 0R2J-2-GP EMMC_CMD_R M5 CMD VSS N5 VSS P4 EMMC_RCLK R6322 1eMMC 2 10R2F-L1-GP EMMC_RCLK_R H5 DATA_STROBE VSS P6 EMMC_RESET# K5 RST# VSS VSS VSS 072.KMBG4.0C0U C C U6301B 2 OF 2 A1 NC#A1 NC#J3 J3 A2 NC#A2 NC#J12 J12 A8 NC#A8 NC#J13 J13 eMMC_E9 1 TP6301 TPAD14-OP-GP A9 NC#A9 NC#J14 J14 eMMC_E10 1 TP6302 TPAD14-OP-GP A10 NC#A10 NC#K1 K1 eMMC_F10 1 TP6303 TPAD14-OP-GP A11 NC#A11 NC#K2 K2 eMMC_K10 1 TP6304 TPAD14-OP-GP A12 NC#A12 NC#K3 K3 A13 K12 A14 NC#A13 NC#K12 K13 B1 NC#A14 NC#K13 K14 B7 NC#B1 NC#K14 L1 B8 NC#B7 NC#L1 L2 B9 NC#B8 NC#L2 L3 B10 NC#B9 NC#L3 L12 B11 NC#B10 NC#L12 L13 B12 NC#B11 NC#L13 L14 B13 NC#B12 NC#L14 M1 B14 NC#B13 NC#M1 M2 C1 NC#B14 NC#M2 M3 C3 NC#C1 NC#M3 M7 C5 NC#C3 NC#M7 M8 C7 NC#C5 NC#M8 M9 C8 NC#C7 NC#M9 M10 C9 NC#C8 NC#M10 M11 0510 C10 NC#C9 NC#M11 M12 EMMC_VCCQ Corrected to S5 C11 NC#C10 NC#M12 M13 B C12 NC#C11 NC#M13 M14 B C13 N1 1D8V_S5 C14 NC#C12 NC#M14 N3 21 D1 N6 10KR2J-L-GP D2 NC#C13 NC#N1 N7 R6323 D3 NC#C14 NC#N3 N8 G D4 NC#D1 NC#N6 N9 D12 N10 eMMC eMMC D D13 NC#D2 NC#N7 N11 D14 NC#D3 NC#N8 N12 EMMC_RESET# E1 NC#D4 NC#N9 N13 S PLT_RST# E2 NC#D12 NC#N10 N14 E3 P1 Q6301 Vth(max)=1.0V E12 NC#D13 NC#N11 P2 E13 P8 PJA138KA-GP E14 NC#D14 NC#N12 P9 F1 P11 084.00138.0A31 F2 NC#E1 NC#N13 P12 F3 P13 F12 NC#E2 NC#N14 P14 F13 NC#E3 NC#P1 A7 F14 NC#E12 NC#P2 E5 1 DY 2 G1 NC#E13 NC#P8 E8 G2 NC#E14 eMMC NC#P9 E9 R6324 G12 E10 0R2J-2-GP G13 NC#F1 NC#P11 F10 G14 NC#F2 NC#P12 G3 H1 NC#F3 NC#P13 G10 H2 NC#F12 NC#P14 K6 H3 NC#F13 K7 H12 NC#F14 K10 H13 NC#G1 RFU#A7 P7 H14 NC#G2 RFU#E5 P10 J1 NC#G12 RFU#E8 J2 NC#G13 RFU#E9 eMMC_E9 NC#G14 RFU#E10 eMMC_E10 A NC#H1 RFU#F10 eMMC_F10 <Core Design> A NC#H2 RFU#G3 eMMC_K10 NC#H3 RFU#G10 NC#H12 RFU#K6 Wistron Corporation NC#H13 RFU#K7 NC#H14 RFU#K10 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, NC#J1 RFU#P7 Taipei Hsien 221, Taiwan, R.O.C. NC#J2 RFU#P10 Title eMMC 072.KMBG4.0C0U Size Document Number Rev A3 Vegas SKL/KBL-R A00 Date: W ednesday, November 08, 2017 Sheet 63 of 105 543 21

5 4 3 21 D Main Func = Power BTN Power button [24] LID_CL_SIO# RN6401 4 Layout note: PW R1 [24] KBC_PW RBTN# 1 3 G6401 place to buttom 6 2 4 D Vinafix.comG6402 place to top LID_CLOSE#_C 3 KBC_PW RBTN#_C 2 3D3V_S5 DY DY SRN100J-3-GP 21 1 21 5 21 21 21 21 DY SCD1U16V2KX-3GPDY ACES-CON4-88-GP C6401 3D3V_S5 1 AFTP6402 020.K0005.0004 AFTP6401 GAP-OPEN LID_CLOSE#_C 1 AFTP6404 G6402 2nd = 020.K0264.0004 1 GAP-OPEN AFTP6403 G6401 KBC_PW RBTN#_C1 AZ5725-01FDR7G-GP ED6401 SC1KP50V2KX-L-1-GP EC6403 SCD1U16V2KX-3GP EC6401 Main Func = Battery LED Low actived from KBC GPIO Q6403 5V_S5 R1 E [24] CHG_AMBER_LED# R6405 1 2 CHG_AMBER_LED_R# B R2 C AMBER_LED_BAT R6407 1 2 BAT_AMBER Battery LED1 0R0402-PAD 422R2F-2-GP (ALEDM1 BER_LED) R1 RN2418-GPR2 21DY SCD1U25V2KX-GP EC6402 084.02418.0011 1 +C Yellow C 2+ -3 White Low actived from KBC GPIO Q6404 5V_S5 LED-YW -5-GP E [24] BATT_W HITE_LED# R6404 1 2 BATT_W HITE_LED_R# B C W HITE_LED_BAT R6406 1 2 BAT_W HITE 083.1212A.0070 0R0402-PAD 274R2F-GP (BaWtHIteTEr_yLELDED)2 RN2418-GP 21DY SCD1U25V2KX-GP EC6404 084.02418.0011 Main Func = HDD LED 0516 Follow KY15 1D8V_S0 SATA HDD LED R6401G2 1 B LOW actived from PCH GPIO 10KR2J-L-GP HWHDLED [24] MASK_SATA_LED# B [16] SATA_LED#_R S D BATT_W HITE_LED_R# Q6401 DMN5L06K-7-GP HWHDLED A <Core Design> A 543 Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title LED Board&Power Button Size Document Number Rev A3 Vegas SKL/KBL-U A00 Date: W ednesday, November 08, 2017 Sheet 64 of 105 21