DE_MF

8.8 Counter Design & Explain Data sheet of 7492, 74190,74192We wish to design a synchronous sequential circuit whose state diagram isshown in Figure 13. The type of flip-flop to be use is J-K. Figure 13. State diagramFrom the state diagram, we can generate the state table shown in Table 9.Note that there is no output section for this circuit. Two flip-flops are needed torepresent the four states and are designated Q0Q1. The input variable islabelled x.Present State Next State Q0 Q1 x=0 x=100 00 0101 10 0110 10 1111 11 00Table 9. State table.We shall now derive the excitation table and the combinational structure. Thetable is now arranged in a different form shown in Table 11, where the presentstate and input variables are arranged in the form of a truth table. Remember,the excitable for the JK flip-flop was derive in Table 1.NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 157

Table 10. Excitation table for JK flip-flopOutput Transitions Flip-flop inputs Q �Q(next) JK 0 �0 0X 0 �1 1X 1 �0 X1 1 �1 X0Table 11. Excitation table of the circuitPresent State Next State Input Flip-flop Inputs Q0 Q1 Q0 Q1 X J0K0 J1K1 00 00 00 01 0 0X 0X 01 10 01 01 1 0X 1X 10 10 10 11 0 1X X1 11 11 11 00 1 0X X0 0 X0 0X 1 X0 1X 0 X0 X0 1 X1 X1In the first row of Table 11, we have a transition for flip-flop Q0 from 0 in thepresent state to 0 in the next state. In Table 10 we find that a transition ofstates from 0 to 0 requires that input J = 0 and input K = X. So 0 and X arecopied in the first row under J0 and K0 respectively. Since the first row alsoshows a transition for the flip-flop Q1 from 0 in the present state to 0 in thenext state, 0 and X are copied in the first row under J1 and K1. This process iscontinued for each row of the table and for each flip-flop, with the inputconditions as specified in Table 10.NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 158

The simplified Boolean functions for the combinational circuit can now bederived. The input variables are Q0, Q1, and x; the output are the variables J0,K0, J1 and K1. The information from the truth table is plotted on the Karnaughmaps shown in Figure 14.Figure 14. Karnaugh MapsThe flip-flop input functions are derived:J0 = Q1*x' K0 = Q1*xJ1 = x K1 = Q0'*x' + Q0*x = Q0�xNote: the symbol �is exclusive-NOR.The logic diagram is drawn in Figure 15.NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 159

Practical example of counterWe use counters in many applications. Where ever we come across the use of timers, therewe use counters of synchronous type.  For suppose, in our kitchen appliances, we use microwave ovens. In that we set some temperature to heat the food item kept in it. Internally the counter calculates the increase or decrease in temperature and time. If it reaches the pre-set temperature, then it prevents from further heating and spoiling of that food item.  Washing machines: We use counters in washing machines also. Similar to the counting operation in microwave oven, the counter in washing machine counts the time which we set it to operate.  In both microwave oven and washing machine, we set the device to particular time, and it starts decreasing for every second. When the value of counter becomes zero, it activates the switch ON / OFF. Thus the operation of the device is controlled by counters.Some other applications of counters: To calculate the number of people entering andleaving a stadium or auditorium we use , counters at entry gate or door. These counters willcount the persons. For entry of each person, the value of counter increases by 1. In thesame manner, for every leaving of each person, the counter value decreases by 1.7492Pin diagram:The 7492 is a 4-stage ripple counter containing a high speed flip-flop acting as a divide bytwo and three flip-flops connected as a divide by six. HIGH signals on the Master Reset(MR) inputs override the clocks and force all outputs to the LOW state.NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 160

74190Pin diagram:  Counts 8421 BCD or Binary  Single Down/Up count control line  Count Enable control Input  Ripple clock output for cascading  Asynchronously presettable with load control  Parallel outputs  Cascadable for n-Bit applications74192Pin diagram:NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 161

8.9 Applications of countersCounter found their applications in many digital electronic devices. Some of theirapplications are listed below.  Frequency counters  Digital clocks  Analog to digital convertors.  With some changes in their design, counters can be used as frequency divider circuits. The frequency divider circuit is that which divides the input frequency exactly by ‗2‘.  In time measurement. That means calculating time in timers such as electronic devices like ovens and washing machines.  We can design digital triangular wave generator by using counters.There are many other type of counters rather than synchronous and asynchronouscounters, such as Decade counter, Binary counter, Ring counter, Johnson counter, Up /Down counter etc. , which we will discuss about them in our upcoming sessions.8.10 Register Concept- Types of Registers- SISO,SIPO,PISO,PIPO and applicationTwo basic functions: data storage and data movement. The storage capabilityof a register makes it an important type of memory device. A register canconsist of one or more flip-flops used to store and shift data. They are a groupof flip-flops connected in a chain so that the output from one flip-flop becomesthe input of the next flip-flop. Most of the registers possess no characteristicinternal sequence of states. All flip-flop is driven by a common clock, and allare set or reset simultaneously.NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 162

TYPES OF REGISTERS-SIS0, SIPO, PISO, PIPO – Bidirectional Shift Registers Shift Register Counters This sequential device loads the data present on its inputs and then moves or ―shifts‖ it to its output once every clock cycle, hence the name Shift Register. A shift register basically consists of several single bit ―D-Type Data Latches‖, one for each data bit, either a logic ―0‖ or a ―1‖, connected together in a serial type daisy-chain arrangement so that the output from one data latch becomes the input of the next latch and so on. Data bits may be fed in or out of a shift register serially, that is one after the other from either the left or the right direction, or all together at the same time in a parallel configuration. The number of individual data latches required to make up a single Shift Register device is usually determined by the number of bits to be stored with the most common being 8-bits (one byte) wide constructed from eight individual data latches. Shift Registers are used for data storage or for the movement of data and are therefore commonly used inside calculators or computers to store data such as two binary numbers before they are added together, or to convert the data from either a serial to parallel or parallel to serial format. The individual data latches that make up a single shift register are all driven by a common clock ( Clk ) signal making them synchronous devices. Shift register IC‘s are generally provided with a clear or reset connection so that they can be ―SET‖ or ―RESET‖ as required. Generally, shift registers operate in one of four different modes with the basic movement of data through a shift register being: Serial-in to Parallel-out (SIPO) - the register is loaded with serial data, one bit at a time, with the stored data being available at the output in parallel form. Serial-in to Serial-out (SISO) - the data is shifted serially ―IN‖ and ―OUT‖ of the register, one bit at a time in either a left or right direction under clock control. Parallel-in to Serial-out (PISO) - the parallel data is loaded into the register simultaneously and is shifted out of the register serially one bit at a time under clock control. Parallel-in to Parallel-out (PIPO) - the parallel data is loaded simultaneously into the register, and transferred together to their respective outputs by the same clock pulse. The effect of data movement from left to right through a shift register can be presented graphically as:NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 163

Also, the directional movement of the data through a shift register can beeither to the left, (left shifting) to the right, (right shifting) left-in but right-out,(rotation) or both left and right shifting within the same register thereby makingit bidirectional. In this tutorial it is assumed that all the data shifts to the right,(right shifting).Serial-in to Parallel-out (SIPO) Shift Register4-bit Serial-in to Parallel-out Shift RegisterThe operation is as follows. Lets assume that all the flip-flops ( FFA to FFD )have just been RESET ( CLEAR input ) and that all the outputs QA to QD are atlogic level ―0‖ ie, no parallel data output.If a logic ―1‖ is connected to the DATA input pin of FFA then on the first clockpulse the output of FFA and therefore the resulting QA will be set HIGH to logic―1‖ with all the other outputs still remaining LOW at logic ―0‖. Assume now thatthe DATA input pin of FFA has returned LOW again to logic ―0‖ giving us onedata pulse or 0-1-0.The second clock pulse will change the output of FFA to logic ―0‖ and theoutput of FFB and QB HIGH to logic ―1‖ as its input D has the logic ―1‖ level onNTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 164

it from QA. The logic ―1‖ has now moved or been ―shifted‖ one place along theregister to the right as it is now at QA.When the third clock pulse arrives this logic ―1‖ value moves to the outputof FFC ( QC ) and so on until the arrival of the fifth clock pulse which sets allthe outputs QA to QD back again to logic level ―0‖ because the input to FFA hasremained constant at logic level ―0‖.The effect of each clock pulse is to shift the data contents of each stage oneplace to the right, and this is shown in the following table until the completedata value of 0-0-0-1 is stored in the register. This data value can now be readdirectly from the outputs of QA to QD.Then the data has been converted from a serial data input signal to a paralleldata output. The truth table and following waveforms show the propagation ofthe logic ―1‖ through the register from left to right as follows.Basic Data Movement Through A Shift RegisterClock QA QB QC QDPulse No 0 0000 0 00 1 0011 0 10 0 0120 0 00304050NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 165

Note that after the fourth clock pulse has ended the 4-bits of data ( 0-0-0-1 )are stored in the register and will remain there provided clocking of the registerhas stopped. In practice the input data to the register may consist of variouscombinations of logic ―1‖ and ―0‖. Commonly available SIPO IC‘s include thestandard 8-bit 74LS164 or the 74LS594.Serial-in to Serial-out (SISO) Shift RegisterThis shift register is very similar to the SIPO above, except were before thedata was read directly in a parallel form from the outputs QA to QD, this timethe data is allowed to flow straight through the register and out of the otherend. Since there is only one output, the DATA leaves the shift register one bitat a time in a serial pattern, hence the name Serial-in to Serial-Out ShiftRegister or SISO.The SISO shift register is one of the simplest of the four configurations as ithas only three connections, the serial input (SI) which determines what entersthe left hand flip-flop, the serial output (SO) which is taken from the output ofthe right hand flip-flop and the sequencing clock signal (Clk). The logic circuitdiagram below shows a generalized serial-in serial-out shift register.4-bit Serial-in to Serial-out Shift RegisterNTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 166

You may think what‘s the point of a SISO shift register if the output data isexactly the same as the input data. Well this type of Shift Register also actsas a temporary storage device or it can act as a time delay device for the data,with the amount of time delay being controlled by the number of stages in theregister, 4, 8, 16 etc or by varying the application of the clock pulses.Commonly available IC‘s include the 74HC595 8-bit Serial-in to Serial-out ShiftRegister all with 3-state outputs.Parallel-in to Serial-out (PISO) Shift RegisterThe Parallel-in to Serial-out shift register acts in the opposite way to the serial-in to parallel-out one above. The data is loaded into the register in a parallel format in which all the databits enter their inputs simultaneously, to the parallel input pins PA to PD of the register. Thedata is then read out sequentially in the normal shift-right mode from the registerat Q representing the data present at PA to PD.This data is outputted one bit at a time on each clock cycle in a serial format. It is importantto note that with this type of data register a clock pulse is not required to parallel load theregister as it is already present, but four clock pulses are required to unload the data.4-bit Parallel-in to Serial-out Shift RegisterAs this type of shift register converts parallel data, such as an 8-bit data word into serialformat, it can be used to multiplex many different input lines into a single serial DATAstream which can be sent directly to a computer or transmitted over a communications line.Commonly available IC‘s include the 74HC166 8-bit Parallel-in/Serial-out Shift Registers.Parallel-in to Parallel-out (PIPO) Shift RegisterThe final mode of operation is the Parallel-in to Parallel-out Shift Register. This type of shiftregister also acts as a temporary storage device or as a time delay device similar to theSISO configuration above. The data is presented in a parallel format to the parallel inputpins PA to PD and then transferred together directly to their respective outputpins QA to QA by the same clock pulse. Then one clock pulse loads and unloads theregister. This arrangement for parallel loading and unloading is shown below.NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 167

4-bit Parallel-in to Parallel-out Shift RegisterThe PIPO shift register is the simplest of the four configurations as it has only threeconnections, the parallel input (PI) which determines what enters the flip-flop, the paralleloutput (PO) and the sequencing clock signal (Clk).Similar to the Serial-in to Serial-out shift register, this type of register also acts as atemporary storage device or as a time delay device, with the amount of time delay beingvaried by the frequency of the clock pulses. Also, in this type of register there are nointerconnections between the individual flip-flops since no serial shifting of the data isrequired.Application :Registers are used in digital electronic devices like computers as  Temporary data storage  Data transfer  Data manipulation  As counters.  Serial in – serial out register are used for time delays.  Serial in – parallel out registers are used for converting the data from serial form to parallel form. So these are also called ―Serial to parallel converters‖.  Parallel in – serial out registers are used for converting the data from parallel form to serial form. So these are also called ―Parallel to serial converters‖.NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 168

8.11 Bidirectional Shift Registers, Data sheets of 7491,74198 and 74199IC’sThe registers discussed so far involved only right shift operations. Each rightshift operation has the effect of successively dividing the binary number bytwo. If the operation is reversed (left shift), this has the effect of multiplying thenumber by two. With suitable gating arrangement a serial shift register canperform both operations.A bidirectional, or reversible, shift register is one in which the data can be shift either left orright. A four-bit bidirectional shift register using D flip-flops is shown below.Here a set of NAND gates are configured as OR gates to select data inputs from the right orleft adjacent bistables, as selected by the LEFT/RIGHT control line.The animation below performs right shift four times, then left shift four times.Notice the order of the four output bits are not the same as the order of theoriginal four input bits. They are actually reversed!7491Pin diagram:NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 169

This is serial-in, serial-out, 8-bit shift registers utilize TTL circuits and arecomposed of eight RS master slave FFs, input gating, and a clock driver.74198/74199Pin diagram:This is 8-bit R/L shift register. It is parallel load, hold, shift right and shift leftmodes as determined by the select inputs. State changes are initiated by therising edge of the clock.8.12 Introduction to IC Shift Registers – 74164, 74165, 7495, 74194Universal Shift RegisterToday, there are many high speed bi-directional ―universal‖ type ShiftRegisters available such as the TTL 74LS194, 74LS195 or the CMOS4035 which are available as 4-bit multi-function devices that can be used ineither serial-to-serial, left shifting, right shifting, serial-to-parallel, parallel-to-serial, or as a parallel-to-parallel multifunction data register, hence the name―Universal‖.These universal shift registers can perform any combination of parallel andserial input to output operations but require additional inputs to specify desiredfunction and to pre-load and reset the device. A commonly used universal shiftregister is the TTL 74LS194 as shown below.NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 170

7495 4-bit shift register (parallel in, parallel out)74164 8-bit shift register (serial in, parallel out)NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 171

74165 8-bit shift register (parallel in, serial out)4-bit Universal Shift Register 74LS194NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 172

Universal shift registers are very useful digital devices. They can be configured to respond to operations that require some form of temporary memory storage or for the delay of information such as the SISO or PIPO configuration modes or transfer data from one point to another in either a serial or parallel format. Universal shift registers are frequently used in arithmetic operations to shift data to the left or right for multiplication or division. Shift Register Tutorial Summary Then to summarise a little about Shift Registers A simple Shift Register can be made using only D-type flip-Flops, one flip-Flop for each data bit. The output from each flip-Flop is connected to the D input of the flip-flop at its right. Shift registers hold the data in their memory which is moved or ―shifted‖ to their required positions on each clock pulse. Each clock pulse shifts the contents of the register one bit position to either the left or the right. The data bits can be loaded one bit at a time in a series input (SI) configuration or be loaded simultaneously in a parallel configuration (PI). Data may be removed from the register one bit at a time for a series output (SO) or removed all at the same time from a parallel output (PO). One application of shift registers is in the conversion of data between serial and parallel, or parallel to serial. Shift registers are identified individually as SIPO, SISO, PISO, PIPO, or as a Universal Shift Register with all the functions combined within a single device. In the next tutorial about Sequential Logic Circuits, we will look at what happens when the output of the last flip-flop in a shift register is connected directly back to the input of the first flip-flop producing a closed loop circuit that constantly recirculates the data around the loop. This then produces another type of sequential logic circuit called a Ring Counter are used as decade counters and dividers. This serial movement of data through the resister occurs after a preset number of clock cycles thereby allowing the SISO register to act as a sort of time delay circuit to the original input data signal. But what if we were to connect the output of this shift register back to its input so that the output from the last flip-flop, QD becomes the input of the first flip-flop, DA. We would then have a closed loop circuit that ―recirculates‖ the same bit of DATA around a continuous loop for every state of its sequence, and this is the principal operation of a Ring Counter. Then by looping the output back to the input, (feedback) we can convert a standard shift register circuit into a ring counter. Consider the circuit below.NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 173

8.13 Shift Register Counters-Ring Counter, Johnson Counter & application4-bit Ring CounterThe synchronous Ring Counter example above, is preset so that exactly onedata bit in the register is set to logic ―1‖ with all the other bits reset to ―0‖. Toachieve this, a ―CLEAR‖ signal is firstly applied to all the flip-flops together inorder to ―RESET‖ their outputs to a logic ―0‖ level and then a ―PRESET‖ pulseis applied to the input of the first flip-flop ( FFA ) before the clock pulses areapplied. This then places a single logic ―1‖ value into the circuit of the ringcounter.So on each successive clock pulse, the counter circulates the same data bitbetween the four flip-flops over and over again around the ―ring‖ every fourthclock cycle. But in order to cycle the data correctly around the counter we mustfirst ―load‖ the counter with a suitable data pattern as all logic ―0‘s‖ or all logic―1‘s‖ outputted at each clock cycle would make the ring counter invalid.This type of data movement is called ―rotation‖, and like the previous shiftregister, the effect of the movement of the data bit from left to right through aring counter can be presented graphically as follows along with its timingdiagram:NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 174

Rotational Movement of a Ring CounterSince the ring counter example shown above has four distinct states, it is alsoknown as a ―modulo-4‖ or ―mod-4‖ counter with each flip-flop output having afrequency value equal to one-fourth or a quarter (1/4) that of the main clockfrequency.The ―MODULO‖ or ―MODULUS‖ of a counter is the number of states thecounter counts or sequences through before repeating itself and a ring countercan be made to output any modulo number. A ―mod-n‖ ring counter will require―n‖ number of flip-flops connected together to circulate a single data bitproviding ―n‖ different output states.For example, a mod-8 ring counter requires eight flip-flops and a mod-16 ringcounter would require sixteen flip-flops. However, as in our example above,only four of the possible sixteen states are used, making ring counters veryinefficient in terms of their output state usage.Johnson Ring CounterThe Johnson Ring Counter or ―Twisted Ring Counters‖, is another shiftregister with feedback exactly the same as the standard Ring Counter above,NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 175

except that this time the inverted output Q of the last flip-flop is now connectedback to the input D of the first flip-flop as shown below.The main advantage of this type of ring counter is that it only needs half thenumber of flip-flops compared to the standard ring counter then its modulonumber is halved. So a ―n-stage‖ Johnson counter will circulate a single databit giving sequence of 2n different states and can therefore be considered as a―mod-2n counter‖.4-bit Johnson Ring CounterThis inversion of Q before it is fed back to input D causes the counter to ―count‖ in adifferent way. Instead of counting through a fixed set of patterns like the normal ring countersuch as for a 4-bit counter, ―0001‖(1), ―0010‖(2), ―0100‖(4), ―1000‖(8) andrepeat, the Johnson counter counts up and then down as the initial logic ―1‖passes through it to the right replacing the preceding logic ―0‖.A 4-bit Johnson ring counter passes blocks of four logic ―0‖ and then four logic―1‖ thereby producing an 8-bit pattern. As the inverted output Q is connected tothe input D this 8-bit pattern continually repeats. For example, ―1000‖, ―1100‖,―1110‖, ―1111‖, ―0111‖, ―0011‖, ―0001‖, ―0000‖ and this is demonstrated in thefollowing table below.NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 176

Truth Table for a 4-bit Johnson Ring CounterClock FFA FFB FFC FFDPulse No0 0 0 001 1 0 002 1 1 003 1 1 104 1 1 115 0 1 116 0 0 117 0 0 01As well as counting or rotating data around a continuous loop, ring counterscan also be used to detect or recognise various patterns or number valueswithin a set of data. By connecting simple logic gates such as the AND orthe OR gates to the outputs of the flip-flops the circuit can be made to detect aset number or value.Standard 2, 3 or 4-stage Johnson Ring Counters can also be used to dividethe frequency of the clock signal by varying their feedback connections anddivide-by-3 or divide-by-5 outputs are also available.For example, a 3-stage Johnson Ring Counter could be used as a 3-phase,120 degree phase shift square wave generator by connecting to the dataoutputs at A, B and NOT-B.The standard 5-stage Johnson counter such as the commonly availableCD4017 is generally used as a synchronous decade counter/divider circuit.Other combinations such as the smaller 2-stage circuit which is also called a―Quadrature‖ (sine/cosine) Oscillator or Generator can be used to produce fourindividual outputs that are each 90 degrees ―out-of-phase‖ with respect to eachother to produce a 4-phase timing signal as shown below.NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 177

Unit 9 Data Converters9.1 Introduction to DAC, its symbol & Applications of DACConnecting digital circuitry to sensor devices is simple if the sensor devicesare inherently digital themselves. Switches, relays, and encoders are easilyinterfaced with gate circuits due to the on/off nature of their signals. However,when analog devices are involved, interfacing becomes much more complex.What is needed is a way to electronically translate analog signals into digital(binary) quantities, and vice versa. An analog-to-digital converter, or ADC,performs the former task while a digital-to-analog converter, or DAC,performs the latter.An ADC inputs an analog electrical signal such as voltage or current andoutputs a binary number. In block diagram form, it can be represented assuch:A DAC, on the other hand, inputs a binary number and outputs an analogvoltage or current signal. In block diagram form, it looks like this:NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 178

Together, they are often used in digital systems to provide complete interfacewith analog sensors and output devices for control systems such as thoseused in automotive engine controls:It is much easier to convert a digital signal into an analog signal than it is todo the reverse. Therefore, we will begin with DAC circuitry and then move toADC circuitry.9.2 Explain the performance parameters of DAC-Resolution, accuracyand conversion timeResolution - normally given in bits.Resolution indicates the smallest increment of its output corresponding to a 1LSB input code change. For example for 10 bit DAC, 2^10 = 1024 codes, sothe resolution is 1/1024 of the output range.Full scale range (FSR) - maximum output signal for the DAC, specified ascurrent or voltage (ma or V). Can be negative, positive or both.Offset error - difference between the ideal and actual DAC output when zero digital codeapplied to the input.Gain error - the difference between the ideal and actual output when full scale digitalcode applied to the input.Strongly depends on VREF stability. The next two important parameters, DNL and INL, areusually measured with the input code representing a ramp applied to the input of a DAC.Now it is a good time to discuss the reference line for our measurements, because it usuallyNTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 179

causes confusions and misunderstanding. The drawing below compares the ideal line, bestfit line and end-point line which is used most frequently.Max conversion rate - it is the maximum input signal frequency the DAC can handle. Theworst case is when input signal changes from zero to max, and the output should reach themax level and settle.Settling time - the time required for the output to reach the final value and remain within +/-1 LSB after overshoot.PSRR - power supply rejection ratio. The output signal should remain within limits whilepower supply voltage changes from Min to Max.9.3 binary weighted resistor DAC & R-2R Ladder type DACBINARY-WEIGHTED RESISTOR DACThe binary-weighted-resistor DAC employs the characteristics of the inverting summer OpAmp circuit. In this type of DAC, the output voltage is the inverted sum of all the inputvoltages. If the input resistor values are set to multiples of two: 1R, 2R and 4R, the outputvoltage would be equal to the sum of V1, V2/2 and V3/4. V1 corresponds to the mostsignificant bit (MSB) while V3 corresponds to the least significant bit (LSB).The circuit for a 4-bit DAC using binary weighted resistor network is shown below:NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 180

The binary inputs, ai (where i = 1, 2, 3 and 4) have values of either 0 or 1. The value, 0,representsan open switch while 1 represents a closed switch.The operational amplifier is used as a summing amplifier, which gives a weighted sum ofthebinary input based on the voltage, Vref.For a 4-bit DAC, the relationship between Vout and the binary input is as follows:The negative sign associated with the analog output is due to the connection to a summingamplifier, which is a polarity-inverting amplifier. When a signal is applied to the latter type ofamplifier, the polarity of the signal is reversed (i.e. a + input becomes -, or vice versa).For a n-bit DAC, the relationship between Vout and the binary input is as follows:Analog Voltage Output: An ExampleAs an example, consider the following given parameters: Vref = 5 V, R = 0.5 k and Rf = 1 k.Thevoltage outputs, Vout, corresponding to the respective binary inputs are as follows:NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 181

Table 1: Voltage Output of 4-bit DAC using Binary Weighted Resistor NetworkThe LSB, which is also the incremental step, has a value of - 0.625 V while the MSB or thefullscale has a value of - 9.375 V.Practical Limitations:The most significant problem is the large difference in resistor values required betweenthe LSB and MSB, especially in the case of high resolution DACs (i.e. those that has largenumber of bits). For example, in the case of a 12-bit DAC, if the MSB is 1 k, thenthe LSBis a staggering 2 M.The maintanence of accurate resistances over a large range of values is problematic. Withthe current IC fabrication technology, it is difficult to manufacture resistors over a wideresistance range that maintain an accurate ratio especially with variations in temperature.NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 182

R-2R Ladder type DACAn alternative to the binary-weighted-input DAC is the so-called R/2R DAC, which usesfewer unique resistor values. A disadvantage of the former DAC design was itsrequirement of several different precise input resistor values: one unique value per binaryinput bit. Manufacture may be simplified if there are fewer different resistor values topurchase, stock, and sort prior to assembly.Of course, we could take our last DAC circuit and modify it to use a single input resistancevalue, by connecting multiple resistors together in series:Unfortunately, this approach merely substitutes one type of complexity for another:volume of components over diversity of component values. There is, however, a moreefficient design methodology.By constructing a different kind of resistor network on the input of our summing circuit, wecan achieve the same kind of binary weighting with only two kinds of resistor values, andwith only a modest increase in resistor count. This ―ladder‖ network looks like this:Mathematically analyzing this ladder network is a bit more complex than for the previouscircuit, where each input resistor provided an easily-calculated gain for that bit. For thoseNTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 183

who are interested in pursuing the intricacies of this circuit further, you may opt to useThevenin‘s theorem for each binary input (remember to consider the effects of the virtualground), and/or use a simulation program like SPICE to determine circuit response. Eitherway, you should obtain the following table of figures:Binary Output voltage 000 0.00 V 001 -1.25 V 010 -2.50 V 011 -3.75 V 100 -5.00 V 101 -6.25 V 110 -7.50 V 111 -8.75 VAs was the case with the binary-weighted DAC design, we can modify thevalue of the feedback resistor to obtain any ―span‖ desired. For example, ifwe‘re using +5 volts for a ―high‖ voltage level and 0 volts for a ―low‖ voltagelevel, we can obtain an analog output directly corresponding to the binaryinput (011 = -3 volts, 101 = -5 volts, 111 = -7 volts, etc.) by using a feedbackresistance with a value of 1.6R instead of 2R.9.4. IC-1408 / 832 DAC with pin configurationThe 1408 DAC is a 8 bit DAC, that is it takes 8 parallel digital signals from themicroprocessor or microcontroller. Internally it has 8 current switches whichare controlled by the 8 digital inputs, R-2R resistor network, reference currentamplifier. It has 16 pins and produces current output.The pin diagram of MC1408 is shown below,NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 184

This DAC requires 2mA reference current input and voltage supplies of +5VVcc and -15V Vee.The MC1408 produces current output at pin 4. This is converted to voltageusing op-amp like 741. The MC1408 can be operated in unipolar mode orpolar mode.A typical MC1408 circuit producing unipolar voltage output is shown below,The current output equation is given by,The A1 to A8 denotes the digital inputs which can take values 0 or 1. For these 8 inputs wehave 2^8=256 bit combination and therefore we have 256 different current magnitude at theoutput pin 4. also note that the current direction is inward which indicates that the device issinking current. We get maximum current when A1 to A8 are all 1 in which case we get theoutput current as 1.992mA which is 1 LSB less than current reference of 2mA.The op-amp connected to the output converts the current into voltage. The output voltage isthen,Vo = Io * Rf = 4.98V which is also less by 1 LSB from 5V.So when digital input is 00H we get 0V output and when the input is FFH then we get 4.98V.Hence this circuit is called unipolar DAC.The above circuit can be modified to produce bipolar analog voltage. For this, a resistor Rbis connected Vref and the output current pin as shown,NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 185

In this case, when the input is 00H the output current is zero. Due to this the1mA current flows from Vref through Rb and through Rf into the output and theoutput voltage is -4.98V. When binary input is 80H the output current at pin 4 is1mA which causes the output voltage to be 0V. Final condition is that when thedigital data input is FFH the output current is 2mA which then produces aoutput voltage of -4.98V.9.5 Introduction - Logic symbol - A/D ConversionWhat is an analog-digital converter?an analog-to-digital converter (ADC, A/D, A–D, or A-to-D) is a system thatconverts an analog signal, such as a sound picked up by a microphone or lightentering a digital camera, into a digital signal. An ADC may also provide anisolated measurement such as an electronic device that converts an inputanalog voltage or current to a digital number proportional to the magnitude ofthe voltage or current.Typically the digital output is a two's complement binary number that isproportional to the input, but there are other possibilities.There are several ADC architectures. Due to the complexity and the need forprecisely matched components, all but the most specialized ADCs areimplemented as integrated circuits (ICs).A digital-to-analog converter (DAC) performs the reverse function; it converts adigital signal into an analog signal.NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 186

The Sampler subsystem is the front-end of the correlator system. Its main task is to convertthe analog signals coming from the various antennae to digital format which can be furtherprocessed. Analog signals are continuous in time and amplitude, existing at every instant oftime with any possible intermediate amplitude values. DSPs mathematically process signalrepresented as a series of numbers that are discrete in time and amplitude. Analog toDigital Conversion (ADC) consists of sampling, hold, quantize and code. Sometimesthese four functions are integrated into one device( ADC card ).SamplingSampling converts a signal that is continuous in time to one that is discrete in time.Sampling is done in accordance with the Nyquist Theorem that states that if sampling isperformed at a rate exceeding the Nyquist rate or two times the bandwidth of the signal, nosignal information is lost. The number of samples taken per second is called the samplingrate or sampling frequency.Hold and QuantizeAfter sampling the signal is discrete in time but it is still continuous in amplitude. The signalis made discrete in amplitude as well by quantizing or representing each signal as a numberwith finite resolution. A hold function is used to maintain the sampled value constant duringthe time it takes to quantize the signal. Flash converters are used for this task. Flashconverters use a bank of comparators and voltage references, one for each quantizationlevel. Unlike Nyquist sampling, which loses no information, quantizing produces an errorcalled quantizing error. The difference between the exact value and the quantized value isthe quantizing error.CodingCoding is the representation of the quantized value in a particular numerical format usuallya form of binary. The various codes used for bipolar signals differ in their representation ofthe sign and the transition from positive to negative values.NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 187

9.6 Performance parameters1. Resolution2.Speed3. Linearity4. Settling Time5. Reference Voltages6. Errors7. Conversion time1.ResolutionDAC‗s typically come in 8-, 10-, 12-, 14-, 16-, & 18-bitversions.8-bit type ischeaper but 12-bit DAC‗s are very popular because they are a good balancebetween cost and accuracy. 14- and 16-bit types are expensive.Resolution =VR/2N2. SpeedWhen the input changes rapidly, the conversion speed must be high.3. LinearityMaximum deviation from the expected value over the full range of the output.Often expressed as a percentage of the full scale voltage.4. Settling TimeThis is the time it takes a converter to settle within +/- 1/2 of a LSB of its finalvalue when a change occurs in the input code.5. Reference Voltages.Given by IC manufacturer‗s data sheet.NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 188

6. Errorsa .Gain Errorb. Offset Errorc. Full Scale ErrorD.Non-monotonic Output Errore.Diff- Non-linearity Error (A.K.A. Linearity Error)f. Settling Time and Overshoot Errorg. Resolution Error7. Conversion timeConversion is time required for ADC to convert each analog level to its digitalformat.8. MonotonicityA monotonic DAC is the one whose analog output increases for an increase indigital input.9. StabilityThe performance of converter changes with temperature,age and powersupply variations.9.7 Types of ADCRamp type (single slope) & Dual slope - A/D ConverterAlso known as the stairstep-ramp, or simply counter A/D converter, this isalso fairly easy to understand but unfortunately suffers from severallimitations.The basic idea is to connect the output of a free-running binary counter tothe input of a DAC, then compare the analog output of the DAC with theanalog input signal to be digitized and use the comparator‘s output to tell thecounter when to stop counting and reset. The following schematic shows thebasic idea:NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 189

As the counter counts up with each clock pulse, the DAC outputs a slightly higher (morepositive) voltage. This voltage is compared against the input voltage by the comparator. Ifthe input voltage is greater than the DAC output, the comparator‘s output willbe high and the counter will continue counting normally. Eventually, though,the DAC output will exceed the input voltage, causing the comparator‘soutput to go low. This will cause two things to happen: first, the high-to-lowtransition of the comparator‘s output will cause the shift register to ―load‖whatever binary count is being output by the counter, thus updating the ADCcircuit‘s output; secondly, the counter will receive a low signal on the active-low LOAD input, causing it to reset to 00000000 on the next clock pulse.The effect of this circuit is to produce a DAC output that ramps up towhatever level the analog input signal is at, output the binary numbercorresponding to that level, and start over again. Plotted over time, it lookslike this:NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 190

Note how the time between updates (new digital output values) changesdepending on how high the input voltage is. For low signal levels, theupdates are rather close-spaced. For higher signal levels, they are spacedfurther apart in time:For many ADC applications, this variation in update frequency (sample time) would not beacceptable. This, and the fact that the circuit‘s need to count all the way from0 at the beginning of each count cycle makes for relatively slow sampling ofthe analog signal, places the digital-ramp ADC at a disadvantage to othercounter strategies.9.8 Flash ADCAlso called the parallel A/D converter, this circuit is the simplest tounderstand. It is formed of a series of comparators, each one comparing theinput signal to a unique reference voltage. The comparator outputs connectto the inputs of a priority encoder circuit, which then produces a binaryoutput. The following illustration shows a 3-bit flash ADC circuit:NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 191

Vref is a stable reference voltage provided by a precision voltage regulator aspart of the converter circuit, not shown in the schematic. As the analog inputvoltage exceeds the reference voltage at each comparator, the comparatoroutputs will sequentially saturate to a high state. The priority encodergenerates a binary number based on the highest-order active input, ignoringall other active inputs.When operated, the flash ADC produces an output that looks something likethis:NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 192

For this particular application, a regular priority encoder with all its inherent complexityisn‘t necessary. Due to the nature of the sequential comparator output states(each comparator saturating ―high‖ in sequence from lowest to highest), thesame ―highest-order-input selection‖ effect may be realized through a set ofExclusive-OR gates, allowing the use of a simpler, non-priority encoder:And, of course, the encoder circuit itself can be made from a matrix ofdiodes, demonstrating just how simply this converter design may beconstructed:NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 193

Not only is the flash converter the simplest in terms of operational theory, butit is the most efficient of the ADC technologies in terms of speed, beinglimited only in comparator and gate propagation delays. Unfortunately, it isthe most component-intensive for any given number of output bits. Thisthree-bit flash ADC requires seven comparators. A four-bit version wouldrequire 15 comparators. With each additional output bit, the number ofrequired comparators doubles. Considering that eight bits is generallyconsidered the minimum necessary for any practical ADC (255 comparatorsneeded!), the flash methodology quickly shows its weakness.An additional advantage of the flash converter, often overlooked, is the abilityfor it to produce a non-linear output. With equal-value resistors in thereference voltage divider network, each successive binary count representsthe same amount of analog signal increase, providing a proportionalresponse. For special applications, however, the resistor values in the dividernetwork may be made non-equal. This gives the ADC a custom, nonlinearresponse to the analog input signal. No other ADC design is able to grant thissignal-conditioning behaviour with just a few component value changes.NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 194

9.8 Successive Approximation ADCOne method of addressing the digital ramp ADC‘s shortcomings is the so-called successive-approximation ADC. The only change in this design is avery special counter circuit known as a successive-approximation register.Instead of counting up in binary sequence, this register counts by trying allvalues of bits starting with the most-significant bit and finishing at the least-significant bit. Throughout the count process, the register monitors thecomparator‘s output to see if the binary count is less than or greater than theanalog signal input, adjusting the bit values accordingly. The way the registercounts is identical to the ―trial-and-fit‖ method of decimal-to-binaryconversion, whereby different values of bits are tried from MSB to LSB to geta binary number that equals the original decimal number. The advantage tothis counting strategy is much faster results: the DAC output converges onthe analog signal input in much larger steps than with the 0-to-full countsequence of a regular counter.Without showing the inner workings of the successive-approximation register(SAR), the circuit looks like this:It should be noted that the SAR is generally capable of outputting the binary numberin serial (one bit at a time) format, thus eliminating the need for a shift register. Plottedover time, the operation of a successive-approximation ADC looks like this:NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 195

Note how the updates for this ADC occur at regular intervals, unlike the digital ramp ADCcircuit.9.9 . ADC IC 0808 / 0809ADC0808 is a converter which has 8 analog inputs and 8 digital outputs. ADC0808 allows us to monitor up to 8 different transducers using only asingle chip. This eliminates the need for external zero and full scaleadjustments.ADC0808 is a monolithic CMOS device, offers high speed, high accuracy,minimal temperature dependence, excellent long-term accuracy andrepeatability and consumes minimal power. These features make this deviceideally suited to applications from process and machine control to consumerand automotive applications. The pin diagram of ADC0808 is shown in figurebelow:Features: Easy interface to all microprocessors No zero or full-scale adjust required 8-channel multiplexer with address logic 0V to 5V input range with single 5V power supply Outputs meet TTL voltage level specifications Carrier chip package with 28-pinNTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 196

Specifications: Resolution: 8 Bits Total Unadjusted Error: ±½ LSB and ±1 LSB Single Supply: 5 VDC Low Power: 15 mW Conversion Time: 100 μsGenerally, the ADC0808 input which is to be changed over to digital form canbe selected by using three address lines A, B, C which are pins 23, 24 and 25.The step size is chosen dependent upon set reference value. Step size is thechange in analog input to cause a unit change in the output of ADC. ADC0808needs an external clock to operate unlike ADC0804 which has an internalclock.The continuous 8-bit digital output corresponding to instantaneous value ofanalogue input. The most extreme level of input voltage must be reducedproportionally to +5V.The ADC 0808 IC requires clock signal of typically 550 kHz, ADC0808 is usedto convert the data into digital from required for the microcontroller.Application of ADC0808:The ADC0808 has got many applications; here we have given someapplication on ADC:From the below circuit the clock, start and EOC pins are connected tomicrocontroller. Generally, we have 8 inputs; here we are using only 4 inputsfor the operation. LM35 temperature sensor is using which is connected to fist 4 inputs of the analog to digital convertor IC. The sensor has got 3 pins i.e., VCC, GND and output pins, when the sensor heated the voltage at output increases. The address lines A, B, C are connected to microcontroller for the commands. In this the interrupt follows the low to high operation. When the start pin is held high no conversion begins, but when the start pin is low the conversion will start within 8 clock periods. The point when the conversion is completed the EOC pin goes low to indicate the finish of conversion and data ready to be picked up.NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 197

The output enable (OE) is then raised high. This enables the TRI-STATEoutputs, allowing the data to be read.Data sheet of IC 0808/0809 Added as annexure 1NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 198

Unit 10 Integrated logic families10.1 Introduction to logic families A logic family may refer to one of two related concepts. A logic family of monolithic digital integrated circuit devices is a group of electronic logic gates constructed using one of several different designs, usually with compatible logic levels and power supply characteristics within a family.The type of transistors with which all integrated circuits are implemented are either bipolar junction transistors or MOSFETs . Two types of digital circuit technology that use bipolar junction transistors are TTL and ECL. Of these two TTL is most widely used. The major circuit technologies that use MOSFETs are CMOS and NMOS. Microprocessors use MOS technology.10.2 TTL Logic- CMOS LOGIC Transistor-Transistor Logic, refers to the technology for designing and fabricating digital integrated circuits that employ logic gates consisting primarily of bipolar transistors. It overcomes the main problem associated with DTL, i.e., lack of speed. The input to a TTL circuit is always through the emitter(s) of the input transistor, which exhibits a low input resistance , the output taken from its collector.Circuit operation: LOW state, current-sinkingCircuit operation: HIGH state, current-sourcing.NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 199

TTL Circuits are: • TTL Inverter • TTL NAND gate • Open-collector TTL gates • Tristate TTL gates • Schottky TTL NAND gateT.T.L InverterT.T.L NAND GATE Page 200NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017