DE_MF

5.6 MULTIPLEXERS (Dat A multiplexers (MUX) isinformation from several sourcefor transmission over that line to The basic multiplexers hassingle output line. It also has ddigital data on any one of thoutput line.

ta Selectors) a device that allows digitales to be routed onto a single lineo a common destination. several data input lines and adata- select inputs, which permithe inputs to be switched to the 50

MUX-continued... A modern stereo system may h from one of four sources: a cass an auxiliary input such as au switch selects one of the electr four sources and sends it to the In simple terms, this is what selects one of several input s output.

have a switch that selects musicsette tape, CD, a radio tuner , orudio from a VCR or DVD. The ronic signals from one of these power amplifier and speakers.t a multiplexer (MUX) does; itsignals and passes it on to the 51

Functional diagram

m of MUX 52

Two-input multip

plexer 53

Four-input multiplex

xer 54

Logic symbol for a 1-o selector / multiplex

of-4 data xer 55

Logic symbol for a 1 selector/multip

1-of-4 dataplexer 56

DEMULTIPLEXERS A DEMULTIPLEXER (DEMUmultiplexing function. It takes datthem to a given number of outdemultiplexers is also known as a A multiplexer takes several into the output. A demultiplexer (DEMUX) petakes a single input and distributes

UX) basically reverses the ta from one line and distributestput lines. For this reason, thea data distributor.nputs and transmits one of themerforms the reverse operation ; it s it over several outputs. 57

General demultip T lin w tr In o one dist just

plexer The large arrow indicates one or more nes. The select i/p code determines to which output the DATA input will be ransmitted other words, the demultiplexer takes e data input source and selectively tributes it to 1 of N output channels t like multiposition switch. 58

A 1-line-to-4-line demu

ultiplexer 59

5.7 Parity Generators and What is parity bit The parity generating technique is detection techniques for the data when binary data is transmitted subjected to noise so that such no and 1s to 0s. Hence, parity bit is added to the make number of 1s either even or , during the transmission of binary data bits along with parity bit is tr receiver node. At the receiving end, the number o if it doesn’t match with the transmi error in the data.

d Checkerss one of the most widely used errora transmission. In digital systems,d and processed , data may beoise can alter 0s (of data bits) to 1se word containing data in order to odd. Thus it is used to detect errorsy data .The message containing theransmitted from transmitter node toof 1s in the message is counted and itted one, then it means there is an 60

Parity Genera It is combinational circuit that ac generates the additional bit that stream. This additional or extra bit i In even parity bit scheme, the number of 1s in the data stream are odd number of 1s in the data s In odd parity bit scheme, the parity of 1s in the data stream and the number of 1s in the data stream. parity generators.

atorccepts an n-1 bit stream data and is to be transmitted with the bit is termed as a parity bit. parity bit is ‘0’ if there are evenm and the parity bit is ‘1’ if there stream. y bit is ‘1’ if there are even number e parity bit is ‘0’ if there are odd. Let us discuss both even and odd 61

Even Parity Gen Let us assume that a 3-bit me an even parity bit. Let the thre to the circuits and output bit number of 1s must be even, to The figure below shows th generator in which 1 is placed 1s as even when the number o

nerator essage is to be transmitted withee inputs A, B and C are applied t is the parity bit P. The totalo generate the even parity bit P.he truth table of even parity as parity bit in order to make all of 1s in the truth table is odd. 62