altair_8800b

SCHOTTKY BIPOLAR 8212 8080 SYSTEM INPUT PORTS OUTPUT PORTS I I STROBE 0 - STB ..... c:::>INPUT 8212 ~8212 OUTPUT PORT 0l PORT 0 ISee Note 11 iNT CLR l0- r-< CLR AAo -,_ -~ G~OC- _---=r vi ..~ ee 8080 A2 - 8205 -~ STROBE 1 - STB ADDRESS ... A:J-<: E, l q1INPUT 8212 ......... ~8212 1OUTPUT A4 -< E2 BUS PORT PORT Vee - E., iNi' Ci:R po ~ CLR 1/0 DEVICE 9 GND C- ~ Vee 9 SELECTOR INP 2 _STROBE STB I ...Jl. STATUS _ 2INPUT!q 8212 ...E':. F>, 8212 2OUTPUT BITS PORT PORT iNT CLR 10- +-:: Ci:R 9 GND c:....... I---.:J V(\"(\" 9 LOUT STROBE 3 - STB INT - - - - - - - - - - - - - - - - - - - , 8212INPUT,~ 8212 I-V~ OUTPUT PORT 3 1ro- -, PORT 3 \\-,I .------d iNT Ci:R P- BUFFERED I IIQ~~DC-I \", Vee OATA I II III STROBE 4 - STB I BUS Vee I I INPUT,~ I ~i~li~~~~PO:R~T~~4~=~~8;21~2~~;~J::lj[IJf;~~82~1;2I ...Jl. Ih-V. OUTPUT PORT 4 8080 ... ~l8212 -- I 2 II , OATAC: •.~ 8212 :57 I \" r+-:: CLR BUS r\"'\" rINT CLR po ...f--,.:.J Vee I !L,-..........:~: :~ G~O -e-I- I !I V~e STROBE5- STB GND I I I 8212INPUT ~ 8212 :-v'oJ>... OUTPUT I'- .JI PORT5~ PORT 5 L-----OI iiiiT CLR 0- INTERRUPT f GND L..- INSTRUCTION I STROBE6- STB PORT IRST) 3212INPUT, ,.....,.., Up PRIORITY .. 8212 h /~ OUTPUT PORT 6l....y' PORT 6 GND ENCODER & INTERRUPT L------OIINT Ci:R 10- AINCKT - - - - - - - - - i i J - - - - ' GENERATING LOGIC CIRCUITS r G1o·e- BI·DIRECTIONAL IUSER OESIGNEDI . BUS ORIVER I..8212INPUT ~ PORT7~ STROBE 7 - STB JoI.~' \"-...[ I\" 8212 hoi~ OUTPUT PORT 7 <:: L--- od .........TG~D L..--!Nt,CLR , I- H- 4 CUi ~ SYSTEM_ RESET 1. 8080 256 8212Note This baSIC 1/0 configuration for the and lhe appropriate decoding. can be expanded to input deVices and 256 output devices all using

SCHOTTKY BIPOLAR 8212 Absolute Maximum Ratings * Temperature Under Bias Plastic .. -65°C to +75°C ·COMMENT. Stresses above t!lose lis/ed under \"Absolute Muimum Ratings\" Storage Temperature -65°C to +160°C may cause permenent damage to the device. Tllis 1$ a stress rating only and functional operation of the device at these or at any OU'Ier condition above these rndjcated in the operational sections of this specifIcatIon is not implied. All Output or Supply Voltages -0.5 to + 7 Volts All Input Voltages -1.0 to 5.5 Volts Output Currents ' 125 rnA D.C. Characteristics TA = O°C to + 75°C Vec == +5V ±5% Symbol Parameter Limits Unit Test Conditions Typ. rnA IF Input Load Current Min. Max. VF = .45V ACK, OS2' CR, Ol,-Olll Inputs 4.0 -.25 2.0 90 VF == .45V IF Input Load Current 3.65 -.75 I rnA MO Input -1.0 VF = .45V -15 10 I rnA IF Input Load Current VR == 5.25V OS, Input I VR = 5.25V IR Input Leakage Current p..A VR = 5.25V ACK, OS. CR, Ol,-Olll Inputs 30 p..A Ie == -5 rnA IR Input Leakage Current MO Input 40 ,u.A 10L == 15 rnA IR Input Leakage Current -1 V IOH = -1 mA OS, Input .85 V Va = OV Ve Input Forward Voltage Clamp V V!L Input \"Low\" Voltage .45 V Vo = .45V/S.25V V1H Input \"High\" Voltage V VOL Output \"Low\" Voltage -75 rnA 20 p.A VOH Output \"High\" Voltage 130 rnA Isc Short Circuit Output Current :1 01 Output Leakage Current High Impedance State lec Power Supply Current 3-24 Apr; i, 19n 8800b

SCHOTTKY BIPOLAR 8212 Typical Characteristics INPUT CURRENT VS. INPUT VOLTAGE OUTPUT CURRENT VS. OUTPUT \"LOW\" VOLTAGE o I k ~I 100..----..----..,...----,----.., Vee' +5.ov -so vee' +5.0V I8 0 1 - - - - . . l - - - -.......----1----~ .< -100 I 1I .3 FrI I I ~ 6 O f - - - - + - . - - -......----'-..\".~C-_1 z ! I 'aa\":: ...'~\" -150 TA .crc~ ~TA'25\"C i I ~TA'~C I :l :l :I I <.l <.l :l ,, I I I ..S 401----4--~---::.~~:...;...---~ ~ -200 I I I o:l Ii I ! \\ i 201----I--no~=--------~ ii, ! , I ,I -250 : I I i i!I I ! I I! 01.-_ _ ..l_ .J -300 0iGil~ .8 -3 -2 -1 o +1 +2 +3 o2 .4 .6 INPUT VOLTAGE IVI OUTPUT \"LOW'\" VOLTAGE (V, OUTPUT CURRENT VS. DATA TO OUTPUT DELAY OUTPUT \"HIGH\" VOLTAGE VS. LOAD CAPACITANCE o , . - - - \" \" : - - - - - - . . . , - - - - r -_ _ 50,.----------...,...-----. vee' +e.OV ! -5 f----I +---i -~-..........- - - - , / - ' H - - i i 4 0 1 - - - - -.. . ; . . . - - . . l - - - - - - - - - I - 1 0 1 - - -.......- - - + - - · ,,\" -- --301----·--1---;--.....,.----....,.,~ I \"\".. .... -151---...:.----....---7':;64=---·-.:..-.---1 \\ 'r 'r ..\",. .... ·201---....,....--.,..,.~- 20 I-----\".,....\". ~\"--=_~~-----I 10 -30 I-~~:..-------+-------l 1.0 2.0 3.0 4.0 5.0 00L.---50---,00---,..i.SO---200--2..i.SO--..J3oo OUTPUT \"HIGH\" VOLTAGE {V, LOAD CAPACITANCE (pFl DATA TO OUTPUT DELAY WRITE ENABLE TO OUTPUT DELAY VS. TEMPERATURE vs. TEMPERATURE I2 2 , . . - - - . . . , - - - . . . , . . - - . . . , - - - . , . - - - 40,----,- : - \" , , - - _ , _ Vee' +eI.OV ' ii, vee' +5.0V I I I I: 201-,- - - ; i - - - - - - - ' - - i - - - - i i - - - - - I 351-----; /1>.«... 18 f----!-i,---,---I ___.-II-:\"-, L-J----.1 301------ -~----_.---;-- 'Q\". ,;,-\",\"\"r I, ----- ........\\;..~ . I:ol ::l 16 f---\";!---::\"''''''=..,,------+---1 2S 1---_....0-- - ----.----- o#\".e.~ \" .. <:..~---; : .,,;;, i i STB .... - c \" ,..r+; _ :---...:.'.;,;,--ir-......~ .« 14 f-.....,.----....,....-----:--~\"----.1Q DSz '~;..........-. -- _ ...,. -,_.----i ..« ! i 20 D5,~, --- • Q 12 f - - -......- - - - - - - J .i - - - ' \" - - - - I 151---- ._- --'---'~---1 !i 1~2L.5------J\"'5---SO---7\"\"'5.--~100 ,~2S·'\":---......---2.,.5--....S. O---7.,.5--~,oo TEMPERATURE I'CI TEMPERATURE ( Cl April, i9i7 3-25 88COb

SCHOTTKY BIPOLAR 8212 Timing Diagram 1.svX---------Y.sv DATA -----~ . .\\'·SV'_.s...lVI~-----:..'._-- tpw.. :. tH:~--- ST8 0' 5S,_._D_S2 10:-------r--tvvE~ OUTPUT _ _ _ _ _ _ _ _ _ _ _ _ -J , \",.~ L5V! '}.'_.s_V _ ~ to--1 ~ r- IE -: - - - - - - - - - __OUTPUT ----------..,~r (SEE NOTE BELOWl _______ J\\ r~'==== l.SVr\\ 1,SVetA tP'IV---j DO · I. te ..-.-I.IVV----- DATA \"SV';(---------y'5V -----~ - _. ~--- tSET 'SV-\\'- ST8 0' 65, • DS2 ~V----------· OUTPUT ------_--1 IST8 \\\"l.5V ----- - tpw _ , '------------------- \\,---{L5V ts~-- tpw • I. • I N,OTE: ALTERNATIVE TEST LOAD \\\"'---_----.JF 3-26 Aoril. i977 3aOGb

SCHOTTKY BIPOLAR 8212 A.C. Characteristics =T,.., OOC to + 75 0 C Vee = +5V :t 5% I Parameter Limits Unit Test Conditions Symbol I Typ. Min. Max. ns I 30 ns 30 ns i 40 ns ns , 40 ns ns Pulse Width 30 ns ns Data To Output Delay I 45 Write Enable To Output Delay [ 55 D~aS~upTIme I 15 Data Hold Time 20 t Reset To Output Delay t, Set To Output Delay t. Output Enable/Disable Time Clear To Output Delay CAPACITANCE\" F .. 1 MHz VOl'S - 2.5V Vee - +5V T. - 25°C Symbol Test UMITS Typ. Max. OS, MO Input Capacitance 9 pF 12 pF OS2' CK, ACK, 01,-019 5 pF 9 pF Input Capacitance COUT OO,-OOg Output Capacitance 8 pF 12 pF \"This parameter is sampled and not 100% tested. Switching Characteristics TEST LOAD 15mA & 30pF CONDITIONS OF TEST TO 300 Input Pulse Amplitude = 2.5 V D.U.T. 600 Input Rise and Fall Times 5 ns I\"30pF Between 1V and 2V Measu rements made at 1.5V with 15 mA & 30 pF Test Load \" INCLUDING JIG & PROBE CAPACITANCE April, 1977 3-27 8S00b

inter Schottky Bipolar 8216/8226 4 BIT PARALLEL BIDIRECTIONAL BUS DRIVER • Data Bus Buffer Driver for 8080 CPU • 3.65V Output High Voltage for Direct Interface to 8080 CPU • Low Input Load Current - .25 mA Maximum • Three State Outputs • High Output Drive Capability for • Reduces System Package Count Driving System Data Bus The 8216/8226 is a 4-bit bi-directional bus driver/receiver. All inputs are low power TTL compatible. For driving MOS, the DO outputs provide a high 3.65V VOH. and for high capaci· tance terminated bus structures, the DB outputs provide a high 50mA IOl capability. A non-inverting (8216) and an inverting (8226) are available to meet a wide variety of applications for buffering in micro- computer systems. PIN CONFIGURATION LOGIC DIAGRAM LOGIC DIAGRAM 8216 8226 cs 18 vee 010 010 080 15 5iEiii 0°0 080 OB, 000 14 01, DB: 003 00, 000 O~ os., 4 8216/ 13 O~ 012 5 8226 12 O~ 01, • cs 010 002 08 , 00, 6 11 OB2 OB, 7 O~ 00, 8 01, 012 OB2 GND 0°2 PIN NAMES 0°2 013 O~ OB3 080·D~ OATA BUS 0°3 Bl-OlR,eCTIONAI. OleN 003 I 01o·0~ OATAINPUT cs 000.003 DATA OUTPUT OleN OleN DATA IN eNA81.e DIReCTION CONTROl. C! CHIP se I.eCT 3-28 Apr; 1, 1977 8800b

SCHOTTKY BIPOLAR 8216/8226 FUNCTIONAL DESCRIPTION .----oO~ Microprocessors like the 8080 are MOS devices and are oooo---l--{\"l-+---1 generally capable of driving a single TTL load. The same is true for MOS memory devices. While this type of drive is .--.-,08, sufficient in small systems with few components, quite often DO, o---~I-_~-+--J it is necessary to buffer the microprocessor and memories when adding components or expanding to a multi·board 012 0----4--1 \"':l_-I.- .... system. j ..----0082 The 8216/8226 is a four bit bi-directional bus driver specif· :,: bfp_-oo002o---.......I,;..._~I--+--J ically designed to buffer microcomputer system components. 083 Bi-Directional Driver ~_R R Each buffered tine of the four bit driver consists of two (a) 8216 separate buffers that are tri·state in nature to achieve direct bus interface and bi-directional capability. On one side of 010 o------nlO--I.-.... the driver the output of one buffer and the input of another are tied together (DBl. this side is used to interface to the 01, 0----4--I>c-+_--. system side components such as memories, I/O, ete., be- cause its interface is direct TTL compatible and it has high DO, o-----1-ooc~-_!_.....J drive (SOmA). On the other side of the driver the inputs and outputs are separated to provide maximum flexibility. 1.-_ _4 ..... 00 cs Of course, they can be tied together so that the driver can be used to buffer a true bi·directional bus such as the 8080 D i E N o - -. . . .- , . . . - - - - l Data Bus. The DO outputs on this side of the driver have a special high voltage output drive capability (3.65Vl so that (b) 8226 direct interface to the 8080 and 8008 CPUs is achieved with an adequate amount of noise immunity (350m V worst case). ; OlEN i cs : - - -Control Gating OlEN, CS o 0' 01- 08 The CS input is actually a device select. When it is \"high\" 1 008-00 the output drivers are all forced to their high·impedance state. When it is at \"zero\" the device is selected (enabled) o1 and the direction of the data flow is detenTlined by the OlEN input. -HIGH IMPEOANCE i 1 ;1 The OlEN input controls the direction of data flow (s~ Figure 11 for complete truth table. This direction control is accomplished by forcing one of the pair of buffers into its high impedance state and allowing the other to transmit its data. A simple two gate circuit is used for this function. The 8216/8226 is a device that will reduce component count in microcomputer systems and at the same time enhance noise immunity to assure reliable, high performance Ope eration. Figure 1. 8216/8226 Logic Diagrams Apr; 1. 19i7 3-29 38000

SCHOTTKY BIPOLAR 8216/8226 D.C. AND OPERATING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS· Temperature Under Bias o°C to 70°C Storage Temperature -65°C to +150°C All Output and Supply Voltages , -0.5V to +7V All Input Voltages : -1.0Vto+5.5V Output Currents '.' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 125 mA ·COMMENT: Stresses above those listed under \"Absolute Maximum Rating\" may caUSlt permanent damage to the device. This is a stress rating only and functional operation of the dlYic:e at these or at any other condition above those indic:ated in the ooerational sections of this specifi· cation is not implied. Symbol Parameter Min. Limits Unit Conditions Typ. Max. IFl Input Load Current OlEN, CS -0.15 -.5 mA VF =0.45 IF2 Input Load Current All Other Inputs -0.08 -.25 mA VF-0.45 IRl Input Leakage Current OlEN, CS 20 JJ,A VR =5.25V IR2 Input Leakage Current 01 Inputs 10 JJ,A VR =5.25V - Vc Input Forward Voltage Clamp -1 V Ic= -5mA V1L Input \"Low\" Voltage .95 V VIH Input \"High\" Voltage 2.0 V 1101 Output Leakage Current DO 20 JJ,A Va - 0.45V/5.25V 100 (3-Statel IDB 8216 95 130 mA I Icc Power Supply Current 85 120 mA 8226 VOLl Output \"Low\" Voltage 0.3 .45 V DO Outputs 10L=15mA DB Outputs 10L-25mA VO L2 8216 3.65 0.5 I .6 V DB Outputs 10L=55mA Output \"Low\" Voltage 0.5 .6 DB Outputs 10L=50mA VO H1 2.4 IV DO Outputs 10H - -lmA VOH2 8226 -15 4.0 DB Outputs 10H = -lamA los Output \"High\" Voltage -30 I DO Outputs Vo==OV. Output \"High\" Voltage DB Outputs Vcc=5.0V Output Short Circuit Current V 3.0 V -35 -65 mA -75 -120 mA NOTE: Tvpic:al values are for TA\" 25\"C, VCC-S.OV. -- 3-31 April. 1977 8800b

SCHOTTKY BIPOLAR 8216/8226 WAVEFORMS X~\"-j...J \"\"'_5Y INPUTS \"\")(~ I _ ~~l:~~ ~'=:j ,~X _ j(. .1.5Y OUTPUTS ~'j r - A.C. CHARACTER ISTICS '\"\"~ ';'\" f VOL TA =aOc to +70°C, Vec =+5V ±5% .5Y Symbol Parameter Limits Max. Unit Conditions Typ.[11 Input to Output Delay DO Outputs 15 I 25 ns CL =30pF,R1=300n i R2=600n I. C L =300pF, R 1=90n Input to Output Delay DB Outputs 20 30 R2 = 180n 8216 (Note 2) - - - - - - - - - - - - - - - .8-22.6 . . . . . - - ' - - - -161 I -25- ' - -n-s - -I- TE Output Enable Time I 8216 65 ns 8226 54 ns (Note 3) TO Output Disable Time 35 ns (Note 41 TEST CONDITIONS: TEST LOAD CI RCUIT Vee Input pulse amplitude of 2.5V. r Input rise and fall times of 5 ns between 1 and 2 vol ts. Output loading is 5 mA and 10 pF. ~ R, Speed measurements are made at 1.5 volt levels. OUT C>---[~-----OlI T\" r I . ----~r i. Capacitance (5) .J.. Limits- - - - - - - - - - - - - . . . , . - - - - . . , . - , . . . - , - - - - Symbol 1 Parameter Min. Typ.(1) Max. Unit CIN Input Capacitance 4 8 pF COU T1 Output Capacitance 6 10 pF CO UT2 Output Capacitance 13 18 pF .TEST CONDITIONS: VBIAS =2.5V, VCC =5.0V, TA = 25°C, f = 1 MHz. NOTES: 1. Typical values are for TA =25° C, VCC =5.0V. 2. DO Outputs, CL = 30pF, R1 = 300/10 Kfl., R2 = 180/1Kfl.; DB Outputs, CL = 300pF. R1 = 90/10 Kfl.. R2 = 180/1 Kfl.. =3. DO Outputs, CL = 30pF. Rl =300/10 Kfl., R2 =600/1 K; DB Outputs, CL 300pF, R1 =90/10 Kfl., R2 =180/1 Kfl.. = =4. DO Outputs, CL = 5pF, R1 = 300/10Kfl., R2 600/1 Kfl.; DB Outputs, CL = 5pF, R1 =90/10 Kfl., R2 180/1 Kfl.. 5. This parameter is periodically sampled and not 100% tested. 3-32 April. 1977 a800b

Schottky Bipolar 8224 CLOCK GENERATOR AND DRIVER FOR' aOaOA CPU • Single Chip Clock Generator/Driver • Oscillator Output for External for 8080A CPU System Timing • Power-Up Reset for CPU • Crystal Controlled for Stable System • Ready Synchronizing Flip-Flop Operation • Advanced Status Strobe • Reduces System Package Count The 8224 is a single chip clock generator/driver for the 8080A CPU. It is controlled by a crystal, selected by the designer, to meet a variety of system speed requirements. Also included are circuits to provide power-up reset, advance status strobe and synchronization of ready. The 8224 provides the designer with a significant reduction of packages used to generate clocks and timing for 8080A. PIN NAMES RESET INPUT XTAL l' 'I CONNECTIONS ' ! XTAL2 RESET RESET OUTPUT I TANK \\ FOR CRYSTAL USED WITH OVERTONE XTAL RDYIN READY INPUT OSC OSCILLATOR OUTPUT 02 ClK (TTL LEVELl READY I READY OUTPUT Vee +5V Vee +12V SYNC , SYNC INPUT GND OV : STATUSSTB I IACTIVE LOW) 0, 18080 '-0-'-2-~I \\ CLOCKS An,.11 _ 1q77 3-33

SCHOTTKY BIPOLAR 8224 FUNCTIONAL DESCRIPTION The waveforms generated by the decode gating follow a simple 2-5·2 digital pattern. See Figure 2. The clocks gen· General erated; phase' and phase 2, can best be thought of as con- sisting of \"units\" based on the oscillator frequency. Assume The 8224 is a single chip Clock Generator/Driver for the that one \"unit\" equals the period of the oscillator frequency. 8080A CPU. It contains a crystal·controlled oscillator, a By multiplying the number of \"units\" that are contained in \"divide by nine\" counter, two high·level drivers and several a pulse width or delay, times the period of the oscillator fre- auxiliary logic functions. quency, the approx imate time in nanoseconds can be derived. Oscillator The outputs of the clock generator are connected to two high level drivers for direct interface to the 8080A CPU. A The oscillator circuit derives its basic operating frequency TTL level phase 2 is also brou'ght out ¢2 (TTL) for external from an external, series resonant, fundamental mode crystal. timing purposes. It is especially useful in DMA dependant Two inputs are provided for the crystal connections (XTAL\" activities. This signal is used to gate the requesting device on- XTAL2). to the bus once the 8080A CPU issues the Hold Ack- nowledgement (HLDA). The selection of the external crystal frequency depends mainly on the speed at which the 8080A is to be run at. Several other signals are also generated internally so that Basically, the oscillator operates at 9 times the desired pro- optimum timing of the auxiliary flip-flops and status strobe cessorspeed. (STSTB) is achieved. A simple formula to guide the crystal selection is: Crystal Frequency = -'- times 9 IE> XTALl 0lIC @> tCY IE> ., [!> Example': (500ns tCY) Example 2: 2mHz times 9 = l8mHz· @> ~ @> (800ns teY) CLOCK \"21TTt.11!> GEN. 1.25mHz times 9 = 1'.25mHz mft·[D +9 AESETl1> Another input to the oscillator is TANK. This input allows [[> SYNC-----;---....,J the use overtone mode crystals. This type of crystal gen- (D miN---t>--t-i READVG> erally has much lower \"gain\" than the fundamental type so an external LC network is necessary to provide the additional II> ROYIN-----;--i \"gain\" for proper oscillator operation. The external LC net· work is connected to the TANK input and is AC coupled to ground. See Figure 4. The formula for the LC network is: F= __1__ 2;r v'LC The output of the oscillator is buffered and brought out 1 UNIT._1 _ on E:lSC (pin 12) so that other system timing signals can be derived from this stable, crystal-controlled source. CSC. ·When using crystals above 10mHz a small amount of frequency FREQ. \"trimming\" may be necessary to produce the exact desired fre- quency. The addition of a small selected capacitance (3pF • 10pF) rI in series with the crystal will accomplish this function. I Clock Generator 5 1..._l....._2_i....__ The Clock Generator consists of a synchronous \"divide by nine\" counter and the associated decode gating to create the EXAMPLE: 18080 ICY' 500nll waveforms of the two 8080A clocks and auxiliary timing OSC • 18mHzi55nl signals. '1 • 110m (2 )( 55ns! 3-34 -'2'0, •'-'2 ·275\", (5 x 55\"$) 110nl 12. 5Sml ,.l,ori1, lSi? 880Cb

SCHOTTKY BIPOLAR 8224 STSTB (Status Strobe) The READY input to the aOSOA CPU has certain timing specifications such as \"set-up and hold\" thus, an external At the beginning of each machine cycle the 8OS0A CPU is- synchronizing flip-flop is required. The 8224 has this feature sues status information on its data bus. This information built-in. The ROYIN input presents the asynchronous \"wait tells what type of action will take place during that machine request\" to the \"0\" type flip-flop. By clocking the flip-flop cycle. By bringing in the SYNC signal from the CPU, and with <1>20, a synchronized READY signal at the correct in- gating it with an internal timing signal (<I>lA), an active low put level, can be connected directly to the aOaOA. strobe can be derived that occurs at the start of each ma- chine cycle at the earliest possible moment that status data The reason for requiring an external flip-flop to synchro- nize the \"wait request\" rather than internally in the a080 is stable on the bus. The STSTB signal connects directly to CPU is that due to the relatively long delays of MOS logic such an implementation would \"rob\" the designer of about the 8228 System Controller. 200ns during the time his logic is determining if a \"wait\" is necessary. An external bipolar circuit built into the clock The power-on Reset also generates STSTB, but of course, generator eliminates most of this delay and has no effect on for a longer period of time. This feature allows the a228 to component count. be automatically reset without additional pins devoted for this function. Power-On Reset and Ready Flip-Flops ~------~ A common function in a080A Microcomputer systems is the : ~I generation of an automatic system reset and start-up upon initial power-an. The 8224 has a built in feature to accomp- i jY ! lish this feature. I: ..J.. :I An external RC network is connected to the R'ESiN input. I I The slow transition of the power supply rise is sensed by an I -:- I internal Schmitt Trigger. This circu it converts the slow trans- I -\"I ition into a clean, fast edge when its input level reaches a I1.. predetermined value. The output of the Schmitt Trigger is connected to a \"0\" type flip-flop that is clocked with 4>20 F _ _,/ _ r9~_, 3.10pF (an internal timing signal). The flip-flop is synchronously reset and an active high level that complies with the aOaOA 1 input spec is generated. For manual switch type system Me- set circuits, an active low switch closing can be connected 2\"/LC' to the RESIN input in addition to the power-on RC net- network. USED ONLY FOR OVERTONE CRYSTALS I It I \"\"T' I IONLY NEEDED l. - ' _.J ABOVE 10 MHrI 131 1. 15 I!!> lCTALI osc IE> 11 22 fiE> lCTAU I!!> TANK. --~ IE> OSC 12 10 15 Cl.0ClC: ~ l§> ~2 GEN. ~ITTUI!> RDYIN • 23 +t Vee READY smi [!> 822. SVNC----+--lL...~ ..:r. 8080A CPU r o-+--<:t mTN 12 TGND RESET GND 19 SYNC II>FlESET STSTB ITO 8228 PIN l' It> RDVIN-----+--f5ClI----- REAOVf!> .A.or; 1. 1977 3-35 SaCCb

SCHOTTKY BIPOLAR 8224 D.C. Characteristics TA \"\" DoC to 70°C; Vee = +5.0V ±5%; Voe \"\" +12V :i:5%. Limits Symbol Parameter Min. Typ. Max. Units Test Conditions mA IF Input Current Loading -.25 pA VF = .45V V IR Input Leakage Current 10 V VR = 5.25V Ve V'L Input Forward Clamp Voltage I 1.0 IV Ie\"\" -SmA VIH V'WVIL , Input \"Low\" Voltage I .8 I mV Vee:ll 5.0V VOL I Input \"High\" Voltage 2.6 I V Reset Input VO H 2.0 I All Other Inputs I REDIN Input Hysteresis I V Ise[l] I Output \"Low\" Voltage I .25 Vee = 5.0V Icc .45 V I V ! (¢l1.¢l21. Ready, Reset, S'T'S'f8 100 .45 V I I mA IOL =2.5mA ~ I I mA I -60 mA All Other Outputs I I IOL= 15mA i I i I Output \"High\" Voltage 9.4 I IOH = -100J,tA 3.6 IOH = -100pA <P1 ,<P2 I 115 IOH = -1mA I 2.4 I 12 I READY, RESET Vo =OV Vee = 5.QV I All Other Outputs I Output Short Circuit Current -10 (All Low Voltage Outputs Only) I Power Supply Current I i Power Supply Current Note: 1. Caution. <P1 and ¢2 oUq)ut drivers do not have short circuit protection CRYSTAL REQUIREMENTS Tolerance: .005% at OOC _70°C Resonance: Series (Fundamental) * Load Capacitance: 20·35pF Equivalent Resistance: 75-20 ohms Power Dissipation (Min): 4mW ·With tank circuit use :ltd overtone mode. 3-36 Aor11, 1977 8800b

SCHOTTKY BIPOLAR 8224 A. C. Characteristics vcc = +5.0V ± 5%; Voo = +12.0V ± 5%; TA = O°C to 70°C Symbol Parameter Min. Limits Max. Units Test !;P1 <P1 Pulse Width -2tcy- 20ns Typ. Conditions t</l2 <P2 Pulse Width 9 tcy 2tcy + 20ns ns to, ¢, to 1'1. Delay 9 9 CL m 20pF to SOpF ~-35ns 20 t01. 4>2 to 4>, Delay 20 ns <p1.TTL,Cls30 9 +15 R,=300n t03 rPl to <P1. Delay R2-600n tR a 6tcy tF 91 and <P1. Rise Time 9 to</l2 2-t-c1y 4ns 4>, and t/12 Fall Time 9 2tcy 91. to <P1. (TTL) Delay ~ -5 toss I 6tcy _ JOns 9 t/11. to STSTB Delay -- tpw STSTB Pulse Width !Sl_ 15ns STSTB, Cl= 15pF 9 R1 s 2K R2\" 4K tORS ROYIN Setup Time to SOns _ 4tcy Status Strobe I I9 tORH ROYIN Hold Time 4tcy After STSTB 9 tOR RDYIN or RESIN to -4tcy- 25ns Ready & Reset 91. Delay 9 Cls10pF R1=2K R'Z\"4K tCLK ClK Period 27 MHz f max Maximum Oscillating 8 pF VcC\"+5.0V Cm Frequency Voo=+12V VBIAS=2.5V Input Capacitance f=l MHz TEST ace CIRCUIT I _ ~INPUT>-' fRl ~CL !L, GND lGND Apr; 1, 1977 3-37 aaOOb

SCHOTTKY BIPOLAR 8224 WAVEfORMS 1 I r,.-4 b I l 1,1 --+ f-~ - t /~\\\" ~-'~'~\"-;\"-~-~~~-_---'Il!Z---_-_-_-*-1==--=-~------Jl! -V'\" . .~2tn1J I --1I \\1f0--.. _ \\..... I -J! ! SYNC (FROM_AI -------------------x: i . - - - - - - - - - - - - - - -FlEAOYOUT - - -!__._ 1-----_- ;, - - - - - - - - - - - - - - - - - - - - 011 FlESITOUT +~-------------- VOLTAGE MEAStJREMeNT?OINTS: 41,.412 Logic \"0\" ,. 1.0V, Logic \"'\"'' S.OV. All om.. signals ml!llsurecl at 1.SV. EXAMPLE; A.C. Characteristics (For tCY ~ 48&28 nsl TA = O\"C to 70\"C; VOO .. +5V =5%; Voo \". +12V ::5%. Symbol Parameter I Min.. l.imits Max. I Units Test Conditions Typ. ~1 <Il, Pulse Width I t¢2 I 89 I nsI ns tcy=488.28ns to' toz I lI,I t03 tr I <P2 Pulse Width I 236 I ns I tf i toss I tOtbZ i Delay <P, to 4lz !a I II! ns tpw i Delay 4J2 to <tI, i 95 129 ~I ns 4J, & ~2 Loaded to tORS i CL .. 20 to 50pF tORH I 20 tOR I Deiay 4J, to ¢Jz Leading Edges 109 20 fMAX I Output Rise Time I ns 326 3-38 I Output Fall Time I ns JI ¢J2 to STSTa Delay I 296 ns I I <P2 to ¢2 (TTL) Delay -5 +15 ns StatUs Strobe Pulse Width 40 ns I Ready & Reset Loaded I ROYIN Set1JpTimeto STSTB -167 I ns ,to 2mA/10pF 217 ROYIN Hold Time after STSTB I ns All measurements READY or RESET 192 I II ns referenced to 1.5V to q)Z Delay unless specified I I I otherwise. I Oscillator Frequency I 18.432 I MHz I I Apl\"il. 19n 8aOCb

3-4. SCHEMATIC REFERENCING The detailed schematics of the Interface circuit, CPU circuit, and Display/Control panel are provided to aid in determining signal direction and tracing .. A solid arrow (~) on the signal line indicates direction, and the tracing of the signal through the schematics is referenced as it leaves the page. The reference is shown as a number - letter number (e.g. 2-A3) , indicating sheet 2 and schematic zone A3. The reference may be shown alone or in a bracket. If the reference is bracketad, the signal is going to another schematic which is referenced outside the bracket. If the reference is shown alone, the signal is going to another page of the multisheet schematic. 3-5. 8800b 8LOCK DIAGRAM DESCRIPTION (Figure 3-1) The 8800b computer contains four basic circuits; the Central Processing Unit (CPU), Memory, an Input/Output (I/O) section, and the Front Panel. The CPU controls the interpretation and execution of software instructions, and Memory stores the software information to be used by the CPU. The I/O section provides a communication link between the CPU and external devices. The Front Panel allows the operator to manually perform various operations with the 8800b. The 8800b basic block diagram and accompanying text (paragraphs 3-6 and 3-7) explain the CPU's communication with the memory (and I/O) circuits and with the front panel. The system clock, power-on oper- ation and run operation are explained in paragraphs 3-8 through 3-10. 3-6. CPU TO MEMORY OR I/O OPERATION The Memory or I/O $ection operation repuires several signals that allow transfer of data to and from the CPU. The ADDRESS bus (A0-A15) consists of sixteen individual lines from the CPU to Memory and I/O devices. The signals on this bus. represent a particular ;:'cr~I,1977 3-39 380Cb

W ADDRESS (A0-A I 1 - - - - -----. -.-.-.- ...-.. -.- .... --- -.-- --- . - - - - - - o-Po STATUS - ROY ~ f.-I-------------- ... ~_I._=__OATA__ (_D CPU .-----1-_._---_ ... _ - - -- - - -PO-BIN- - _________________._ Figure 3-1. 8800

A15) -.-.. - - ' ....------.---- .._ . -. -.' .----..-.-- - .-._-- - .... MEMORY OR - Vo D0-~-OA-TA- IN (OI0--U 17)-_. DEVICE Be - .~ - --~VOAT-A---O-U.T- -_.(000-007) I' FOI0-FOI7 --- FRONT I3C - - PANEl ~---- ( .__. J 0b Basic Block.

memory address location or external device number that is needed to establish communications with Memory or I/O devices. Once the ad- dress data (A0-A15) is presented to Memory or I/O devices, the CPU generates various STATUS signals. The STATUS signals enable decoding of a memory address or conditions the I/O device card to send or re- ceive data from the CPU Data from Memory or I/O devices is presented on the DATA ~N lines (OI0-017) and applied to eight non-inverting bus drivers. The drivers are enabled by a PDBIN signal from the CPU and a BC (bus con- trol) signal. The BC signal is LOW when the Front Panel is not in operation. The eight non-inverting bus drivers, when enabled, present the input data to BI-DATA lines (00-07) which input the data to the CPU. Data outputted to Memory or I/O devices is presented to the DATA OUT lines (000-007) from the CPU. The ROY (ready) line either forces the CPU to a wait state while data is being transferred or allows the CPU to process data. 3-7. FRONT PANEL OPERATION The Front Panel Operation is very similar to Memory or I/O section operation. The Front Panel gains control of the CPU by producing a HIGH BC signal. The BC signal disables the DATA IN (OI0-017)· lines from a Memory or I/O Device and·enables the FDI0-FDI7 lines. The FDI0-FDI7 lines contain Front Panel data which is transferred to the CPU upon the occurence of the POBIN signal. All data from the CPU to the Front Panel is applied to the DATA OUT (D00-D07) lines and displayed on the Front Panel. 3-8. SYSTEM CLOCK 3-41 The system clock (F) for the 8800b is located on the CPU circuit card (Figure 3-14, zone B7). The system clock generates phase 1 and phase 2 outputs derived from the external crystal (XTAll). The 01 and 02 outputs operate at a frequency of 2 MHz, which determines the speed at which the 8080 (M) will operate. The 01 and 02 clock signals are presented to the bus (zone A7) through inverter A and inverter bus driver J, respectively. The 01 clock is used by memory and external I/O cards, and the 02 clock is applied to the 24-bit counter on the Display/Control card (Figure Aoril. 1977 saOOb

3-16, sheet 1, zone 02) through the Interface card (Figure 3-15, sheet 2, zone 83). 3-9. POWER ON CLEAR OPERATION Positioning the ON/OFF switch to ON causes a power on clear (PaC) operation to be performed, resetting the 8800b circuitry. The pac signal is generated on the CPU card (Figure 3-14, zone A3) when VCC is applied. With vce present, capacitor C4 will charge to the vec potential in 100 milliseconds because of the RC time constant of C4 and resistor R17. The 100 millisecond delay disables (turns off) transistor Q3, producing a LOW pac signal to the bus (pin 99) through inverters Sand J (zone A2). The pac signal is inverted by U on the Interface card (Figure 3-15, sheet 2, zone 82) and presented to the Display/Control card as a HIGH pac signal (Figure 3-16, sheet 2, zone 06). The poe input is inverted LOW by Tl (zone C6) and applied to three circuits on the Display/Control Card. It clears the Ml flip-flops (zone C7) through NOR gate Tl and inverter Jl (zone C6), insuring that single step operation is disabled. It presets the Ml flip-flop (zone C9) and disables NAND gate Pl (zone 88) to insure that the 8800b is not running. The pac signal (zone 09) is also present at NOR gate Rl which inverts it HIGH to reset the PROM counter. The pac signal is present to the external input/ output (I/O) cards and memory for similar initialization operations. During the pac operation, ~#o other functions are being performed. On the Display/Control card (Figure 3-16, sheet 1, zone 02), a 24-bit counter is being clocked by 02 which wili condition circuits on the Display/Control card. The C13 output (zone 01) from the counter is applied to the clock (CK) input of quad latches Cl, Fl, Hl, Gl, Nl, Ul, Yl, and Wl (zones 89-81) through non-invert- ing bus driver Kl (zones Al and 01) and inverter Jl (zone Cl). The C13 signal clears the quad latches in the following manner to insure all latches are conditioned after poe. The inputs to quad latches Cl, Fl, Hl, and Gl are HIGH because no switches are activated. After the first rT! clock, all the Q outputs are LOW and applied to the inputs of quad latches Nl, Ul, Yl, and Wl (zones 89-81). 3-42 April. 197i 880Gb

The occurrence of the next C13 clock latches the Q outputs LOW and the Q outputs HIGH during the POC operation. When VCC is present in the CPU circuits, another RC time constant affects the clock generator F (Figure 3-14, zone B7). Capacitor C2 will charge to the VCC potential in 33 micro- seconds which is the time constant of C2 and resistor Rlo. The 33 microsecond delay allows the RESET output from F (zone B7) to clear the 8080 Minternal circuits. The 8080 remains in this state because the READY output (zone B7) is LOW from F. The READY output from F will be affected during the run operation. 3-10. RUN OPERATION The Run Operation allows the 8080 on the CPU Board to start processing data to and from memory and external devices. The Run Operation is activated when the RUN/STOP switch on the 8800b front panel is momentarily depressed to RUN. The RUN/STOP circuits are located on the Display/Control card (Figure 3-16, sheet 2, zone A9). When the RUN/STOP switch is momentarily depressed, a LOW is applied to quad latch 'Cl, input 02. The occurrence of the next C13 clock (zone Al) causes the Q output at pin 6 of Cl (zone 89) to go HIGH. This HIGH is applied to quad latch Nl, input 02. The next C13 clock causes the Q out- put at pin 2 of Nl (zone B9) to go HIGH and allows NAND gate Pl to clear Ml (zone C9). The Q output of Ml generates a LOW RUN signal and LOW FROY signal through NOR gate Pl and inverter Rl (zone 09). The RUN signal is applied to the Interface Card (Figure 3-15, sheet 2, zone 02) to condition the MO input of data latch G (sheet 3, zone A6). With MO enabled, output data from the CPU can be displayed on the 8800b front panel if a ST8 input is present to G (discussed in Paragraph 3-40). The FRDY signal is applied to the Interface Card (Figure 3-15, sheet 2) to allow the 8080 to start processing data. The FRDY output is applied to pin 58 of the bus through inverter Rand non-inverting bus driver H as a HIGH ,(zone Al). Jhe HIGH on pin 58 of the bus enables NAND gate C, pin 8, LOW on the CPU (Figure 3-14, zone A7) which is inverted HIGH by B (zone 87) and applied Aori1. 1977 3-43 8800b

to the clock generator F RYDIN input. The RYDIN signal enables the READY output at F HIGH (zone 87) which allows the 8080 M(zone A8) to start processing data. 3-11. 8800b DATA PROCESSING OPERATION The 8800b data processing begins when the 8080 IC is enabled (Paragraph 3-10). With the 8080 IC enabled, the program (P) counter in the 8080 starts to increment or begins at a predeter- mined count established by the operator. The count in the P counter represents a location in memory which is examined by the CPU before the P counter increments to the next location. To examine each memory location, the CPU initiates an instruction cycle operation. Every instruction cycle consists of one, two, three, four, or five machi~e cycles. In order to perform a data processing operation, basic machine cycles are required. The Instruction Fetch Machine cycle is a basic machine cycle needed to allow the CPU to fetch an instruction from memory. A memory read machine cycle is also a basic machine cycle that enables the CPU to communicate with a memory or ~xternal device for data transfer operations. The following paragraphs discuss data transfers from an externa1 device to-the CPU, from the CPU to memory, from memory to the CPU, and from the CPU to an external device. However, the instruction fetch and memory read machine cycles used in the data transfers are discussed first because their operation is identical in all of the data transf~rs. It is important to note that there are many variations of data transfer which are dependent on the programmer. 3-12. INSTRUCTION FETCH CYCLE The Instruction Fetch Cycle is the first machine cycle (Ml) to be performed by the CPU in any data transfer operation. The memory location specified by the P counter contains data that the CPU interprets as an instruction. The first cycle must be a fetch cycle because, during the fetch cycle, the CPU is informed as to what operation will be performed next. 3-44 Apr~1, 1977 3800b

3-13. INSTRUCTION FETCH CYCLE OPERATION (Figure 3-2) The Instruction Fetch Cycle is initiated whenever the P counter is incremented to a new memory address location (e.g. 000 1008) where an instruction (e.g. 0728) is stored. In order to fetch the 0728 data from memory during machine cycle one, several signals are generated by the CPU. A PSYNC output from the CPU is applied to memory to condition for address decoding. Next the ADDRESS (000 1008), consisting of sixteen parallel outputs (A~-A15) from the CPU, is presented to the Display/Control Card and memory. The A0 through A15 signals drive the appropriate address buffers, illuminating the light emitting diodes (LEDs) on the Display/Control Card. The ADDRESS and PSYNC signals present at the memory from the CPU initiate decoding of the memory address (000 1008), The CPU then generates three signals, SM1, SMEMR, and 01 CLOCK to complete the Instruction Fetch Cycle. The SMl output is applied to the Display/Control Card through the Interface Card to light the Ml (machine cycle 1) LEO on the 880Gb front panel. The SMEMR and 01 CLOCK outputs are applied to memory to allow decoding of the memory address (000 1008), With the memory address decoded, the 0728 data present in that location is transferred to the CPU on the eight DATA IN (010-017) lines. The DIG 1 input to the CPU from the Interface Card is enabled when the 880Gb is in the run mode (see paragraph 3-10). This permits the memory data to be trans- ferred to the CPU. The SMEMR output is applied to the Disp1ay/ Control Card through the Interface Card to light the MEMR (memory read) LED on the 8800b front panel. This operation is performed when the P counter is incremented, indicating a new memory address. 3-14. INSTRUCTION FETCH CYCLE DETAILED OPERATION 3-45 The following paragraphs describe the Instruction Fetch Cycle operation in detail. Refer to Figure 3-3, Instruction Fetch Cycle Timing, during the explanation. The Instruction Fetch Cycle operation (M1) requires four 01 and 02,clock pulse~. Each clock period performs a particular operation as described in the follow- ing paragraphs. April. 1977 38CCb

W I ~ Q) DIG 1 sr~EMR 5'11 ADDRESS (A0-A15) L-P-Sy-N-C-- L--~.:.:.:..::=---1!--- . :. ~.: . ll -_ _ _C...:....10.:....C:...:..:k c o om:;~ 0\"1 0-0· CS\"-' Figure 3-2. Instruction

ii'ilii;.ii!...:I----'-+----------------------·:1loI -------------------j,\"I·:.:·:·:MEMORy·:·:·:· ;~liilii n Fetch Cycle Block Digaram

TI MI T4 T2 T3 n01 ...,j n n~r\\ 02 _F\\. - \"-BYTE r-'ONE ------ / • -I IPSYNC \\.0 PO BIN JI _,\" I I I STATUS I \\ INFORMATION I I SMEMR MI Figure 3-3. Instruction Fetch Cycle Timing. April, i9ii 3-4i 28COb

During the latter portion of T1, several outputs are gener- .A.pri 1, 1977 ated by the CPU (M) (Figure 3-14): address data A0 through A15 (zone B8), status data 00 through 07, and a SYNC signal (zone aBOOb C8). The A0 through A15 data is applied to memory via the bus through non-inverting bus drivers, U, P, and N (zone B9) on the CPU. The address data (A0-A15) is also applied through inverters P, N, aryd X on the Interface card (Figure 3-15, sheet 1, zone B5) and presented to the Display/Control card. The A0 through A15 signals present on the Display/Control card light the appropriate A0 through A15 LEOs, indicating the memory address. The 00 through 07 data is applied to K (zone B5) on the CPU through the bi-directiona1 circuits 0 and E. The status data is enabled through 0 and E at this time because CS and OlEN are LOW. The SYNC output is applied to the clock generator F (zone B7) and memory as PSYNC via pin 76 (zone 01) on the bus through the non-inverting bus driver V (zone 08). The PSYNC signal conditions memory to decode the address data. The SYNC input at F will enable a signal during T2. During the beginning of T2, a low STSTB (zone B7) is generated from F as a result of the HIGH SYNC input and internal timing of F. The STSTB is applied to the data latch K (zone B5), allowing the'status data 00 through 07 to be stored in K. The status data present at the output of K conditions the memory to fetc~_ the instruction (0728) from its addressed memory location (e.g. 000 1008) by enabling the following signals. A SMl and SMEMR HIGH output from K is presented on pins 44 and 47 of the bus (zone A5) through non-inverting bus drivers X and R. The SMl and SMEMR signals are applied through inverter V on the Interface card (Figure 3-15, sheet 2, zone 85) and presented to the Display/Control card as SM1 and SMEMR. The SM1 and SMEMR signals present on the Display/Control card light the M1 and MEMR LEOs (Figure 3-16, sheet 3, zone C3) on the front panel of the 8800b, indicating machine cycle one is performing a memory rea~ operation. The SMEMR output from the CPU (Figure 3-14, zone A5) is applied to memory, initiating a data transfer to the CPU during T3. 3-48

At the beginning of T3, the instruction (072S) data is transferred from memory to Mon the CPU. The memory data (010 through 017) issupplied to the CPU card (Figure 3-14, zone Bl) from the bus. The data is presented to Mthrough bi-directional gates 0 and E (zone C7), inverter bus drivers Land J (zone 84), and inverters Y and S (zone 83) by the D8IN signal. At the latter portion of T2 and the beginning of T3, a high OBIN output (zone CS) is generated by M. The DBIN output is applied to the OlEN inputs (zone C7) of 0 and E and pin 4 of NAND gate C (zone 84) as PDBIN. This signal enables pin 6 of NAND gate CLaW (DIGl is high when the front panel is not used). This allows data input from memory (010-017) to be enabled through inverting bus drivers Land J (zone 84) and applied through bi-directional gates 0 and E to M(zone C7). Clock period T4 of machine cycle one allows for SOSO process- ing of the received instruction data from memory. If the instruc- tion data present in the CPU requires a data transfer to or from an external device, a memory read cycle (M2) is initiated. However, if the instruction data present in the CPU requires a data transfer to or from memory, two memory read ~ycles (M2 and M3) are initiated. 3-15. MEMORY READ CYCLE The Memory Read Cycle (M2) follows the Instruction Fetch Cycle (Ml). During a Memory Read Cycle, an address is transferred to the CPU from memory. This address is either an external device number or a memory location (depending upon the instructions received during Ml). 3-16. MEMORY READ CYCLE OPERATION (Figure 3-4) The CPU performs one or two Memory Read Cycle operations. If the CPU is to communicate with an external device, one Memory Read Cycle is required because the exte~nal device number consists of 8 data Aori 1. 1977 3-49 8800b

0 'cCoo-~o DIG 1 0· PSYNC CT ..... Sf·'H1R ( ADDRESS A@-A15 rOBIN o CLOCK DATA IN (010-017) Figure 3-4. Mem

PSYNC mory Read Cycle Block Diagram

bits (1 byte). However, if the CPU is instructed to communicate with memory, two Memory Read Cycles are required because the memory address consists of 16 data bits (2 bytes). The two Memory Read Cycles obtain the memory address (e.g. 000 200a ) that is required by the CPU to complete the instruction. Since one byte (a bits) of the two byte address is transferred during one Memory Read Cycle, two cycles are required. The first Memory Read Cycle obtains the least significant bits (LSBs) of the address (200a) from memory and stores them in the CPU. The second cycle obtains the most significant bits (MSBs) of the address (OOOa) from memory and stores them in the CPU. The Memory Read Cycles are very similar to the Instruction Fetch Cycle. They require a memory address location (e.g. 000 lOla and 000 102a) that indicates where the LSBs and MSBs of the address (000 200a) are stored. After completion of the Instruction Fetch Cycle, the program counter in the CPU is incremented to 000 lOla and the first Memory Read Cycle is initiated. Severa1 signals are generated by the CPU in order to read the LSBs of the address (200a) from memory. A PSYNC output from the CPU is applied to memory through the Interface Card to condition the memory for address decoding. Next the ADDRESS (000 lOla)' consisting of sixteen parallel outputs (A0- A15) from the CPU, is presented to the Display/Control Card and memory. The A0 through A15 signals light the appropriate ~ddress light emitting diodes (LEOs) on the Display/Control Card. The ADDRESS and PSYNC signals present at the memory from the CPU initi- ate decoding of the address (000 lOla)' The CPU then generates three signals, SMEMR, POBIN, and 01 to complete the Memory Read Cycle. The SMEMR, POBIN, and 01 outputs are presented to memory to enable decoding of the address (000 lOla)' With the address decoded, the 200a data prese~~ in that location is transferred to the CPU on the eight DATA IN (010-017) lines. The DIGl input to the CPU from the Interface Card is enabled when the aaOOb is in the run mode, permitting memory data to be transferred to the CPU. Aori1. 1977 3-51 8aOOb

The SMEMR output is presented to the Display/Control Card through the Interface Card to light the MEMR (memory read) LED on the 8800b front panel. The second Memory Read Cycle operation is identical to the first. It transfers the MSBs of the address (OOOS) to the CPU. 3-17. MEMORY READ CYCLE DETAILED OPERATION The following paragraphs describe the Memory Read Cycle opera- tion in detail. Refer to Figure 3-5, Memory Read Cycle Timing, dur- ing the explanation. The two Memory Read Cycle operations (M2 and M3) obtain the memory address (e.g. 000 200S) required by the CPU to complete an instruction. As stated previously, the LSBs of the address (200S) are transferred to the CPU during M2, and the MSBs of the address (0008) are transferred to the CPU during M3. There are three clock periods (Tl-T3) required for each Memory Read Cycle operation. During the latter portion of Tl, several outputs are generated by the CPU (Figure 3-14); Address data A0 through A15 (zone 8S), status data 00 through 07, and a SYNC signal (zone CS). The A0 through A15 data is presented to memory and the S800b front panel via the bus through non-inverting bus drivers U, P, and N (zone 89) on the CPU. The 00 through 07 data is applied to K (zone 85) on the CPU through the bi-directional circuits 0 and E. The status data is enabled through 0 and E at this time because CS and OlEN are LOW. The SYNC output is applied to the clock generator F (zone B7) and memory as PSYNC via pin 76 (zone 01) on the bus through non-inverting bus driver V (zone OS). The PSYNC signal conditions memory to decode the address data. During the beginning of T2, a STSTB (zone 87) is generated (LOW) from F as a result of the HIGH SYNC input and internal timing of F. The STSTB is applied to the data latch K (zone 85), allowing the status data 00 through 07 to be stored in K. The status data present at the output of K allows the CPU to read the LSBs of the memory address 3-52 April, 1977 330Gb

01 _r---\\'-----lf\\ h h'------(n 'n~ 02 \",\",--\",1\\ A 15 - 0 -!-_-' I 0 7 _ 0 _ - / STt TUS BYTE \\ \"'-_---J I ONE BYTE i (. ,)'--- TWO I ,LSSS, ST ~TUS ,, MSS'SI·' ., '--_....I '--_....I _ - IPSYNC .... \\. PO BIN -lo----+---- -P 'N R -.,.----+----+-----j----l----+------i .KSTATU S ~_ _--.j ...... I+-_ _...,j ,. 1 ..., I K iSMEMR I NFORIoIATION I SMEMR Figure 3-5. >!e!:1cry Read Cycle 7i:1ing. ....ori i. 1977 3-53 380Gb

location (ex. 000 101 8 ) by enabling the SMEMR signal. A SMEMR output (HIGH) from K is presented on pin 47 of ~he bus (zone A4) through non-inverting bus drivers X and R. The SMEMR signal is applied through inverter V on the Interface Card (Figure 3-15, sheet 2, zone 84) and presented ~o the Display/Control card as SMEMR. The SMEMR signal present on the Display/Control card lights the MEMR LED (Figure 3-16, zone C3) on the front panel of the 8800b, indicating a memory read operation is occurring. ihe SMEMR output from the CPU (Figure 3-14, zone AS) is applied to memory in order to initiate a data transfer to the CPU during n. At the beginning of T3, the LSBs of the memory storage location (2008) are transferred from memory to the S080 (M) on the CPU. The memory data in (010 through 017) is applied to the CPU card (Figure 3-14, zone 81) from the bus. The data is presented to Mthrough bi-directional gates 0 and E (zone C7), inverter bus drivers Land J (zone 84), and inverters Y and S (zone 83) by the PDBIN signal. At the latter portion of T2 and the beginning of T3, a DBIN output (zone CS) HIGH is generated by M. The OBIN output is applied to theDIEN inputs (zone C7) of 0 and E and pin 4 of NAND gate C (zone B4) as POBIN. ihis signal enables pin 6 of NAND gate C LOW (DIG 1 is high when front panel is not used). This allows the data in from memory (010 - 017) to be enabled through invert- ing bus drivers Land J (zone 84) and applied through bi-directional gates 0 and E to M (zone C7). The second Memory Read Cycle operation (M3) transfers the contents of memory address (000 102S) which contain the MSBs of the memory address number to the CPU. It is important to note that only one Memory Read Cycle operation is required if the CPU is to communicate with an external device. 3-18. EXTERNAL DEVICE TO CPU DATA TRANSFER An External Device to CPU data transfer is accomplished when an input instruction (333S) is fetched from a memory location during Ml, and the external device number (XXXS) is read from a memory location during M2 by the CPU. The data from the external device is transferred to the CPU by an Input Read Cycle operation (M3). 3 - 5 4 o l p r i l , ~377 saCOb

3-19. INPUT READ CYCLE OPERATION (Figure 3-6) The Input Read Cycle operation will allow the CPU to obtain data from an external device. After the completion of the Memory Read Cycle (M2), the program counter is not incremented until the completion of the Input Read Cycle. Several signals are generated by the CPU in order to obtain data from the external devi ceo The SINP output and external device ADDRESS (XXX8) number, consisting of the first eight individual outputs (A0-A7) from the CPU, is presented to the external device input/output channel, thereby enabling the I/O card. With the I/O enabled, a PDBIN signal from the CPU allows the I/O to transfer the external device data to the CPU on the eight DATA IN (010-017) lines for storage. The DIG 1 input to the CPU from the Interface is enabled during the 8800b run mode and allows the external device data to be stored in the CPU. The SINP and A0 through A15 outputs are supplied to the Display/Control Card through the Inter- face Card to illuminate the INP (input) and ADDRESS LEOs on the 8800b front panel. 3-20. INPUT READ CYCLE DETAILED OPERATION 3-55 The following paragraphs describe the Input Read Cycle operation in detail. Refer to Figure 3-7, Input Read Cycle Timing, during the explanation. The Input Read Cycle operation (M3) requires three 01 and 02 clock pulses. During each clock period, a specific operation is performed as described in the following paragraphs. During the latter portion of Tl, several outputs are gen- erated by the CPU (Figure 3-14); address data A0 through A15 (zone B8), status data 00 through 07, and a SYNC signal (zone C8). The A0 through A15 data contains the external device number (A0-A7 and A8-A15 contain identical data) and is applied to the I/O card via the bus through non-inverting bus drivers U, P, and N (zone B9) on the CPU in order to enable the I/Q card. The address data (A0-A15) is also applied through inverters P, W, and X on the Interface Card (Figure 3-15, sheet 1, zone 85) and Aoril, 1977 3800b

(AJ I Ul (;I) SINP ADDRESS (AO-A7) '------t----------- POBIN +- L-- '------ -.---p-Sy-N-C- DATA IN (DI~-OI7) Figure 3-6. Input Re

SINP (AO-A15) ----------.I,)/~~))r)~:~r)}~{{)ff):}:I__-__. - . ... .;:::::;::. PEDREIPVIIIECREAL...;-::: ,. (t~~ ~tt - - - - - - - - - - - - - - - - l i-I.;Iro.II.:.ljl:j::t:t:j:;~j~I:/1:O~:~j::C~~)Aj\\~R\\:\\D:)i::i;:1:~:1· ead Cycle Block Diagram (

01 PSYNC poe 1N -I----+__- P Wi' ~----+----+------! STATUS -+----i\\ ,._ _-+ ~ INFORMATION SINP Fi gure 3-7. Input Kead Cyc1e Tim;~g. Aoril, 19ii 3-57 3aOOb

presented to the Display/Control card. The A~ throuqh A15 signals present on the Display/Control card (Figure 3-16, sheet 3, zone A9-A4) light the appropriate A0 through A15 LEDs, indi- cating the address of .the external device. (Recall that when addressing an I/O device, the address is repeated on the upper eight and lower eight address LEOs.) The 00 through 07 data is applied to K (Figure 3-14, zone 85) on the CPU through the bi- directional circuits 0 and E. The status data is enabled through o and E at this time because CS and OlEN are LOW. The SYNC out- put is applied to the clock generator F (zone B7), conditioning F to generate a signal during T2. At the beginning of T2, a =STS=TB (zone B7) is generated LOW from F as a result of the HIGH SYNC input and internal timing of F. The STSTB is applied to the data latch K (zone 85), allowing the status data 00 through 07 to be stored into K. The status data present at the output of K conditions the I/O card to send data to the CPU by enabling the SINP signal. A SIN? output from K is presented HIGH on pin 46 of the bus (zone A4) through non-inverting bus driver R. The SIN? signal is applied through inverter V on the Interface Card (Figure 3-15, sheet 2, zone B5) and presented to the Display/Control card as SINP. The SINP signal .present on the Display/Control card lights the INP LED (Figure 3-16, sheet 3, zone C3) on the front panel of the 8800b, indicating data is being received from an external device. The SlNP'output from the CPU is applied to the external device I/O card in order to initiate a data transfer to the CPU duri ng 13. At the beginning of T3, the external device data is trans- ferred to Mon the CPU via the bus. The external device data in (010 through 017) is applied to the CPU card (Figure 3-14, zone 81) from the bus. The data is presented to the 8080 (M) through bi-directiona1 gates D and E (zone C7), inverter bus drivers L and J (zone B4), and inverters Y and S (zone B3) by the POBIN signal. At the latter portion of T2 and the beginning of T3, a DBlN output (zone C8) HIGH is generated by M. The DBIN output is applied to the OlEN inputs (zone C7) of 0 and E, pin 4 of NAND gate C (zone B4) and the bus pin 78 (zone D1) as POBIN: This 3-58 Aero; 1. 1977 880Cb

signal enables pin 6 of NAND gate C LOW (DIG 1 is HIGH when the front panel is not used), allowing the data input from the I/O card (010- 017) to be enabled through inverting bus drivers Land J (zone B4) and applied through bi-directional gates 0 and E to M(zone C7). The data at the external device is presented on the bus by the occurrence of POBIN. After the external device data is stored in the CPU, the P counter is incremented, thus ending the Input Read Cycle operation. 3-21. CPU TO MEMORY DATA TRANSFER A CPU to Memory data transfer is accomplished whenever an instruction is encountered to perform this operation. For example, a store accumulator STA (0628) instruction requires the accumu- lator in the CPU to transfer its contents to memory. The STA instruction is fetched during Ml and its storage location determined in memory read cycles M2 and M3. The accumulator data is transferred to memory by a Memory Write Cycle operation (M4). 3-22. MEMORY WRITE CYCLE BASIC OPERATION (Figure 3-8) The Memory Write Cycle operation will allow the CPU to transfer data to the memory. Several signals are generated by the CPU in order to transfer data to the memory. The SWO output from the CPU is applied to the Display/Con- trol through the Interface to light the WO (write out) LED on the 880Gb front panel. The ADDRESS (XXX XXX8) , consisting of fifteen individual outputs (A0-A15) from the CPU, is presented to the Display/Control and memory. The A0 through A15 signals light the appropriate address LEOs on the Display/Control. The ADDRESS and PSYNC signals present at the memory from the CPU can also initiate decoding of the memory address. With the memory con- ditioned, eight DATA OUT lines (000-007) transfer the CPU data to the memory for storage. The PWR and SOUT outputs from the CPU are applied to the Interface to produce a MWRITE signal which allows the memory to store the data. Aoril. 1977 3-59 88COb

W mI o ADDRESS (A0-A 15) ,';. . ------'----PS_Y_ll_C DA~: ~~~C(:_00_-_0(_J_7-:.) aOJ ) .• to 0'\"'1 0 ......· [T ~ Figure 3-8. Memory W

- -t1-1~H-IT-E - _ . _ - - - - - - - - - - - - - - :-:.:-:.:.:.:-::~;.;.;.:~:::::::: ---------------I~b·I~~~~~J ;.I •••••••••·1•••1•1.1 Write Cycle Block Diagram

3-23. MEMORY WRITE CYCLE DETAILED OPERATION 3-61 The following paragraphs describe the Memory Write Cycle operation in detail. Refer to Figure 3-9, Memory Write Cycle Timing, during the explanation. The Memory Write Cycle operation (M4) requires three 01 and 02 clock pulses. Each period performs a certain operation as described in the following paragraphs. During the latter portion of Tl, several outputs are generated by the CPU 8080 IC (Figure 3-14); Address data A0 through A15 (zone 88), status data 00 through 07, and a SYNC signal (zone C8). The A0 through A15 data contains the memory storage location address (ex. 000 2008) which is applied to the memory card via the bus through non-inverting bus drivers U, P, and N (zone B9) on the CPU in order to enable the memory. The address data (A0-A15) is also applied through inverters P, W, and X on the Interface Card (Figure 3-15, sheet 1, zone B5) and presented to the Display/Control card. The A0 through A15 signals present on the Display/Control card (Figure 3-16, sheet 3, zones A9-A5) light the appropriate A0 through A15 LEOs, indicating the memory 1ocati on address. The 00· through 07 data i6 appl i ed to K on the CPU (Figure 3-14, zone B5) through the bi-directional circuits 0 and E. The status data is enabled through 0 and E at this time because CS and OlEN are LOW. The SYNC output is applied to the clock generator F (zone B7), conditioning F to generate a signal during T2. During the beginning of T2, a LOW STSTB (zone 87) is generated from F as a result of the HIGH SYNC input and internal timing of F. The STSTB is applied to the data latch K (zone B5) allowing the status data 00 through 07 to be stored into K. The status data present at the output of K indicates a write output operation is being performed. However, the distinction of whether the data from the CPU is being transferred to a memory or an external device is determined by the status of the SOUT signal (zone AS). During a Memory Write Cycle, the SOUT signal is LOW and applied to the Interface Card (Figure 3-15, sheet 2). The SOUT signal is inverted HIGH by V and applied to pi'n 2 of NAND gate A (zone C3). April. 19ii 8S00b

ACCUMULATOR PSYNC PO BIN --+0----+-----+---+-+--- P WR -+----+----.... STATUS I tC FOR MAT ION -+-----4. ,.-W--O--+----+---- Fi~:J~~ 3-9. \\ler.1o ry Itlri te eye1e Ti i:1i :1 9. 3-62 Aori 1, 19i7 880Gb

The SWO output from K is presented on pin 97 of the bus (zone A4) through non-inverting bus driver X as a LOW. The SWO signal is applied through inverter Mon the Interface Card (Figure 3-15, sheet 2, zone 86) and presented to the Display/ Control card as SWO. The SWO signal present on the Display/ Control card lights the WO LED (Figure 3-16, zone C3) on the front panel of the 8800b, indicating data is being transferred to memory from the CPU. At the beginning of T3, the CPU data is transferred to the memory via the bus. The CPU data out (000 through 007) is applied to the bus (zone C1) through bi-directiona1 gates 0 and E (CS and OlEN are LOW) and non-inverting bus drivers Mand W (zones C7 and C3). The bus data is presented to memory and written in by the MWRITE signal. After the CPU data is settled on the bus and presented to memory, a WR signal (zane C8) is generated LOW by M. The WR signal is applied to pin 77 (zone 01) of the bus through non- inverting bus driver V (zone 08) as PWR. The PWR signal is inverted HIGH by U on the Interface Card (Figure 3-15, sheet 2, zane 83) and applied to pin 1 of NAND gate A (zone C3), enabling pin 6 LOW (SOUT is HIGH on pin 2). The LOW at pin 6 forces the output of NOR gate A (zone C2) HIGH which is applied to pin 68 of the bus through non-inverting bus driver H (zone 82) as MWRITE. The MWRITE signal allows the memory to store the.CPU data in the addressed memory location, thus completing the CPU to memory data transfer. 3-24. MEMORY TO CPU DATA TRANSFER 3-63 A Memory to CPU data transfer is accomplished whenever an instruction is encountered to perform this operation. For example, a load accumulator LOA (0728) instruction requires the specified addressed memory location to transfer its contents to the accumu- lator in the CPU. The LOA instruction was fetched during M1 and the specified memory location determined during the memory read cycles, M2 and M3. The memory data is transferred to the CPU by an additional Memory Read Cycle operation (M4). The M4 operation April, 197i 8800b

requires the CPU to output the specified addressed memory location to memory, allowing the data in the specified addressed memory location to be transferred to the CPU in an identical manner as M2. For a detailed operation description of the M2 cycle, refer to Paragraph 3-17. Note as you read the description that the specified memory address location is presented to memory on the fifteen individual ·address lines, allowing that location to transfer its data to the CPU. 3-25. CPU TO EXTERNAL DEVICE DATA TRANSFER A CPU to External Device data transfer is accomplished when an output instruction (3238) is fetched from a memory location during Ml, and the external device number (XXX8) is read from a memory location during M2 by the CPU. The data from the CPU is transferred to the external device by an Output Write Cycle operation (M3). 3-26. OUTPUT WRITE CYCLE BASIC OPERATION (Figure 3-10) The Output Write Cycle operation will allow the CPU to output data to an external device. After completion of the Memory Read Cycle (M2), the program counter is not incremented until the completion of the Output Write Cycle. Several signals are generated by tne CPU in order to transfer the data to the external device. The SOUT and PSYNC external device ADDRESS (XXX8) number, consisting of sixteen individual outputs (A0-A7) from the CPU, is presented to the external device (I/O) to condition the I/O card. With the I/O conditioned, a PWR signal from the CPU allows the I/O to trans fer the CPU data vi a the DATA OUT (000-007) 1i nes to the external device. The SWO output from the CPU is presented to the Display/Control through the Interface to light the WO (write output) LED on the 8800b front panel. The SOUT and A0 through A15 outputs are applied to the Display/Control through the Interface to light the OUT output and ADDRESS LEOs on the 8800b front panel. 3-64 A!:lrii. 19ii 8800b

(AO-A '-- I D_AT_A_OU I PSYNC '------ ~ I------------------------------·-~ Figure 3-10. Output W

A15 ) ._---------- U_T--.:-{D_0_0-_D_07-.:} -1>~:!!!f:{{ i!({{Wi\\? :;:;PERIPHEnAL ;:: ----------------~~ ~!i!\\~ DEVICE :i!i!: -..J::::::::,/O CARD ::::: ~----~-;.Jiiiiiiii!!!i! !f!i!i!iti!iii . r- .0 ·... 0 1-0 u<XJ ...-'( OJ Write Cycle Block Diagram

3-27. OUTPUT WRITE CYCLE DETAILED OPERATION Aorii, 1977 The following paragraphs describe the Output Write Cycle 8800b operation in detail. Refer to Figure 3-11, Output Write Cycle Timing, during the explanation. The Output Write Cycle operation (M3) requires three 01 and 02 clock pulses. Each clock period performs a certain operation as described in the following paragraphs. During the latter portion of Tl, several outputs are generated Dy the CPU 8080 Ie (Figure 3-14); Address data A0 through A15 (zone 86), status data 00 through D7, and a SYNC signal (zone C8). The A~ through A15 data contains the external device number and is applied to the I/O card via the bus through non- inverting bus drivers U, P, and N (zone B9) on the CPU in order to enable the I/O card. The address data (A0-A15) is also applied through inverters P, W, and X on the Interface Card (Figure 3-15, sheet 1, zone B5) and presented to the Display/ Control card. The A0 through A1S signals present on the Display/ Control card light the appropriate A0 through A1S LEOs, indicating the address of the external device. The 00 through 07 data is applied to K (zone 85) en the CPU through bi-directional circuits o and E. The status data is enabled through 0 and E at this time because CS and DIEN are LOW. The SYNC output is applied to the clock generator F (zone B7) which conditions F to generate a signal during T2. At the beginning of T2, a STSTB (zone B7) is generated LOW from F as a result of the HIGH SYNC input and internal timing of F. The STST8 is applied to the data latch K (zone 85), allowing the status data 00 through 07 to be stored into K. The status data present at the output of K conditions the I/O card to receive data from the CPU by enabling the SOUT and SWO signals. A SOUT output from K is presented HIGH on pin 45 of the bus (zone A4) through non-inverting bus driver X. The SOUT signal is applied through inverter V on the Interface Card (Figure 3-15, zone B5) and presented to NAND gate A (zone C3) and the Display/Control card as SOUTo The SOUT signal disables NAND gate A to insure that a ~~RITE output is not produced when writing data to an external 3-66

Dt ACCUMULATOR PSYNC poe tN -!----+-----i......-t--t--- P WR -i-----!----_\\. - i o - - -. .STATUS SOUT J N FORMATION Figu~e 3-11. Output Write Cycle Ti~i,g. -- 3-67 Apr; 1, ;?ii 3800b