altair_8800b

["M3 Mol MS T1 T2121 T3 T1 T2121 T3 Tl T2121 T3 T4 TS HLOUT ITMPI-I-0ATA 8US I STATUS71 83J..,h PC OUT pc-pc., I I STATUsi61 I I : PC-PC+, WZOUT OATA--tA t 83-t-W STATUsl61 I IAI 1 OATA 8US 'i I PC-PC+' I ~~~~~i71 i OATA~ ~ ! PC-PC+I ~~W IWZOUT OATA---+L ~~~~(61 I I WZ-WZ+' , ~iA~~~{71 pc OUT I I STATUsl61 STATUsi61 i PC-PC+' 83-l,.W ~A~'ifst71 ILl \u2022 OATA SUS IHI-i-oATA SUS S3-1-W WZ-WZ\u00b71 I I I [91 IACTI+iTMPI-A i I,i91 IACTI~TMPl-A i[91 IACT1+iTMPI+CY-A , I I i[91 IACTl+(TMPI+CY-A I II [91 IACTI-(TMPl-A I II I II I -[91 I ACTl-(TMPI-A I \\\" i I [91 I (ACTl-{TMPI-CY-A I I I I ! I[91 IACTl-ITMPl-CY-A !I I ALU ~OATA SUS I t i f HLOUT I ISTATUS!?I ~A~~l7I I ALU- f-0ATA SUS I'hl-ACT ,I I Hl':'TMP ALU-H, CY I I IACTI+(TMPI+CY-ALU I II I i19i IACT)+ITMPI-A I April, 1977 2-37 8800b","MNeMONIC opcooe Mlll1 M% T1 T:j!12I 07\u00b06 0 5 0 4 030%01 DO IT1 nl21 T3 T4 ! T5 T3 I ANI dl'ta 1I I 0 0I I 0 pC OUT PC-PC\u00b7, INST-TMPIIR (AI-ACT PC OUT PC\u00b7PC\u00b7' 82+TMP XRAr I SSS STATUS ,0 I 0 \u2022\u2022 (AI-ACT STATusl61 ISSSI-TMP (AI-ACT I 191 IACTl.(TPMI-A (AI-ACT I I XRAM 10I 0 1I 10 (AI-ACT HLOUT OATA- f-TMP XRldlltI (SSSI-TMP ,1 10 ,1 1 0 iSTATusl61 I PC OUT PC-PC\u00b7, 82- f-TMP STATUS(61 ORA' I 01I 0 SSS 191 (ACTI.(TMP,-A ORAM ORI dati I CMP, CMf'M I 0I CPt data i , ,1 0 0 (AI-ACT I IHL OUT OATA+TMP RLC ! RRC , (AI-ACT STATUsl61 RAL ! I RAR , ,i, PC OUT i PC-Pc\u00b7, CMA 1 I 1i0 0 I IAI-ACT I STATUsl61 I a2--+-TMP CMC I STC , , ,0 I i ISSSI-TMP I I 15 SS I I IAI-ACT i [91 i (ACTI-ITMP1, FLAGS I , ,I I i I HL OUT I DATA -j-TMP i 0 1 11I 0 I I, ! IAI-ACT STATUS(61 82 TNP I I ! I PC OUT , ,i 1 1 1 IAI-ALU STATUsl61 i Pc-pc., ,! ROTATE I I I ,0 0 0 0 1 I0 :91 ALU-A,CY 0 1I , ,i 0000 1 1 IAI-ALU 191 ALl.f-A,CY I iI ROTATE I191 I ALl.f-A, CY , I ,!I 0 0 0 0I 1 : I I IAI, CY-ALU I191 ALl.f-A,CY , ,0 0 0 I 1 ! I ROTATE II i II ! I I IAI. CY-ALU I , ,0 0 1 C 1 ! i II i ROTATE ,0 0 1 I 1 ! I I ! (AI-A I I I : I II I II II ! CY-CY I , ,0 0 I I I I i 0 ! I l-CY ii I ! I IiPC OUT 100 00 11 i i ,I JMPaddr i X, PC' pc \u2022 , 82-tZ I l ', ,J cond BOdrl171 STATUSI61 82TZ I ,CALL add, ! PC-PC., 82 ---!-Z I I , ,C cona addr(11) I I I I CC C0 0 1 ,UDGE CONDITION IPC OUT i 82~Z i SP - SP - 1 STATUS'61 ! I 10 0 1I 0I II JUDGE CONDITION pC OUT I PC-PC., OATA-+-Z i IF TRUE,SP-SP - 1 STATUSI61 1 I ! I X pC OUT I CC C 0 0 i STATUS(61 I PC\u00b7PC+' DATA+Z !I I JUOGECONDITION(l41 I I i ,I SP\u00b7SP.I I !RET I IPCHI---!-OATA 8US I 100 1 I 00 1 1 SPOUT I SP\u00b7 SP. , I I i STATUS(151 i I INST-TMPIIR I iR cond addr ti71 I SP\u00b7 SP. I 1 1CC C0 0 0 I , SP OUT STATUS(l51 I i<>-W i FIST\\\" i !INST-TMPIIR SP OUT i Sp-SP.' \\\"CHL , ,!I 1 N N N 1 1 I PUSH,p ! I STATUsll61 I PUSH PSW I POP rp ,1 I I 0 I , IIi I 10 0 I : lNST-TMPIIR I H L I - - - - 4 PC I I Ii i \u2022 R 0I 0I i I SP\u00b7SP., ISP OUT ! SP'SP-l \\\"hl-1.0ATA 8US P ! I I , ,i 1 I I 1 STATUSI161 I i I ! I SP OUT I SP-SP-1 STATUSl161 ! IAI-\\\"-,DATA BUS 0 10 1 I i sp-SP-, I i I I ,I 1 R P i 0 0 0 1 DATA~' I .1 II X SP OUT SP-SP., I I ,I I ! STATUSl151 000I I POP PSW I 1 1I II 1 X SP OUT I SP _\u00b7SP + 1 OA TA -l-F LAGS I I ! I STATUSl151 i I I SP - SP \u2022 1 DATA-tZ XTHL iI 1 1 0 00 I I IX SP OUT IN-, STATUs!'51 B2iZ,W OUT-, , , ,0 I 10 1 I II X PC OUT PC-PC.' I , II ,I 0 I 0 0 1 !I STATUSI61 82 -+-Z. W I ! I \u00b71 Xi PC OUT pc-PC\u00b7, I I STATUSl61 SeT INTE F\/F EI I 1 1 1 ! 1 0 I I Ii I II I I DI I 1I 1 00I 1 II i RESET INTE F\/F I IHLT ! I IX I PC OUT HA LT MOOEIJJI 0 1I 1 0 1 10 I STATUS ! PC OUT I ,i , IX I i~JOP I0 000 0000 STATUS PC - PC \u2022 ,! INST-TMP\/IR I i 2-38 Apri 1. 1977 8800b","M3 Me Me T1 T2121 T3 T1 T2121 T:J IT1 nl21 T3 T4 n I I I191 IACTI+ITMPl-A 191 IACTl'1TMPI-A 191 IACTI'1TMPl-A I!I IACTI+lTMPl-A 191 i IACTl+ITMPI-A I I [!I IACTI-{TMP), F\\\\.AGS I [91 IACTI-ITMPI, FLAGS , I~ I PC OUT I PC-PC\u00b7, B3~W WZOUT . IWZI + I-PC STATUsl11 ) STATUS{61 PC OUT PC-PC\\\"\\\" BJl- :fA~II,121 IWZl+l-PC STATUsl61 PC-PC ... , ~~~slI61 I WZOUT IWZl + I-PC STATUS(11) PC OUT B3-+, -w SPOUT IPCHI---1-0ATA BUS IPCU-+ OATA BUS STATUS!SI STATUS[I81 SP-SP-l I i PC OUT PC-PC'\\\" BJ -t-w{IJI IS1' OUT IPCHI--__ OATA BUS S1' OUT i IPCl..lTOATA SUS :f...~111.121 {WZl + I-PC STATUsiSI STATUsI' 61 I I STATusllSI SI\\\" sp\u00b7 1 I SPOUT SP\u00b7 SJll+- 1 OATA~W WZOUT I IWZl + I-PC ISTATUs11 51 STATusl11 I I I SI' OUT i, SP-SP.1 DATA-,-W IWZOUT {WZI.,-PC STATUS1151 SPOUT I STATUsl\\\".'21 STATUSl161 I WZOUT IWZl+I-PC STATUsll1 I i ITMP - OONNNmL-+.tATA BUS SPOUT Idl-f-OATA BUS STATUsI161 , SPOUT I FLAGS-J-oATA BUS STATUS1161 S1' OUT , I STATUS!151 I SP\u00b7SP., OATA-J...\\\" ! I SPOUT SP-SP+l OATA--;''' ISPOUT , IHI OATA BUS SPOUT II U - t DATA BUS IWZl -HI.. STATusl151 STATUS(ISI , SPOUT i DATATW STATUsll61I STATUsl151 ! O. . T A - . . . . . I I i 1AI7Ql\\\\TA BUS IWZOUT STATUS{181 WZOUT I! STATUS1181 II 2-39 April. 1977 8800b","NOTES: 12. If the condition was met, the contents of the register pair WZ are output on the address lines (AQ.1S) instead of 1. The first memory cycle (M1) is always an instruction the. contents of the program counter (PC). fetch; the first (or only) byte. containing the op code. is fetched during this cycle. 13. If the condition was not met, sub-cycles M4 and M5 are skipped; the processor instead proceeds immedi~tely to 2. If the READY input from memory is not high during T2 of each memory cycle. the processor will enter a wait the instruction fetch (M1) of the next instruction cycle. state (TW) until READY is sampled as high. 14. If the condition was not met, sub-cycles M2 and M3 3. States T4 and T5 are present. as required. for opera- are skipped; the processor instead proceeds immediately to tions which are completely internal to the CPU. The con\u00b7 the instruction fetch (Ml) of the next instruction cycle. tents of the internal bus during T4 and T5 are available at the data bus; this is designed for testing purposes only. An 15. Stack read sub-eycle. \\\"X\\\" denotes that the state is present, but is only used for such internal operations as instruction decoding. 16. Stack write sub-cycle. 4. Only register pairs rp = B (registers B and C) or rp = D 17. CONDITION CCC (registers D and E) may be specified. NZ not zero (Z = 0) 000 001 5. These states are skipped. Z zero (Z = 1) 010 011 6. Memory read sub-cycles; an instruction or data word NC no carry (CY =0) 100 will be read. 101 C carry (CY '\\\" 1) 110 7. Memory write sub-cycle. 111 PO parity odd (P '\\\" 0) 8. The READY signal is not required during the second and third sub-cycles (M2 and M3). The HOLD signal is PE parity even (P = 1) accepted during M2 and M3. The SYNC signal is not gene- rated during M2 and M3. During the execution of DAD, P plus (S\\\"'O) M2 and M3 are required for an internal register-pair add; memory is not referenced. M minus (S= 1) 9. The results of these arithmetic. logical or rotate in\u00b7 18. I\/O sub-cycle: the I\/O port's 8-bit select code is dupli- structions are not moved into the accumulator (A) until cated on address lines 0\u00b77 (AQ.7) and 8-15 (AS-1S). state T2 of the next instruction cycle. That is, A is loaded while the next instruction is being fetched; this overlapping 19. Output sub-cycle. of operations allows for faster processing. 20. The processor will remain idle in the halt state until 10. If the value of the least significant 4-bits of the accumu- an interrupt, a reset or a hold is accepted. When a hold re- lator is greater than 9 ~ if the auxiliary carry bit is set, 6 quest is accepted, the CPU enters the hold mode; after the is added to the accumulator. If the value of the most signifi- hold mode is terminated, the processor returns to the halt cant 4-bits of the accumulator is now greater than 9, ~ if state. After a reset is accepted, the processor begins execu- the carry bit is set, 6 is added to the most significant tion at memory location zero. After an interrupt is accepted, 4-bits of the accumulator. the processor executes the instruction forced onto the data bus (usually a restart instruction). 11. This represents the first sub-cycle (the instruction retch) of the next instruction cycle. SSS or DOD I Value , rp I Value A ! 111 IB ! 00 I 01 B I 000 i D I 10 I C I 001 IH I 11 0 i 010 i SP E I 011 I I IH i 100 l L 101 2-40 April, 1977 3aOCb","This chapter will illustrate, in detail, how to interface Control Bus A uni-directional set of signals that indicate the 8080 CPU with Memory and I\/O. It will al~o show the the type of activity in current process. benefits and tradeoffs encountered when using a variety of system architectures to achieve higher throughput, de- Type of activities: 1. Memory Read creased component count or minimization of memory size. 2. Memory Write 3. I\/O Read 8080 Microcomputer system design lends itself to a 4. I\/O Write simple, modular approach. Such an approach will yield the 5. Interrupt Acknowledge designer a reliable, high performance system that contains a minimum component count and is easy to manufacture and maintain. The overall system can be thought of as a simple block diagram. The three (3) blocks in the diagram repre- sent the functions common to any computer system. CPU Module* Contains the Cantral Processing Unit, system CPU timing and interface circuitry to Memory and I\/O devices. MODUl.c Memory Contains Read Only Memory (ROM) and ReadlWrite Memory (RAM) for program and data storage. I\/O Con't2ins circuitry that allows the computer Figure 3-1. Typical Computer System Block Diagram system to communicate with devices or structures existing outside of the CPU or Memory array. for example: Keyboards, Floppy Disks, Basic System Operation Paper Tape, etc. ,. The CPU Module issues an activity command on the Control Bus. There are three busses that interconnect these blocks: 2. The CPU Module issues a binary code on the Address Bus to identify which particular Memory location or Data Busf A bi-directional path on which data can flow I\/O device will be involved in the current process between the CPU and Memory or I\/O. activity. Address Bus A uni-directional group of lines that identify 3. The' CPU Module receives or transmits data with the a particular Memory location or I\/O d~evice. selected Memory location or I\/O device. \u00b7\\\"Module\\\" refers to a functional block, it does not ref- CD4. The CPU Module returns to and issues the next enmce a printed circuit board manufactured by INTEL. activity command. t\\\"Sus\\\" refers to a set of signals grouped together because of the similarity of their functions. It is easy to see at this point that the CPU module is the central element in any computer system. Apri', i97i 2-41 88CCb","The following pages will cover the detailed design of the design and to achieve operational characteristics that the CPU Module with the 8080. The three Busses (Data, are as close as possible to those of the 8224 and 8228. Address and Control) will be developed and the intercon- Many auxiliary timing functions and features of the 8224 nection to Memory and 1\/0 will be shown. and 8228 are too complex to pr~ctically implement in standard components, so only the basic functions of the Design philosophies and system architectures pre- 8224 and 8228 are generated. Since significant benefits in sented in this manual are consistent with product develop\u00b7 system timing and component count reduction can be realized by using the 8224 and 8228, this is the preferred ment programs underway at INTEL for the MCS~80. Thus, method of implementation. the designer who uses this manual as a guide for his total 1. 8080 CPU system engineering is assured that all new developments in components and software for MCS-80 from INTEL will be The operation of the 8080 CPU was covered in pre- compatible with his design approach. vious chapters of this manual, so little reference will be made to it in the design of the Module. CPU Module Design 2. Clock Generator and High Level Driver The CPU Module contains three major areas: The 8080 is a dynamic device, meaning that its inter- 1. The 8080 Central Processing Unit nal storage elements and logic circuitry require a timing reference (Clock), supplied by external cir- 2. A Clock Generator and High Level Driver cuitry, to refresh and provide timing control signals. 3. A bi-direetional Data Bus Driver and System Control The 8080 requires two (2) such Clocks. Their wave\u00b7 Logic forms must be non-overlapping, and comply with the timing and levels specified in the 8080 A.C. and D.C. The following will discuss the design of the three Characteristics, page 5-1 S. major areas contained in the CPU Module. This design is presented as an alternative to the Intel\u00ae 8224 Clock Gener- Clock Generator Design ator and Intel 8228 System Controller. By studying the alternative approach, the designer can more clearly see the The Clock Generator consists of a crystal controlled, considerations involved in the specification and engineering of the 8224 and 8228. Standard TTL components and Intel general purpose peripheral devices are used to implement GNO 2 ~5 ,00 '5V 20 -;V 11 AD 26 Al 27 A2 A2 43 . ' 2 v . - 2 !.. A3 29 30 ,.4 A4 A5 31 A5 A6 8080 A6 32 A7 C?U A7 33 ADDRESS 8US 13 34 A8 A8 A9 SYSTEM OMA REO HOLD \\\"9 35 AID 1 Ala All >0 jAll SySTEM ;NT REO. \\\" INT A12 37 :;~ A13 38 ,.14 INT. ENA8LE ~ INTE A14 39 ,.'5 A15 36 rl\u00b0nm WA 18 . 11 0 17 081N 21 HLOA 22 .>, DO 'a I+-- 080 15 I+-- 081 .'2 9 ~BI\u00b7OIREC- CLOCK 24 01 D82 DATA BUS GENERATOR 23 WAIT 083 12 READY 8 WAIT Reo --0 DRivER 19 RESET 02 I + - -TIONAL OB4 - =SYS RESET SYNC 7 SUS DRivER 03 ~I+-- 087c_le- 04 3 085 4 086 05 ,5 06 07 1NfA~Ie-ac I STATUS STROBE .--- lOWMEM'R SYSTEM .\\\".EMW CONTROL BUS CONTROL 10 R Figure 3-2. 8080 CPU Interface Apr; 1, 19i7 8800b 2-42","OSCILLATOR 74504 II-I~D<:>-\\\"\\\"-or:>-_-------------_--------O_SC CLOCK GENERATOR ,--;::==n:>--r),.....l---------. ;;i ITTI.) GNO-....-- tl......~~;....\\\"j -Tt-;:n::>-rr~....l---------+~ (TTl.) AUXILIARY FUNCTIONS SYNC 74HOO WAveFORMS t-----l--lo 74S74 I.K c r l - . ; - - - - - + 'Il1A ITTW <\/J1~ U -t '~~ I!.-SOnt WAIT Rea ----l-~ ReAOY 92.-l \\\\ I250ftl -.J \\\\SOn.~ f.- --i r-SOnl 01A 250ns SYNC OMA Rea ----+-~ ,\\\"01.0 ffi'frj - - - - - - - - . - . , .\\\\ - - - - - ' Figure 3-3. 8080 Clock Generator positIve transition when biased from the 8080 VOO supply (12V) but to achieve the low voltage specifi\u00b7 20 MHZ oscillator, a four bit counter, and gating circuits. cation (VILC) .8 volts Max. the driver is biased to the 8080 Vas supply (-5VI. This allows the driver to The oscillator provides a 20 MHZ signal to the input swing from GND to Voo with the aid of a simple of a four (4) bit, presettable, synchronous, binary counter. By presetting the counter as shown in figure resistor divider. 3\u00b73 and clocking it with the 20 MHZ signal, a simple A low resistance series network is added between the driver and the 8080 to eliminate any overshoot of the decoding of the counters outputs using standard TTL pulsed waveforms. Now a circuit is apparent that can gates, provides.proper timing for the two (2) 8080 easily comply with the 8080 specifications. In fact clock inputs. rise and fall times of this design are typically less than 10 ns. Note that the timing must actually be measured at the output of the High Level Driver to take into ac\u00b7 +12V count the added delays and waveform distortions within such a device. 680 pF 6 47!1 01 High Level Driver Design -?l-IT-TI.)~, 2 MH0026 ~--_-VJ'.r-+ 18080 PIN 22) The voltage level of the clocks for the 8080 is not OR TTL compatible like the other signa'$~hat input to ;;Ti'i'TLi - - l680 pF 4 47!1 the 8080. The voltage swing is from .6 volts (VILC ) EQUIV. 5 <1>2 to 11 volts (V1HC ) with risetimes and falltimes under 50 ns. The Capacitive Drive is 20 pf (max.). Thus, a IS080 PIN lSI High Level Driver is required to interface the outputs of the Clock Generator (TTL) to the 8080. 3 The two (2) outputs of the Clock Generator are ca\u00b7 M\\\"'I----J. r'L...---__- ......,. 15K 15K pacitivity coupled to a dual- High Level clock driver. . lN4002 The driver must be capable of complying with the \\\".\\\". 8080 clock input speci fications, page 5\u00b715. A driver -SV of this type usually has little problem supplying the Figure 3-4. High Level Driver AOl\\\"il. 197i 8300b 2-43","Auxiliary Timing Signals and Functions 3. Bi-Directional Bus Driver and System Control Logic The Clock Generator can also be used to provide The system Memory and I\/O devices communicate other signals that the designer can use to simplify with the CPU over the bi-directional Data Bus. The large system timing or the interface to dynamic system Control Bus is used to gate data on and off memories. the Data Bus within the proper timing sequences as dictated by the operation of the 8080 CPU. The data Functions such as power-on reset, synchronization of lines of the 8080 CPU. Memory and I\/O devices are external requests (HOLD. READY, etc.) and single 3-s13te in nature, that is. their output drivers have step. could easily be added to the Clock Generator to the ability to be forced into a high-impedance mode further enhance its capabilities. and are, effectivety. removed from the circuit. This 3- state bus technique allows the designer to construct a For instance, the 20 MHZ signal from the oscillator system around a single, eight (8) bit parallel, bi-direc- can be buffered so that it could provide the basis for tional Data Bus and simply gate the information on communication baud rate generation. or off this bus by selecting or deselecting (3-stating) Memory and I\/O devices with signals from the Con\u00b7 The Clock Generator diagram also shows how to gen- trol Bus. erate an advanced ~iming signal (<t>lA) that is handy to use in clocking \\\"0\\\" type flipflops to synchronize Bi\u00b7Directional Data Bus Driver Design external requests. It can also be used to generate a strobe (STSTB) that is the latching signal for the sta- The 8080 Data Bus (07\u00b700) has two (2) major areas tus information which is available on the Data Bus at of concern for the designer: the beginning of each machine cycle. A simple gating of the SYNC signal from the 8080 and the advanced 1. Input Voltage level (V1H ) 3.3 volts minimum. (<t>lA) will do the job. See Figure 3\u00b73. 2. Output Drive Capability (I0L) 1.7 mA maximum. - au DO 2.4 r- 8216 3 DBO 01 5.7 r- 6 DBl 02 9.11r- OlEN cs 10 03 12.14 r- 13 OB2 15'1' '(1 OB3 04 05 2.4 r- 3 OB4 DB 5.7 r- 6 07 OBS OBIN 9.11r- 8216 10 DBB 8080 I CE-J12.14,- 13 OlEN OB7 WA 1SY '-'1 ....... .... I - ...... ---~ ~K4 INTA ~ 7 9 8212 '\\\"i'O'Hi:TA p . y -16 15 OUT 1B 17 Ml 20 19\\\"iNP I 22 21 ~eMR - i - l JSTSTB 12 113 LLY- Vee .... \u00b7V ....... I....L):>-- Figure 3\u00b75. 8080 System Control Apr; 1. 19i7 2-44 88COb","The input level specification implies that any semi- Status information. The signal that loads the data conductor memory or I\/O device connected to the into the Status Latch comes from the Clock Gener\u00b7 8080 Data Bus must be able to provide a minimum of ator. it is Status Strobe (STSTB) and occurs at the 3.3 volts in its high state. Most semiconductor mem- start of each Machine Cycle. ories and standard TTL I\/O devices have an output capability of between 2.0 and 2.8 volts. obviously a Note that the Status Latch is connected onto the direct connection onto the 8080 Data Bus would re- 8080 Data Bus (07-00) before the Bus Buffer. This is quire pullup resistors. whose value should not affect to maintain the integrity of the Data Bus and simplify the bus speed or stress the drive capability of the Control Bus timing inOMA dependent environments. memory or I\/O components. As shown in the diagram. a simple gating of the out- The 8080A output drive capability (I0L) 1.9mA max. is sufficient for small systems where Memory size and puts of the Status Latch with the DB INand W\\\"R I\/O requirements are minimal and the entire system is contained on a single printed circuit board. Most sys\u00b7 signals from the 8080 generate the (4) four Control tems however. take advantage of the high\u00b7perfor- signals that make up the basic Control Bus. mance computing power of the 8080 CPU and thus a more typical system would require some form of buf\u00b7 These four signals: 1. Memory Read (MEM R) fering on the 8080 Data Bus to support a larger array of Memory and I\/O devices which are likely to be on 2. Memory Write (MEM W) separate boards. 3. I\/O Read (I\/O R) A device specifically designed to do this buffering function is the INTE~ 8216, a (4) four bit bi-direc- 4. I\/O Write (I\/O W) tional bus driver whose input voltage level is compat- ible with standard TTL devices and semiconductor -M memory components, and has output drive capability of 50 mA. At the 8080 side. the 8216 has a \\\"high\\\" connect directly to the MCS-80 component \\\"family\\\" output of 3.65 volts that not only meets the 8080 of ROMs. RAMs and I\/O devices. input spec but provides the designer with a worse case 350 mV noise margin. A fifth signal. Interrupt AcknOWledge (I NTA) is added to the Control Bus by gating data off the A pair of 8216's are connected directly to the 8080 Status Latch with the DBfN signal from the 8080 Data Bus (07-00) as shown in figure 3-5. Note that CPU. This signal is used to enable the Interrupt the DB IN signal from the 8080 is connected to the Instruction Port which holds the RST instruction direction control input (0\/ EN) so the correct flow of onto the Data Bus. data on the bus is maintained. The chip select (CS) of Other signals that are part of the Control Bus such as the 8216 is connected to BUS ENABLE (B'OSEN) to WO, Stack and M1 are present to aid in the testing of allow for DMA activities by deselecting the Data Bus the System and also to simplify interfacing the CPU Buffer and forcing the outputs of the 8216's into to dynamic memories or very large systems that re- their high impedance (3-state) mode. This allows quire several levels of bus buffering. other devices to gain access to the data bus (DMA). Address Buffer Design System Control Logic Design The Address Bus (A 15-AO) of the 8080, like the Data Bus, is sufficient to support a small system that has a The Control Bus maintains discipline of the bi-direc- moderate size Memory and I\/O structure. confined to tional Data Bus. that is, it determines what type of a single card. To expand the size of the system that device will have access to the bus (Memory or I\/O) the Address Bus can support a simple buffer can be arc generates signals to assure that these devices added, as shown in figure 3-6. The INTEL@8212 or transfer Data with the 8080 CPU within the proper 8216 is an excellent device for this function. They timing \\\"windows\\\" as dictated by the CPU operational provide low input loading (.25 mAl. high output characteristics. drive and insert a minimal delay in the System Timing. As described previously. the 8080 issues Status infor- mation at the beginning of each Machine Cyele on its Note that BUS ENABLE (BUSEN) is connected to Data Bus to indicate what operation will take place the bdfers so that they are forced into their high- during that cycle. A simple (8) bit latCh. like an impedance (3-state) mode during DMA activities so INTEL\u00ae 8212. connected directly to the 8080 Data that other devices can gain access to the Address Bus. Bus (07-00) as shown in figure 3\u00b75 will store the 2-45 Apri 1, 1977 3800b","INTERFACING THE 8080 CPU TO MEMORY This feature eliminates the need for extra equipment like tape readers and disks to load programs initially, an im- AND I\/O DEVICES portant aspect in small system design. The 8080 interfaces with standard semiconductor Interfacing standard ROMs, such as the devices shown Memory components and I\/O devices. In the previous text in the diagram is simple and direct. The output Data lines the proper control signals and buffering were developed are connected to the bi-directional Data Bus, the Address which will produce a simple bus system similar to the basic inputs tie to the Address bus with possible decoding of the system example shown at the beginning of this chapter. most significant bits as \\\"chip selects\\\" and the MEMR signal from the Control Bus connected to a \\\"chip select\\\" or data In Figure 3-6 a simple, but exact 8080 typical system buffer. Basically, the CPU issues an address during the first is shown that can be used as a guide for any 8080 system, portion of an instruction or data fetch (T1 & T2). This regardless of size or complexity. It is a \\\"three bus\\\" archi- value on the Address Bus selects a specific location within tecture, using the signals developed in the CPU module. the ROM, then depending on the ROM's delay (access time) the data stored at the addressed location is present at the Note that Memory and I\/O devices interface in the Data output lines. At this time (T3) the CPU Data Bus is same manner and that their isolation is only a function of in the \\\"input Mode\\\" and the control logic issues a Memory the definition of the Read-Write signals on the Control Bus. Read command (MEMR) that gates the addressed data on This allows the 8080 system to be configured so that Mem- to the Data Bus. ory and I\/O are treated as a single array (memory mapped\u00b7 I\/O) for small systems that require high thruput and have RAM INTERFACE less than 32K memory size. This approach will be brought out later in the chapter. A RAM is a device that stores data. This data can be program, active \\\"look-up tables,\\\" temporary values or ex- ROM INTERFACE ternal stacks. The difference between RAM and ROM is that data can be written into such devices and are in A ROM is a device that stores data in the form of essence, Read\/Write storage elements. RAMs do not hold Program or other information such as \\\"look-up tables\\\" and their data when power is removed so in the case where Pro- is only read from, thus the term Read Only Memory. This gram or \\\"look-up tables\\\" data is stored a method to load type of memory is generally non-volatile, meaning that when the power is removed the information is retained. HOLO REQ 8702A ROMs 8302 8101\u00b72 RAMs 8102A\u00b74 8704 8308 8111\u00b72 5101 8107B-4 a70B a316A 2102\u00b72 8210 8222 OAT'\\\" BUS lal D DL--=~----JII '0' DL--_--Ji I (r i L _ _ _---JL.CIJ {l CONTROL BUS 161 LCILJ I I[JTJ LC AOORESS BUS 1161 8251 1\/0 8212 1\/0 PRIORITY 8255 PERIPHERAL INTERRUPT COMMUNICATION INTERFACE INTERFACE Figure 3-6. Microcomputer System Apr; 1. 1977 !!800b 2-46","RAM memory must be provided, such as: Floppy Disk, The memories chosen for this example have an access Paper Tape, etc. time of 850 nS (max) to illustrate that slower, economical devices can be easily interfaced to the 8080 with little ef\u00b7 __ The CPU treats RAM in exactly the same manner as fect on performance. When the 8080 is operated from a ROM for addressing data to be read. Writing data is very clock generator with a tCY of 500 nS the required memory similar; the RAM is issued an address during the first por\u00b7 access time is Approx. 450\u00b7550 nS. See detailed timing tion of the Memory Write cycle (Tl & T2) in T3 when the specification Pg. 5\u00b716. Using memory devices of this speed data that is to be written is output by the CPU and is stable such as Intel<!l8308, 8102A, 8107A, etc. the READY input on the bus an MEMW command is generated. The MEMW to the 8080 CPU can remain \\\"high\\\" because no \\\"wait\\\" signal is connected to the R\/W input of the RAM and states are required. Note that the bus interface to memory strobes the data into the addressed location. shown in Figure 3\u00b77 remains the same. However, if slower memories are to be used, such as the devices illustrated In Figure 3\u00b77 a typical Memory system is illustrated (8316A, 8111) that have access times slower than the min\u00b7 to show how standard semiconductor components interface imum requirement a simple logic control of the READY to the 8080 bus. The memory array shown has 8K bytes input to the 8080 CPU will insert an extra \\\"wait state\\\" that (8 bits\/byte) of ROM storage, using four Intet~8216As is equal to one or more clock periods as an access time and 512 bytes of RAM storage, using Intel 8111 static \\\"adjustment\\\" delay to compensate. The effect of the extra RAMs. The basic interface to the bus structure detailed \\\"wait\\\" state is naturally a slower execution time for the here is common to almost any size memory. The only ad\u00b7 instruction. A single \\\"wait\\\" changes the basic instruction dition that might have to be made for larger systems is cycle to 2.5 microSeconds. more buffers (8216\/8212) and decoders (8205) for gener\u00b7 ating \\\"chip selects.\\\" 8K + 512 8K o RAM ROM MEMORY MAP ROM RAM #4 =3 =2 =1 8111 alll -L... a31SA CS3 f4- I\/O 1\u00b74 1\/01-4 \\\"- CSi 01\u00b70a CS2 \\\"- A\/W 00 AO\u00b7A7 L... RiW 00 AO\u00b7A7 AO\u00b7Al0 \\\"MEMW ~~r} \\\" 1 fM\\\"EM'R ..:: ). \\\"ME'MA t: ::. All\u00b7 0:: AQ-A7 DAo.A7 MEMW'\\\" AQ-A10 7 A12 _0_-,--0 DATA'US\\\"tJ'-----_Dl...-----I-.-_O____ _ _L i lCONTROl. BUS 16l Il~ ADDRESS BUS (16l Figure 3-7. Typical Memory Interface 2-47 Apr; 1, 1977 S8COb","I\/O INTERFACE General Theory MEMR } TO MEMORY As in any computer based system, the 8080 CPU must 1:>----- __ DEVICES be able to communicate with devices or structures that exist MEMW outside its normal memory array. Devices like keyboards, paper tape, floppy disks, printers, displays and other control SYSTEM iTciR} TO I\/O DEVICES structures are used to input information into the 8080 CPU CONTROL and display or store the results of the computational activity. p...----I\/OW 182281 Probably the most important and strongest feature of the 8080 Microcomputer System is the flexibility and power Figure 3-9. Isolated I\/O. of its I\/O structure and the components that support it. There are many ways to structure the I\/O array so that it will \\\"fit\\\" Memory Mapped I\/O the total system environment to maximize efficiency and minimize component count. By assigning an area of memory address space as I\/O a powerful architecture can be developed that can manipulate The basic operation of the I\/O structure can best be I\/O using the same instructions that are used to manipulate viewed as an array of single byte memory locations that can memory locations. Thus, a \\\"new\\\" instruction set is created be Read from or Written into. The 8080 CPU has special in- that is devoted to i\/O handling. structions devoted to managing such transfers (I N, OUT). These instructions generally isolate memory and I\/O arrays As shown in Figure 3-10, new control signals are gene- so that memory address space is not effected by the I\/O rated by gating the MEMR and MEMW signals with A1S, the structure and the general concept is that of a simple transfer most significant address bit. The new I\/O control signals con- to or from the Accumulator with an addressed \\\"PORT\\\". An- nect in exactly the same manner as Isolated I\/O, thus the other method of I\/O architecture is to treat the I\/O structure system bus characteristics are unchanged. as part of the Memory array. This is generally referred to as \\\"Memory Mapped I\/O\\\" and provides the designer with a By assigning A15 as the I\/O \\\"flag\\\", a simple method of powerful new \\\"instruction set\\\" devoted to I\/O manipulation. I\/O discipline is maintained: ISOLATED 110 If A15 is a \\\"zero\\\" then Memory is active. If A 15 is a \\\"one\\\" then I\/0 is active. I II~-a------------------6-5K~ Other address bits can also be used for this function. A15 was I ;S chosen because it is the most significant address bit so it is easier to control with software and because it still allows \\\"'EMORY memory addressing of 32K. j) I\/O devices are still considered addressed \\\"ports\\\" but instead of the Accumulator as the only transfer medium any a 256 of the internal registers can be used. All instructions that could be used to operate on memory locations can be used : 8 .I I in I\/O. r---------------------~ Examples: 1 ._\\\" T ,~ ri lI MOVr, M (Input Port to any Register) I~ \\\"'EMORY MAPPED I\/O MOV M, r (Output any Register to Portl MVIM (Output immediate data to Port) Figure 3-8. Memory\/I\/O Mapping. LOA (I nput to ACC) (Output from ACC to Port) Isolated I\/O STA (16 Bit Input) (16 Bit Output) In Figure 3-9 the system control signals, previously de- LHLO (Add Port to ACC) tailed in this chapter, are shown. This type of I\/O architecture SHLO (\\\"AND\\\" Port with ACC) separates the memory address space from the I\/O address ADD M space and uses a conceptually simple transfer to or from Ac- ANAM cumulator technique. Such an architecture is easy to under- stand because I\/O communicates only with the Accumulator It is easy to see that from the list of possible \\\"new\\\" using the IN or OUT instructions. Also because of the isola- instructions that this type of I\/O architecture could have a tion of memory and 1\/0, the full address space (65K) is un- drastic effect on increased system throughput. It is concep- effected by I\/O addressing. tually more difficult to understand than Isolated I\/O and it does limit memory address space, but Memory Mapped I\/O can mean a significant increase in overall speed and at the same time reducing required program memory area. 2-48 Apl\\\"~l. 1977 8800b","10-------..,.--- MEMii TO The second example uses Memory Mapped I\/O and linear select to show how thirteen devices (8255) can be ad- MEMORY dressed without the use of extra decoders. The format shown cou Id be the second and third bytes of the LOA or STAin\u00b7 Io-----~-+--- MEMW } DEVICES structions or any other instructions used to manipulate I\/O using the Memory Mapped technique. SYSTEM I\/OR(MM~ CONTROL TO 1\/0 It is easy to see that such a flexible I\/O structure, that DEVICES can be \\\"tailored\\\" to the overall system environment, provides 182211 I\/OWIMMI the designer with a powerful tool to optimize efficiency and minimize component count. EXAMPLE #2 Figure 3\u00b710. Memory Mapped I\/O. I\/O Addressing I } PORT SELECTS With both systems of I\/O structure the addressing of ,-.__I,.I,------lI ---~-------JO~,tt\\\"'~ each device can be configured to optimize efficiency and reo duce component count. One method, the most common, is 1 to decode the address bus into exclusive \\\"chip selects\\\" that enable the addressed I\/O device, similar to generating chip- '------'--------------J o~..,,'~ selects in memory arrays. ' - - - - - - - - - - - - 1\/0 FLAG I-I\/O Another method is called \\\"linear select\\\". In this method, D-MEMORY instead of decoding the Address Bus, a singular bit from the ADDRESSES - 13 -82550 bus is assigned as the exclusive enable for a specific I\/O de- 139 PORTS - 312 BITS1 vice. This method, of course, limits the number of I\/O de- vices that can be addressed but eliminates the need for extra decoders, an important consideration in small system design. A simple example illustrates the power of such a flexi\u00b7 ble I\/O structure. The first example illustrates the format of the second byte of the IN or OUT instruction using the Iso- lated I\/O technique. The devices used are Intel\u00ae8255 Pro- grammable Peripheral Interface units and are linear selected. Each device has three ports and from the format it can be seen that six devices can be addressed without additional de- coders. EXAMPLE #1 Figure 3\u00b712. Memory Mapped I\/O - (Linear Select (8255) I\/O Interlace Example LJ:.1~1~1~1~1~1~1~1~1 In Figure 3-16 a typical I\/O system is shown that uses a } PORT SELECTS variety of devices (3212,8251 and 82551. It could be used '- I }o~,tt\\\"'~ to interface the peripherals around an intelligent CRT termi\u00b7 ADDRESSES - 6 - 82550 nals; keyboards, display, and communication interface. An\u00b7 (18 PORTS - 144 81TS1 other application could be in a process controller to interface sensors, relays, and motor controls. The limitation of the ap- Figure 3-11. Isolated I\/O - (Linear Select) (8255) plication area for such a circuit is solely that of the designers ':'ori 1, 197i imagination. 8800b The I\/O structure shown interfaces to the 8080 CPU using the bus architecture developed previously in this chap\u00b7 ter. Either Isolated or Memory Mapped techniques can be used, depending on the system I\/O environment. The 8251 provides a serial data communication inter\u00b7 face so that the system can transmit and receive data over communication links such as telephone lines. 2-49","The three 8212s can be used to drive long lines or LED indicators due to their high drive capability. (15mA) ~LOOA'11 Ao O-OATA CiO CONTROL I-COMMAND _ 8251 SELECT ' - - - - - - - - iACTlVE LOW) 1...- ~~~~:~~~~; Figure 3-13. 8251 Format. '----------- ~~~~:~7~~T The two (2) 8255s provide twenty four bits each of 1...- ~. .J : ~ 7 ~ ~ programmable I\/O data and control so that keyboards, sen\u00b7 sors, paper tape, ete., can be interfaced to the system. ao -PORT A Figure 3\u00b715. 8212 Format. aI-PORTS Addressing the structure is described in the formats il\u00b7 lustrated in Figures 3\u00b713,3\u00b714,3-15. Linear Select is used so '0 -PORTC that no decoders are required thus, each device has an ex- '1 -COMMAND clusive \\\"enable bit\\\". S255 ..1 SELECT The example shows how a powerful yet flexible I\/O L:=:=L=.}.'\\\"\\\"\\\"\\\"'''I I structure can be created using a minimum component count (ACTIVE LOW) with devices that are all members of the 8080 Microcomputer System. 1..-. ~~~~~~~c;r Figure 3-14. 8255 Format. SERIAL DATA -- COMMUNICATION =1 ,I 8255 8251 iT<iR DATA BUS CONTROL sus ADDRESS SUS 8212 8212 8212 =3 \\\"2 =1 MD MD MD Figure 3\u00b716. Typical I\/O Interface. Aoril. 1977 88COb 2-50","A computer, no matter how sophisticated, can only are programs available which convert the programming lan- do what it is \\\"told\\\" to do. One \\\"tells\\\" the computer what guage instructions into machine code that can be inter- to do via a series of coded instructions referred to as a Pro- preted by the processor. gram. The realm of the programmer is referred to as Soft\u00b7 ware, in contrast to the Hardware that comprises the actual One type of programming language is Assembly Lan- computer equipment. A computer's software refers to all of guage. A unique assembly language mnemonic is assigned to the programs that have been written for that computer. each of the computer's instructions. The programmer can write a program (called the Source Program) using these When a computer is designed, the engineers provide mnemonics and certain operands; the source program is then converted into machine instructions (called the Object the Central Processing Unit (CPU) with the ability to per\u00b7 Code). Each assembly language instruction is converted into one machine code instruction (1 or more bytes) by an form tahaptaartiscpuelcairficseot poefraotipoenr\u2022aitsiopnesr.foTrmheedCPwUheins designed Assembler program. Assembly languages are usually ma- such the CPU chine dependent (I.e.\u2022 they are usually able to run on only one type of computer). control logic decodes a particular instruction. Consequently, THE 8080 INSTRUCTION SET the operations that can be performed by a CPU define the The 8080 instruction set includes five different types computer's Instruction Set. of instructions: Each computer instruction allows the programmer to \u2022 Data Transfer Group-move data between registers initiate the performance of a specific operation. All com- or between memory and registers puters implement certain arithmetic operations in their in\u00b7 struction set, such as an instruction to add the contents of \u2022 Arithmetic Group - add. subtract, increment or two registers. Often logical operations (e.g.. OR the con- decrement data in registers or in memory tents of two registers) and register operate instructions (e.g.\u2022 increment a register) are included in the instruction set. A \u2022 Logical Group - AND, OR, EXCLUSIVE\u00b7OR, computer's instruction set will also have instructions that compare, rotate or complement data in registers move data between registers, between a register and memory, or in memory and between a register and an I\/O device. Most instruction sets also provide Conditional Instructions. A conditional \u2022 Branch Group - conditional and unconditional instruction specifies an operation to be performed only if jump instructions, subroutine call instructions and certain conditions have been met; for example, jump to a return instructions particular instruction if the result of the last operation was zero. Conditional instructions provide a program with a \u2022 Stack, I\/O and Machine Control Group - includes decision-making capability. I\/O instructions, as well as instructions for main- taining the stack and internal control flags. By logically organiZing a sequence of instructions into a coherent program, the programmer can \\\"tell\\\" the com- Instruction and Data Formats: puter to perform a very specific and useful function. Memory for the 8080 is organized into 8-bit- quanti\u00b7 The computer, however, can only execute programs ties, called Bytes. Each byte has a unique 16-bit binary whose instructions are in a binary coded form (i.e .\u2022 a series address corresponding to its sequential position in memory. of 1's and O's), that is called Machine Code. Because it would be extremely cumbersome to program in machine 2-51 code. programming languages have been developed. There Apr; i, i 9i7 3800b","The 8080 can directly address up to 65,536 bytes of mem- address where the data is located (the ory, which may consist of both read-only memory (ROM) high-order bits of the address are in the elements and random-access memory (RAM) elements (read\/ first register of the pair, the low-order write memory). bits in the second). Data in the 8080 is stored in the form of 8-bit binary \u2022 Immediate - The instruction contains the data it\u00b7 integers: self. This is either an 8-bit quantity or a 16-bit quantity (least significant byte first, DATA WORD most significant byte second). MSB LSB Unless directed by an interrupt or branch instruction, the execution of instructions proceeds through consecu\u00b7 When a register or data word contains a binary num\u00b7 tively increasing memory locations. A branch instruction ber, it is necessary' to establish the order in which the bits can specify the address of the next instruction to be exe- of the number are written. In the Intel 8080, BIT 0 is re- cuted in one of two ways: ferred to as the Least Significant Bit (LSBI. and BIT 7 (of an 8 bit number) is referred to as the Most Significant Bit \u2022 Direct - The branch instruction contains the ad- (MSB). dress of the next instruction to be exe- cuted. (Except for the 'RST' instruction, The 8080 program instructions may be one, two or three bytes in length. Multiple byte instructions must be byte 2 contains the low-order address and stored in successive memory locations; the address of the byte 3 the high-order address.) first byte is always used as the address of the instructions. The exact instruction format will depend on the particular \u2022 Register indirect - The branch instruction indi- operation to be executed. cates a register-pair which contains the address of the next instruction to be exe- Single Byte Instructions cuted. (The high-order bits of the address are in the first register of the pair. the I I07 I I j I Do Op Code low-order bits in the second.) Two-Byte Instructions The RST instruction is a special one-byte call instruc- tion (usually used during interrupt sequences). RST in- IByte One 07 j Ii Do Op Code cludes a three-bit field; program control is transferred to the instruction whose address is eight times the contents of this three-bit field. :==;:::::;:::::::;::::=;::::::;:::=;::::::::::;::= I IByte Two 07 I 1.... I Do A?adtdareosrs Condition Flags: -::;J. Three-Byte Instructions There are five condition flags associated with the exe- cution of instructions on the 8080. They are Zero, Sign, IByte One 0 7 I II Do Op Code Parity. Carry, and Auxil iary Carry, and are each represented ~::::;=:;:=:;::::::::;=::;:::::;:~ by a l-bit register in the CPU. A flag is \\\"set\\\" by forcing the I I}Byte Two 071 bit to 1; \\\"reset\\\" by forcing the bit to O. I Do Data IByte Three 07 I I or Unless indicated otherwise, when an instruction af- fects a flag, it affects it in the following manner: I Do Address Zero: If the result of an instruction has the value 0, this flag is set; otherwise it is Addressing Modes: reset. Often the data that is to be operated on is stored in Sign: If the most significant bit of the result of memory. When multi-byte numeric data is used, the data, the operation has the value 1, this flag is like instructions, is stored in successive memory locations, set; otherwise it is reset. with the least significant byte first, followed by increasingly significant bytes. The 8080 has four different modes for Parity: If the modulo 2 sum of the bits of the re- addressing data stored in memory or in registers: sult of the operation is 0, (i.e., if the result has even parity), this flag is set; \u2022 Direct - Bytes 2 and 3 of the instruction contain otherwise it is reset (i.e., if the result has the exact memory address of the data odd parity). item (the low-order bits of the address are in byte 2, the high-order bits in byte 3). Carry: If the instruction resulted in a carry (from addition), or a borrow (from sub- \u2022 Register - The instruction specifies the register or traction or a comparison) out of the high- register-pair in which the data is located. order bit, this flag is set; otherwise it is reset. \u2022 Register Indirect - The instruction specifies a reg- 2-52 ister-pair which contains the memory Apr; 1. 1977 a8COb","Auxiliary Carry: If the instruction caused a carry out rh The first (high-order) register of a designated of bit 3 and into bit 4 of the resulting register pair. value, the auxiliary carry is set; otherwise it is reset. This flag is affected by single rl The second (low-order) register of a desig\u00b7 precision additions, subtractions, incre\u00b7 nated register pair. ments, decrements, comparisons, and log- ical operations, but is principally used PC 16\u00b7bit program counter register (PCH and with additions and increments preceding pel are used to refer to the high-order and a DAA (Decimal Adjust Accumulator) low-order 8 bits respectively). instruction. SP 16-bit stack pointer register (SPH and SPl are used to refer to the high\u00b7order and low\u00b7 order 8 bits respectively). Symbols and Abbreviations: rm Bit m of the register r (bits are number 7 through 0 from left to right). The following symbols and abbreviations are used in the subsequent description of the 8080 instructions: Z,S,P,CY,AC The condition flags: Zero, SYMBOLS MEANING Sign, Parity, accumulator Register A Carry, and Auxiliary Carry, respectively. addr 16-bit address quantity data 8-bit data quantity data 16 16\u00b7bit data quantity ( ) The contents of the memory location or reg\u00b7 byte 2 The second byte of the instruction - isters enclosed in the parentheses. \\\"'s transferred to\\\" byte 3 The third byte of the instruction ;\\\\ Logical AND port 8\u00b7bit address of an I\/O device V Exclusive 0 R r,rl,r2 One of the registers A,B,C,D,E,H,L V Inclusive OR DDD,SSS The bit pattern designating one of the regis- + Addition ters A,B,C,D,E,H,L (DOO=destination, SSS= source): Two's complement subtraction DOD or SSS REGISTER NAME -* Multiplication \\\"Is exchanged with\\\" 111 A 000 B The one's complement (e.g., (A)) 001 C 010 D n The restart number a through 7 all E 100 H NNN The binary representation 000 through 111 101 L for restart number a through 7 respectively. rp One of the register pairs: Description Format: B represents the B,C pair with B as the high\u00b7 The following pages provide a detailed description of order register and C as the low-order register; the instruction set of the 8080. Each instruction is de- scribed in the following manner: D represents the D,E pair with D as the high- order register and E as the low-order register; 1. The MAC 80 assembler format, consisting of the instruction mnemonic and operand fields, is H represents the H,L pair with H as the high- printed in BOLDFACE on the left side of the first order register and L as the low\u00b7order register; line. SP represents the 16-bit stack pointer 2. The name of the instruction is enclosed in paren- register. thesis on the right side of the first line. RP The, bit pattern designating one of the regis- 3. The next line(s) contain a symbolic description of the operation of the instruction. ter pairs B,D,H,SP: ' 4. This is followed by a narative description of the RP REGISTER PAIR operation of the instruction. 00 B-C 5. The following !ine(s) contain the binary fields and 01 D-E patterns that comprise the machine instruction. 10 H-L 11 SP 2-53 April, 197i 88COb","6. The last four lines contain incidental information MVI r. data (Move Immediate) about the execution of the instruction. The num- ber of machine cycles and states required to exe\u00b7 (r) - (byte 2) cute the instruction are listed first. If the instruc\u00b7 tion has two possible execution times. as in a The content of byte 2 of the instruction is moved to Conditional Jump. both times will be listed. sep\u00b7 arated by a slash. Next. any significant data ad\u00b7 register r. dressing modes (see Page 4\u00b72) are listed. The last line lists any of the five Flags that are affected by the execution of the instruction. Data Transfer Group: This group of instructions transfers data to and from registers and memory. Condition flags are not affected by any instruction in this group. Mav r1. r2 (Move Register) (r1) - (r2) MVI M. data (Move to memory immediate) The content of register r2 is moved to register r1. ((H) (l)) - (byte 2) The content of byte 2 of the instruction is moved to I0 I 0 i 0 0 5 I 5 I 5 the memory location whose address is in registers H and L. Cycles: 1 oj 0 oo States: 5 Addressing: register data Flags: none Mav r, M (Move from memory) Cycles: 3 5tates: 10 (r) _ ((H) (l)) Addressing: immed.\/reg. indirect Flags: none The content of the memory location. whose address is in registers Hand l. is moved to register r. 0I 0 0 0 0 Cycles: 2 LXI rp, data 16 (Load register pair immediate) States: 7 Addressing: reg. indirect (rh) _ (byte 3). Flags: none (rt) - (byte 2) Byte 3 of the instruction is moved into the high-order register (rh) of the register pair rp. Byte 2 of the in\u00b7 struction is moved into the low\u00b7order register (rl) of Mav M. r (Move to memory) the register pair rp. ((H)(l))- (r) Io I o \/ R I P o I o I o I 1 The content of register r is moved to the memory 10' cation whose address is in registers Hand L. low-order data _0_1_ _1_' 0_1_5_1_5_1_5_ high-order data Cycles: . 2 Cycles: 3 States: 7 States: 10 Addressing: reg. indirect Addressing: immediate Flags: none Flags: none 2-54 April. 1977 880Gb","LOA addr (Load Accumulator direct) SHLO addr (Store Hand L direct) (A) - ((byte 3) (byte 2)) ((byte 3)(byte 2)) - (L) The content of the memory location, whose address ((byte 3) (byte 2) + 1) - (H) is specified in byte 2 and byte 3 of the instruction, is The content of register L is moved to the memory 10- moved to register A. eation whose address is specified in byte 2 and byte 3. The content of register H is moved to the succeed- ing memory location. low-order addr o I o I 1 I 0 10 I o I 1 I 0 high-order addr low-order addr Cycles: 4 high-order addr States: 13 Addressing: direct Cycles: 5 Flags: none States: 16 Addressing: direct Flags: none LOAX rp (Load accumulator indirect) (A) - ((rp)) STA addr (Store Accumulator direct) The content of the memory location, whose address ((byte 3)(byte 2)) _ (A) is in the register pair rp. is moved to register A_ Note: The content of the accumulator is moved to the only register pairs rp:=B (registers B and C) or rp=O memory 19cation whose address is specified in byte (registers D and E) may be specified. 2 and byte 3 of the instruction. ooR p 0 I 0 I 1 I1 I0 i 0 I 1 r0 Cycles: States: low-order addr Addressing: 2 Flags: 7 high-order addr reg_ indirect none Cycles: 4 STAX rp (Store accumulator indirect) States: 13 Addressing: ((rp)) - (A) Flags: dire~t The content of register A is moved to the memory lo- none cation whose address is in the register pair rp. Note: only register pairs rp=B (registers B and C) or rp=O (registers D and E) may be specified. Io I 0 R p o I 0 I0 LHLO addr (Load Hand L direct) Cycles: 2 States: 7 (Ll - ((byte 3)(byte 2)) Addressing: reg. indirect (H) - Flags: none ((byte 3)(byte 2) + 1) The content of the memory location, whose address is specified in byte 2 and byte 3 of the instruction, is moved to register L. The content of the memory loca- XCHG (Exchange Hand L with D and E) tion at the succeeding address is moved to register H. (H)-(D) o I 0 I 1 I0 I1 I0 I 1 I0 (Ll-(E) The contents of registers Hand L are exchanged with low-order addr the contents of registers D and E. high-order addr I I0 Cycles: 5 Cycles: 1 States: 16 States: 4 Addressing: direct Addressing: register Flags: none Flags: none April, 1977 2-55 8S00b","Arithmetic Group: ADe r (Add Register with carry) This group of instructions performs arithmetic oper- (A) _ (A) + (r) + (CY) ations on data in registers and memory. The content of register r and the content of the carry Unless indicated otherwise, all instructions in this group affect the Zero, Sign, Parity, Carry, and Auxiliary bit are added to the content of the accumulator. The Carry flags according to the standard rules, result is placed in the accumulator. All 'Subtraction operations are performed via two's complement arithmetic and set the carry' flag to one to in- 1I aI a a IS S 5 dicate a borrow and clear it to indicate no borrow. Cycles: 1 States: 4 Addressing: register Flags: Z,S,P,CY,AC ADO r (Add Register) ADe M (Add memory with carry) (A) - (A) + (r) (A) - (A) + ((H) (L)) + (CY) The content of register r is added to the content of the The content of the memory location whose address is accumulator. The result is placed in the accumulator. contained in the Hand L registers and the content of I1 I 0 I 0 0 0 S I 5 I S the CY flag are added to the accumulator. The result is placed in the accumulator. Cycles: 1 o States: 4 Addressing: register Cycles: 2 Flags: Z,S,P,CY,AC States: 7 Addressing: reg. indirect Flags: Z.S.p,CY,AC ADD M (Add memory) (A) - (A) + ((H) (L)) ACt data (Add immediate with carry) The content of the memory location whose address (A) - (A) + (byte 2) + (CY) is contained in the Hand L registers is added to the The content of the second byte of the instruction and content of the accumulator. The result is placed in the content of the CY flag are added to the contents the accumulator. of the accumulator. The result is placed in the 1I 0 I 0 a a accumulator. a oa a Cycles: 2 data States: 7 Addressing: reg. indirect Cycles: 2 Flags: Z,S,? ,CY,AC States: 7 Addressing: immediate Flags: Z.S,p ,CY,AC ADt data (Add immediate) (A) - (A) + (byte 2) SUB r (5ubtract Register) The content of the second byte of the instruction is (A) _ (A) - (r) added to the content of the accumulator. The result The content of register r is subtracted from the con- tent of the accumulator. The result is placed in the is placed in the accumulator. 1 I o I, a I a a accumulator. data oI0 o I_S__5__S_ Cycles: 2 Cycles: 1 States: 7 States: Addressing: immediate Addressing: 4 Flags: Z,S,P,CY,AC Flags: register Z,5,P,CY,AC 2-56 April, 1977 3800b","SUB M (Subtract memory) S81 data (Subtract immediate with borrow) (A) - (A) - (H) (L)) (A) - (A) - (byte 2) - (CY) The content of the memory location whose address is The contents of the second byte of the instruction contained in the Hand L registers is subtracted from and the contents of the CY flag are both subtracted the content of the accumulator. The result is placed from the accumulator. The result is placed in the in the accumulator. accumulator. Ia Ia I1 a a 1I o 1 o Cycles: 2 data States: 7 Addressing: reg. indirect Cycles: 2 Flags: Z.S.p.CY,AC States: 7 Addressing: immediate Flags: Z,S,P,CY,AC SUI data (Subtract immediate) (A) - (A) - (byte 2) The content of the second byte of the instruction is INR r (Increment Register) subtracted from the content of the accumulator. The (r) - (r) + 1 result is placed in the accumulator. The content of register r is incremented by one. Note: All condition flags except CY are affected. data I0 I 0 D I D D 1 I 0 I 0 Cycles: 2 Cycles: 1 States: 7 States: 5 Addressing: immediate Addressing: register Flags: Z,S.P,CY,AC Flags: Z,S,P,AC SBB r (Subtract Register with borrow) INR M (I ncrement memory) (A) - (A) - (r) - (CY) (H) (L)) - (H) (L)) + 1 The content of register r and the content of the CY The content of the memory location whose address flag are both subtracted from the accumulator. The is contained in the Hand lregisters is incremented result is placed in the accumulator. by one. Note,: All condition flags except CY are 1I 0 I 0 IS I S I s affected. o I0 o o I0 Cycles: 1 Cycles: 3 States: 4 States: Addressing: register Addressing: 10 Flags: Z,S,P,CY,AC Flags: reg. indirect Z,S,PAC SBB M (Subtract memory with borrow) (A) - (A) - ((H) (L)) - (CY) The content of the memory location whose address is DCR r (Decrement Register) contained in the Hand L registers and the content of (r) _ (r)-1 the CY flag are both subtracted from the accumula- The content of register r is decremented by one. tor. The result is placed in the accumulator. Note: All condition flags except CY are affected. 1I 0 I 0 II 1I 0 0 I 0 \\\\' D I D D I 1 I, 0 I 1 1 Cycles: 2 Cycles: 1 States: 7 States: 5 Addressing: reg. indirect Addressing: register Flags: Z,S,P,CY,AC Flags: Z,S,PAC Apr; 1, 1977 2-57 3aOOb","OCR M (Decrement memory) DAA (Decimal Adjust Accumulator) ((H) (L)) - ((H) (L)) - , The eight-bit number in the accumulator is adjusted The content of the memory location whose address is to form two four-bit Binary-Coded\u00b7Decimal digits by contained in the Hand L registers is decremented by the following process: one. Note: All condition flags except CY are affected. 1. If the_ value of the least significant 4 bfts of the accumulator is greater than 9 or if the AC flag oI o o I1 I0 I1 is set, 6 is added to the accumulator. Cycles: 3 2. If the value of the most significant 4 bits of the States: 10 accumulator is now greater than 9, or if the CY Addressing: reg. indirect flag is set, 6 is added to the most significant 4 Flags: Z,S,P,AC bits of the accumulator. NOTE: All flags are affected. INX rp (Increment register pair) 0I0 I0 0 (rh) (rl) - (rh) (rf) + 1 Cycles: 1 States: 4 The content of the register pair rp is incremented by Flags: Z,S,P,CY,AC one. Note: No condition flags are affected. 0 I 0 R P 0 I0 I I Cycles: 1 Logical Group: States: 5 Addressing: register This group of instructions performs logical (Boolean) none operations on data in registers and memory and on condi- Flags: tion flags. Unless indicated otherwise, all instructions in this group affect the Zero, Sign, Parity, Auxiliary Carry, and Carry flags according to the standard rules. DCX rp (Decrement register pair) (rh) (rl) - (rh) (rf) - 1 ANA r (AND Register) The content of the register pair rp is decremented by (A) - (A) 1\\\\ (r) one. Note: No condition flags are affected. The content of register r is logically anded with the oI0 I0 I content of the accumulator. The result is placed in R , the accumulator. The CY flag is cleared. Cycles: 5 ____'_0 0_ _0_' SiS S States: register Addressing: none Cycles: 1 Flags: States: 4 Addressing: register Flags: Z,S,P,CY,AC DAD rp (Add register pair to Hand L) ANA M (AND memory) (A) - (H) (L) - (H) (L) + (rh) (rl) (A) 1\\\\ ((H) (L)) The content of the register pair rp is added to the The contents of the memory location whose address content of the register pair Hand L. The result is is contained in the Hand L registers is logically anded placed in the register pair Hand L. Note: Only the with the content of the accumulator. The result is CY flag is affected. It is set if there is a carry out of placed in the accumulator. The CY flag is cleared. the double precision add; otherwise it is reset. '_R_ 1--,o I 01 I 0 0 0 I1 I1 I0 _ p o_'_0_1_ --l Cycles: 3 Cycles: 2 States: States: Addressing: 10 Addressing: 7 Flags: register Flags: reg. indirect CY Z,S,P,CY,AC 2-58 Apr; 1. 1977 S800b","ANI data (AND immediate) ORA r (OR Register) (A) - (A) \/\\\\ (byte 2) (A) - (A) V (r) The content of the second byte of the instruction is The content of register r is inciusive-OR'd with the logically anded with the contents of the accumulator. content of the accumulator. The result is placed in The result is placed in the accumulator. The CY and the accumulator. The CY and AC flags are cleared. AC flags are cleared. _1,0_1_'_1_'_1_0 I0 I 1 0 S I S I S _ _ _ _ _ _ _0 data . Cycles: 1 States: 4 Cycles: 2 Addressing: register States: 7 Flags: Z,S,P,CY,AC Addressing: immediate Flags: Z,S,? ,CY ,AC ORA M (OR memory) (A) - (A) V ((H) (Ll) XRA r (Exclusive OR Register) The content of the memory location whose address is contained in the Hand L registers is inctusive-QR'd (A) - (A) 'V (r) with the content of the accumulator. The result is The content of register r is exclusive-or'd with the placed in the accumulator. The CY and AC flags are content of the accumulator. The result is placed in cleared. the accumulator. The CY and AC flags are cleared. 0 i0 S I S I ooo , ICycles.: S States: 4 Cycles: 2 States: 7 Addressing: register Addressing: reg. indirect Flags: Z,S,P ,CY,AC Flags: Z,S,?,CY,AC XRA M (Exclusive OR Memory) ORI data (OR Immediate) (A) - (A) V (byte 2) (A) - (Al'V ((H) (L)) The content of the second byte of the instruction is The content of the memory location whose address inclusive-OR'd with the content of the accumulator. is contained in the Hand L registers is exciusive\u00b7OR'd The result is placed in the accumulator, The CY and with the content of the accumulator. The result is AC flags are cleared, placed in the accumulator. The CY and AC flags are cleared. 1I 0 0 oo I0 data Cycles: 2 Cycles: 2 States: States: Addressing: 7 Addressing: 7 Flags: reg. indirect Flags: immediate Z,S,? ,CY ,AC Z,S,P ,CY,AC XRI data (Exclusive OR immediate) CMP r (Compare Register) (A) - (A) 'V (byte 2) (A) (r) The content of the second byte' of the instruction is The content of register r is subtracted from the ac\u00b7 exclusive-QR'd with the content of the accumulator. cumulator. The accumulator remains unchanged. The The result is placed in the accumulator. The CY and condition flags are set as a result of the subtraction. AC flags are cleared. o The Z flag is set to 1 if (A) = (r). The CY flag is set to ,o 1 if (A) < (r). data .\\\\ 0 . 1 , ICycles: SIS S Cycles: 2 States: 4 States: 7 Addressing: register Addressing: immediate Z,S,P,CY,AC Flags: Z,S,P,CY,AC Flags: April, 1977 2-59 8800b","CMP M (Compare memory) RRC (Rotate right) (AI ((HI (L)) (An) - (An-,); (A7) - (AO) (CY) - (AO) The content of the memory location whose address The content of the accumulator is rotated right one is contained in the Hand L registers is subtracted from the accumulator. The accumulator remains un- position. The high order bit and the CY flag are both changed. The condition flags are set as a result of the set to the value shifted out of the low order bit posi- subtraction. The Z flag is set to 1 if (AI = ((H) (L)). tion. Only the CY flag is affected. The CY flag is set to 1 if (AI < ((HI (L)). 0I I0 j I1 I1 I 1 0 0 a a Cycles: 1 States: 4 Cycles: 2 Flags: CY States: Addressing: ] RAL (Rotate left through carry) Flags: reg. indirect Z,S,P,CY,AC (An+1) - (An) ; (CY) - (A]) (AO) - (CY) The content of the accumulator is rotated left one position through the CY fiag. The low order bit is set equal to the CY flag and the CY flag is set to the value shifted out of the high order bit. Only the CY CPI data (Compare immediate) flag is affected. (AI (byte 2) aI 0 Ia I1 o I1 I1 I, The content of the second byte of the instruction is subtracted from the accumulator. The condition flags Cycles: 1 States: 4 are set by the result of the subtraction. The Z flag is Flags: CY set to 1 if (AI = (byte 2). The CY flag is set to 1 if (A) < (byte 2). 1I , I a RAR (Rotate right through carry) (An) - (A n+1); (CY) - (AO) (CY) data (A]) - The content of the accumulator is rotated right one Cycles: 2 position through the CY flag. The high order bit is set States: ] Addressing: immediate to the CY flag and the CY flag is set to the value Flags: Z,S,P,CY,AC shifted out of the low order bit. Only the CY flag is affected. aI a Ia I1 I1 I1 I1 Cycles: 1 States: 4 Flags: CY RLC (Rotate left) CMA (Complement accumulator) (A n+1) - (An) ; (A0) - (A]) (CY) - (A7) (A)-(A) The content of the accumulator is rotated left one position. The low order bit and the CY flag are both The contents of the accumulator are complemented set.to the value shifted out of the high order bit posi- tion. Only the CY flag is affected. (zero bits become 1, one bits become 0). No flags are a I a Ia Ia o I 1 I 1 I1 affected. aI oI1 Ia I1 I1 I1 Cycles: 1 Cycles: 1 States: 4 States: 4 Flags: CY Flags: none 2-60 Aoril, 1977 B800b","CMC (Complement carry) dress is specified in byte 3 and byte 2 of the current instruction. (CY) - (CY) The CY flag is complemented. No other flags are 1 I 1 f 0 I 0 I0 I0 I 1 I 1 affected. low-order addr oI 0 high-order addr Cycles: 1 Cycles: 3 States: States: 10 Flags: 4 Addressing: immediate Flags: none CY STC (Set carry) Jcondition addr (Conditional jump) (CY) - 1 The CY flag is set to 1. No other flags are affected. If (CCC), oI a o (PCl - (byte 3) (byte 2) If the specified condition is true, control is trans\u00b7 C,\/cles: 1 ferred to the instruction whose address is specified in States: 4 Flags: CY byte 3 and byte 2 of the current instruction; other\u00b7 wise, control continues sequentially. I I1 I 1 C I C I C a I 1 I a low-order addr high-order addr Branch Group: Cycles: 3 States: 10 Addressing: immediate Flags: none This group of instructions alter normal sequential CALL addr (Call) program flow. ((SP) - 1) - (PCH) Condition flags are not affected by any instruction in this group. ((SP) - 2) - (PCl) The two types of branch instructions are uncondi- (SP) - (SP) - 2 tional and conditional. Unconditional transfers simply per- form the specified operation on register PC (the program (PC) - (byte 3) (byte 2) counter). Conditional transfers examine the status of one of the four processor flags to determine if the specified branch The high-order eight bits of the next instruction ad- is to be executed. The conditions that may be specified are as follows: dress are moved to the memory location whose address is one less than the content of register SP. The low-order eight bits of the next instruction ad\u00b7 dress are moved to the memory location whose CONDITION cee address is two less than the content of register SP. NZ - not zero (Z = 0) 000 The content of register SP is decremented by 2. Can\u00b7 Z - zero (Z = 1) 001 010 trol is transferred to the instruction whose address is NC - no carry (CY = 0) 011 C - carry (CY = 1) 100 specified in byte 3 and byte 2 of the current PO - parity odd (P = 0) 101 110 instructi on. PE - parity even (P = 1) 111 P - plus (S = 0) 1I 1I 0 I a I 1 I1 Ia I 1 M -minus(S=l) low\u00b7order addr high-order addr JMP addr (Jump) Cycles: 5 States: 17 (PC) - (byte 3) (byte 2) Addressing: immediate\/reg. indirect Control is transferred to the instruction whose ad- Flags: none Aori1, 19\/i 2-61 8800b","Ccondition addr (Condition call) RST n (Restart) If (CCC), ((SP) -1) - (PCH) ((SP) -1) - (PCH) ((SP) - 2) - (PCL) ((SP) - 2) - (PCL) (SP) - (SP) - 2 (SP) - (SP) - 2 (PC) - 8* (NNN) (PC) - (byte 3) (byte 2) The high-order eight bits of the next instruction ad- If the specified condition is true, the actions specified dress are moved to the memory location whose in the CALL instruction (see above) are performed; address is one less than the content of register SP. otherwise, control continues sequentially. The low-order eight bits of the next instruction ad- I I1 I 1 1I 0 I 0 dress are moved to the memory location whose CI CI C address is two less than the content of register SP. low-order addr The content of register SP is decremented by two. Control is transferred to the instruction whose ad- high-order addr dress is eight times the content of NNN. Cycles: 3\/5 __1_1 _1_'_N 11 _ States: 11\/17 Addressing: immediate\/reg. indirect N __ N - - ' - _ 1 _ Flags: none Cycles: 3 States: 11 Addressing: reg. indirect Flags: none RET (Return) (PCL) - ((SP)); 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (PCH) - ((SP) + 1); (SP) - (SP) + 2; liEG10J oioliEJololN~ The content of the memory location whose address Program Counter After Restart is specified in register SP is moved to the low-order eight bits of register PC. The content of the memory location whose address is one more than the content of register SP is moved to the high-order eight bits of register PC. The content of register SP is incremented by 2. oI0 oI0 I PCHL (Jump Hand L indirect - move Hand L to PC) Cycles: 3 (PCH) - (H) States: 10 Addressing: reg. indirect (PCL) - (Ll Flags: none The content of register H is moved to the high-order eight bits of register PC. The content of register L is moved to the low-order eight bits of register PC. 1I 1I aI 0 I 0 Rcondition (Conditional return) If (CCC), Cycles: 1 States: (PCL) - ((SP)) Addressing: 5 Flags: register (PCH) - ((SP) + 1) none (SP) - (SP) + 2 If the specified condition is true, the actions specified in the RET instruction (see above) are performed; otherwise, control continues sequentially. 1I C Cycles: 1\/3 States: 5\/11 Addressing: reg. indirect Flags: none 2-62 April, 1977 aeOOb","Stack, 1\/0, and Machine Control Group: FLAG WORD This group of instructions performs I\/O, manipulates '-' the Stack, and alters internal control flags. Unless otherwise specified, condition flags are not affected by any instructions in this group. PUSH rp (Push) POP rp (Pop) ((SP) - 1) - (rh) (rt) - ((SP)) ((SP) - 2) - (~I) (rh) - ((SP) -+- 1) (SP) - (SP) -+- 2 (SP) - (SP) - 2 The content of the memory location, whose address is specified by the content of register SP, is moved to The content of the high-order register of register pair the low-order register of register pair rp. The content of the memory location, whose address is one more rp is moved to the memory location whose address is than the content of register SP, is moved to the high- order register of register pair rp. The content of reg- one less than the content of register SP. The content ister SP is incremented by 2. Note: Register pair rp = SP may not be specified. of the low-order register of register pair rp is moved to the memory location whose address is two less than the content of register SP. The content of reg- ister S? is decremented by 2. Note: Register pair rp = SP may not be specified. I I1 I 1 R P 0 0 I_R__I 1P_ _O_ _O_ _O _ Cycles: 3 Cycles: 3 States: 11 States: Addressing: reg. indirect Addressing: 10 Flags: none Flags: reg. indirect none POP PSW (Pop processor status word) PUSH PSW (Push processor status word) (CY) - ((SP))O (P) - ((SP))2 ((SP) - 1) - (Al (AC) - ((SP))4 (Z) - ((SP))6 ((SP) - 2)0 - (CY) ,((SP) - 2)1 - 1 (S) - ((SP))7 (A) - ((SP) -+- 1) ((SP) - 2)2 - (P), ((SP) - 2)3 - 0 (SP) - eSP) -+- 2 ((SP) - 2)4 - (AC) ,((SP) - 2)5 - 0 The content of the memory location whose address ((SP) - 2)6 - (Z), ((SP) - 2)7 - (S) is specified by the content of register SP is used to restore the condition flags. The content of the mem- (SP) - (SP) - 2 ory location whose address is one more than the content of register SP is moved to register A. The The content of register A is moved to the memory content of register SP is incremented by 2. location whose address is one less than register SP. The contents of the condition flags are assembled into a processor status word and the word is moved to the memory location whose address is two less than the content of register SP. The content of reg- ister SP is decremented by two. I1 I1 o 1I o 0 Cycles: 3 States: Cycles: 3 Addressing: 10 States: 11 reg. indirect reg. indirect Flags: Z,S,? ,CY ,AC Addressing~ none Flags: April, 1977 2-63 8aCOb","XTHL (Exchange stack top with Hand L) EI (Enable interrupts) The interrupt system is enabled following the execu- (L) -liSP)) tion of the next instruction. (H) - ((SP) + 1) 1I o The content of the L register is exchanged with the content of the memory location whose address is specified by the content of register SP. The content of the H register is exchanged with the content of the Cycles: 1 States: memory location whose address is one more than the Flags: 4 none content of register SP. I0 o o Cycles: 5 01 (Disable interrupts) States: 18 The interrupt system is disabled immediately fol- Addressing: reg. indirect lowing the execution of the 01 instruction. Flags: none oI0 I 1 SPHL (Move HL to SP) Cycles: 1 States: 4 (S?) - (H) (Ll Flags: none The contents of registers Hand L (16 bits) are moved to register SP. 1I 1I oo HLT (Halt) The processor is stopped. The registers and flags are Cycles: 1 unaffected. States: 5 Addressing: register 0I 1I 0 I 1 I 1 I0 Flags: none IN port (I nput) Cycles: 1 States: 7 (Al - (data) Flags: none The data placed on the eight bit bi-directional data bus by the specified port is moved to register A. 1I o I 1 I0 I1 NOP (No op) No operation is performed. The registers and flags port are unaffected. Cycles: 3 0I 0I 0 0 0 0 I0 0 States: 10 Addressing: direct Cycles: 1 Flags: none States: Flags: 4 none OUT port (Output) (data) - (A) The content of register A is placed on the eight bit b;-<...irectional data bus for transmission to the spec- ified port. o .\\\\ 0 o port Cycles: 3 States: 10 Addressing: direct Flags: none 2-64 April, 1977 8800b","_. INSTRUCTION SET Summary of Processor Instructions Imlrueti1lft Cod.PI Cloek(2i Instruction Cod.lll Clock (21 Mnlllluic OIKCri,rion 0-, ~ ~ 14 03 ~ 0, 00 Cyell, Mn.monic Ollcription 0-, ~ ~ O. 03 02 0, 00 Cyells MOV\\\".'2 May. ,\\\"\\\"til' to (..ster a1 0 0 0S SS 5 RZ Raturn on zero a a10 0a 5\/11 MOV M,r 0 1 1 1 aS S S 7 RNZ Return an no zero a aa0 c0 5\/11 MOVr,M M,,\\\" 'IlJI'ter t1l IfIImo,y ,a 1 0 0 0 1 1 a 7 RP Rttur\\\" on POSitiVI 1 1 aa a0 5\/11 HlT a1 1 1 a1 a 7 RM Return on minus 1 I 1 aaa 5\/11 MVI, Mav. Iftlmorv to ,tglSttf 7 RPE 5\/11 MVIM 10 RPO R.turn on plntv ''''ft 5\/11 INR, HIH aa 0 0 0 1 1a 5 RST 11 OCR, 5 IN Rltu,n on panlY odd 10 INRM Move Immediate ''''Stir aa 1 1 a 1 1a 10 OUT Rlltan 1 a 1 0 aa 10 OCR M M..I ,mml,lIan m\\\"\\\"ory 10 lXI 8 Input 1 0 aa0 a 10 \\\"'DO r ,0 0 0 0 0 1 0 0 4 OUIPUI MC, Incnm,nt f\\\"tlter 4 lXI 0 load ,mmed,all \\\"!Cl'\\\"lf ,'0\\\"'1\\\"'1\\\"1 1 1 '0 SU8, 4 Pai, 8 &C 0 1 588 r Olcremenl'l9i lllf O\u00b7 0 0 0 0 01 4 LXIH Laid immediate register 10 InctlfRlnt mtmory Pai,O & E ANA r 00 10 1 00 7 LXISP Load Immediate flfJlstet a 100 1 10 XRA, 7 PUSH 8 11 OftA, OlCl1mlntlfllmory 00 1 10101 1 ~ai,H&l a 0 00 1 CMP, 4 PUSH 0 11 ADO M \\\"'dd 'l9\\\"ter 10 A 10 0 0 0S SS 4 load immediate stack pointer AOC M Add '\\\",\\\"er 10 A wtlh carry 4 PUSH ,; 11 SU8 M 10 0 a1S SS Push 'eglSI., Pa\\\" 8 & C on S88 M 10 PUSH PSW 11 ,,,,stltSubt'''1 r\\\"'Stl< from A 10 0 10S SS 10 stack ANA M 10 ~OPS ~ush 'eg\\\"Ie, Pa\\\" 0 & E on 10 XRA M Subt'acl f,om A 10 0 1 1S SS 10 ORA M 10 POP 0 stack 10 CMPM wnhborrnw 10 Push ,e,!,,,e, Pa\\\" H& L on AOI 10 POP H stack 10 ACI And 'IlJI'ter w'Ih A 01 S SS 10 Push A and Flags 01 S SS 10 POP PSW on stack 10 SUI Exclusive Or registlf Wlm A 01 S SS 17 58' S SS 11\/17 'TA PO. regISter POI' a & C off 13 0, '191StI' Wllh A a1 1 10 11\/17 LOA 13 .......... aa 1 10 11\/17 XCHG $tar.k 4 ANI Com.a\\\", raqlStlf wIlh A 11\/17 XRl 00 ,1 1 0 11\/17 XTHl ~oP ,eq'ste' pa\\\" 0 & E otf '8 Add mlmory 10 A 00 10 11\/17 SPHl stack 5 ORI 11\/17 PCHL Pop '''llSte' pa\\\" H 8. L off 5 CPt Add mlmory to A WI!I1 carry 0a 11\/17 DAO 8 Hack 10 RlC 10 OAO D Po. A and Flags :0 RRC Subtr\\\"1 memory f'om A 5\/11 OAD H off stack '0 RAl 5\/11 OAO SP Slcra A direct 10 RAR Subtract memorv from A STAX S Loaa A di,ecI 7 STAX 0 Exchenqe 0 8. E, H& L 7 JMP wllh borrow 00 LDAX 8 7 JC And mlmory ...Ih A 00 LDAX 0 AeglSter~ 7 JNC INX 8 5 JZ Exctuslvt Or memorv wIth At 1a INX 0 Excnanqe top 01 SlIck, H& L 5 JNZ INX H H8. L '0 stack pOinter 5 JP Or memory ....'th A I0 INX SP H& L 10 p,oqnm counte' 5 JM Q0 OCX B Add 8 & C to H & L 5 JPE ComQare memory with A OCX 0 Add 0 & E to H8. L 5 JPO Ja OCX H AddH&LroH&L 5 CAU Add immediate to A OCX SP Add SlIck po,n.e' to H & L 5 CC CMA Store A indirect 4 CNC Add Immediate to A Wit\\\" STC Sto(e A. lndirtct 1 CZ carry CMC 4 CNZ OAA Load A. indlrett 4 CP Subtract Immldiafl from A. SHlO Load A Indirect 16 eM LHLO 16 CPE Subtratf Immediart from A EI Increm'\\\"t 8 & C registers 0 CPO 01 InCrlment 0 & E(eglsten 0 4 RET 'Mth borrow NOP l\\\"erement 11 & L registers 0 4 AC Ii1cremtnt ~tack pOInter 4 RNC And lmmtdiao With A 0 Oec,ement 8 & C Exctuslye Or immediate w1th Decrement 0 & E a oecnmtnt H & 1. A 11 000 11 Or Immediatl with A Decrem.nt stack pOlnrtr 11 Complement A 1 I 0 a1 Compare Immediate WIth A Set carry AOlale A left Complement carrv 11 0 10 0 1 Oec,me' adjust A ROle.e A \\\"9ht Stora H 8. L direcl a0 ,0 I 0 a 1 Rotatl A lett throuqh carry Load H & L di,ecI 11 a Enabtllntlfrupts 1 10 0 Oisabjl interrupt J0 0 10 0 1 No-operation a0 1 10 a1 Rorall A \\\"9hl 'h,ouqh carry a0 c a0 0 10 Jump uncondltlona' 0 0 00 11 00 0 10a10 Jumo on carrv 0 1 10 10 ,0 0 0 0 1 0 1 0 Jump on no carrv 0 100 I 0 0a 0 1a 10 Jumo on zero 0 0 1a 10 0a a0 00 1 I Jump an no lero , ,0 0 0 0 1 a 00 0 100 1 00 10 Jump on POSltlv, 00 1 0 J 0 I 1 Jump on mlnu! 1 1 10 I 0 0 0 1 1 a0 Jumg on plnty enn 1 a10 10 00 0 0 I 0 1 1 Jump on partly odd 1 0 00 10 00 a 1 10 Call uncondil'lQnl1 0 0 1101 00 1 0 10 1 CaU on carry 0 1 1100 00 1 1 10 1 CiU on no Cinv 0 1 0 1 a0 00 1 0 11 1 1 CaU on zero 0 0 11 00 0a 1 I 01 1 ,0 0 0 1 0 0 0a 1 1 I 1 Call on no ZlfO Calf on pasmYe 1 10 00 00 1 0 01 1 1 I 1 a0 00 0 CaU an minus 00 1 0 a0 0, Call on oatlt.., ,Yen 0 1100 1 1 0 10 CaU on pa,ity odd 1 a01 00 1 1 1 10 Return 0 10 0 1 1 1 a0 Return on carry 1 10 00 0 0 0 00 0 Return on no carrv 100 00 NOTES: 1, DDDcrSSS-OOOB-001 C-010D-011 E-l00H-101 L-110Memory-1', A. 2. Two possible cycle times, (5i\\\") indicate instruction cycles dependent on condition flags. April. 197i 2-65 88QQb","ill~vill~OO ffirn\u00ae\u00ae~ ~rn\u00a9lf~\u00ae~] ~~~ Voorn\u00aeoow \u00ae~ \u00aeUJrnrnillu~\u00ae~ -- 3-1\/(3-2 blank)","3-1. GENERAL This section contains information needed to understand the operation of the MITS Altair 8800b computer (8800b). It contains a basic description of the logic symbols used in the 8800b schematics and detailed theory of the 8800b Central Processing Unit, Interface and Front Panel circuits. 3-2. LOGIC CIRCUiTS The logic circuits used in the 880Gb drawings are presented as a tabular listing in Table 3-1. The table is constructed to present the functional name, symbolic representation, and a brief description of each logic circuit. Where applicable, a truth table is provided to aid in understanding circuit operation. Although Table 3-1 does not include every logic circuit used in the drawings, all unmentioned circuits (and their symbolic repre- sentations) are variations of the circuits presented with their .functional descriptions basically the sa.me. The active state of the inputs and outputs of the logic circuits is graphically displayed by small circles. A small circle, at an input to a logic circuit, indicates that the input is an active LOW; that is, a LOW signal will enable the input. A small circle, at the output of a logic circuit, indicates that the output is an active LOW; that is, the output is low in the actuated state. Conversely, the absence of a small circle indicates that the input or output is active HIGH. Acril. 1977 3-3 8S0Cb","Table 3-1. Symbol Definitions - NAME LOGIC DESCRIPTION NAND gate SYMBOL The NAND gate performs one of the NOR gate Y = AS \u2022\u2022\u2022 N fundamental logic functions. Y = A + B .\u2022\u2022 +N All of the inputs have to be enabled Inverter (HIGH) to produce the desired (LOW) Non-Inverting output. The output is HIGH if any Bus Driver of the inputs are LOW. Inverting The NOR gate performs one of the Bus Driver Ifundamental logic functions. Any of the inputs need to be enabled (HIGH) to produce the desired (LOW) output. The output is HIGH if all of the inputs are LOW. The inverter is a device whose output is the opposite state of the input. The non-inverting bus driver is a device whose output is the same state as the input. Data is enab1ed through the device by applying a (LOW) signal to the E input. The inverting bus driver is a device 1 whose output is the opposite state of the input. Data is enabled I through the driver by applying a (LOW) signal to the E input. 3-4 ;'ori 1. 19ii 2800b","Table 3-1. Symbol Definitions - Continued NAME LOGIC DESCRIPTION SYMBOL Edge triggered Appl~ing a LOW signal to the preset in- D type flip-flop 1p put (P) sets the flip-flop with output . -0 Q- Q HIGH and output QLOW. Applying a - Cl< Qf- LOW signal to the clear input (C) re- sets the flip-flop with Q LOW and Q C HIGH. This method of setting and re- setti ng the fl i p-fl op is; ndependent QUAD 0 flip-flop Truth Table of the clock (asynchronous). If a signal is applied to the 0 input, the I t Tn Tn+1 flip-flop Q output is directly affect- 1 ed on the positive edge of the clock DQQ (truth table). LLH ihe information on the 0 inputs is H Ht stored during the positive edge of the clock (CK). The clear (C) input, I,'i4 5 when LOW, resets all flip-flops in- dependent of the clock or 0 inputs. II The 4-bit binary ripple counter oper- \u00b00 01 \u00b02 0, .ation requires that the QA output be externally connected to input CPS. CK The input taunt pulses (negative edge) are applied to input CPA enabling a -C divide by 2, 4, 8, and 16 at the QA, '\\\" 0; Qn Q, Q, Q2 Q-z Q; Q~ QB, QC, and QD outputs. The reset (RO) input resets the counter regard- IIIIIIII less of the clock input (CPA) when both inouts are HIGH. 3 2 I 7 11 10 14 IS 3-5 4-Bit Binary Ripple Counter .~pri 1, 1977 saOOb","Table 3-1. Symbol Definitions - Continued LOGIC DESCRIPTION NAME SYMBOL l2-Bit Binary 10-ca The 12-bit counter is triggered on the Counter negative edge of the clock input (CP). MR Q Q Q Q Q Q Q Q Q Q Q Q 1!! !!!1t ttL I A HIGH on the master reset input (MR) J, clears all counter stages and forces all outputs (QO-Qll) LOW which is independent of the clock input. Bi-Directional 4 7 \u2022 12 2 5 11 14 Output data from a device is present on Device I~ 1~1'\/i\\\\ the 01 0-01 3 lines and is enabled when OrEN and CS are LOW. Lines 080-08 3 -u 1\/,11 II transfer the data to the receiving unit 15_--01'=-:101;.,.,0O~1l2013l:OQICltOO2illJ Input data to the device is present '\\\" OlEN on the OBO-OB 3 lines and is enabled when OlEN is HIGH and CS is LOW. l _ _{]~CS Input data is transferred to the de- OSo OS, OS2 OS, vice on the 000-003 lines. J1t ! 10 13 I 3 Clock Generator The XTAL 1 and 2 inputs allow for an external crystal connection which pro- 2 - rnm RESET - 1 duces a 01 and 02 master clock for the 8800b. Tne SYNC input from the 8080 3 - RDYIN READY _ 4 (CPU) and internal timing generate a 5 - SYNC STS'fB ~7 LOW status strobe (STSTB) signal. The reset in (RESIN) input generates a RE- 14- XTAL 2 02 _10 SET output to condition the 8080 (CPU). 15- XTAL 1 01 -11 A HIGH ready in (ROYIN) input gener- ates a READY output to enable the CPU. 3-6 April, i977 8300b","Table 3-l.Symbol Definitions - Continued NAME LOGIC DESCRIPTION Data Latch SYMBOL fifiirrr The data latch is used to store or I--C 010 - 01 7 transfer data On the 000-00 7 outputs OSI by affecting the data latch control 3-052 inputs. There are several different ways used to store data or transfer 2----!MD 000- 00 7 it to the data latch \u2022 1 1 _ - - - 1 STB .1I I I r I I I When data is presented to the 010-017 inputs and the device selection 2 4 I I 10 21 11 17 15 (052), mode MO, and strobe (STB) are HIGH, a LOW device selection 1 (051) allows the input data to be present on the 000-007 outputs. When data is presented to the 010-017 inputs and Mo and STB are HIGH, a HIGH 052 and LOW 051 allow the input data to be present on the 000-00 7 out- puts. When data i-s051preansdenMteOdatroe the 010-017 inputs and LOW, a HIGH 052 and STB allow the input data to be present on the 0\u00b00-007 outputs. When data is presented to the 010-017 inputs, and MO and DS2 are HIGH with OS1 LOW, the input data is directly transferred to the 000-00 7 outputs as ! long as these states are present. Apr; 1, 1977 3-7 8800b","Table 3-1. Symbol Definitions - Continued NAME LOGIC DESCRIPTION SYMBOL PROM (programmable When the chip select input (CS) is LOW, read only memory) the binary address at input AO through A7 is decoded to select one of 256 ad- 2 A1 dress locations. The data is present 1 AZ on the 001 through 008 outputs. J Ao 21 A3 20 A4 19 AS 18 ~ 17 A7 14 CS 4 S 6 7 8 9 10 11 3-3. INTEL 8080 MICROCOMPUTER SYSTEMS USER'S INFORMATION Pages 3-9 through 3-38 are excerpts from the Intel 8080 Micro- computer Systems User's Manual, reprinted by per~ission of Intel Corporation, Copyright, 1975. Included is information on the 8080A Microprocessor, the 8212 Input\/Output Port, the 8216 Bi-Directional Bus Driver, and the 8224 Clock Generator and Driver. It is recom- mended that a good understanding of these integrated circuit operations be developed before continuing this section. 3-8 April, 1977 3aOOb","inter Silicon Gate MOS 8080 A SINGLE CHIP a-BIT N-CHANNEL MICROPROCESSOR The 8080A is functionally and electrically compatible with the Inref\u00ae 8080. \u2022 TTl. Drive Capability \u2022 Sixteen Bit Stack Pointer and Stack \u2022 2 JJ.S Instruction Cycle Manipulation Instructions for Rapid Switching of the Program Environment \u2022 Powerful Problem Solving \u2022 Decimal,Binary and Double Instruction Set Precision Arithmetic \u2022 Six General Purpose Registers\u00b7 \u2022 Ability to Provide Priority Vectored and an Accumulator Interrupts \u2022 Sixteen Bit Program Counter for \u2022 512 Directly Addressed 110 Ports Directly Addressing up to 64K Bytes of Memory The Intellll 8080A is a complete 8\u00b7bit parallel central processing unit (CPU). It is fabricated on a single LSI chip using Intel's n-channel silicon gate MOS process. This offers the user a high performance solution to control and processing applications. The 80aOA contains six 8\u00b7bit general purpose working registers and an accumulator. The six general purpose registers may be addressed individually or in pairs providing both single and double precision operators. Arithmetic and logical instructions set or reset four testable flags. A fifth flag provides decimal arithmetic operation. The 80S0A has an external stack feature wherein any portion of memory may be used as a last in\/first out stack to store\/ retrieve the contents of the aa:umulator. flags, program counter and all of the six general purpose registers. The sixteen bit stack pointer controls the addressing of this external stack. This stack gives the 80aOA the ability to easily handle multiple level priority interrupts by rapidly storing and restoring processor status. It also provides almost unlimited subroutine nesting. This microprocessor has been designed to simplify systems design. Separate 16\u00b7line address and S-Iine bi-directional data busses are used to facilitate easy interface to memory and I\/O. Signals to control the interface to memory and I\/O are pro- vided directly by the 80S0A. Ultimate control of the address and data busses resides with the HOLD signal. It provides the ability to suspend processor operation and force the address and data busses into a high impedance state. This permits OR- tying these busses with other controlling devices for (DMA) direct memory access or multi-processor operation. 8080A CPU FUNCTlONAL 0, -Do BLOCK DIAGRAM Bl-OIRECTIONAI. DATA BUS U DATA BUS ~ BUFFe;\/LATCH (lam (Bam INTeRNAl. DATA BUS INTeRNAl. DATA BUS ~ j J TeMP. ~eG_,1 INSTRUCTION It I MULTIPLeXeR '8' I IACCUMULATO~ ReGISTeR ,\\\"I II' I r-FLAG 15'1- w 18' Z III FLIP\u00b7 FLOPS l .. B 18' JL L .. t TEMP ~eG_ TeMP ReG. I IACCUMULATO~ ...tJ REG. C t81 LATCH '8' ~eG. - - .... ,\\\"0 '8' ARITHMeTIC INST~UCTION ..; e LOGIC DeCODeR ~eG_ ~eG. ;=...UNIT AND 0: IALUI ... H 18' MACHINE .. ~eG_ L 18' I -RAeRGRIASTYER 18' CYCLE (3 ReG. eNCODING ... 11&1 0: STACK POINTeR \u2022t PROG~AM COUNTeR ('1) I DeCIMAL I ~ INCReMENreR\/oeCReMeNTe~ ADJUST ADORess LATCH ('61 -Rl-\u00b7suPl\\\"l..les _ I TIMING I ANO CONT~OL - '<: m I, DATA BUS INTeRRUPT HOLD ADDRESS BUFFeR i16. +5V WAIT tL _-5V W~ITe CONTROL CONTROL CONTROL CONTROL SYNC CLOCKS A,.-Ao -GNO t ! wL t sy~c ~tWft DBIN 11E INt H01t.D JLD ADOAESSBUS READV 12 ReseT April. 1977 3-9 8800b","SILICON GATE MOS 8080 A 8080A FUNCTIONAL PIN DEFINITION The following describes the function of all of the 8080A I\/O pins. -A10 1 40 - A\\\" Several of the descriptions refer to internal timing periods. 39 - A14 GNO 2 38 - A13 A1S-AO (ouqJut three-state) 37 - A12 ADDRESS BUS; the address bus provides the address to memory 04 3 36 (up to 64K 8-bit words) or denotes the I\/O device number for up Os 4 - A1S to 256 input and 256 output devices. Ao is the least significant 35 address bit. 06 5 34 - Ag - As 07-00 (input\/output three-state) 07 ~ 6 33 DATA BUS; the data bus provides bi-directional communication 32 -.\\\"'\\\" A7 between the CPU, memory, and I\/O devices for instructions and 03 7 31 data transfers. Also, during the first clock cycle of each machine 30 ...... As cycle, the 8080A outputs a status word on the data bus that de- O2 8 INTEt= 29 scribes the current machine cycle. Do is the least significant bit. 8080A 28 ,.. As 0, 0 - 9 27 SYNC (output) 26 ,.. A4 SYNCHRONIZING SIGNAL; the SYNC pin provides a signal to DO 10 25 indicate the beginning- of each mach ine cycle. -SV 11 24 -.... A3 23 DBIN (output) RESET 12 - +12V DATA BUS IN; the DBIN signal indicates to external circuits that 13 22 the data bus is in the input mode. This signal should be used to -HOLD 14 - A2 enable the gating of data onto the 8080A data bus from memory -INT 15 21 or I\/O. -~2 J\\\"\\\\ A 1 INTE 0 - 16 -..... Ao oBIN 0 _ 17 - WAIT -WR 18 \\\"'\\\" READY 19 SYNC \\\"1-\\\"\\\" +5V 20 ,.. HLOA Pin Configuration READY (input) will go to the high impedance state. The HLDA signal begins at: \u2022 T3 for READ memory or input. READY; the READY signal indicates to the 8080A that valid \u2022 The Clock Period following T3 for WR ITE memory or OUT- memory or input data is available on the 8080A data bus. This signal is used to synchronize t~e CPU with slower memory or I\/O PUT operation. devices. If after sending an address out the a080A does not re- ceive a READY input, the 8080A will enter a WAIT state for as In either case, the HLDA signal appears after the rismg edge of \u00a2'1 long as the READY line is low. READY can also be used to single and high impedance occurs after the rising edge of \u00a2J2. step the CPU. INTE (output) WAIT (output) INTERRUPT ENABLE; indicates the content of the internal inter- WAIT; the WAIT signal acknowledges that the CPU is in a WAIT rupt enable flip\/flop. This flip\/flop may be set or reset by the En- state. able and Disable Interrupt instructions and inhibits interrupts from being accepted by the CPU when it is reset. It is auto- WR (output) matically reset (disabling further interrupts) \u00b7at time T 1 of the in- WRITE; the WR signal is used for memory WRITE or I\/O output struction fetch cycle (M 1) when an interrupt is accepted and is control. The data on the data bus is stable while the WR signal is also reset by the RESET signal. active low (WR = 0). INT (input) HOLD (input) INTERRUPT REQUEST; the CPU recognizes an interrupt re- HOLD; the HOLD signal requests the CPU to enter the HOLD quest on this line at the end of the current instruction or while state. The HO LD state allows an external device to gain control halted. If the CPU is in the HOLD state or if the Interrupt Enable of the 8080A address and data bus as soon as the 8080A has com- flip\/flop is reset it will not honor the request. pleted its use of these buses for the current machine cycle. It is recognized under the following conditions: RESET (input) [1 J \u2022 the CPU is in the HALT state. RESET; while the RESET signal is activated, the content of the \u2022 the CPU is in the T2 or TW state and the READY signal is active. program counter is cleared. After RESET, the program will start As a result of entering the HOLD stllte the CPU ADDRESS BUS at location 0 in memory. The INTE and HLDA f1iplflops are also (A15 -Ao) and DATA BUS (07-00) will be in their high impedance reset. Note that the flags, accumulator, stack pointer, and registers state. The CPU acknowledges its state with the HOLD AC- are not cleared. KNOWLEDGE (HLDA) pin. Vss Ground Reference. HLDA (output) Voo +12 \u00b1 5% Volts. HOLD ACKNOWLEDGE; the HLDA signal appears in response Vec +5 \u00b1 5% Volts. to the HOLD signal and indicates that the data and address bus VBS -5 \u00b15% Volts (substrate bias). <P1. <P2 2 externally supplied clock phases. (non TTL compatible) 3-10 April, 1977 8800b","SILICON GATE MOS 8080 A ABSOLUTE MAXIMUM RATINGS'\\\" Temperature Under Bias. . . . . . . . . . . . . .. OcC to +70c C \u00b7COMMENT: Stresses above those listed under \\\"Absolute Maxi- -65cC to +150cC mum Ratings\\\" may cause permanent damage to the device. Storage Temperature This is a str.ess rating only and functional operation of the de- vice at these or any other conditions above those indicated in All Input or Output Voltages the operational sections of this specification is not implied. Ex\u00b7 posure to absolute maximum rating conditions for extended With Respect to VBa -O.3V to +20V periods may affect device reliability. Vee, VOO and Vss With Respect to Vaa -0.3V to +2OV Power Dissipation .. 1.5W D.C. CHARACTERISTICS =TA O\u00b0C to 70\u00b0C, VOO \\\"\\\" +12V :t 5%. Vee\\\"\\\" +5V :t 5%, VaB \\\"\\\" -5V :t 5%, Vss \\\"\\\" OV, Unless Otherwise Noted. Symbol ! Parameter Min. Typ. II Max. Unit Test Condition ! VILC i Clock Input Low Voltage I Vss-l I VSS+Q.8 V ! I V1HC ! Clock Input High Voltage I 9.0 I i Voo+l I V V'L I VsS+0.8 i V VIH Input Low Voltage II V : Input High Voltage iVec+l Vss-l I 3.3 I I VOL : Output Low Voltage I i I 0.45' V } 10L \u2022 1.9mA on all outputs, VCH ! Output High Voltage I I V IoH ,. -150\/-LA. I I 3.7 I i'OO(AVI Avg. Power Supply Current (Voo ) I I! 40 70 I rnA I I } Ope,\\\";on I TCY \\\"\\\" .48 J.Lsec leCIAvl : Avg. Power Supply Current (Vce) 60 80 rnA IlaB (AVl Avg. Power Supply Current (Vaa ) .01 1 rnA i t I IlL i Input Leakage I i:tl0 \/-LA I VSS \\\"..; VIN \\\"..; Vee 'eL I Clock Leakage I II i :tl0 I Vss ~ VeLoeK ~ Voc I \/-LA 'OL[2J Data Bus Leakage in Input Mode i -100 I\/-LA I VSS<;VIN \\\"\\\";Vss+0.8V -2.0 rnA I Vss +O.8V ';;;VIN ~Vee II Address and Data Bus Leakage +10 J.LA VAOCR\/DATA = Vee 'FL During HOLD -100 VAOCR\/OATA \\\"\\\" Vss + OASV I CAPACITANCE TYPICAl. SUPPl.Y CURRENT VS. TEMPERATURE, NORMAl.IZED. (3) = =TA 25\u00b0C Vec VOO \\\"\\\" VSS \\\"\\\" OV, VBB \\\"\\\"-5V 1.5 Symbol Parameter Typ. Max. Unit Test Condition .. Cq) I Clock Capacitance 17 25 pf fc = 1 MHz CIN 10 z COUT IInput Capacitance 6 20 pf Unmeasured Pins ..;\\\"'~\\\";'; 1.0 Output Capacitance 10 pf Returned to Vss > NOTES: . It 1. The RESET signal must be aCfive for a minimum of 3 clock cycles. :l 2. When OBIN is high and VIN > VIH an internal active pull up will 0.5 1 be switched onto the Cata Bus. 0 +25 ~ +75 3. ~I supplv \/ ~ TA = -Q.45%f e. AMBIENT TEMPERATURE I'CI OATA BUS CHARACTERISTIC CURING CBIN MAX~ ~- lo~ I 0o:-'---\\\"\\\"--------'7've-e - V 1N April. 1977 3-11 P.ROOb","slueON GATE MOS 8080A A.C. CHARACTERISTICS . TA = o\u00b0c to 70\u00b0C, VOO .. +l2V \u00b1 5%, Vce = +5V \u00b1 5%. Vas\\\" -5V \u00b1 5%, Vss .. OV, Unless OtherwisE! Noted Svmbol Parameter Min. Max. Unit Test Condition tCy[31 tr , tf Clock Period 0.48 2.0 JJsec Clock Rise and Fall Time ~1 a 50 nsec ~2 4>1 Pulse Width 60 nsec t01 t02 4>2 Pulse Width 220 nsec t03 Delay rp, to 4>2 tOA [2J a nsec too [21 toc[2J Delay 4>2 to rp, 70 nsec tOF [2J to,[l1 Delay \u00a2, to 4>2 Leading Edges I 80 nsec Address Output Delay From \u00a2J2 I tOS1 I 200 nsec } CL = 100pf 220 nsec Data Output Delay From 92 }ee120 nsec Signal Output Delay From \u00a2\\\" or 4>2 (SYNC. WR.WAIT.HLOAI I :50pl DBIN Delay From 4>2 I 25 140 nsec Delay for Input Bus to Enter Input Mode tOF nsec Data Setup Time During 4>, and DB IN 30 nsec TIMING WAVEFORMS [14J (Note: Timing measurements are made at the following reference VOltages: CLOCK \\\"1\\\" = B.OV \\\"0\\\" .. 1.0V; INPUTS \\\"1\\\" = 3.3V, \\\"0\\\" .. O.SV; OUTPUTS ''1'' .. 2.QV, \\\"0\\\" = O.SV.) --r1TQ, _ICY~:h,--' f\\\\'----_ I~,I - I! ' ----!I __~ I I~I~ J!I I -.-1I--~-V--,nII---I -;_I --iTI I - ....I II \\\"'Ij;---~IrI ~ A,s,An ----------!1_-.-...-J..tI..cr-___ I i-'o..-i II1t II 'If-'oD---j .~i '01 1- AW I, I r-'OD--1 I ! I iI r---pO,..()O f II 4= II .....SYNC' ------------~-----. I -'-o.,.c..I~...-..-I.....-~-,~_ ''a--oS-,S~12-----i1~i~l --~ilII,iI'------.,.:~1i!4I ---.~ow.\\\"JH''!-!~'i!-I!r-!(:-DIA-,Ti-A---!O-~U~l!T-l':1j'4f i .. ---------1~', '-'0: r- I ! tDBIN I IF-~!!-------~lj-.....,.-,--!~I--~:I- \/-.-to,~ !,~tOF~ 1\\\\ :1\\\\ \\\\ i: ':1 II 1 i i i '-.F.,.11_ _........i---f :i 1,1\\\", :1' ~~!tIHI-I~~-'o!ici---!-::1ii, ~1 . --:I~'II-4 _ _I ~III ~r:::r~ ~ :~I'READY 'RS~.O~~ 1- : _-_:--,~~-_-_!:...WAIT II HOLD -~--~!i--4 -1 'HS ~ Ii HLOA !I INT -_:AiJIiX ',s~li, tH~i~ I INT! 3-12 Apri 1, 1977 oonnl.","SILICON GATE MOS 8080A A.C. CHARACTERISTICS (Continued) aOc av,TA = to 70\u00b0C, Voo .. +12V \u00b1 5%, Vee = +5V \u00b1 5%, Ves = -5V \u00b1 5%, Vss = Unless Otherwise Noted Symbol Parameter . Min. Max. Unit Test Condition toS2 Data Setup Time to <l>z During DBIN 150 nsec toH [1) Data Hold Time From \u00a2z During DBIN [1 ) nsec tIE[ZI tRS INTE OutPut Delay From <Pz 200 nsec Ct.'\\\" 50pt tHS READY Setup Time During \u00a2z 120 nsec tIS HOLD Setup Time to \u00a2z 140 nsec tH tFo INT Setup Time During \u00a22 (During 411 in Halt Model 120 nsec tAW[Z) tow [2] Hold Time From <Pz (READY, INT. HOI-D) 0 nsec two[Z) tWA [2) Delay to Float During Hold (Addressand Data Busl 120 nsec tHF[2) Address Stable Prior to WR -(5) nsec tWF[Z) tAH [2) Output Data Stable Prior to WR (6) nsec Output Data Stable From WR [7] nsec Address Stable From WR [7) nsec I- CI-'\\\" 100pf: Address, Data CL =SOpf: WR, HLDA, DB IN HLOA to Float Delay ,(8) nsec iNA to Float Delay (9) nsec Address Hold Time After DBIN During HLDA --20 nsec NOTES: 1. OaUl inpUt should beenebled with OBIN StaIUS. No bul conflict can Ihen occur and deta hold lime il allUred. '0104 - SO nl or tOF. whiche.er is I.... 2. Loed Circuit. l-'--f' 1 L 8080A r-! \\\"I 't'O OUTP\\\\JT :I 'I .Ix:. -i- - ..;... --~-~., ..... J-~-_J.._, I ;.\\\"._--- i Ir~& 1 I fI ,) r------~: ---~.\u00b7I,- :: \u00b7 .! -~--~---'i TYPICAL ~ OUTPUT DEl.AY VS. ~ CAPACITANCE I! i-r---l ~o +20 , . - - - - , . - - - - . , . . . . . - - - - . . ,......- - - , I ..! ! ! SYNC .<>.. +10 I-_-,-,-----,...-.....;;;;::=1 AM- - Q I- 0 !DBIN ;:) Il ~ I- ::) -10 0 <l +100 READY .:. CAPACITANCE (pI) (CACTUAL - Csnel WAIT t- 4. The followi\\\"9 are relevent when interfaci\\\"9 the 8080A 10 devic.. \\\"..ing VIH - 3.3V: HOLD al Maximum output rise time from .BV to 3.3V \u2022 lOOns <iI CL. \u2022 SPEC. HLOA t------x.-:.:j '-o-e---+--- bl OutPut deley wilen measured to 3.0V \u2022 SPEC ~ (ijl CL. \u2022 spec. INT --'~------- cl If CL. ... SPEC, add .6ns\/pF if CL> Cspec subtract .3ns\/pF (from modified deleyl if CL < CSPEC. INTE S. 'AW - 2 tCY -103 -lr4>2 -140nsec. '6. lOW - tCY -103 -t,.4>2 -170nsec. 7. If nOI HLOA. IWO -IWA S 103 + Ir4>2 +10ns. If HLOA.IWO -IWA -IWF. 8. 'HF - t03 + Ir4>2 -SOns. 9. IWF - t03 + t r4>2 -10ns 10. Oata in must be stable for Ihil period during OBIN \u00b7T3. 80th tOSl and tOS2 must be satisfied. 11. Re8dv signal must be stable for thil period dUring T2 or TW. (Must be externally svnchronized.) 12. Hold si9na1 must be stable for this period during T2 or TW when entering.hold mode. and during T3. T4. TS and TWH when in hold mod \u2022. (External svnchronization is not required.) 13. Interrupt signal must be stable during this period of the last clock cycle of any instruction in ord.... to be r~gnized on Ihe following instruCtion. IExternal svnchronization is not rlQuir8Cl.) 14. This timing diagram shows timi\\\"9 relationships only; it doel not repre..nt any specific machine cycle. 3-13","SILICON GATE MOS 8080 A increment and decrement memory, the six general registers and the accumulator is provided as well as extended incre- INSTRUCTION SET ment and decrement instructions to operate on the register pairs and stack pointer. Further capability is provided by The accumulator group instructions include arithmetic and the ability to rotate the accumulator left or right through logical operators with direct, indirect, and immediate ad- or around the carry bit. dressing modes. Input and output may be accomplished using memory ad- Move, load, and store instruction groups provide the ability dresses as I\/O ports or the directly addressed I\/O provided to move either a or '6 bits of data between memory, the for in the a080A instruction set. six working registers and the accumulator using direct, in- direct, and immediate addressing modes. The following special instruction group completes the aOaOA instruction set: the NOP instruction, HALT to stop pro- The ability to branch to different portions of the program cessor execution and the OAA instructions provide decimal is provided with jump, jump conditional, and computed arithmetic capability. STC allows the carry fl~g to be di- jumps. Also the ability to call to and return from sub- rectly set, and the CMC instruction allows it to be comple- routines is provided both conditionally and unconditionally. mented. CMA complements the contents of the accumulator The RESTART (or single byte call instruction) is useful for and XCHG exchanges the contents of two l6-bit register interrupt vector operation. pairs directly. OOl:.lble precision operators such as stack manipulation and double add instructions extend both the arithmetic and interrupt handling capability of the aOaOA. The ability to Data and Instruction Formats Oata in the a080A is stored in the form of a-bit binary integers. All data transfers to the system data bus will be in the same format. 107 0 6 0 5 04 03 02 0, 001 OATA WORO The program instructions may be one, two, or three bytes in length. Multiple byte instructions must be stored in successive words in program memory. The instruction formats then depend on the particular operation executed. One Byte Instructions TYPICAL INSTRUCTIONS Register to register, memory refer- I I0 7 Os 0 5 0 4 03 O2 0, 0 0 OP COOE ence, arithmetic or logical, rotate, return, push, pop, enable or disable Two Byte Instructions Interrupt instructions I1 0 7 0 6 05 0 4 03 O2 0, 0 0 OP COOE Immediate mode or I\/O instructions I107 0 6 05 0 4 03 02 0, 0 0 OPERAND Three Byte Instructions Jump, call or direct load and store instructions I1 0 7 06 05 0 4 03 02 0, 0 0 OP COOE I1 0 7 0 6 0 5 0 4 0 3 O2 0 1 00 LOWAOORESSOR OPERANO 1 I1 0 7 06 05 0 4 03 02 0, 0 0 HIGH ADORESS OR OPERANO 2 For the aOaOA a logic \\\"'\\\" is defined as a high level and a logic \\\"0\\\" is defined as a low level. 3-14 April, ~977 8800b","SILICON GATE MOS 8080A INSTRUCT10N SET '-' Summary of Processor Instruetions InstrucUoa Codel1l Clock 121 InstrucU\\\" Codel11 C1ocld21 Mumoaic Oncrilltion Oo,Qe Os O. 03 ~ 0, Do CVeils Mn....onic Oeaiption Oo,Oe Os O. o,~ 0, Do CV. MOV r1.r2 Move r..illll' 10 rtgiatll' a1 0 0 05 55 5 RZ Rlturn on mo 1I a01000 5111 MOVM.r Mon IWglItIl' 10 m.mory a1 I I a5 5 5 7 RNZ Rnum on no lIl'Il 1 1 0 0 aaQa 5\/11 MOVr.M Mon memory 10 r.ter a1 0 0 0 1 I a 7 RP R.tum on ,Ofitiw 1 1 I t a0 aa 5\/11 HLT Hilt aI I I aI I a 7 RM Rnum on milllll 1 1 I I I a aa 5\/11 MYlr Move immlCliatl,..iltlr aa 0 0 0 1 I a 7 RI'! Rnum on \\\"';ty _n 1 I 1 a 1 0 a9 5\/11 MYIM Mon immlCli.tI m.mory aa 1 I a1 1 a 10 RPO R.turn on \\\"';1'1 odd 1 1 1 a 0 aQa 5\/11 'NAr Incr.mltl1 rlllJillII aa 0 0 0 I aa 5 RST RII1Ift 11 OCR r 0 a 0 0 0 1 a1 5 IN In,ut A AAI 1 1 10 INA M O_tnt 'IIlJi1tlr aa 1 1 aI a0 10 OUT OUl1lut 10 OCR M 0 a 1 1 aI aI 10 LXIB LOId immediate 'IIlJiIIII' a 11aI 1 10 ADO r Incnment memory I a 0 a a5 5 5 4 PairB &C a 1 a0 1 1 AOCr OlCflment memory 1a 0 0 15 5 5 4 LXI 0 LOId immedi.tI....- 0 0 0 a0 10 5UB r AcId rlllJiJtar 10 A 1 0 0 1 a5 5 5 , ,I 1 5B8r Add ..giltll'to A with ClITV '4\\\" LXIH \\\"\\\"erPairO&E 10 5ulltract ngisftt from A I 0 0 1 15 55 1I ANAr 5ubtract rtrjisler from A 4 LXI5P LOId immlCliltl 1 10 XRAr with borrow 4 PUSH B Pai,H&L 11 OI;Ar And register with A 4 Load immedi.t. nack poinm a0 eMP, Exclusin Or rlllJistIl' with A 4 PUSH 0 Push ,..imr Pair B& C an 11 AOOM O,,..istIl'withA 7 $lack 0a a 00 a AOCM Cam,_ registar with A 7 PUSH H Push rlllJistar Pair 0 & E an 11 5UB M Add memory to A 7 stxk 00 0000 5B8M Add memory to A with carry 7 PUSH PSW Push regiltlr Pair H& L an 11 a 1 a05 5 5 stICk 00 I I 00a ANAM 5ulltnt:t memory f'lIAl A a I 0 I 5 55 7 POP B PusilAand Fl... I 1 0 a0 I 0 10 XRAM SubtflCt memory from A 0 I 1 a5 5 5 7 OAAM with borrow 7 POP 0 ,ai,on nack 0 a0 10 CMPM And m.mory with A 0 1 1I 555 7 AOI Exclusiv. Or memory with A 7 POPH Po, r.1I' B& C off 00 0 10 ACI 0, m.mory WIth A 0 0 00I I0 7 Comoar. memory with A POPPSW stKlt a0 10 5UI Add immediate 10 A 0 aa11 10 \u00b77 Po, regiltlr pu 0 &E off SBI Add immediate 10 A with 0 0 I a1 I 0 7 STA SlICk 13 carry 0 a I I 1 1a LOA Po, tlllJiStll' pair H & L off 13 ANI 7 XCHG sticlt 4 XRl 5ubtrICt immediate from A a 1 aa a 7 Po,Aand FI... a aa a 5ubtrICt immlCli.t. from A a 1 aI a 4 XTHL OffSlKk 18 ORI WIth borrow aI Ia a 4 5PHL 5to,. A direct 0 aa 5 CPt And immlCliat. with A a 4 PCHL LalCl A direct 5 RLC exclusive Or immedi.t. with 0 1 11 a 4 DAD B Exch.nge 0 &E. H&L aaaa 10 RRC A a OAO 0 RlIlJislll'1 10 RAL Or immlCliat. with A 1 aaa 10 DAD H exeh.nlJl to, of nack. H& L aaa 10 RAA Com,. . immedi.t. with A 1 aa1 10 OA05P H& L to StICk ,oinm 10 Rotltl A l.ft 10 5TAX B H& L to ,rogram countll' 7 JMP RODD A ritht 0a a 10 5TAX 0 AddB&ClaH&L aa 1 aa a 7 JC Rotltl A I.ft througll carry a1 a 10 LOAX B AddO&EtoH&L a0 1 I a a 7 JNC Rotat. A right throuth 10 LOAX 0 AddH&LIOH&L 11 a1a 1 7 JZ carry aa a 10 INX B Add stick poinm to H& L 5 JNZ a1 a 10 INXO 5lOre A indirect 11 1 00a11 5 JP Jump unconditionli 10 INX H 510,. A indirect 5 JM Jum, on e.1TV ,I 1 1 1 a 0 17 INX5P LoICI A indirect 11 1 1 I aaI 5 JPE Jum, on no carry 11 1 I 11\/17 OCX B LolCI A indirect 1 1 1 a1aaI 5 JPO Jump on zero a0 a 0 0 a 11\/17 OCX 0 5 Jump on no zero 0a 0 aI 11\/17 OCX H Incnment B& Cregiltlrs 0 a 0 aI a0 1 5 CALL Jum, on positive 1 11\/17 OCX 5P Incnment 0 & E regimn aa a 1 1a aI 5 Jump on minus 0a 0 I a 11\/17 CMA I_ _nt H& L r'9ialll'1 aa 1 a 1aa1 4 CC 0a a 1 I 1 11\/17 STC aa 1 I 1 aaI 4 CNC Jump on P\\\"'1'I enn I 11\/17 CMC Incr.ment stKlt ,oinm 4 CZ Jum, on , ..itv odd 11\/17 OM D_tB&C 4 CNZ Call uncondition.1 1 10 5HLO D_tO&E 16 CP Call on carry 5\/11 LHLD Oecrem.m H& L 16 Callan no carry ,0 a a, a 1 1 5\/11 EI Decrem.nt stacIt pointer aa a 0 aa 1a 4 eM Callan zero 01 Com,l.mtnt A a0 a 1 a0 1 a 4 Callan no zero a I 1a1a NOP 5.t carry aa a a I a 10 4 CPE Call on positive a 1 aa a Com,l.ment carry aa a 1 1 a 1a CPO Call on minus a a1a1a Decimal .djust A aa 0 aaa1 I AET Callan parity even a aaa1 a SIO,. H& L diract aa a 1 aa 1 I RC Call on ,arilV odd I I aa1 a Load H & L direct ,a a 1 a a a I 1 RNC Rlturn Enallle Intaml'ts 00 I 10a Rnu,n on carry 1 110 10 Disabl. intaml,t 1 R.tu,n on no ClITV 1 0 1a10 No\u00b7o,.\\\"tion 00 0 0 I 0 1I 1 a0 0 10 00 0 1 10 11 ,0 0 I 1 a I aa 1 0 1 a I 1 0 1100 aa I 1 1 a 1 I 00 I a1 1 I 1 a 1 0 1 a0 0 0 1 1 a1 1 1 a0 I 100 0 0 a1 0 a 00 I I I I 1I 1 1 a1 a0 I 11I 0a aa I 0 0 1 1 I 1 a1100 00 1 0 00 1a I 0 0I 0a 0 a1aa1 00 1 0 I 0 10 a1 I 1 1 I 1I I 1 I 1 aa 1 1 0 a 0 a0 0 aa 0 I 1 0 0 0 0 1 0 a a 0 NOTES; 1. 000 orSSS -000 B -001 C -010 0 -011E -100 H - 101 L -110 Memory -111 A. 2. Two possible cycle times. (5\/11) indicate instruction cycles deQendent on condition flags. 3-15","Schottky Bipolar 8212 EIGHT-BIT INPUT\/OUTPUT PORT \u2022 Fully Parallel 8-Bit Data \u2022 3.65V Output High Voltage Register and Buffer for Direct Interlace to 8080 CPU or 8008 CPU \u2022 Service Request Flip-Flop for Interrupt Generation \u2022 Asynchronous Register Clear \u2022 Low Input Load Current - .25 mA Max. \u2022 Replaces Buffers, Latches and Multiplexers in Micro- \u2022 Three State Outputs computer Systems \u2022 Outputs Sink 15 mA \u2022 Reduces System Package Count The 8212 input\/output port consists of an 8\u00b7bit latch with 3-state output buffers along with control and device selection logic. Also included is a service request f1ip\u00b7flop for the generation and control of interrupts to the microprocessor. The device is multimode in nature. It can be used to implement latches, gated buffers or multiplexers. Thus, all of the princi- pal peripheral and input\/output functions of a microcomputer system can be implemented with this device. PIN CONFIGURATION LOGIC DIAGRAM os, vec SERVICE REQUEST FF MO INT \\\\ 01, Dis DEVICE SEl.ECTION 00, ODs -\\\"'--U>OSl 01 2 01 7 0\u00b02 007 IE> 052 01 3 Dis 003 006 II> MO ---+H~~ OUTPUT 01 4 015 IE> STB--.....--1L~ BUFFER 0\u00b04 0\u00b05 11> 01, -------+-H STB CLR OND D~ PIN NAMES 1\u00a7>015-------~H 01,-0\\\" I DATA IN \u00a7>Ols--------i-H 00,-00. i DATA OUT ~017-------+-H ~-DS1 DEVICE SELECT \u00a7>018-------.J.....j~ MD I MODE STB ! STROBE [9 Ci:R-----...q \\\"\u00bb+--....... INT I INTERRUPT (ACTIVE LOWI (ACTiVe LOW) CLR I CLEAR (ACTIVE LDWI ~pl\\\"i 1, 1977 38COb 3-16","SCHOTTKY BIPOLAR 8212 Functional Description Service Request Flip-Flop Data Latch The (SR) flip-flop is used to generate and control The 8 flip-flops that make up the data latch are of a interrupts in microcomputer systems. It is asyn- \\\"0\\\" type design. The output (Q) of the flip-flop will chronously set by the CLR input (active low). When follow the data input (D) while the clock input (C) is the (SR) flip-flop is set it is in the non-interrupting high. Latching will occur when the clock (C) returns state. low. The data latch is cleared by an asynchronous reset The output of the (SR) flip-flop (Q) is connected to input (eLR). (Note: Clock (C) Overides Reset (CLR).) an inverting input of a \\\"NOR\\\" gate. The other input to the \\\"NOR\\\" gate is non-inverting and is connected Output Suffer to the device selection logic (051 \u2022 OS2). The output The outputs of the data latch (Q) are connected to of the \\\"NOR\\\" gate (INT) is active low (interrupting 3-state, non-inverting output buffers. These buffers state) for connection to active low input priority have a common control line (EN); this control line generating circuits. either enables the buffer to transmit the data from the outputs of the data latch (Q) or disables the SERVICE REOUEST FF buffer, forcing the output into a high impedance state. (3-state) \\\\ This high-impedance state allows the designer to connect the 8212 directly onto the microprocessor OEVICE SELECTION bi-directionat data bus. \\\"'-, Control Logic The 8212 has control inputs 051, 052. MO and 1DDSi' STB. These inputs are used to control device selec- tion, data latching, output buffer state and service @>OS2 request flip-flop. rI> MO --'-++-!l-J OUTPUT IE> STB----t_..1 BUFFER 0, G> rn:>012 ------.....;:=-IH DS1, DS2 (Device Select) \u00a7>Ots-------+-f-I These 2 inputs are used for device selection. When 051 is low and 052 is high (051 \u2022 052) the device is selected. In the selected state the output buffer is enabled and the service request flip-flop (SR) is asynchronously set. MD (Mode) 1!E>0Is-------+-f-I This input is used to control the state of the output buffer and to determine the source of the clock input [\u00a7> 017 - - - - - - - + - H (C) to the data latch. When MO is high (output m9de) the output buffers fll> 0'8 - - - - - - -......+1 are enabled and the source of clock (C) to the data latch is from the device selection logic (051 \u2022 052). I2>CLR-----.-q \u00bb+--\\\"'--'\\\" When MO is low (input mode) the output buffer state (ACTIVE LOWI is determined by the device selection logic (051 \u2022 052) and the source of clock (e) to the data latch is L IST8 . ~_los,'OS,1 \u2022 OA.T~ll.UT.Eau..~.J CLR \u2022 I~'OS,I 'ST8 !'SA [ INT the.STB (Strobe) input. :- ~. ~. i. o \u00b7 0 . 0 0 ,J\u00b7STATE . ;! ~ ! STS (Strobe) ti-.:J.; -g. >%1.l~~TI;'i.--\\\"1 ~. ~ ~ This input is used as the clock (C) to the data latch ~..l-_.__ -.'!__ ~,__ ~a _~ Q~!~~.T.-r;~_n_---'; l ' 1 . 0 0 0, l-~-ij--=-~~ :~.: .-:~-tiUr.c!'~~-_-~ [\u00b1 ~ -Z- for the input mode MO = 0) and to synchronously 1a reset the service request flip-flop (SR). ~'~ Note that the SR flip-flop is negative edge triggered. I1 1 1 OATA IN 'INTEANAL SA FLIP\u00b7FLOP April. 1977 CLR - RESETS DATA LATCH 8800b SETS SR FLIP\u00b7FLOP (NO EFFECT ON OUTPUT SUFFER) 3-17","SCHOTTKY BIPOLAR 8212 Applications Of The 8212 _. For Microcomputer Systems I Basic Schematic Symbol VII 8080 Status Latch II Gated Buffer VIII 8008 System III Bi-Directional Bus Driver IX . 8080 System: IV Interrupting Input Port V Interrupt Instruction Port 8 Input Ports VI Output Port 8 Output Ports 8 Level Priority Interrupt I. Basic Schematic Symbols as a system bus (bus containing 8 parallel lines). The output to the data bus is symbolic in referenc- Two examples of ways to draw the 8212 on system ing 8 parallel lines. schematics-(1) the top being the detailed view showing pin numbers. and (2) the bottom being the symbolic view showing the system input or output BASIC SCHEMAnc SYMBOLS INPUT DEVICE OUTPUT DEVICE (OeTAILEO) INPUT n 113 12 ~ 1 OUTJOUT STROBE I FLAG Ve,e. - SYSTEM INPUT (SYMBOt.lC) GND DATA BUS DATA BUS II. Gated Suffer ( 3 . STATE ) GATED BUFFER 3-5TATE The simplest use of the 8212 is that of a gated buffer. By tying the mode signal low and the strobe Vee - . . . , . . - - - - - - - , input high. the data latch is acting as a straight through gate. The output buffers are then enabled STB from the device selection logic D51 and D52. INPUT OUTPUT When the device selection logic is false, the outputs DATA DATA are 3-state. (250 i'At (1SmA) (3.65V MIN) When the device selection logic is true, the input '------qCiJl' data from the system is directly transferred to the Apri1, 1977 output. The input data load is 250 micro amps. The GATING { GND ...l output data can sink 15 milli amps. The minimum C(D~ST10R0SO2Ll aaCOb high output is 3.65 volts. 3-18","SCHOTTKY BIPOLAR 8212 III. Bi-Directional Bus Driver BI-DIRECTIONAL BUS DRIVER A pair of 8212's wired (back-to-back) can be used 1 as a symmetrical drive, bi-directional bus driver. The devices are controlled by the data bus input STB control which is connected to OS1 on the first 8212 and to OS2 on the second. One device is active, and DATA I .... .J. OATA acting as a straight through buffer the other is in BUS BUS 3-state mode. This is a very useful circuit in small ...) 8212 system design. '\\\" ~ r-<= ctR IV. Interrupting Input Port -DATA BUS Y I L..- This use of an 8212 is that of a system input port CONTROL that accepts a strobe from the system input source, (0- L -Rt GND which in turn clears the service request flip-flop (I. R- Ll and interrupts the processor. The processor then STB goes through a service routine, identifies the port, and causes the-device selection logic to go true- 8212 vA-- enabling the system input data onto the data bus. L Ci:R ~ P GND INTERRUPTING INPUT PORT INPUT OATA STROBE BUS STB SYSTEM INPUT SYSTEM RESET - - a r - - - 'PORT Ao-. TO PRIORITY CKT lS l l iCT10N r (OSl00S2) - - - - -.. (ACTIVE LOW) OR TO CPU INTERRUPT INPUT V. Interrupt Instruction Port INTERRUPT INSTRUCTION PORT The 8212 can be used to gate the interrupt instruc- DATA tion, normally RESTART instructions, onto the data BUS bus. The device is enabled from the interrupt acknowledge signal from the microprocessor and STB from a port selection signal. This signal is normally tied to ground. (OS1 could be used to mu'ltiplex a R'ESTART variety of interrupt instruction ports onto a com- INSTRUCTION mon bus). IRST 0 - RST 71 - - - - I(DSll PORT SELECTION INTERRUPT ACKNOWLEDGE - - - - - - ' Apr; 1, i 977 3-19 880Gb","SCHOTTKY BIPOLAR 8212 VI. Output Port (With Hand-Shaking) OUTPUT PORT (WITH HANO-SHAKING) The 8212 can be used to transmit data from the data DATA bus to a system output. The output strobe could be BUS a hand-shaking signal such as \\\"reception of data\\\" from the device that the system is outputting to. It . . . - - - - - OUTPUT STROBE in turn, can interrupt the system signifying the re- ception of data. The selection of the port comes SYSTEM OUTPUT from the device selection logic. (051\u00b7 052) SYSTEM P - - - SYSTEM RESET INTERRUPT ' - - - - l PORT SELECTION '-I (LATCH CONTROLl ' - - - - - - - ... (DSi.OS2l VII. 8080 Status Latch Note: The mode signal is tied high so that the output on the latch is active and enabled all the time. Here the 8212 is used as the status latch for an 8080 microcomputer system. The input to the 8212 latch It is shown that the two areas of concern are the is directly from the 8080 data bus. Timing shows bidirectional data bus of the microprocessor and the that when the SYNC signal is true, which is con- control bus. nected to the 052 input and the phase 1 signal is true, which is a TTL level coming from the clock generator; then, the status data will be latched into the 8212. 8080 STATUS LATCH Do 10 0, 9 O2 8 7 03 8080 04 3 4 Os 5 06 6 0, 19 STATUS SYNC LATCH OBIN ~ ,;1 02 22 15 -..,12V r \\\\ . ~5 0, Do . ! - INTA - L WO OV-J \\\\......L, 7 W8 STACK 9 16 1F58212 HLTA 01 18 OUT BASIC 02 20 CONTROL 22 ~ Ml ~ INP -- .li- MEMR BUS CLOCK GEN. SYNC & DRIVER Ilo1TTL) r,i CLR 1 DATA II D~ MO OS, 13 12 '( 1 J0\\\",. !I STATUS 3-20 Apr; 1, 1977 8800b","SCHOTTKY BIPOLAR 8212 VIII. 8008 System This shows the 8212 used in an 8008 microcomputer sor to be interrupted from the input port directly. system. They are used to multiplex the data from The control of the input bus consists of the data bus three different sources onto the 8008 input data bus. input signal, control logic, and the appropriate The three sources of data are: memory data, input status signal for bus discipline whether memory data, and the interrupt instruction. The 8212 is also read, input, or interrupt acknowledge. The combina- used as the uni-directional bus driver to provide a tion of these four signals determines which one of proper drive to the address latches (both low order these three devices will have access to the input and high order are also 8212's) and to provide ade- data bus. The bus driver, which is implemented in quate drive to the output data bus. The control of an 8212, is also controlled by the control logic and these six 8212's in the 8008 system is provided by clock generator so it can be 3-stated when neces- the control logic and clock generator circuits. These sary and also as a control transmission device to circuits consist of flip-flops, decoders, and gates to the address latches. Note: The address latches can generate the control functions necessary for 8008 be 3-stated for DMA purposes and they provide 15 microcomputer systems. AlsO' note that the input miHi amps drive, sufficient for large bus systems. data port has a strobe input. This allows the proces- INPUT 8008 SYSTEM ADDRESS DATA LATCHES BUS BUS DRIVER LOW ORDER (8 BITS) MEMORY DATA GND INPUT 00-07 So 8212 HIGH ORDER STROBE (SBITS) 8008 S, INPUT DATA S2 INTERRUPT SYNC INSTRUCTION INT Apr; 1, 1977 READY ---, 880Cb '02 _.-- .~--- ' - -.......- vcc \u2022 \u2022 \u2022 \u2022 \u2022 \u2022~DATABUS '---------<:tMEM READ ,\u2022 L . . . . - - - - - - - - - e t INPUT OUT (04,5,6,7) .-----------1 b - - - - - - - - -,-----------etINT ACK WR DATA BUS IN I . OUT '-++----------aINT REa. \\\" WAIT REQ.--'-\\\"'......;,.,.'~I L. J CONTROL LOGIC & CLOCK GEN. 3-21","SCHOTTKY BIPOLAR 8212 IX. 8080 System bit, which is common to all input ports. This drawing shows the 8212 used in the I\/O section Also present is the address of the device on the of an 8080 microcomputer system. The system con- 8080 address bus which in this system is connected sists of 8 input ports, 8 output ports, 8 level priority to an 8205, one out of eight decoder with active low systems, and a bidirectional bus driver. (The data outputs. These active low outputs will enable one of bus within the system is darkened for emphasis). the input ports, the one that interrupted the proces- sor, to put its data onto the buffered data bus to be Basically, the operation would be as follows: The 8 transmitted to the CPU when the data bus. input ports, for example, could be connected to 8 key- signal is true. The processor can also output data boards, each keyboard having its own priority level. from the 8080 data bus to the buffered data bus The keyboard could provide a strobe input of its when the data bus input signal is false. Using the own which would clear the service request flip-flop. same address selection technique from the 8205 The INT signals are connected to an 8 level priority decoder and the output status bit, we can select encoding circuit. This circuit provides a positive with this system one of eight output ports to trans- true level to the central processor (INT) along with mit the data to the system's output device structure. a three-bit code to the interrupt instruction port for the generation of RESTART instructions. Once the Note: This basic I\/O configuration for the 8080 can processor has been interrupted and it acknowledges be expanded to 256 input devices and 256 output the reception of the interrupt, the Interrupt Acknowl- devices all using 8212 and, of course, the appropri- edge signal is generated. This signal transfers data ate decoding. in the form of a RESTART instruction onto the buf- fered data bus. When the OBI N signal is true this Note that the 8080 is a 3.3-volt minimum high input RESTART instruction is gated into the microcom- requirement and that the 8212 has a 3.65-volt mini- puter, in this case, the 8080 CPU. The 8080 then per- mum high output providing the designer with a 350 forms a software controlled interrupt service routine, milli volt noise margin worst case for 8080 systems saving the status of its current operation in the when using the 8212. push-down stack and performing an INPUT instruc- tion. The INPUT instruction thus sets the INP status 3-22 Apr; 1. 1977 8800b"]