altair_8800b

device. It is applied to the Display/Control to light the \"OUT\" LED (Figure 3-16, sheet 3, zone 83), indicating data is being trans- ferred from the CPU to an external device. The SOUT output from the CPU (Figure 3-14, zone AS) is applied to the external device I/O card in order to initiate a data transfer from the CPU during T3. At the beginning of T3, the CPU data is transferred to the external device via the bus. The CPU data out (000 through 007) is applied to the bus (zone Cl) through bi-directional gates 0 and E (CS and OrEN are LOW) and non-inverting bus drivers Mand W (zones C7 and C3). The bus data ;s presented to the external device and written in py the PWR signal. After the CPU data is settled on the bus, a WR signal (zone C8) is generated LOW by M. The WR signal is applied to pin 77 (zone 01) of the bus through non-inverting bus driver V (zone 08) as PWR. The PWR signal allows the external device to store the CPU data, thus completing the CPU to external device data transfer. 3-28. FRONT PANEL OPERATION A variety of functions may be performed through the operation of the front panel: e.g. selecting a starting location for a program, examining memory locations, single stepping through a program, depositing and displaying CPU accumulator data, and depositing data into a specified memory location. Each of the functions performed on the 8800b front panel are discussed in the following paragraphs. The run operation was discussed in Para- graph 3-10. 3-29. FRONT PANEL BLOCK DIAGRAM (Figure 3-12) The front panel switches allow the operator to assume control of the CPU. The CPU is controlled by a FRDY signal which is generated from the front panel display control circuits. T~e FROY signal places the CPU in either a wait condition or a run operation. The CPU is placed in a wait condition when the Switches and Decoding circuits sense that the RUN/STOP switch on the front panel is positioned to STOP. A STOP signal is applied to the Stop/Run 3-68 ,\"or; 1, 1977 3eOOb

, CPU , ir , SWITCIlES RUN •-. STOP/RUN ....AND CONTROL DECODING STOP 55 SLOW Figure 3-12. Front

FRDY RUN ~ , ir -=L)- PSYUC SS ss· 005 CONTROL STSTB -a .-. . ~ .0 ·~O La .Or:-CcOo Panel Block Diagram

Control circuits to disable (HIGH) the RUN signal. The RUN signal forces the CPU to a wait condition by disabling (LOW) the FRDY line. The CPU will not enter a wait condition until the PSYNC, 005, and STSTB signals are presented to the Stop/Run Control circuits. The presence of these signals insures that the CPU will stop during the first machine cycle of an instruction cycle. The CPU is placed in a single step (SS) or slow run operation by the generation of an SS or SLOW signal from the Switches and Decoding circuits. The SS or SLOW run operation aJlows the CPU to perform one instruction cycle. The SS signal is applied to the SS Control circuit, enabling (LOW) the SS signal. The SS signal allows the CPU to execute one instruction cycle by enabling the FRDY signal. Upon the completion of the instruction cycle, the CPU attempts to perform another instruction cycle, but the PSYNC, 005, and STSTB signals reset the SS Control circuits forcing the CPU to a wait condition. 3-30. STOP OPERATION The stop operation allows the operator to use the switches on the 880Gb front panel. The stop operation is activated when the RUN/STOP switch on the 880Gb front panel is momentarily depressed to STOP. The RUN/STOP circuits are located on the Display/Control card (Figure 3-16, sheet 2, zone A9). With the RUN/STOP switch momen- tarily depressed, a LOW is applied to quad latch Cl, input 01. The occurrence of the next C13 clock (zone Al) causes the Q output at pin 3 of Cl (zone 89) to go HIGH which is applied to quad latch Nl, input 01. The next C13 clock causes the Q output at pin 7 of Nl (zone 89) to go HIGH which is applied to the 0 input of Ml. A HIGH present at 0 produces a clock pulse to set Ml, stopping the CPU. The clock pulse that sets Ml is derived from three signals: 005, PSYNC, and STSTB (zone 08). The signals are enabled during machine cycle 1 (paragraph 3-14) of an 8800b instruction cycle, and their presence generates a clock to Ml (zone C9). This insures that the 880Gb stops during the first machine cycle of an instruc- 3-70 April. 1977 SaaOb

tion cycle. The 005 signal is generated by the CPU (Figure 3-14, zone Cl) and presented to pin 39 of the bus as a HIGH through the bi-directional gate E (zone C7) and non-inverting bus driver W (zone C3) and applied to the Interface Card (Figure 3-15, sheet 2, zone C2). The 005 signal is inverted by Y (zone B2) and inverted again by Rl on the Display/Control Card (Figure 3-16, sheet 2, zone 08) and applied HIGH to pin 3 of NAND gate 01 (zone C8). The PSYNC is generated by the CPU (Figure 3-l4,zone 01) on pin 76 of the bus as a HIGH through non-inverting bus driver V (zone 08) and applied to the Interface Card (Figure 3-15, sheet 2, zone A3). PSYNC is inverted by U (zone B3) and Rl on the Display/Control Card (sheet 5, zone B3) and applied HIGH to pin 4 of NAND gate 01 (zone C8). The STSTB is generated by the CPU (Figure 3-14, zone A4) to pin 56 of the bus as a LOW through non-inverting bus driver Rand applied to the Interface Card (Figure 3-15, sheet 2, zone A4). The STSTB is inverted and then inverted again by the Interface Card (sheet 2, zone A4) and applied to pin 5 of NAND gate Dl on the Display/ Control Card (Figure 3-16, sheet 2, zone C8) as a HIGH. These signals allow NAND gate 01 to produce a HIGH at gate Pl, pin 6 (zone C8), which sets Ml. The Qoutput of Ml goes LOW and is applied through Kl (zone A8) to enable all the front panel switches. The Q output is also presented to gate Pl which keeps a high on the CK input of Ml (zone C9), insuring that Ml remains set after the stop switch is released. Because Ml is set, the Q output of Ml (zone C9) is HIGH, disabling the RUN and FRDY signals. The FRDY signal is applied to NAND gate C on the CPU (Figure 3-14, zone A8) through the Interface (Figure 3-15, sheet 2, zone Al) as a LOW. This inhibits the RDYIN signal at F (Figure 3-i4, zone B7) which disables the READY signal to M(zone A8), thereby halting the CPU. 3-31. SINGLE STEP OPERATION The single step operation allows the operator to increment one instruction cycle at a time. The single step operation is activated when the SINGLE STEP/SLOW switch is momentarily positioned to SINGLE STEP. - The SINGLE STEP circuits are located on the Display/Control card (Figure 3-16, sheet 1, zone A8). With the SINGLE STEP/SLOW ,:'pri 1, 19/7 3-71 8800b

switch momentarily positioned to SINGLE STEP, a LOW is presented to pin 1 of gate P1 (zone C8). The LOW input at 01 generates a clock pulse which sets Ml (zone A7), producing a LOW at the Q output of M1. The LOW output is applied to pin 13 of gate Pl (zone C9), enabling the FRDY signal (zone 09). The CPU performs one instruction cycle with FRDY enabled. At the completion of the instruction cycle, the 005, PSYNC, and STSTB input (zone 08) enable NAND gate T1, pin 12 (zone C6), LOW which produces a LOW at the output of inverter J1 (zone C6). The LOW clears the Ml flip-flop, thereby ending the first single step operation. Additional single step operations are enabled by momentarily depressing the SINGLE STEP/SLOW switch to SINGLE STEP. The 005 input is applied to pin 1 of NAND gate Tl through jumpers JE and JF (zone 07). If this jumper is removed, pin 1 of NAND gate is always HIGH. Under this condition, the PSYNC and STSTB signals would reset Ml after each machine cycle. 3-32. SLOW OPERATION The slow operation is very similar to the single step operation except the slow operation allows the 8800b to execute instruction cycles at a very slow rate (786 milliseconds vs. 3 milliseconds normal operation). The slow circuits are located on the Display/Control card (Figure 3-16, sheet 2, zone A8). When the SINGLE STEP/SLOW switch is positioned to SLOW, a HIGH is presented to pin 9 of NAND gate Pl (zone 87). The HIGH at pin 9 enables the C18 clock (zone 07) from a 24-bit counter (sheet 1, zone 01) through NAND gate Pl (sheet 2, zone 87). This clock enables pin 12 of gate 01 (zone C8) HIGH, providing a clock pulse to set Ml (zone An, producing a LOW at the Q output, Ml. The LOW output is applied to pin 13 of gate P1 (zone C9), enabling the FRDY signal (zone 09). With FRDY enabled, the CPU performs one instruction cycle. At the completion of th~ instruction cycle, the 005, PSYNC, and STSTB input (zone 08) enable NAND gate Tl, pin 12 (zone C6), LOW which produces a LOW at the output of inverter J1 (zone C6). This LOW clears the M1 flip- flop, ending the first single step operation. If the SINGLE STEP/ 3-72 ,Apr; 1. 1977 8S00b

SLOW switch is still positioned to SLOW, another instruction cycle operation is performed. Otherwise, the machine halts. If jumpers JE and JF (zone C7) are removed, the machine may not stop at the beginning of an instruction cycle. 3-33. RESET OPERATION The reset operation allows the operator to reset the CPU at anytime during machine operation. The reset is activated when the RESET/EXT CLR switch on the front panel is positioned to RESET. The reset circuits are located on the Display/Control card (Figure 3-16, sheet 2, zone A2). With the RESET/EXT CLR switch momentarily positioned to RESET, a PRESET signal (zone 03) is applied to the Interface (Figure 3-15, sheet 2, zone 01) as a HIGH. The HIGH is inverted by R and applied to pin 75 (zone Al) of the bus through non-inverting bus driver N (zone Bl). The CPU receives the PRESET signal and inverts it twice through G and B (Figure 3-14, zone B6). The output of B is applied to the clock generator F RESIN (reset in) input (zone B7), producing a RESET output to the 8080 (M). 3-34. PROTECT AND UNPROTECT OPERATION The protect/unprotect operati on either preven~s any new data from being written into a particular region of memory (protect) or allows new data to be written into a particular region of memory (unprotect). The protect/unprotect operation is con- trolled by the positioning of the PROTECT/UNPROTECT switch on the front panel. The protect/unprotect circuits are located on the Display/ Control card (Figure 3-16, sheet 2, zone Al). With the PROTECT! UN PROTECT switch positioned to either PROTECT or UNPROTECT, a PROTECT or UNPROTECT signal (zone 03) is applied to the Interface as a LOW. The LOW is inverted by R (Figure 3-15, sheet 2, zone B6) and applied to pin 70 and 20 on the bus to condition the memory. These signals are used to set or reset the protect/ unprotect circuits on the addressed memory board. Apr; 1, i 9ij 3-73 88COb

3-35. PROGRAMMABLE READ ONLY MEMORY (PROM) CIRCUIT The PROM circuit on the Display/Control Card is used when one of the following operations is performed: Examine, Examine Next, Deposit, Deposit Next, Accumulator Display, Accumulator Load, Accumulator Input and Accumulator Output. Each of the functions requires a program operation that is stored in the PROM. Access to these programs is determined by the type of function to be performed. The PROM operation is similar for each function, therefore two funr- tions are discussed in detail. 3-36. PROM BLOCK DIAGRAM (Figure 3-13) The PROM circuit contains eight individual programs which are used in conjunction with the following switches: EXAMINE/EX NEXT, DEPOSIT/DEP NEXT, ACCUMULATOR DISPLAY/LOAD, and ACCUMULATOR INPUT/ OUTPUT. Activating any of these switches produces a specific binary number on the RA4, RA5, RA6, and RA7 lines (MSBs) from the Switches and Decoding circuit. At the same time the RA4 through RA7 data is generated, a RESET signal is applied to the 4-Bit Counter, conditioning the RA0, RA1, RA2, and RA3 outputs (LSBs) to zero. The RA0-RA7 signals are applied to the PROM, and they represent an 8-bit starting address location. There are eight different starting address locations which correspond to the eight different front panel switch settings (refer to Table 3-2). Any of the eight different starting address locations are always even because of the resetting of the 4-Bit Counter. The PROM circuit outputs a DATA OUT (RD0-RD7) signal, consisting of eight individual lines, to either the Control Latch or the non- inverting bus driver F. The DATA OUT is transferred to one of these two circuits by the status of the RA0 signal from the 4-Bit Counter. When the RA0 signal is LOW, representing a PROM even address, the Control Latch receives the data. The even addresses of the PROM contain data that is used to enable the Control Latch output lines (51-58). After the Control Latch receives the PROM data, a CLOCK signal increments the 4-Bit Counter to an odd PROM address location. During an odd PROM address cycle, the CPU will execute one machine cycle (assuming the S8 bit has been set in the Control Latch). If the cycle is a memory read cycle, an instruction 3-74 Aori 1. 19i7 880Cb

(0 ;Do 000--0, o~· t:T ~ SWITCHES RA7 PROM DATA OU AND 1---=':\"\"'--- --~ (RD~-RD7 DECODING ___--R-~~-----.-.._ r-- RA5 1---R-A-4 -----..- RA3 - RA2 RESET RAl RA~ 4-BIT .-----------t-----' COUNTER 1-------- ~ HALT CLOCJ< _ 1 - - - - - - -C-LOC W I - - - - _. . PSYNC - - - - - - - - - - - '-! U1 _--_._ FROM -- CPU Figure 3-13. PROM

FDI0 - FDI7 - - - e , - - - - TO INTERFACE ~ -.UT ADDRESS LATCH 7) CONTROL S5 LATCH '-' A8-A15 S4 -~ ----- --.. -~ ADDRESS S3 LATCH A0-A7 -Y>-- / A8-A15 ~.-~ A0-A7 S6 (DEP) TO 57 (FDIG2 ) INTERFACE -S8- -(SB-) - ._~CK _.__ ------------------- SS CONTROL FRDY TO CPU Block Diagram

TABLE 3-2. PROM Programs Front Panel PROM PROM Function Operations Address DATA Examine Set S5, S7, S8 160* I013* Jam Jump Instruction to CPU i 161 Set Sl, S7, S8 162 303 Jam A0-A7 switch data to CPU 163 203 Set S2, S7, S8 164 000 i Jam A8-A15 switch data to CPU 103 Cl ear control latch 165 ,i 000 Stop 166 ! 000 167 177 Examine Next 260 013 Set S5, S7, S8 261 000 Jam NOP instruction to CPU 262 000 Clear control latch 263 177 Stop Deposit 320 206 Set Sl, S6, S7 ,, 321 000 Put A0-A7 switch data and I 322 i4WRITE pulse on bus 323 000 Clear control latch I 177 Stop 340 I 341 013 Set S5, S7, 58 342 000 Jam Nap instruction to CPU i Deposit Next' 343 206 Set Sl, S6,S7 000 Put A0-A7 switch data and I MWRITE pulse on bus 344 000 Clear control latch 345 li7 Stop Display 060 013 Set 55, S7, 58 Accumulator 061 323 Output Instruction 062 013 Set 55, 57, 58 *A11 PROM address and data information is octal. Apr; 1, i 977 3-76 380Gb

TABLE 3-2. PROM Programs - Continued Front Panel PROM PROM Function Operations Address DATA 063* 377* Jam front panel address to CPU 064 065 001 Set S8 066 000 Data in accumulator is' 067 transferred to the 00-07 LEOs I I 013 Set S5, S7, S8 Jam jump instruction to CPU 070 I 303 Set S3, S7, S8 I 071 043 j 072 073 COO Jam A0-A7 latch data to CPU 074 075 023 Set S4, S7, S8 I 000 Jam A8-A15 latch data to CPU I 000 ,! Cl ear control 1atch J ! I I 177 Stop , Accumulator 220 I 013 Set S5, S7, S8 Deposit 221 333 Jam input instruction to CPU 222 013 Set S5, S7, S8 223 376 , Jam front panel address to CPU I 224 i i I 203 I Set Sl, 57, 58 225 000 Data in accumulator is trans ferred to CPU i Set S5, S7, S8 226 I 013 Jam jump instruction to CPU i Set S3, S7, S8 ; I 227 I 303 I ; I I 230 I I 043 231 000 Jam A0-A7 latch data to CPU 232 023 Set S4, S7, S8 233 000 Jam A8-Als latch data to CPU 234 000 Clear control latch 235 177 Stop Input from 300 013 Set SS, S7, S3 301 333 . Jam' input instruction to CPU externa1 de- 302· 103 Set S2, S7, S8 vice selected 303 000 Jam A8-Als switch data to CPU by ADDRESS switches AS-A1S *Al1 PROM address and data information is octal. ;'~r;i, i 977 3-77 880:Jb

TABLE 3-2. PROM Programs - Continued I Front Panel PROM PROM Function I Address DATA I Operati ons j I 304* 001* 5et 58 305 000 Data in accumulator is transferred to specific I/O device 306 013 5et 55, 57, 58 307 303 Jam jump instruction to CPU 310 043 5et 53, 57, S8 311 000 Jam A0-A7 latch data to CPU 312 023 5et 54,57,58 313 000 Jam A8-A15 latch data to CPU 314 000 Clear control latch 315 177 Stop Output from 240 013 5et 55, 57, 58 241 323 Jam output instruction to CPU externa 1 de- 242 103 Set 52, 57, S8 vice selected 243 000 Jam A8-A15 switch data to CPU by ADDRE5S 244 001 5et 58 switches A8- A15 245 000 Data is transferr~d from specific I/O devi~e to accumulator 246 013 5et 55, 57, 58 247 303 Jam jump instruction to CPU 250 043 Set 53, 57, 58 251 000 Jam A0-A7 latch data to CPU 252 023 5et 54, 57, 58 253 000 Jam A8-A1S latch data to CPU 254 000 Clear control latch 255 177 5top *All PROM address and data information is octal. 3-78 Acril,1977 88COb

byte is supplied to the CPU on the FDI0-FDI7 lines. The instruction data at the odd PROM address is transferred to the CPU through the Interface from five different sources. The source is determined by the output control lines 51 through 55 from the Control Latch. The 51 and 52 control lines enable the front panel switch data, A0 through A15, to the Interface. The 53 and 54 control lines enable the Address Latch data, A0.through A15, to the Interface. The 55 control line enables the DATA OUT (RD0-RD7) from the PROM to the Interface. The data present at the Interface is applied to the CPU by output control lines 57 and 58 from the Control Latch. The 57 cantrall ine all.ows the Interface to apply the instruction data to the CPU, and the S8 control line enables the FRDY signal. The FRDY signal allows the CPU to receive the instruction data and execute one machine cycle. After the completion of the machine cycle, the PSYNC and ST5TB signals from the CPU reset the S5 Control circuit. The 56 control line is enabled from the Control Latch to allow data to be deposited into memory. Upon the comple- tion of a PROM program, a HALT signal is generated by the PROM, disabling the CLOCK signal to the 4-Bit Counter. 3-37. EXAMINE OPERATION The examine operation allows the operator to examine a memory location by using the ADDRESS switches on the front panel. Refer to Table 3-2 during the explanation. The examine operation is activated when the EXAMINE/EXAMINE NEXT switch is momintarily positioned to EXAMINE. The EXAMINE circuit is located on the Display/Control card (Figure 3-16, sheet 2, zone 87). With the EXAMINE/EXAMINE NEXT switch momentarily positioned to EXAMINE,a LOW is generated at pin 6 of inverter Vl (zone 87) and a HIGH at the output of the remaining Vl and Zl inverters (zones B6 through 83). The LOW output is applied to pin 6 of gate Xl which gener,ates a HIGH to set Ll (zone 04). The RC-CLR (LOW) and AL-STB (HIGH) outputs April, 1977 3-79 8800b

from Ll reset a 4-bit binary counter to zero (sheet 2, zone A9) and strobes the current address data into data latches 81 and Tl (zone 86). The Ll latch is cleared by the C6 signal from the 24-bit binary counter (sheet 1, zone 03). The LOWs and HIGHs from the inverters are presented as RA7 through RA4 inputs to the PROM (sheet 1, zone 89). The RA0 through RA7 inputs to the PROM (zone 89) represent an address location (160S)' This location is the beginning of the examine program stored in the PROM. The data in address location 160S is presented on the ROO~ through R007 outputs (013S) and applied to data latch A (zone OS). After the 4-bit binary counter (zone B9) is LOW during the even addresses (RA0=0), and a control strobe (CS) to OS2 (zone CS) is generated, the data present at latch A is stored by the A output. The CS strobe is produced by the 24-bit counter outputs C6, C7, and CS (zone 03). When the C6, C7, and CS counter outputs are HIGH, NAND gate V (zone 05) is enabled LOW, and C5 (zone 06) is applied HIGH to the 052 input of data latch A (zone CS). With 052 and OSl enabled, the RD0 through R07 data (013S) ;s latched into A. The 013S data enables outputs S5, 57, and 5S (zone 07) HIGH. Output 55 ;s inverted LOW by Al (zone A6), enabling inverting bus drivers Rand S. Outputs S7 and SS are applied to pins 3 and 13 of NAND gates J (zone 06). With the PROM data stored in latch A and the associated circuits conditioned, NAND gate Z (zone A7) produces a clock pulse to INP A of the 4-bit counter (zone AS). When CS goes HIGH from the 24-bit counter (zone 03). the 4-bit counter, A output, goes HIGH which addresses PROM location 161 S' The data in address location 161 S is present on the RD0 through R07 outputs 303S' The 303S data is transferred to the Interface on the FOI0-FDI7 (zone C2) outputs through enabled inverting bus drivers Rand S (zone A6). The data is not stored in Latch A because the A output (zone 89) of the 4-bit counter is HIGH (odd address RA0=1), disabling the OSl input (zone C7). The A output is applied to pins 1 and 5 of NAND gates J (zone 06). 3-80 Apri1, 1977 3aOOb

The FDI0 through FOIl data presented to the Interface Card 3-81 (Figure 3-15, sheet 2, zone 08) represents a jump instruction to be ,- ...... stored in the CPU. The CPU cannot receive this instruction and execute it until the FDIG2 (zone D7) signal is LOW, and the CPU is released from the wait condition generated when the CPU was stopped. The following operation allows the CPU to receive the jump instruc- tion. When th~ C6, C7, and C8 outputs of the 24-bit counter on the Display/Control (Figure 3-16, sheet 1, zone D3) are HIGH, another CS signal (zone D6) is generated. The CS signal allows NAND gate J, pins 6 and 12, to produce 5B (zone D4) and FDIG2 (zone .C2) signals. The SB signal is applied to pin 13 of gate 01 (sheet 2, zone C8) as a LOW, producing a HIGH clock pulse to set Ml (zone C7). The Q output of M1 is app1i ed to pi n 13 of NOR gate PI and inverter .' Rl (zone D9), allowing the FRDY signal to release the CPU from its wait condition. The FDIG2 signal)s applied to pin 12 of NOR gate B (Figure 3-15, sheet 2, zone Cl) on the Interface as a LOW which enables NAND gate B, pin 6, LOW (POBIN is HIGH because the CPU is in a wait condition). The LOW enables the non-inverting drivers F (zone B7), allowing the PROM data (3038 ) to be applied to Mon the CPU through bi-directiona1 gates D and E on the CPU (Figure 3-14, zone C7). Because the READY line to M (zone A8) is HIGH, the CPU inputs the 3038 data which is interpreted by the CPU as a jump instruction. After the completion of the machine cycle, the =PSY~NC and 005 signals (sheet 2, zone 08) are inverted by R1 and applied to pins 11 and 10 of NAND gate Tl (zone 06). These signals and 58 (zone 08) enable Tl which generates a clear to MI (zone C7), halting the CPU. The CPU contains a jump instruction but no information as to where to jump. The remaining part of the examine operation allows the ADDRESS switch data to be read into the CPU from the front panel in order for the CPU to jump to that address. NAND gate Z (sheet 1, zone A7) produces another clock pulse to ,INP A of the 4-bit counter. When C8 goes HIGH and returns LOW (zone 03), the 4-bit counter increments to an even PROM address 1628. ,Apri 1. 1977 88COb

The data in address location 1628 is present on the R00 through R07 outputs (2038) and applied to data latch A (zone 08). The data present at latch A is stored by the LOW A output (zone 89) during even addresses (RA0=O) and the generation of the CS strobe (C6, C7, and C8 HIGH). The 2038 data enables outputs Sl, S7, and S8 (zone 07) HIGH. Output Sl is applied through inverters Y and W(zone C4) to the A0 through A7 switches (open switch HIGH, closed switch LOW), and the switch information is presented to the Interface as FOI0 through FOI7. Outputs S7 and S8 are applied to pins 3 and 13 of NAND gate J (zone 06) and are used to generate the FOIG2 and S8 siQna1s as described in the jump instruction transfer. With the data presented to the Interface Card and the associated circuits conditioned, NAND gate (zone A7) is enabled (C8 HIGH), producing a clock pulse to INP A, incrementing the 4-bit counter (zone A8) to address 1638, The data in address 1638 is not stored in latch A because it is an odd address. However, the A output (zone 89) is applied to pins 1 and 5 of NAND gates J (zone 06) as a HIGH, allowing the CS signal to produce the S8 and FOIG2 outputs. The S8 and FOIG2 signals allow the transfer of the first eight address data bits (address switches A0-A7) to the CPU, and the operation is identical to the jump instruction. After the CPU receives the eight address bits, the 4-bit binary counter is incremented to address 1648, The data in 1648 (01000110 - 1038) is stored in latch A (zone 07) because it is an even address. The 1038 data enables S2, S7, and S8 (zone 07) HIGH. Output S2 is applied to inverter Al (zone C6), gate Z (zone C5), and inverters Wand U (zone C4) to the A8 through A15 address switches. The switch information is presented to the Interface as FDI0 through FOI7. Outputs S7 and S8 condition NAND gates J (zone 06) and are used to generate S8 and FOIG2 during the next address. With the data present to the Interface and the associated circuits conditioned, NAND gate Z (zone A7) is enabled (C8 HIGH), producing a clock pulse to INP A, incrementing the 4-bit counter (zone A8) to address 1658 , Address 1658 operation is the same as address 1633, allowing the A8 through A15 address data to be stored in the CPU. After 3-82 April,1977 380Cb

the CPU receives the second byte of the address, it executes a jump to that address. Address 1668 clears the data latch A (zone 07) and allows the CPU to address memory (Figure 3-14, zone B9). The memory presents the addressed memory location data to the CPU via data input lines DI~ through 017 (zone Bl). The data is enabled through inverters Y, S, L, and J (zone B4) and non-inverters P, W(zone C3) to the Interface (Figure 3-15, sheet 1, zone Bl). The data is enabled through the G data latch (sheet 3, zone B4) to the Display/Control (Figure 3-16, sheet 3, zone 01) and displayed on the LEDs. The G latch (sheet 3, zone B4) is enabled because the RUN signal (zone A6) is HIGH, producing a HIGH at input MD of the data latch. While the memory data was being displayed, the 4-bit binary counter (Figure 3-16, sheet 1, zone A9) is incremented to address 1678, The data in 1678 (01111111 - 1778) is applied to NAND gate N (zone B7), producing a HIGH at gate Z (zone B8). The HIGH at gate Z disables NAND gate Z (zone A8), inhibiting any following clock pulses to the 4-bit binary counter, thus ending the examine operation. 3-38. ACCUMULATOR DISPLAY OPERATION 3-83 The accumulator (ACC) display operation allows the operator to monitor the contents of the CPU accumulator. Refer to Table 3-1, PROM Programs, during the explanation. The ACC display operation is activated when the ACC DISPLAY/ACe DEPOSIT switch is momentarily positioned to ACC DISPLAY. The ACC DISPLAY circuit is located on the Display/Control card (Figure 3-16, sheet 2, zone A5). With the ACe DISPLAY/ACC DEPOSIT switch momentarily positioned to ACC DISPLAY, a LOW is generated at pins 8 and 10 of inverter Vl (zone B5), and a HIGH is generated at the output of the remaining Vl and Zl inverters (zones B7 through B3). The LOW outputs are applied to pins 6 and 5 of gate Xl which generates a HIGH to set Ll (zone 04). The RC-CLR (LOW) and AL-STB (HIGH) outputs from Ll reset a 4-bit binary counter to all zeros (sheet 1, zone A9) and strobe the address in the P counter i~to data latches Bl and T (zone B6). The P counter address data is stored because the P counter incre- ments during the accumulator display operation. The original P ADril. 1377 SSCOtl

count is saved and restored in the CPU after the ACC display operation is complete. The Ll latch is cleared by the C6 signal from the 24-bit binary counter (sheet 1, zone 03). The LOW and HIGHs from the inverters are presented as RA7 through RA4 inputs to the PROM (sheet 1, zone 89). An ACC 05P signal (zone 03) is also applied LOW to the Interface (Figure 3-15, sheet 3, zone Al), producing a LOW to the MD input of data latch G (zone A4). The RA0 through RA7 inputs to the PROM (zone 89) represent an addr~ss location (0608), This location is the beginning of the ACC display program stored in the PROM. The data in address location 0608 is presented on the RD0 through R07 outputs (0138) and applied to data latch A (zone D8). The data present at latch A is stored by the LOW A output (zone 89) during the even addresses (RA0=O) and the generation of a control strobe (C5) to 052 (zone C8) . The CS strobe is produced by the 24-bit counter outputs C6, C7, and C8 (zone 03). When the C6, C7, and ca counter outputs are HIGH, NAND gate V (zone 05) is enabled LOW, the C5 (zone 06) is applied HIGH to the D52 input (zone C8). The RD0 through R07 data - (013a) is latched into A with D52 and 051 enabled. The 0138 data enables outputs 55, 57, and 58 (zone 07) HIGH. Output 55 is inverted LOW by A1 (zone A6), enabling inverting bus drivers Rand 5. Outputs 57 and 58 are applied to pins 3 and 13 of NAND gates J (zone 06). With the PROM data stored in latch A and the asso- ciated circuits conditioned, NAND gate Z (zone A7) is enabled, producing a clock pulse to IN? A of the 4-bit counter (zone A8). When C8 goes HIGH from the 24-bit counter (zone 03), the 4-bit counter A output goes HIGH which addresses PROM location 061 8, The data in address location 06'8 is present on the R00 through RD7 outputs (3238), The 323a data is transferred to the Interface on the FDI0-FOI7 (zone C2) outputs through enabled inverting bus drivers Rand 5 (zone A6). The data is not stored in latch A because the A output (zone B9) of the 4-bit counter is HIGH (odd address), disabling the OSl input (zone C7). The A output is applied to pins 1 and 5 of NAND gates J (zone 06). The FOI0 through FOI7 data presented to the Interface (Figure 3-15, sheet 2, zone 08) represents an output instruction to be 3-84 stored in the CPU. The CPU cannot receive this instruction and Af:ril, 1977 3S00b

execute it until the FOIG2 (zone 07) signal is LOW, and the CPU is released from the wait condition generated when the CPU was stopped. The following operation allows the CPU to receive the output instruction. When the C6, C7, and CS outputs of the 24-bit counter on the Display/Control (Figure 3-16, sheet 1, zone 03) are HIGH, another C5 signal (zone 06) is generated. The C5 signal allows NAND gate .J, pins 6 and 12, to produce a FDIG2 (zone C2) and 5B (zone 04) signal. The 5B signal is applied to pin 13 of gate 01 (sheet 2, zone CS) as a LOW which produces a HIGH clock pulse to set Ml (zone C7). The Q output of Ml is applied to gate Pl and inverter Rl (zone 09), allowing the FRDY signal to release the CPU from its wait condition. The FDIG2 signal is applied to pin 12 of gate 13 (Figure 3-15, sheet 2, zone C7) as a LOW which enables NAND gate B, pin 6, LOW. The LOW allows the PROM data (323S) to be applied to Mon the CPU through bi-directional gates 0 and E on the CPU (Figure 3-14, zone C7). Because the READY line to M (zone AS) is HIGH, the CPU inputs the 3238 data which is interpreted as an output instruction. After the completion of the machine cycle, the PSYNC and DOS signals (Figure 3-14, sheet 2, zone OS) are inverted by Rl and applied to sapins 11 and 10 of NAND gate T1 (zone 06). These signals and (zone OS) enable Tl which generates a clear to M1 (zone C7), halting the CPU. The CPU contains an output instruction but no information as to where to output data. The next part of the ACC display opera- tion allows the CPU to output data to the front panel data LEOs (00 through 07). NAND gate Z (sheet 1, zone A7) is enabled (CS HIGH), producing a clock pulse to INP A, incrementing 4-bit counter (zone AS) to address 062S' The data in address location 062S is present on the R00 through RD7 outputs (0138) and stored in data latch A (zone OS) in the same manner as address 060S' This insures that the 55, 57, and 58 outputs (zone 07) are enabled ,as in addre~s 0608' After the completion of this operation, NAND gate Z (zone A7) is enabled, producing a clock pulse to INP A, incrementing the 4-bit counter April. 1977 3-85 3800b

(zone AS) to address 063S. _. The data in address location 0638 is present on the R00 through R07 outputs (3778) which is the I/O channel number for the front panel. The 3778 data is transferred to the CPU in the same manner as the output instruction at address 061 8. The 3778 data allows the CPU to address the front panel and output the accumulator data to the 00 through 07 LEOs on the front panel. With the output instruction and front panel address number stored in the CPU, NAND gate Z (zone.B7) is enabled, producing a clock pulse to INP A, incrementing the 4-bit binary counter (zone AS) to address 0648. The data in address location 0648 is present to the R00 through RD7 outputs (OOlS) and stored in data latch A (zone OS). The 001 8 data enables output SS (zone 07) HIGH which is used during address 0658. After the data in address location 0648 is stored in data latch A, NAND gate Z (zone B7) is enabled, producing a clock pulse to INP A, incrementing the 4-bit binary counter (zone AS) to address 065S. Address 0658 enables the 58 signal (zone 04) as described in address 061 8. The CPU performs one machine cycle with 58 enabled. During the one machine cycle, the CPU outputs address 3778 on the A0 - A7 and A8 - A15 address lines to the bus (Figure 3-14, zone B9). The CPU also outputs accumulator data through bi-directional gates 0 and E (zone C7) and non-inverting bus drivers P and W (zone C3) to the data out (000-D07) bus. The address data (3778) enables NAND gates L on the Interface board (Figure 3-15, sheet 3, zone C6) LOW. The LOWs enable gate 0 (zone C4) HIGH which is applied through jumper JE/JF to pin 9 of NAND gate K (zone 84). During an output instruction, the SOUT and PWR signals (zone B6) are generated by the CPU which enables NAND gate K (zone B4) output LOW. The LOW is applied through jumper JD/JC and inverted HIGH by gate J (zone C3) and presented to the ST8 input (zone B4) of latch G. The data from the CPU is presented to the Interface (sheet 1, zone Cl) and stored in data latch G (sheet 3, zone B4) during the output instruction because the SiS and MO inputs are enabled. 3-86 ,lor; 1, 1977 3800b

The outputs of data latch G light the appropriate data LED (O~­ 3-87 07) on the Display/Control Panel (Figure 3-16, sheet 3, zone 02). After the machine cycle is complete, NAND gate Z (sheet 1, zone 87) is enabled, producing a clock pulse to INP A, incrementing the 4-bit binary counter to address 066S. The data (013S) in address location 066S is stored in data latch A (zone OS) and enables the 55, 57, and SS outputs (zone 07) HIGH. After the completion of this operation, NAND gate Z is enabled, and the 4-bit binary counter is incremented to address 0678. Address 067S contains a jump instruction (303S) which is stored in the CPU in the same manner as the previous instructions. The jump instruction will force the CPU back to the original P counter address which was stored in data latches 81 and T (zone 85) at the beginning of the ACC display operation. The remainder of the ACC display operation will transfer the address stored (A~-A7) in 81 and (AS-A15) in T to the CPU. After the jump instruction is stored in the CPU, the 4-bit binary counter is incremented to address 070S. The data in address location 070S is present on the RD~ through RD7 outputs (043S) and applied to data latch A (zone OS). The data present at latch A is stored by the A output of the 4-bit binary counter (zone 89) being LOW during even addresses and the generation of the CS strobe (C5, C7, and C8 HIGH). The 0438 data enables outputs 53, 57, and 58 (zone 07) HIGH. Output 53 is applied to the OS2 input of data latch 81 (zone C5), presenting the output data (A0-A7) to the Interface as FOI~ through FOI7. Outputs 57 and 58 are applied to pins 3 and 13 of NAND gate J (zone 06) and are used to generate the S8 and FOIG2 signals as described in the previous instruction transfers. With the data present to the Interface and the associated circuits conditioned, NAND gate Z (zone A7) is enabled, producing a clock pulse to INP A, incrementing the 4-bit counter (zone A8) to address 071 S. The data in address 071 8 is not stored in latch A because it is an odd address. However, the A output (zone 89) is applied to pins 1 and 5 of NAND gates J (zone 06) as a HIGH, enabling the CS signal to produce the SB and FoIG2 outputs. The 58 and FDIG2 signals allow the transfer of the first eight address data latch .l,pri 1, 1977 8800b

bits to the CPU, and the operation is identical to the previous ins tructi ons . After the CPU receives the eight address bits, the 4-bit binary counter increments to address 072S' The data in 072S (023S) is stored in latch A (zone 07) because it is an even address. The 023S data enables S4, S7, and SS (zone 07) HIGH. Output S4 is applied to the DS2 input of data latch T (zone A6), presenting the output data (AS-A15) to the Interface as FDI0 through FOI7. Outputs S7 and SS condition NAND gates J (zone 06) and are used to generate sa and FDIG2 during the next address (0738), With the data present to the Interface and the associated circuits conditioned, NAND gate Z (zone A7) is enabled (C8 HIGH), producing a clock pulse to INP A, incrementing the 4-bit counter (zone AS) to address 0738, Address 0738 operation is the same as address 07'8' allowing the A8 through A15 address data to be stored in the CPU. Address 0748 clears the data latch A (zone 07) and allows the CPU to jump to the original P counter address, conditioning the CPU for normal operation. After conditioning the CPU, the 4-bit binary counter (zone A9) is incremented to address 0758, The data in 0758 (177S) is applied to NAND gate N (zone 87), producing a HIGH at gate Z (zone B8). The HIGH at gate Z disables NAND gate Z (zone AS), inhibiting any following clock pulses to the 4-bit binary counter, thus ending the ACC display operation. 3-39. 8800b OPTIONS The 8S00b has several opti ons whi ch. may be selected by the operator. Two options may be used on the Display/Control card, and three options may be used on the Interface card. 3-40. DISPLAY/CONTROL CARD OPTIONS The Display/Control card options contain a choice of front panel slow operation clock frequencies and a choice of completing one instruction cycle or machine cycle in single step or slow operation. The normal slow operation clock frequency requires a 3-88 Aori 1, 19i7 880Cb

connection between jumpers JA and JD (Figure 3-16, sheet 1, zone 02). For slower operation, jumpers JB to JO or JC to JO may be connected. The normal single/step or slow operation requires a connection between jumpers JE and JF (sheet 2, zone 07) which allows the 8800b CPU to complete one instruction cycle before resuming a wait condition. However, if the operator wishes to execute one machine cycle after each single/step or slow operation, remove jumpers JE and JF which disables the DOS signal (zone 08). 3-41. INTERFACE CARD OPTIONS One Interface Card option allows the operator to monitor any data from an external device on the 00 through 07 front panel LEOs. Data may be monitored from an external device if jumpers JA and J8 are connected (Figure 3-15, sheet 3, zone C3). NAND gate K is enabled LOW when the 01, POBIN, and SINP signals (zone C6) are present during an external device to CPU data transfer. The LOW is presented through J8 and JA (zone C3) to gate J which produces a HIGH to the ST8 input of data latch G (zone 84). The HIGH on STS allows the data present on the OO~-007 line (zone B6) to be displayed on the 00-07 LEOs on the front panel. The remaining Interface card options pertain to jumpers JE and JF (zone C4) and jumpers JO and JC (zone C3). If jumpers JE and JF and JC and JD are connected, only data addressed to the front panel (3778) is displayed. If jumpers JE and JF are removed, ali output data from the CPU is displayed on the front panel. 3-42. 8800b POWER SUPPLIES 3-89 The 880Gb requires a positive 8 volt, 18 ampere supply, a positive 18 volt, 2 ampere supply, and a -18 voit, 2 ampere supply (Figure 3-17). When the ON/OFF switch on the front panel is positioned to ON, a 110 AC voltage is applied to transformer Tl. Two bridge rectifiers on the secondary of Tl produce the positive 8, 18, and negative 18 voltage supplies which are applied to the 880Gb circuits. The~positive ~nd negative'18 volt supplies are pre-regulated by the Ql and Q2 transistor circuits on the power supply board. Apr; 1. 1977 8aOOb

The 8800b printed circuit cards receive the supply voltages on the bus. Each printed circuit card contains its own voltage regulator circuits which produce the operating voltage for the particular printed circuit card. The CPU card (Figure 3-18) requires a regulated positive and negative 5 volt source and a regulated positive 12 volt source. These voltages are produced by VR1, VR2, and 02 circuits. The Interface card (Figure 3-19) requires a regulated positive 5 volt source which is produced by the VRl circuit. The Display/Control card (Figure 3-20) reauires an unregu- lated positive 8 volt source, a regulated positive 5 volt source, and a regulated negative 9 volt source. The regulated voltages are produced by the VRl and VR2 circuits. 3-90 April, 1977 eoCOb

Table 3-3. Bus Definitions PIN SYMBOL NAME FUNCTION NUMBER +8v +8 vol ts Unregulated voltage on bus, supplied to PC 1 boards and regulated to 5v. 2 +18v +18 volts Positive pre-regulated voltage. 3 XRDY EXTERNAL READY External ready input to CPU board's ready circuitry 4 VIa Vectored Interrupt Line #0 A second external ready line similar to XRDY 5 VIl Vectored Interrupt Allows the buffers for Line #1 the 8 status lines to be tri -stated 6 VI2 Vectored Interrupt Allows the buffers for Line #2 the 6 output command/ control lines to be tri- 7 VI3 Vectored Interrupt stated Line #3 Input to the memory pro- tect flip-flop on a given 8 VI4 Vectored Interrupt memory board Line #4 9 VIS Vectored Interrupt Line #5 10 VI6 Vectored Interrupt Li ne #6 11 VI7 Vectored Interrupt Line #7 12 *XRDY2 EXTERNAL READY #2 13 To be to defined 17 18 STAT DSB STATUS DISABLE 19 C/,J DSB COMMAND/CONTROL DISABLE 20 UNPROT UNPROTECT *New bus signal for 8800b. May, 1977 3-91 880Cb

PIN SYMBOL NAME FUNCTION '-' NUMBER 55 SINGLE STEP Indicates that the machine is in the process of per- -' 21 forming a single step (i.e. that SS flip-flop on D/C 22 ADD DSB ADDRESS DISABLE is set) Allows the buffers for 23 DO DBS DATA OUT DISABLE the 16 address lines to be tri-stated 24 ~2 PHASE 2 CLOCK Allows the buffers.for the 8 data output lines 25 ~1 PHASE 1 CLOCK to be tri-stated 26 PHLDA HOLD ACKNOWLEDGE Processor command/control output signal that appears 27 PWAIT WAIT in response to the HOLD signal; indicates that 28 PINTE INTERRUPT ENABLE the data and address bus will go to the high impe- 29 A5 Address Line #5 dance state and processor 30 A4 Address Line #4 will enter HOLD state after completion of the 3-92 current machine cycle Processor command/contro1 .. signal that appears in response to the READY signal going low; indi- cates processor will enter a series of .5 microsecond WAIT states until READY again goes high. Processor command/control output signal; indicates interrupts are enabled, as determined by the con- tents of the CPU internal interrupt flip-flop. When the flip-flop is set (Enable Interrupt instruc- tion), interrupts are accepted by the CPU; when it is reset (Disable Interrupt instruction), interrupts are inhibited. May. 1977 8aOOb

- PIN SYMBOL NAME FUNCTION NUMBER A3 Address Line #3 (MSB) 31 A15 Address Line #15 32 A12 Address Line #12 (LSB) 33 A9 Address Line #9 34 001 Data Out Li ne #1 (MSB) 35 000 Data Out Li ne #0 Status output signal that 36 Ala Address Line #10 indicates that the pro- 37 004 Data Out Li ne #4 cessor is in the fetch 38 DOS Data Out Li ne #5 cycle for the first byte 39 006 Data Out Li ne #6 of an instruction 40 DI2 Data In Line #2 Status output signal that 41 013 Data In Li ne #3 indicates the address bus 42 DI7 Data In Line #7 contains the address of 43 SMl MACHINE CYCLE 1 an output device and the 44 data bus will contain the output data when PWR is 45 SOUT OUTPUT active Status output signal that 46 SINP INPUT indicates the address bus contains the address of 47 SMEMR MEMORY READ an input device and the input data should be 48 SHLTA HALT placed on the data bus CLOCK CLOCK when PDBIN is active 49 Status output signal that indicates the data bus May, 1977 will be used to read mem- 8800b ory data Status output signal that acknowledges a HALT instruction Inverted output of the 02 CLOCK 3-93

PIN SYMBOL NAME FUNCTION NUMBER GND GROUND +8v +8 vol ts Unregulated input to 5 50 volt regulators 51 -18v -18 volts Negative pre-regulated voltage 52 SENSE SWITCH INPUT Indicates that an input data transfer from the 53 sense switches is to take place. This signal is 54 EXT CLR EXTERNAL CLEAR used by the Display/ 55 *RTC REAL TIME CLOCK Control logic to: a) Enable sense switch 56 *STSTB STATUS STROBE drivers 57 *DIGl DATA INPUT GATE #1 b) Enable the Display/ 3-94 *New bus signal for 8800b. Control board drivers Data Input (FDI~-FDI7) c) Disable the CPU board Data Input Drivers (DI~-DI7) Clear signal for I/O devices (front panel s~itch closure to ground) 60Hz signal used as timing reference by the Real Time Clock/Vectored Inter- rupt Board Output strobe signal sup- plied by the 8224 clock generator. Primary pur- pose is to strobe the 8212 status latch so that status is set up as soon in the machine cycle as possible. This signal is also used by Display/Control logic. Output signal from the Display/Control logic that determines which set of Data Input Drivers have control of the CPU board's bidirectional data bus. If DIGl ;s HIGH, the CPU drivers have control; if it is LOW the Display/ Control logic drivers have control. May, 1977 8S00b

PIN SYMBOL NAME FUNCTION NUMBER *FRDY FRONT PANEL READY Output signal from D/C logic that allows the 58 front panel to control the READY line to the CPU 59 TO BE to DEFINED Indicates that the data 67 present on the Data Out 68 MWRITE MEMORY WR ITE Bus is to be written into the memory location cur- 69 PS PROTECT STATUS rently on the address bus Indicates the status of 70 PROT PROTECT the memory protect flip- flop on the memory board 71 RUN RUN currently addressed Input to the memory pro- 72 PRDY PROCESSOR READY tect flip-flop on the 73 PINT INTERRUPT REQUEST memory board currently addressed 74 PHOLD HOLD Indicates that the STOP/ RUN flip-flop is Reset; *New bus signal for '88QOb. i.e. machine is in RUN mode May, 1977 Memory and I/O input to 8800b the CPU board wait cir- cuitry The processor recognizes an interrupt request on this line at the end of the current instruction or while halted. If the processor is in the HOLD state or the Interrupt Enable flip-flop is reset, it will not honor the request. Processor command/control input signal that requests the processor enter the HOLD state; allows an external device to gain control of address and data buses as soon as the processor has completed its use of these buses for the current machine cycle 3-95

PIN SYMBOL NAME FUNCTION NUMBER PRESET RESET Processor command/control 75 SYNC input; while activated, WRITE the content of the pro- gram counter is cleared DATA BUS IN and the insesttrutoctiaon reg- ister is Address Li ne #0 76 PSYNC Address Line #1 Processor command/control Address Line #2 . output; provides a signal 77 Address Li ne #6 to indicate the beginning Address Line #7 of each machine cycle Address Line #8 Address Li ne #13 Processor command/control Address Line #14 output; used for memory Address Line #11 write or I/O output con- Data Out Li ne #2 trol. Data on the data Data Out Li ne #3 bus is stable while the Data Out Li ne #7 Data In Line #4 PWR is active Data In Line #5 78 POBIN Data In Line #6 Processor command/control Data In Line #1 output; indicates to Data In Li ne #0 external circuits that INTERRUPT ACKNOWLEDGE the data bus is in the input mode 79 AO (LSB) 80 Al 81 (LSB) 82 A2 83 Status output signal; 84 A6 acknowledges signal for 85 INTERRUPT request 86 A7 87 May, 1977 88 A8 8800b 89 90 A13 91 A14 92 All 93 002 94 95 003 96 007 3-96 DI4 , DIS OI6 OIl DIO SINTA

PIN SYMBOL NAME FUNCTION NUMBER SWO WRITE OUT Status output signal; indicates that the oper- 97 ation in the current machine cycle will be a 98 SSTACK STACK WRITE memory or output function Status output signal indicates that the address bus holds the pushdown stack address from the Stack Pointer 99 POC POWER-ON CLEAR 100 GND GROUND May. 1977 3-97/(3-98 blank) 8800b

9 8 76 Ii vee R2. R21 R24 R4D R38 R,7 2.21< 2.2K 2.21< 3.31< 470A 470SL 2 GI PiNT \"'J 4~ PHOLD '\" ~. CIC DISABLE ~4 V ~ 2~' 12~1I ~ PWR V1!L 6'\" 7 POBIH PWAIT ~9 ikL PSYNC I 14~ 13 PHlOA I V<l'i. PINTE .....1 - - - - - - - ~INTE 1:Jl....~ .....H - - - - - - - - ~IHLDA 00 ho c. ~,~Il!lO-_l----_1_+-I-++_+_H , ,--_ _-,'~9 SYNC 0.1 9 '-', DeJ DIIlI\"L.-+-----+_+_H-I-+~ ' - - - - - - ' 29 WAIT 0.\" 8 'L-' 00.'2 0. 0.21!'6'---I-----l-l-4--I-H D'1'7-1---+-L~~D' 0..1=---1------1-+++-+ '-- -'-'7'-1 08IN ~ ' - ---\"'8,WR DO'[rj''-t-_t___~,~2~DO DO,,..,. ·l-.--I------f-HH_++++-------' '-- --\"\"'31 HOLD D~p°_+-_+....,~D. DO~-_+----_t++-f--I-H-+-------' L _ _-,-- !..:'4'l'NT 0.6 ~ '-'i 0.6 E D6PJIOL-+------f-HH_++++--------- 0.7 ~L~J,j---D-71-!f'6-'-H--+H----+--+++-H+H-_-+-++-+------------ - r2! A0 9~A{f M ----:=========~=t=t+tt=l=j=::;_--------7 Al ~ A2 7lJ\"'\" ' 2 A' ~ 81 A' ~XTAL A4 ~ A' 31 -~ 29 !3\"J ~A2 S1S8 '--+---------- ' -_ _-I- 111)'112 I 2 A3 01 r2-2--Ir--~_'4\" 01 02r15---IH-t9' e2 F ~L7.\" '----I----------- 1~~A4 91~1 I RESETII1\"2 '---IH-t...,' RESET 31 AS L----+---------.,.- f- A6 ~ ~A6 ...-HH-'O,READl' '-------1f-------~+-+-+-+-- A7 ~ A8 • .-14 I • A7 L- c.-! e2TTL R9 8. A9 ~~A8 RESlNIV2L---._..1.5\",K~.VCC \"J ~ i- A'O • .-,;12 ' .. A9 L....::RVDl\"\",•r•.,,\"N....J RID rlCOi~LJiR~D7~ il ~ .... AII ~ ~ ..l.+-C-2~\"\"0'--\"-1~8<E89 0 ~ AI2 W~..3-;\":lt4 7~ AIO 6 G 15 All ~ ~ AI' I '\" ~22UF6 L-----,--,l-,--e+R-,-4. \"L5-:i:iT:'--;D A'4 ~ AI5 ~~AI2 vete_-.----j~--,~~L ~0+-I-~60 7 85 9....p110 I> '\" AI' AA I- W'-J ~A'4 \" 13 7 ~ 7.-,;16 I • A'5 , ,6 10. 8. 8 .. 2'2KvceL ~ I~ I:i 1 ~ ,o.~ READY JJ CI R4 R5 R6 RT 23[ ~.2K2.2K 2.2K &.7 9 2.2K vee 13 II ~ ... AiiODS\"BL R4' -=- • ,0. 12 '\\- :~ 2.2K I.~_~ 'ir~.\"1~\"'1.J· . 9 z in mrn 8800 B 5 8800b

i 43 2 i'HPOIt1Nf<T~7~4 ceOSBl ~ , - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ' - - ' ' ' ' ? > 1PW1ll 7i- POBIN .... ~ ,- -'::=:-'~~Te7~.1~ ~ r - - -R\"2.2K vee PHLDA ~ PINTE L.:..: 12 ~13 'iiO\"OsBi. ... 23 ,----------- -\"\". P ,. Doe, ~ ll- - - - - - - -r-r-r----------------------~-~-:-:_4=1:2I.>~...=.:~I=TI'5=-'1_-_\"'9ll2It~;o-OI9~I DOl, ~ ---------' rr~-----------\"'-l14t;o- ~____________ ......6I'\"\"!.t;7 _ 0.02,,;;& -=~\"-'--==f___\"'i0 ~ DO,,~ . . . - - - - - - - - - ,- 13 I%.- -J=,;:(i=13=,--2'l\"\" • 0.04, ~ ,...----------' ~ DO~'\";g 0.06 ':00 0.07 19(, L.:: .--~---..---..--~--_<p_--~--r-___,-----.---;~vee ..o R'O :i: -' 2.2)( ---'------' -'2~'i• •2 ClQCi(.... ~ 12 vl!l~.----+--+--+---f---+_--I__--t--_+--O~le .~......- \"1' - - . - - t - - t~f+--+l--Jt-\"-'f~-'<-'-.--.(\"Io=~s•.-..;:1'06 \"~\"J~2 0.1' 90 \"J 0.12 __ .. --tj-~tt--Jt--f+---_tt-7~-,'.A--;-:rj.,•\"S~.AL '2 '.~.:I.JI 8 ~9 0.1' __ ~~-~:;; 10 8 '.~.:.9J - *-j-F9:::...<t=-L-,-D+-~-\"''5\"1.3.--J'1-'oo\"~\"'.J 0D.I14~ \"l 0.16 I J}'f' 1I--J112 \"\"'J In ~11 0.17 ... J 22 2D ,., ,-----+-,'~~ R20 '-- ~D6~D~5~D';0~D~•.,D2~~D(~DO;;------_;_D;;~S:;~2~!L-\"L-~2J.2~K_CC~: ~j~ :~: ~~~ ~;~ ~.~~ ~~6K ~.;7K Di'6_..,D;;:;5\"--,;;Dr:_-;D;:;.\"---;;D:r2_~Dr_' _ri,~D5:ff2~~D, ~VCC,--___,....... \"': -6+-I-i-~81--1-'fi'°-f---~2_\"I-I_I_~'9-+-1_1_~'-'7+_1-1-~:-f---:t '[.00-.1\"'_},t~ ~6_v_e_er-;12~i 2~04~I:Or~_6-~- -{~'It~4150 S 6 0 J' ~l!!I bl5~12X 15 4 12R 15 lOX 1 6X I X 15 2X I \\ 2N!410 +C4 RI4 1I 9 7 I II 3 ~~~.n. +- ~_~-1-0-U-F--'2.2K ~ . [!] I!J I 3 Figure 3-14. CPU Schematic z 4 2I n 3-99/(3-100 blank) II n BUS 5I

2 TO OISPLAY/CONTROL .... ..~ .. .. u, u, u A , '\" '\" '\" 1NltD I LIN , L_ • . . . . ... .. .... .....,c, I~ ~ .'\". .'\". ..... 'c\" '\", , OJ , OJ I I '\" '\" '\" '\" '\" '\" '\" '\" I:I~ I~ I~ I~ I~ I~ I~ B .. -., ... o.. . ..coo o'\" ... ... 'o\" o o o o oo ooooo sna ooaa ------ 8800b

3 4 56 TO OISPLAY/CONTROL .. .. .. . .... . ..•... ... •... •..,. •'\" •'\" •'\", '\", C C • , ., ., ., • C • •, • .. . . .. . '\" '\" '\" '\" '\" '\" '\" '\" '\" '\" '\" '\" '\" '\" '\" \"'~ . .,u u u u u . 1--1~-1--it--l--it__l,.A_t . A_! _t. :k-*--A--~:\" '\" '\" '\" '\" -I.... . to lID • • 0 _ IL - L JQ Q. til Q. Jl') Ill. JQ Q.l 1ft If) .. ,. I \" '''I I ' .\"./ ( \\- -\"/-1\\ -\"-/ ( \\. -\"-/1 \\ .\"-'I [ \\- -'\"-11\\~I 1(\\ • I 1. .J ~- .. .. I; I; \\; I; \\;'\" c •- •• I: I; I~ I~ I: I:: r: I~ I: I: I~ ... fij- .....-,'\" t- ., ... 0: .. . . .. .. .0:0: .. 0 ... ... ., ... - ., o o . ... .. ... ..~ ~... > ~ o~ J: J: J: \"'\", .. - -.-..'- '\" '\" '\" '-------; . .. ..... . .... .c• ., ... c- • '\" ... •'\" 'c\" c c '\" • c c• I , /\\ /\\ I\" I I I\" I\" S n a 009 a - - - - - - - - - - - -_ _.11 Figure 3-15. Interface Schematic (sheet 1 of 3) 3-101/(3-102 blank)

9 3-A6 - 3·86 3-C6 .,RUN 3·88 3·86 PWR 3-C6 3 - 8I S INP SO'UT POiTN S'S'Wi \"\"> • .. • =\" ,. P-3-, ... ~ .N. ~...~ II OS ~l,~ OS ~ ,OS ~,,D.0 SI ~....... I OS OS ~ TO CPU ~I .6.... 103 . .. .... .- •z OS , OS ~ 102 0 \" I- l- I- I- -' :> %0 OS ~I ,~'DI . . . ... . .'\" IE \"•'\"0l- .i 0z z I\\ ~IDfli CI :> ~-'~.1 OS \\ I \\ I\\ I\\ I \\ I L..... 8800b

I-- .-on .. .. \".. N \"N . I- .. . C NO N , I- ~II :>;l .o-~II~\" .. ...- = = \".. N '\" oJ \"\"> . . . .. I~ .. .... I~\" ..\" •• ....'\".. I- CI ... . I~..z .. z -' \"Z l- :> o ;; % ;; N i: '\" .'.\". ~ I~ z IE IE I~ ~ ;;: \" \\11 I, \\I \\\\\\ \\I \\ \\I ~1~L:J_:_-'-_:_J:::-I...:J-, 8800 8U S .....J Figure 3-15. Interface Schematic (sheet 2 of 3) 3-103/(3-104 blank)

6 -&1 74LS04 4 - - -P OBIN 2-09 !5 6 II) 2-C9 C C II A7 I 7420 74LS04 1- A3A6 All 2 74LS20 OR 74LSI3 -I - A 3 A4 6 L '\\ 1- A3 IS ~ c I - A3 4 7420 OR 74LS02 8 7400 -- 10 12 1- A3 A3 13 7420 A2 74LS20 OR 9] 0 J -131 J 12 ! 74LSI3 JE ~ RIS I - A3 AI 10 L '- 8 JF 2.2K 1- A3 ....-/ A0 9 7410 OR I - A3 -- 74LS04 9_ SIN P 3C4 K SOUT 9 - - I2-C9 B 2-C9 C 2-09 PWR 1- A2 -- 22 007 006 20 - -B 1- A2 18 DOS 1- A2 I· A 2 - -004 16 I- AI -- 1- A I 9 D 03 7 -- 002 I- AI -- 5 001 I- AI -- 3 DOli ~ -- CL -OS A J 2-D9 -- 7 4L S 0 4 7402 OR 74 I2 12_ RUN C 9~0 174LS04'\" --- 8800b

3 2 POWER CONNECTIONS 174104OR 74LSI0 OTY TYPE VCC GNO OTHER I ,6 ~JB 7400 JA I OR 14 7 -!51 K f R4 74LSOO 2.2K OR 74LSOO 7402 7 VCC I OR 14 7 II 9~0 OR 74LSOO 74LS02 f ~. 7404 1 OR 14 74LS04 7410 I OR 14 7 74LSI0 VCC I 7 4L S 13 14 7 74LSI0 I 74LSI4 14 7 _ -JO JC I 7420 14 7 'f- 8 I 8212 24 12 SS WI 2-C9 II -- ... P--I., S TB LD7 ,'.!.\".\" ,>, ~3--A2 21 L06 19 I'/1'2 ',,'' ~ 3 -A2 17 LDll I i:D4 I :7::, :~3-A2 II - -LD3 15 I 9I 10 i:'i52 '::::~3-A2 TO 8 LOi I, Lilii DISPLAY G ,>~3-A21 10 I CONTROL 8212 AC\"C -OSP I 8, ,'~,! \"\"I 3- AI 6 , ...5 I /~3-AI II 4 'I'''6'''~' -~ - L._.I LR ... P2 ~ FROM SI MO /18>-2-030ISPLAY J2 CONTROL 4LS 02 OS2 13 13 R3 VCC 2.2K 'y Figure 3-15. Interface Schematic (sheet 3 of 3) 3-105/(3-106 blank)





,.. '\" o POe !!! ~VCC 1- A. 6! 2.2 VCC 7400 OR 74LSOO ...-l.. II CI NI R.1 I121o. -Q ~I01 12 14'367 K 15 O. -Q1'4 .... . • ~14~~\" SINGLE STEP SLOW R.' --tlt-I,III- ,1i'i.. I-D3 2K --+--l-----------+++-+---+::C:'::.:\" 1- DI T 4 L 5 17 5 L R•• . .+-.1III1V' -1!--:<l4 01 Q 5 74 L S 17 5410 .flo 6 1405 • 01 Q 7 G I 6 .....hv-..,.. -l-...:·:(,I 0 2 Q' 4 D,2 0 2 I VDC>-2_ _-II-~ R5. UI 2K I.12 D3Q 10 v~.c,>o_!.!12:.---I_+.:;------ .....;;~~ FI r ~--~ - - - - - - _ .. , •.....+-MM....-I~I~. D3Q- '4 *.OCO~JJ;r : :RPI ...-hMIV'....-I~I!dt 04 Q tI - I 14,7K i.R26 9 CK 13 04 Q 15 'VI .. L ---- ---- ............ RA4 I_I' C 7405 I • CK RAG 1·1. RA' 74LSl75 C RA7 I· I. I ...-hMN- -I-<..:l 01 Q S 1-8 • 74LS175 • 1430 OR co 74LS30 OR 5 01 Q 4 74L3Q R71 ~VCC +-h\"\"'N- -t--=q' D 2 Q' 4 D2 Q 2 4 YI RU HI I I S R87 12 03 0 10 2K 0\"IK •,8 o. L!J::VCC I\"D AC·ST~ I .... LI R27KO _ 14 ijblC S 7 RC-CC,\\ I· A. Q C 3! - II Ci Q I -D • 10 IS .C... P2 III ~'.AI'\"r\"\" .. <AI A-C-C -DS,P I I I L---~~----------------=~P;R~E~S~E~T0:1~~l2-DI ~• DI 0 7 ..I... 0\"1 --====-----------------=~~~~J:O~21740' Iw __ .. 01 ~ ~ ~1.D'f'ii\"'f\"\"C\"Lii, I 7US'\" :-t V> R2eKo 4 01 ii I P-R-OT-EC-T ;0 I2D2.• .0.. ~ I I UNPRDTECT ,:.7.~,I.DI ... ~ H-.NoIor-+---r-<5 ll D2 Q' .. D2 Qb\"\"--- . '- R62 o(\"\") OK .::.>.. 81 .(.3... 064 V> ~ O l 01 14 1 WI POWER CONNECTION' :n:r I T I I~ 1' 2 1D' lib lO ----;-r~--;;-~O l-14 1- 7 I UN PROT III I I 7404 I 14 1 7 ~D4 IS I\" I 2 1 7405 1 14 I 1 .~... 2 1 1410 1 14 I 1 ~. 74367 I 1 74 10 I 14 I 1 <AI n 1 I 1 TUS 741 14 I 7 1.01-- ... _13- • 174C81751 II 1 • ..I... ....... I I IT6T I II I I ....o :V:>r <0 III III .'...-... <AI 115 104 0\"14 ..!....... N rt+Jj I m o .o.... 14LS04 - S <AI 15~ :',:\".>.. ~ .......

~ co (') c ! 4_C2 ..IUNREG)+8V .. 1- A 6 I-I e 1- A 6 CD .. CD 1- C 6 . ..- \" . ...... -< ~\" .... . ....~ :: t't .\" ~ :0 .. .- . < \"0z o co 0 !I: ,- C .. .., \"\" .z.. oz \".. .,z...,. • o ;; :0 .. Z .\" );> ..%.. .. ,.,(') STATUS 3! .. <0 c: ~ (1) W I ~ 0'1 o . ~. ....V> \"C ~....... no ::> M- .o~... Vl =nr (1) al W :r. I n ~ ....... ~ .:....~........... V=>r w n> (1) ..... M- 7407 NW (36 DRIVERS) .0...-. o..... ,..l::»:s w ~

TI TB2 [:,,::,:<,-,---'(29) RED (IS) BlK ~4~ ~ (lSI 031 I ,, ,,(IT) 1--<3 '(25) R/BlK , ,,, r---T1--<~ 8 :( 301 Bl UE 8lK ,3 ( 3 7) , ,(l8) 8lK ,2 '( 2 SIB / B l K ,~, ( 391 '(311 GRoEN r- - -., ,,, I '(27) G/8lK (I9) BlK ' I I P5 I FUSE (~;l}~~) :( 2B) W / B l K 3A S lO 9, S W-I • ''\"\" I, TBI :-<5~: (20) r - .. :_ _-_ _<_6_ _~_ _:J YELLOW I !5 I '\" L_I- -{ FAN ,(221 GRN YELl GRN 7 L _ _-, .1 ,._--!!W~H!..!T~--I (41) I YE~~}OW': S I L:_~ 110 V AC ~ /I GREEN a GRN./BlK. TO PIN I /I BLACK a WHT./BlK. TO PIN 2 110 V /1 B l U E a B l U E I B l K. TO PIN I 1/ BLACK a WHT.lBlK'. TO PIN 2 130 V /1 RE 0 a REO/BlK. TO PIN I /I BLACK a WH T./ B l K. TO PIN 2 8800b

AC (14) r - - _ ... - - - - - - --- - - - - - - - ., TBI + I I ,-, ):)- ' - - - ' - '< ) ( 10) (2 4) ,,,<,:'>-_:..:(2=-4.:.:}:......--\"4~)-'- __....:;.(3:.B::.:.l------il~.. + BV C5 CS ...J...C7 40000l/F 400001/F..,... 950001/F: ilOPTION,IF, , USED OMIT' IC5aCS) ,B (40) ,(12) (II) ,( 2 3 1 , (23) L:~ L. ... ...... .J AC lI2 ) + + IBV -= ~ BlK (IS) ,rT4B-2,', BlK (17) , 3, IN I WHT./ BlK. BlK (lBl (15) IN 2 GREEN BlK (19) I ) ~ AC BROGE ~ AC BROGE JUMP 2I (131 BLACK II GREEN/BlK. ,I , 220 V ,I , IN I WHT./ BlK. ) IN 2 BLUE L: _ ~ JUMP AMPS TB2 BLACK a BLUE/ BlK. 0-4 pin 2 4- 9 pin 3 260 V 9 - 18 pin4 IN I WHT.! BlK, IN 2 RED JUMP BLACK a RED/BLACK Figure 3-17. Power Supply Board Schematic 3-113/(3-114 blank)

R2 fil >+8V (UNREG) L3 --PY\"L I Ice =.li.... ~ C6 I.\\..0.. 3 !lUF ...... T· 1UF GJ »..;....:.:18~V'-- L4 ~ _ 135uF '--- lclO T·IUF § >50, GRD fYL'6Tl 100 >-=-==----' L ~>-18V L!l R34 (YVV) ,.......,. 1°,rICI3 3 !l REF OESIG TYPE VCC GRD OTHER REF OESIG TYPE VCC GRD OTH 20 M 80eOA 2 16 G,B 74LS04 14 7 J,X,R,V, 74368 8 7 OR 24 C 74LS13 7 N,U,P 8T98 16 12 .. OR 14 16 8 74LS20 8 K 8212 I 8 VDD- 9 8 VOO -16 S,Y 74LSI4 14 D,E 8216 P,W 74367 16 F 8224 A 4009 Figure 3-18. CPU Voltage

( 22 ~----._--.,. >-------t.~VCC(+5V REG) ..J.:!:CI ..L SC 35UF IUF -r - - - r - - - - - - - - - -••VDD (+ 12V REG) l . C3 -r--'\" ..Lsc r· IUF I'UF . -:-:,L , .VBB (-5V REG) ICII ICI2 I I.lUF ]~35UF ...L. SC HER T.IUF :-i 9 6 e Regulator Schematic

(Xl :P 0 'CO-C 0 ...· D\" -0 > - -r~:-r:-:l ~I 18011 ... 8 V VRI =C2 (UNREG) 3 .111 f + ~ CI 311JJf L3 W I --' --' -.'..-...-J.... W I --' . --' 'CO tT --' :~:s Figure 3-19. Interface \".........

( tL ':! , ) +5V REG (VCC) + C4 I =C3 .lllf 311JJf : SUPPRESSO R .J..C AP'S T.lllf I (22 PLACES) I I 1 Voltage Regulator Schematic