DE_MF

NETTUR TECHNICAL TRAINING FOUNDATION MASTER FILE FOR DIGITAL ELECTRONICS (Common for CP 04 & CP 15) SEMESTER III SUBJECT CODE: CP COM 03 02Prepared by: Ms. Arya S BabuRevn.2015 : Mr.K Ranganath, TTCRevn.2017 : Mr. Pattabiraman, JNTCApproved By: Mr. Ayyappan.R, Course Coordinator, CP15Rev.No. 7 Released -June 2017NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 1

SUBJECT CODE CP COM 03 02 DIGITAL ELECTRONICSSUBJECT NAME 80 HOURS PER 7 SEMESTER 20.06.2017 REVISION NO REVISION DATE1.0 COURSE OBJECTIVES At the end of the semester, students would be able to: 1.0 To understand the difference between analog and digital system 1.1 To familiarize with the number systems and codes. 1.2 To understand the function of various logic gates. 1.3 To develop the basic gates using universal Gates. 1.4 To familiarize with logic circuit design using Boolean algebra & K Map 1.5 To familiarize various flip-flops using logic gates 1.6 To familiarize with various logic families & Data converters 1.7 To understand the working of different types of counters and familiarize with relevant ICs. 1.8 To understand the working of shift register and familiarize with relevant ICs 1.9 To understand timing circuits 1.10 To understand various Semiconductor Memories. 1.11 To understand various display devices and PAL system.NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 2

2.0 TOPICS: Sl.NO TOPIC TIME ALLOTTED 1 Introduction 2 Number Systems and Codes 2H 3 5H 4 Logic gates 6H 5 Boolean algebra & Karnaugh maps 6H 6 9H 7 Combinational logic circuits 8H 8 Latches & Flip flops 5H 9 18H 10 Timers & Timing circuits 11H 11 Sequential logic circuits 2H 12 2H Data Converters 6H Integrated logic families 80 Hrs. Semi-Conductor Memories Display Devices & Drivers TOTAL3.0 SUBJECT CONTENT :SL.NO TOPICS TIME Unit 1 ALLOCATED 1 INTRODUCTION Introduction to digital system & Difference between analog & digital 2Hrs. 1.1 systems 1Hr 1.2 Logic Levels and Pulse waveforms 1Hr 1.3 Importance of digital circuits Unit 2 5Hrs 2 NUMBER SYSTEMS & CODES 1 Hr 2.1 1 Hr 2.2 Decimal, Binary, Octal & Hexa decimal Number Systems 1 Hr 2.3 9‘s & 10‘s Complements – 1‘s & 2‘s Complements Conversion of Number systems 1 Hr 2.4 BCD Code - Digital Codes - Gray, Excess 3, Alphanumeric Codes, 1 Hr ASCII, EBCDIC Codes 2.5 Page 3 Perform Arithmetic operations on all basic number systems(addition &NTTF subtraction) DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017

Unit 3 6Hrs 3 LOGIC GATES 2 Hrs Logic Gates-symbol, function, expression, truth table, IC no's of Inverter, 1Hr3.1 AND, OR, NAND, NOR, EX-OR, EX-NOR gate 1Hr3.2 Universal Property of NAND & NOR 1Hr3.3 Gate Propagation Delay Time & Power Dissipation 1Hr3.4 Noise Immunity & Fan In & Fan Out3.5 Loading Considerations & Applications. 6Hrs 1Hr Unit 4 2Hr 1Hr 4 BOOLEAN ALGEBRA & KARNAUGH MAPS4.1 Boolean Operations 2Hr4.2 Logic Expressions4.3 Rules and Laws of Boolean Algebra 9Hrs4.4 De Morgan's Theorem 1Hr 1Hr Simplifications of Boolean Expressions-- Karnaugh Map of 2Varible,4.5 3 Variable & 4 Variable 1Hr Unit 5 1Hr 5 COMBINATIONAL LOGIC CIRCUITS 2Hr5.1 What is combinational logic, AND - OR Logic, AOI Logic, XOR Logic 2Hr5.2 Half and Full Adders, Applications 1Hr Explain the Concept, comparison and Applications of Serial adders & 8Hrs5.3 Parallel adders 1Hr 2Hr Explain the Concept of Magnitude Comparators (1 bit, 2 Bit & 4 Bit 1Hr5.4 comparator) 2Hr5.5 Explain the Concept of Decoder, Encoder & code conversion circuits5.6 Multiplexers (2:1 &4:1)and De multiplexers(1:2 & 1:4),Concept of N:1 1 Hr5.7 Parity Generators and Checkers –Even & odd Parity 1Hr Unit 6 5Hrs 6 LATCHES & FLIP FLOPS 1Hr6.1 Sequential Circuits clock & explain the types of triggering & Latches 1Hr6.2 Different Types of Latches- D & R-S Operation 1Hr6.3 Flip Flops – Different Types of Flip Flops 1Hr6.4 Operation of R-S, D, J-K& T Flip flop 1Hr Positive & Negative edge triggered Flip flop & Importance of6.5 synchronous and asynchronous signals, Preset and clear signals6.6 Operating Characteristics & Applications of Flip Flops Unit 7 7 TIMERS & TIMING CIRCUITS7.1 Introduction of 555 Timer - Block Diagram7.2 Multivibrators – One Shot7.3 Astable Multivibrators7.4 Modes of Operation7.5 IC Mono shots & Application of Timing CircuitsNTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 4

Unit 88 SEQUENTIAL LOGIC CIRCUITS 18 Hrs 2Hrs8.1 Introduction to Counters& Modulus of a counter 2Hrs Asynchronous Counters - 2 bit & 4 bit & J-K flip flop as divide by 28.2 counter 2 Hrs 1Hr 4- Bit binary counter using IC 7493/IC 74293 & Decade counters 1Hr8.3 using IC 7490/IC 74290 2Hrs 2Hrs8.4 MOD-N counters using flip flop 1Hr 1Hr8.5 4-bit Synchronous counters - using flip flop 2Hrs8.6 Synchronous counters using IC 74161 Up/Down Counters – Synchronous & asynchronous using flip flop and 1Hr8.7 74193 1Hr8.8 Counter Design & Explain the data sheet of 7492, 74190, 74192 11Hrs 1Hr8.9 Applications of counters 1Hr8.1 Register Concept- Types of Registers - SISO, SIPO, PISO, PIPO and 2Hrs8.11 application8.12 Bidirectional Shift Registers ,Data sheets of 7491,74198 and 74199 IC‘s 1Hr Introduction to IC Shift Registers – 74164, 74165, 7495, 74194 1Hr Shift Register Counters-Ring Counter , Johnson Counter with timing 1Hr 2Hrs8.13 diagrams & application 2Hrs Unit 9 2Hrs9 DATA CONVERTERS 1 Hr 2 Hrs9.1 Introduction to DAC ,its symbol & Applications of DAC 2Hrs Explain the performance parameters of DAC-Resolution, accuracy and9.2 conversion time 1Hr9.3 Explain binary weighted resistor DAC & R-2R Ladder type DAC 1Hr Explain IC-1408/832 DAC with pin configuration , Data sheet of IC Page 59.4 0808/08099.5 Introduction - Logic symbol - A/D Conversion & Applications of ADC's Performance parameters - Resolution, Quantization errors, Conversion9.6 time9.7 Types of ADC -- Ramp type (single slope) & Dual slope - A/D Converter9.8 Types of ADC --Successive approximation type ADC& Flash Type ADC Unit 1010 INTEGRATED LOGIC FAMILIES10.1 Introduction to Logic Families10.2 TTL Logic - CMOS Logic10.3 TTL driving CMOS -CMOS driving TTL - ECL Circuits-I2 L Circuits Unit 1111 SEMI CONDUCTOR MEMORIES11.1 Types of Semiconductor memories- Static & dynamic Explain the terms –Access time, speed, reliability , Power11.2 conception and capacity of RAM & ROM(IC‘s) Explain different types of ROM & RAM- PROM,EPROM, EEPROM,11.3 Flash ROM, NVRAM,DRAM-DDR,SDRAM,RDRAMNTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017

Unit 12 12 DISPLAY DEVICES & DRIVERS 6Hrs12.1 Operation of LED and concept of seven segment display12.2 Alpha numeric, matrix display & multiplexed displays 1Hr LCD, its types, Advantages & disadvantages-- dynamic scattering type 1 Hr12.3 and field effect type 2Hrs Explain LED driver-- LED driver using IC 7447 decoder & LCD 1Hr 12.4 Driver -- Seven segment decoder/driver for LCD display 1Hr 12.5 Introduction to PAL - Explain the basic structure and working of PAL 12.6 Implement Full adder using PAL REFERENCE BOOKS:1. Digital Fundamentals - Thomas .L. Floyd2. Digital Fundamentals - Floyd and Jain3. Digital Circuit and Logic Design - Samuel C. Lee4. Digital Fundamentals - Malvino & LeechNTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 6

Unit 1: Introduction1.1 INTRODUCTION TO DIGITAL SYSTEMElectronic system can be divided into to categories-Analog and digital. Digital system isdiscrete. Digital electronics today involves circuits that have exactly two possible states. Asystem having two states is called binary system. It has exactly two values-0 and 1.Digitalsystem consists of positive logic system and negative logic system.In positive logic system.+5V dc=H=1 +0V dc=L=0In negative logic system+5V dc=L=1+0V dc=H=0The voltage levels in an ideal digital circuit will have values of either +5Vdc or 0V dc. Whenthe voltages change between values, they do so in zero time.DIFFERENCE BETWEEN ANALOG AND DIGITAL SYSTEMS Digital System Analog system Values are discrete Values are continuousNon-Linear operation Linear operation For large signals For small signals Values are recorded as a series of distinct values. Represent all possible values Eg-Values of temp measured and Eg-Recording all possible values of recorded only once every minute. temperature from one degree to the OtherDigital watch Sound waves1.2 LOGIC LEVELS AND PULSE WAVEFORMSThe voltage used to represent a ‗1‗ and a ‗0‗ are called logic levels. One voltage levelrepresents a high and the other a low. In a practical digital circuit a HIGH can be anyvoltage between a specified minimum value and a specified maximum value. And low canbe any voltage between a specified minimum and specified maximum. There should be nooverlapping between the accepted HIGH and the accepted low levels.NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 7

For example for a certain digital circuit called TTL ,low values may range from 0 to 0.8V and high values may range from 2V to 5V.And voltages from 0.8V to 2V are unacceptable and never used.PULSE WAVEFORMSDigital waveform consists of voltage levels that are changing back and forth between theHIGH and LOW levels or states. A positive going pulse is generated when voltage or currentgoes from LOW level to HIGH level and then back to its LOW level. The negative goingpulse is generated when the voltage goes from its normally High level to its LOW level andback to its HIGH level. The pulse has two edges a leading edge and a trailing edge. Forpositive- going pulse the leading edge is a rising edge and trailing edge is the falling edgeand for negative going pulse ,just the opposite.The time required for a pulse to go from its LOW value to HIGH value is called rise time (tr)and time required for transition from HIGH value to its LOW value is called fall time(tf).Pulse width (tw) is a measure of the duration of the pulse and it is often defined as th67etime interval between the 50% points on the rising and falling edges.Waveforms are composed of series of pulses, sometimes called pulse trains. They areclassified as periodic and non-periodic. A periodic waveform is one that repeats itself atfixed intervals of time called period (T).The frequency is the rate at which it repeats itselfand is measured in hertz(HZ).A non-periodic waveform don‗t repeat itself a fixed intervals.PeriodicNon periodicNTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 8

1.3 IMPORTANCE OF DIGITAL CIRCUITS 1. Earlier, Logic circuits were built using bulky and unreliable components such as transistors, resistors and vacuum tubes etc. These components existed individually and circuits built using these components did not perform as expected mainly due to the interconnections issues that were common in these circuits. The development of integrated circuits played a significant role in solving the problems of logic circuits. These integrated circuits facilitated to place large number of transistors and on a single chip. 2. Easy to Design: The advent of integrated circuit technology has made it easier to design digital circuits. Today, the designer is not required to know the basic operation of various components such as capacitors, transistors etc which involves complex mathematical calculations. If the designer knows the operations of these components he always has a better hand over other designers. 3. Reliability : Once a digital circuit is designed. For a given set of inputs the circuit always produces the same output at any instant of time unlike analog circuits whose outputs vary with variation in the environment. 4. Highly Flexible : In digital circuits, with the help of the software associated with the underlying digital circuit we can easily change the functionality of the digital circuit without changing the actual circuit. These circuits are generally referred to as programmable digital circuits(we will discuss about this in later chapters). 5. Cheaper : The rapid advancements in IC (integrated circuit) technology such as the existing VLSI(Very Large Scale Integration) technology has made it possible to produce highly complex digital circuits at low costs. UNIT 2 NUMBER SYSTEMS & AND CODES2.1. DECIMAL, BINARY, OCTAL, HEXADECIMAL NUMBERShe study of number systems is useful to the student of computing due to thefact that number systems other than the familiar decimal (Base 10) numbersystem are used in the computer field. Digital computers internally use thebinary (base 2) number system to represent data and perform arithmeticcalculations. The hexadecimal (base 16) number system (often called \"hex\" forshort) provides us with a shorthand method of working with binary numbers.One digit in hex corresponds to four binary digits (bits), so the internalrepresentation of one byte can be represented either by eight binary digits ortwo hexadecimal digits. Less commonly used is the octal (base 8) numbersystem, where one digit in octal corresponds to three binary digits (bits).NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 9

DECIMAL NUMBER SYSTEMThe decimal number system that we are all familiar with is a positional numbersystem. The actual number of symbols used in a positional number systemdepends on its base (also called the radix). The highest numerical symbolalways has a value of one less than the base. The decimal number system hasa base of 10, so the numeral with the highest value is 9; the octal numbersystem has a base of 8, so the numeral with the highest value is 7, the binarynumber system has a base of 2, so the numeral with the highest value is 1,etc.Any number can be represented by arranging symbols in specific positions.You know that in the decimal number system, the successive positions to theleft of the decimal point represent units (ones), tens, hundreds, thousands, etc.Put another way, each position represents a specific power of base 10. Forexample, the decimal number 1,275 (written 1,27510) can be expanded asfollows:(1 2 7 5)105 x 100 = 5 x 1 = 57 x 101 = 7 x 10 = 702 x 102 = 2 x 100 =2001 x 103 = 1 x 1000 = 1000 =12751For fractional numbers the weights are negative powers of ten that decreasefrom left to right beginning with 10-1102 101 100 . 10-110-210-3…………The position of each digit in a decimal number indicates the magnitude of thequantity represented and can be assigned a weight.NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 10

BINARY NUMBER SYSTEMThe same principles of positional number systems we applied to the decimalnumber system can be applied to the binary number system. However, thebase of the binary number system is two, so each position of the binarynumber represents a successive power of two. From right to left, thesuccessive positions of the binary number are weighted 1, 2, 4, 8, 16, 32, 64,etc. A list of the first several powers of 2 follows:20 = 1 21 = 2 22 = 4 23 = 8 24 = 16 25 = 3226 = 64 27 = 128 28 = 256 29 = 512 210 = 1024 211 = 2048DECIMAL BINARY 0 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 1010 10 1011 11 1100 12 1101 13 1110 14 1111 15NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 11

OCTAL NUMBER SYSTEMThe same principles of positional number systems we applied to the decimaland binary number systems can be applied to the octal number system.However, the base of the octal number system is eight, so each position of theoctal number represents a successive power of eight. From right to left, thesuccessive positions of the octal number are weighted 1, 8, 64, 512, etc. A listof the first powers of 8 are as below:80 = 1, 81 = 8, 82 = 64, 83 = 512, 84 = 4096 and 85 = 32768DECIMAL OCTAL 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 10 9 11 10 12 11 13 12 14 13 15 14 16 15 17NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 12

THE HEXADECIMAL NUMBER SYSTEMThe hexadecimal (base 16) number system is a positional number system asare the decimal number system and the binary number system. Recall that inany positional number system, regardless of the base, the highest numericalsymbol always has a value of one less than the base. Furthermore, one andonly one symbol must ever be used to represent a value in any position of thenumber. For number systems with a base of 10 or less, a combination ofArabic numerals can be used to represent any value in that number system.The decimal number system uses the Arabic numerals 0 through 9; the binarynumber system uses the Arabic numerals 0 and1; the octal number systemuses the Arabic numerals 0 through 7; and any other number system with abase less than 10 would use the Arabic numerals from 0 to one less than thebase of that number system.However, if the base of the number system is greater than 10, more than 10symbols are needed to represent all of the possible positional values in thatnumber system. The hexadecimal number system uses not only the Arabicnumerals 0 through 9, but also uses the letters A, B, C, D, E, and F torepresent the equivalent of1010 through 1510, respectively.DECIMAL HEXADECIMAL 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 10NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 13

9 1110 A11 B12 C13 D14 E15 F2.2. 9’s & 10’s Complements-1'S &2'S COMPLEMENTS 1‗s &2‗s complement is used for binary addition and subtraction. 1‗s complement The 1‗s complement of a binary number is found by changing all 1s to 0s and all 0s to 1s, as 1 0 1 1 0 0 1 0 Binary number The 2‗s complement of a binary number is found by adding 1 to the LSB of the 1‗s complement 2‗s complement = (1‗s complement) + 19’s COMPLEMENT AND 10’S COMPLEMENT9‗s and 10‗s complement is used for the addition and subtraction ofdecimal numbers.The 9‗s complement of a decimal number is found by subtracting each digitin the number from 9.E.g. 9‗s complement of 28 = 99 –28 = 71 9‘s complement of 562 = 999 –562 = 437 Subtraction of a smaller decimal number from a larger one can be done by adding the 9‗s complement of the smaller number to the larger number and then adding the Carry to the result (end around Carry). WhenNTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 14

subtracting a larger number from a smaller one .There is no carry and theresult is in 9‗s complement form and negativeEg:110’s complementThe 10‗s complement of a decimal number is obtained by subtracting eachdigit of a number from 10.Eg1: The 10‗s complement of 7 is 3.And 10‗s complement of 89 is 11.100-89=11Eg2: 835If n=4, then 104 -0835 = 10000-835 =9165If n=6, then 106-835= 1000000-000835=9991652.3 CONVERSION of NUMBER SYSTEMS 1. Converting a Binary Number to a Decimal NumberTo determine the value of a binary number (10012, for example), we canexpand the number using the positional weights as follows:(1001)2 =1 0 01 1x 230 x 220 x 211 x 20 = 8 +0+0+1 =9(1101010)2 = 1 1 0 1 0 1 01 x 261 x 250 x 241 x 230 x 221 x 210 x20NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 15

= 64 +32+0+0+8+0+2+0 = 1062. Converting a Decimal Number to a Binary NumberTo convert a decimal number to its binary equivalent, the remainder methodcan be used. (This method can be used to convert a decimal number into anyother base.) The remainder method involves the following four steps:(1) Divide the decimal number by the base (in the case of binary, divide by 2).(2) Indicate the remainder to the right.(3) Continue dividing into each quotient (and indicating the remainder) until thedivide operation produces a zero quotient.(4) The base 2 number is the numeric remainder reading fromthe last divisionto the first (if you start at the bottom, the answerwill read from top to bottom).a)(99)1099/2 =49 1------------------------------------- LSB49/2 =24 -- 124/2 =12 012/2 = 6 06/2 = 3 03/2 = 1 11/2 =0 1 ---------------------------------------- MSB --(99)10 = 1 001110MSB LSBNTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 16

So (99)10=( 1100011)2b) (13)1013/2 = 6 1-------------------------------- LSB -- MSB6/2 = 3 03/2 = 1 11/2 = 0 1------------------------------- ---(13)1 10 10 =1 LSB MSB(13)10 =( 1101)2(C) (0.3125)10 MSB0.3125 *2 =0.625 0------------------------------------ LSB --0.625 * 2 =1.25 10.25 *2 =0.50 00.50 * 2 =1.00 1----------------------------------- --(0.3125 )10 = ( 0.0101)23. Converting an Octal Number to a Decimal NumberTo determine the value of an octal number (3678, for example), we canexpand the number using the positional weights as follows: a) 3678 = 3 x 83 + 6 x 82 + 7 x 818 x 80 = 1536 + 384 +56+8NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 17

= 1984b) (1601)8 = 1 x 83 + 6 x 82 + 0 x 81 +1 x 80 = 512 + 384 + 0 + 1 =8972. Converting a Decimal Number to an Octal NumberTo convert a decimal number to its octal equivalent, the remainder method(the same method used in converting a decimal number to its binaryequivalent) can be used. To review, the remainder method involves thefollowing four steps:(1) Divide the decimal number by the base (in the case of octal, divide by 8).(2) Indicate the remainder to the right.(3) Continue dividing into each quotient (and indicating the remainder) until thedivide operation produces a zero quotient.(4) The base 8 number is the numeric remainder reading from the last divisionto the first (if you start at the bottom, the answer will read from top to bottom).Eg- (465)10 1-------------------------------------- LS465/8 = 58 -- D58/8 = 7 2 7 --------------------------------------- MS7/8 0 -D(465)10 = (721)8 3. Converting a Hexadecimal Number to a Decimal NumberWe can use the same method that we used to convert binary numbers andoctal numbers to decimal numbers to convert a hexadecimal number to aNTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 18

decimal number, keeping in mind that we are now dealing with base 16. Fromright to left, we multiply each digit of the hexadecimal number by the value of16 raised to successive powers, starting with the zero power, and then sumthe results of the multiplications. Remember that if one of the digits of thehexadecimal number happens to be a letter A through F, then thecorresponding value of 10 through 15 must be used in the multiplication.Eg- (20B3)163 x 160 = 3 x 1 = 311 x 161 = 11 x 16 = 1760 x 162 = 0 x 256 = 02 x 163 = 2 x 4096 = 81923+176+0+8192=8371(20B3)16 =(8371)106.Converting a Decimal Number to a Hexadecimal NumberTo convert a decimal number to its hexadecimal equivalent, the remaindermethod (the same method used in converting a decimalnumber to its binaryequivalent) can be used. To review, the remainder method involves thefollowing four steps:(1) Divide the decimal number by the base (in the case of hexadecimal, divideby 16).(2) Indicate the remainder to the right. If the remainder is between 10 and 15,indicate the corresponding hex digit A through F.(3) Continue dividing into each quotient (and indicating the remainder) until thedivide operation produces a zero quotient.(4) The base 16 number is the numeric remainder reading from the last divisionNTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 19

to the first (if you start at the bottom, the answerwill read from top to bottom).Eg: (650)10650/16 =40 10=A------------------------------ LSD40/16 = 2 82/16 = 0 2-------------------------------- MSD(650)10 = (28A)162.4. BCD CODE-Digital Codes –Gray ,Excess 3,Alphanumeric codes, ASCII ,EBCDIC CodesThe 8421 code is called the BCD (Binary Coded Decimal) code.BCD means that each decimal digit, through 9 is representedby a binary code of four bit.The designation 8421 indicates thebinary weights of the four bits (23 , 22 ,21,20).The mainadvantage of BCD code is that conversion between 8421 codenumbers and decimal numbers is easy.NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 20

DIGITAL CODESGRAY CODEGray Code is a form of binary that uses a different method of incrementingfrom one number to the next. With Gray Code, only one bit changes statefrom one position to another. This feature allows a system designer to performsome error checking (i.e. if more than one bit changes, the data must beincorrect). The gray code is sometimes referred to as reflected binary,because the first eight values compare with those of the last 8 values, but inreverse order.Decimal Binary Gray 0 0000 0000 1 0001 0001 2 0010 0011 3 0011 0010 4 0100 0110 5 0101 0111Excess-3 code is an example of weighted code. Excess-3 equivalent of adecimal number is obtained by adding 3 and then converting it to a binaryformat. For instance to find excess-3 representation of decimal number 4, first3 is added to 4 to get 7 and then binary equivalent of 7 i.e. 0111 forms theexcess-3 equivalent.NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 21

DECIMAL EXCESS-3 0 0011 1 0100 2 0101 3 0110 4 0111 5 1000 6 1001 7 1010 8 1011 9 1100ALPHANUMERIC CODEThese codes contain not only numerical but also alphabets. Hence the name.For communication between 2 or more computers, one needs a binary basedcode which can represent the letters of the alphabets as well as the numbers.Common codes used for this have 7 to 8 bits /word and are referred to asalphanumeric codes. There are several types of alphanumeric codes two ofthem are the ASCII and EBCDIC.ASCIIThe American Standard Code for Information Interchange (ASCII) is acharacter-encoding scheme originally based on the English alphabet. ASCIIcodes represent text in computers, communications equipment, and otherdevices that use text. Most modern character-encoding schemes are based onASCII, though they support many more characters than ASCII does.The first thirty-two codes in the ASCII table represent the control characters.The ASCII codes are given below.NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 22

EBCDIC CODEEBCDIC which stands for the Extended Binary Coded Decimal InterchangeCode is an 8 bit character encoding used on IBM mainframes andAS/400s.Single byte EBCDIC takes up eight bits, which are divided in twopieces. The first four bits are called the zone and represent the category of thecharacter, whereas the last four bits are the called the digit and identify thespecific character.2.5 Arithmetic Operations on Binary NumbersBecause of its widespread use, we will concentrate on addition and subtractionfor Two's Complement representation.The nice feature with Two's Complement is that addition and subtraction of Two'scomplement numbers works without having to separate the sign bits (the sign ofthe operands and results is effectively built-into the addition/subtractioncalculation).NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 23

Remember: −2n−1 ≤ Two's Complement ≤ 2n−1 − 1 −8 ≤ x[4] ≤ +7 −128 ≤ x[8] ≤ +127 −32768 ≤ x[16] ≤ +32767 −2147483648 ≤ x[32] ≤ +2147483647 What if the result overflows the representation?If the result of an arithmetic operation is to too large (positive or negative) to fitinto the resultant bit-group, then arithmetic overflow occurs. It is normally left tothe programmer to decide how to deal with this situation. Two's Complement AdditionAdd the values and discard any carry-out bit.Examples: using 8-bit two‘s complement numbers. 1. Add −8 to +3 2. (+3) 0000 0011 3. +(−8) 1111 1000 4. ----------------- 5. (−5) 1111 1011 6. Add −5 to −2 7. (−2) 1111 1110 8. +(−5) 1111 1011 9. ----------------- 10. (−7) 1 1111 1001 : discard carry-outOverflow Rule for additionIf 2 Two's Complement numbers are added, and they both have the same sign(both positive and both negative), then overflow occurs if and only if the result hasthe opposite sign. Overflow never occurs when adding operands with differentsigns.i.e. Adding two positive numbers must give a positive result Adding two negative numbers must give a negative resultOverflow occurs if Page 24  (+A) + (+B) = −C  (−A) + (−B) = +CNTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017

Example: Using 4-bit Two's Complement numbers (−8 ≤ x ≤ +7)(−7) 1001+(−6) 1010------------(−13) 1 0011 = 3 : Overflow (largest −ve number is −8)A couple of definitions:Subtrahend: what is being subtracted Minuend: what it is being subtracted fromExample: 612 - 485 = 127485 is the subtrahend, 612 is the minuend, 127 is the result Two's Complement SubtractionNormally accomplished by negating the subtrahend and adding it to theminuhend. Any carry-out is discarded.Example: Using 8-bit Two's Complement Numbers (−128 ≤ x ≤ +127)(+8) 0000 1000 0000 1000−(+5) 0000 0101 -> Negate -> +1111 1011----- -----------(+3) 1 0000 0011 : discard carry-out Overflow Rule for SubtractionIf 2 Two's Complement numbers are subtracted, and their signs are different, thenoverflow occurs if and only if the result has the same sign as the subtrahend.Overflow occurs if (+A) − (−B) = −C(−A) − (+B) = +CExample: Using 4-bit Two's Complement numbers (−8 ≤ x ≤ +7)Subtract −6 from +7(+7) 0111 0111−(−6) 1010 -> Negate -> +0110---------- -----13 1101 = −8 + 5 = −3 : OverflowNTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 25

Number Circle for 4-bit Two's Complement numbersNumbers can be added or subtracted by moving round the number circle  Clockwise for addition  Anti-Clockwise for subtraction (addition of a negative number)Overflow occurs when a transition is made  from +2n−1−1 to −2n−1 when adding  from −2n−1 to +2n−1−1 when subtractingNTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 26

Two's Complement SummaryAddition  Add the values, discarding any carry-out bitSubtraction  Negate the subtrahend and add, discarding any carry-out bitOverflow  Occurs when adding two positive numbers produces a negative result, or when adding two negative numbers produces a positive result. Adding operands of unlike signs never produces an overflow  Notice that discarding the carry out of the most significant bit during Two's Complement addition is a normal occurrence, and does not by itself indicate overflow  As an example of overflow, consider adding (80 + 80 = 160)10, which produces a result of −9610 in 8-bit two's complement: 01010000 = 80 + 01010000 = 80 -------------- 10100000 = −96 (not 160 because the sign bit is 1.) (largest +ve number in 8 bits is 127)Hexadecimal Number SystemFollowing are the characteristics of a hexadecimal number system.  Uses 10 digits and 6 letters, 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F.  Letters represents numbers starting from 10. A = 10, B = 11, C = 12, D = 13, E = 14, F = 15.  Also called base 16 number system.  Each position in a hexadecimal number represents a 0 power of the base (16). Example − 160  Last position in a hexadecimal number represents an x power of the base (16). Example − 16x where x represents the last position - 1.ExampleHexadecimal Number − 19FDE16Calculating Decimal Equivalent −NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 27

Step Binary Decimal Number NumberStep 1 19FDE16 ((1 × 164) + (9 × 163) + (F × 162) + (D × 161) + (E ×Step 2 19FDE16 160))10 ((1 × 164) + (9 × 163) + (15 × 162) + (13 × 161) + (14 × 160))10Step 3 19FDE16 (65536 + 36864 + 3840 + 208 + 14)10Step 4 19FDE16 10646210Note − 19FDE16 is normally written as 19FDE.Hexadecimal AdditionFollowing hexadecimal addition table will help you greatly to handle Hexadecimal addition.To use this table, simply follow the directions used in this example − Add A16 and 516.Locate A in the X column then locate the 5 in the Y column. The point in 'sum' area wherethese two columns intersect is the sum of two numbers.NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 28

A16 + 516 = F16.Example − AdditionHexadecimal SubtractionThe subtraction of hexadecimal numbers follows the same rules as the subtraction ofnumbers in any other number system. The only variation is in borrowed number. In thedecimal system, you borrow a group of 1010. In the binary system, you borrow a group of210. In the hexadecimal system you borrow a group of 1610.Example - SubtractionNTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 29

Unit 3 Logic gates3.1 Logic Gates-symbol, function, expression, truth table Logic gate is an electronic circuit which provides one output based upon one or more input combinations. Logic gates are used in digital circuits for the purpose of logical decisions. The three basic logic gates are AND, OR, NOT(Inverter).Digital systems are said to be constructed by using logic gates. These gates arethe AND, OR, NOT, NAND, NOR, EXOR and EXNOR gates. The basicoperations are described below with the aid of truth tables.AND gateThe AND gate is an electronic circuit that gives a high output (1) only if all itsinputs are high. A dot (.) is used to show the AND operation i.e. A.B. Bear inmind that this dot is sometimes omitted i.e. ABNTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 30

OR gateThe OR gate is an electronic circuit that gives a high output (1) if one or more ofits inputs are high. A plus (+) is used to show the OR operation.NOT gateThe NOT gate is an electronic circuit that produces an inverted version of theinput at its output. It is also known as an inverter. If the input variable is A, theinverted output is known as NOT A. This is also shown as A', or A with a bar overthe top, as shown at the outputs. The diagrams below show two ways that theNAND logic gate can be configured to produce a NOT gate. It can also be doneusing NOR logic gates in the same way.NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 31

NAND gateThis is a NOT-AND gate which is equal to an AND gate followed by a NOT gate.The outputs of all NAND gates are high if any of the inputs are low. The symbol isan AND gate with a small circle on the output. The small circle representsinversion.NOR gateThis is a NOT-OR gate which is equal to an OR gate followed by a NOT gate.The outputs of all NOR gates are low if any of the inputs are high. The symbol isan OR gate with a small circle on the output. The small circle representsinversion.EXOR gateNTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 32

The 'Exclusive-OR' gate is a circuit which will give a high output if either, but notboth, of its two inputs are high. An encircled plus sign ( ) is used to show theEOR operation.EXNOR gateThe 'Exclusive-NOR' gate circuit does the opposite to the EOR gate. It will give alow output if either, but not both, of its two inputs are high. The symbol is anEXOR gate with a small circle on the output. The small circle representsinversion.The NAND and NOR gates are called universal functions since with either onethe AND and OR functions and NOT can be generated.Note:A function in sum of products form can be implemented using NAND gates byreplacing all AND and OR gates by NAND gates.A function in product of sums form can be implemented using NOR gates byreplacing all AND and OR gates by NOR gates.NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 33

Table 1: Logic gate symbolsTable 2 is a summary truth table of the input/output combinations for the NOTgate together with all possible input/output combinations for the other gatefunctions. Also note that a truth table with 'n' inputs has 2n rows. You cancompare the outputs of different gates.Table 2: Logic gates representation using the Truth table3.2 Universal Gate | NAND and NOR Gate as Universal GateWe have discussed about different types of logic gates in previous articles. Now coming tothe topic of this article we are going to discuss about the Universal Gate. AND, NOTand OR gates are the basic gates; we can create any logic gate or any Boolean expressionby combining them. Now NOR gate and NAND gates have the particular property that anyone of them can create any logical Boolean expression if designed in a proper way. Now wewill look at the operation of each gate separately as universal gates.NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 34

NAND gate as Universal GateThe below diagram is of a two input NAND gate. The first part is an AND gate and secondpart is a dot after it represents a NOT gate. So it is clear that during the operation of NANDgate, the inputs are first going through AND gate and after that the output is reversed andwe get the final output. Now we will look at the truth table of NAND gate.We will consider the truth table of the above NAND gate i.e. a two-input gate. The twoinputs are A and B.Now we will see how this gate can be used to make othergates.This is the circuit diagram of a NAND gate used to make work like a NOT gate, the originallogic gate diagram of NOT gate is given beside.NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 35

The above diagram is of an OR gate made from combinations of NAND gates, arranged in aproper manner. The truth table of an OR gate is also given beside the diagram. Now we willsee the design of an AND gate from NAND gates. Theabove diagram is of an AND gate made from NAND gate. So we can see that all the threebasic gates can be made by only using NAND gates, that‘s why this gate iscalled Universal Gate and it is appropriate.NOR gate as universal gateWe have seen how NAND gate can be used to make all the three basic gates by using thatalone.Now we will discuss the same in case of NOR gate. The above diagram is of an OR gatemade by only using NOR gates. The output of this gate is exactly similar to that of a singleOR gate. As we can see the circuit arrangement of OR gate using NOR gates is similar tothat of AND gate using NAND gates.The above diagram as the name suggests is of AND gate using only NOR gate, again wecan see that the circuit diagram of AND gate using only NOR gate is exactly similar to thatNTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 36

of OR gate using only NAND gates. Now we will finally see how a NOT gate can be madeby using only NOR gates.The above diagram is of a NOT gate made by using a NOR gate. The circuit diagram issimilar to that of NOT gate made by using only NAND gate. So, from the above discussion itis clear that all the three basic gates (AND, OR, NOT) can be made by only using NORgate. And thus, it can be aptly termed as Universal Gate.3.3 GATE PROPAGATION DELAY TIMEA propagation delay time is the interval of time required after an input signalhas been applied for the resulting output change to occur.tPLH is the propagation delay when the output changes from LOW to HIGH.tPHL is the propagation delay when the output changes from HIGH to LOW.tPLH and tPHL are not necessarily equal, and their values depends on thelogic family. POWER DISSIPATIONThe power consumed by the gate that must be available from the powersupply. This does not include the power delivered from another gate.VCC : Supply voltage.ICCH: Current drawn by the circuit when the output of the gate is HIGH.NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 37

ICCL : Current drawn by the circuit when the output of the gate is LOW PD: average power dissipation. ICC : average current drawn by the circuit. P = Vcc*Icc3.4 NOISE IMMUNITY & FAN IN, FAN OUTNoise is present in all real systems .This adds random fluctuations to voltagesrepresenting logic levels. To cope with noise, the voltage ranges defining thelogic levels are more tightly constrained at the output of a gate than at theinput .Thus small amounts of noise will not affect the circuit .The maximumnoise voltage that can be tolerated by a circuit is termed its noise immunity.A measure of circuit‗s noise immunity is called the noise margin, which isexpressed in volts. There are two values of noise margin specified for a givenlogic circuit: the HIGH- level noise margin (VNH) and the LOW –level noisemargin (VNL).VNH = VOH(min) – VIH(min)VNL =VIL(max) – VoL(max)VNH is the difference between the lowest possible HIGH output from a driving gate(VOH(min)) and the lowest possible HIGH input that the gate can tolerate (VIH(min)) .VNL is the difference between the maximum possible LOW input that a gate cantolerate (VIL(max)) and the maximum possible LOW output of the gate(VoL(max)).NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 38

FAN IN & FAN OUTFan in is the number of the inputs given for a logic gate.Fan out is the number of gate inputs that a single output can drive or operatewithout exceeding its worst case loading specifications3.5 LOADING CONSIDERATIONS & APPLICATIONIn most designs, logic gates are connected together to form more complexcircuits. While no more than one logic gate output is connected to any singleinput, it is common for one output to be connected to several inputs. Thetechnology used to implement logic gates usually allows a certain number ofgate inputs to be wired directly together without additional interfacing circuitry.The maximum fan-out of an output measures its load-drivingCapability: it is the greatest number of inputs of gates of the same type towhich the output can be safely connected.APPLICATIONInverter –Used for producing the 1‗s complement of an 8-bit binary number.The bit s of the binary number is applied to the inverter inputs and the 1‗scomplement of the number appears on the outputs.AND gate –Use to enable (to allow) the passage of a signal (pulse waveform)from one point to another at certain times and to inhibit (prevent) the passageat other times.OR gate –Used in open door/window sensors.NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 39

Unit - 4 BOOLEAN ALGEBRA & KARNAUGH MAPS 4.1 Boolean OperationsBoolean algebra can be used to formalize the combinations of binary logicstates. In these relations, A and B are binary quantities, that is, they can beeither logical true or logical false.We can use algebraic expressions to complete our definitions of the basiclogic gates we began above. Note that the Boolean operations ofmultiplication\" and addition\" are defined by the truth tables for the AND andOR gates given above in. Using these definitions, we can define all of thelogic gates algebraically. The truth tables can also be constructed fromthese relations, if necessary.For inversion we can use the notation A‗ instead of over bar notationBoolean AdditionIt is equivalent to OR operation. In Boolean algebra, a Sum term is a sum ofliterals .In logic circuits, a sum term is produced by an OR operation with noAND operations involved. Some examples of sum terms areA sum term is equal to one when one or more of the literals in the term are1.A sum term is equal to zero only if each of the literals is 0.NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 40

Boolean multiplicationIt is equivalent to the AND operation .In Boolean algebra, a product term isthe product of literals. In logic circuits, a product term is obtained by an ANDoperation. Examples are AB, A‗BThe product term is 0 if any of the literals is 0.And the product term is 1 onlyif both of the literal is 1.4.2 Logic Expressions:A logical expression consists of one or more logical operators and logical,numeric, or relational operands. The following are logical operators:Operator Example Meaning .AND. A .AND. B Logical conjunction: the expression is true if both A and.OR. A .OR. B B are true. Logical disjunction (inclusive OR): the expression is true.NEQV. A .NEQV. B if either A, B, or both, are true.XOR. A .XOR. B Logical in equivalence (exclusive OR): the expression is .EQV. A .EQV. B true if either A or B is true, but false if both are true. Same as .NEQV..NOT.1 .NOT. A Logical equivalence: the expression is true if both A and B are true, or both are false. Logical negation: the expression is true if A is false and false if A is true.1 .NOT. is a unary operator.4.3 Rules and Laws of Boolean algebra1. Commutative LawsA+B=B+A (Commutative law of addition)AB=BA (Commutative law of multiplication)NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 41

2. Associative lawsA+ (B+C) = (A+B) +C (Associative law of addition)A (BC) = (AB) C (Associative law of multiplication)3. Distributive LawA (B+C) = AB+ACRules of Boolean algebra1. A+0=A2. A+1=13. A.0= 04. A.1= A5. A+A=A6. A+A‘=17. A.A =A8. A.A‘=09. A‘‘=A10. A+AB=A11. A+A‘B=A+B12. (A+B) (A+C) = A+BCNTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 42

4.4 DEMORGAN’S THEOREMDEMORGAN'S Theorems:4.5 SIMPLIFICATION OF BOOLEAN EXPRESSIONSEXAMPLE:Using Boolean Algebra techniques, simplify this expressionAB + A (B+C) +B (B+C)STEP1. Apply the distributive law to the second and third terms in theexpression,AB+AB+AC+BB+BCSTEP2.Apply rule 7 (BB = B) to the fourth term.AB+AB+AC+B+BCSTEP3.Apply rule 5 (AB+AB=AB) to the first two terms.AB+AC+B+BCSTEP4. Apply rule 10 (B+BC=B) to the last two terms.AB+AC+BB+ACSTANDARD FORMS OF BOOLEAN EXPRESSIONSAll Boolean expressions, regardless of their form, can be converted into eitherof two standard forms: the sum - of- products form or the product of sumsNTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 43

form. Standardization makes the evaluation, simplification, and implementationof Boolean expressions much more systematic and easier.The Sum-of-Products form (SOP)AB+ABC ABC+CDE+B‗CD‗ A‗B+A‗BC‗+ACThe Product-of- sums form (POS)(A‗+B)(A+B‗+C)(A‗+B‗+C‗)(C+D‗+E)(B‗+C+D)(A+B)(A+B‗+C)(A‗+C)STEP5. Apply rule 10 (AB+B=B) TO THE FIRST AND THIRD TERMS.K Map or Karnaugh MapSimplification of Boolean expressions is an important step while designing anydigital system. Karnaugh Maps or K-maps is one among such simplificationtechnique, introduced by Maurice Karnaugh in 1953, which is graphical innature. This method of minimizing the logical expressions is most suitablewhen the number of variables involved is less than or equal to four. This isbecause, K-map employs the use of two-dimensional tables to simplify theexpressions, whose size increases at a very high rate with the increase in thenumber of variables. This fact is further established by Figure 1 which showsNTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 44

the K-maps for two, three and four variables inorder.From the figure, it is evident that the number of cells in the K-map is a functionof number of inputs. In general, if there are n inputs, then the corresponding K-map has to be of 2n cells. For example, if the number of input variables is 2,then we have to consider a K-map with 4 (=22) cells, while if there are 3 inputvariables, then we require a 8 (=23) cell K-map, and similarly for 4 inputs onegets 16 (=24) cell K-map and so on.Structure of K-mapAll the K-maps irrespective of their size, are seen to possess a generalizedstructure (Figure 1). Every K-map has a set of input variables represented atits top left-corner (black alphabets). These are the input variables which areinvolved in the logical expression which needs to be simplified. The value(s) ofthese variable(s) is/are shown in binary along their respective sides(combination of zeros and ones shown in blue). Here, it is seen that the binarypatterns of any two adjacent cells differ by just a single bit. This kind ofencoding scheme is referred to as grey code and is employed in order to easethe process of grouping which intern minimizes the logical expression. Furtherthese binary sequences are seen to assign a definite input bit pattern for eachK-map cell, whose decimal equivalent is shown in red numbers inside each ofthem. For example, third cell of the first row in Figure 1b corresponds to theinput bit pattern ABC = 011 which is represented by its decimal equivalent 3.K-map simplification procedure is initiated by entering the values of the outputvariable (either for sum-of-products, SOP or for product-of-sums, POS) inappropriate K-map cells. Then one has to group the maximum number of'ones' (in case of SOP) or 'zeros' (in case of POS). These groups shouldNTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 45

necessarily be in powers of 2 and should be carried on in descending order only. For instance, if there are 8 cells in the K-map, then, first, try grouping for 8 (=23), then for 4 (=22), next for 2 (=21) and lastly consider the isolated terms. After this, each group is expressed in terms of the combination of input variables which correspond to the common binary values along the associated rows and columns. Finally, these are used to express the output of the logical expression. Advantages of Karnaugh Map Advantages of K-map are showing below1. K-map simplification does not demand for the knowledge of Boolean algebraic theorems2. Usually it requires less number of steps when compared to algebraic minimization technique Disadvantages of Karnaugh Map Disadvantages of K-map are showing below1. Complexity of K-map simplification process increases with the increase in the number of variables2. The minimum expression obtained might not be unique 2 VARIABLE K-MAP Below, we show the adjacent 2-cell regions in the 2-variable K-map with the aid of previous rectangular Venn diagram like Boolean regions.Cells α and χ are adjacent in the K-map as ellipses in the left most K-mapbelow. Referring to the previous truth table, this is not the case. There isanother truth table entry (β) between them. Which brings us to the wholeNTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 46

point of the organizing the K-map into a square array, cells with any Booleanvariables in common need to be close to one another so as to present apattern that jumps out at us. For cells α and χ they have the Booleanvariable B’ in common. We know this because B=0 (same as B’) for thecolumn above cells α and χ. Compare this to the square Venn diagram abovethe K-map.A similar line of reasoning shows that β and δ have Boolean B (B=1) incommon. Then, α and β have Boolean A’ (A=0) in common. Finally, χ and δhave Boolean A (A=1) in common. Compare the last two maps to the middlesquare Venn diagram.To summarize, we are looking for commonality of Boolean variables amongcells. The Karnaugh map is organized so that we may see that commonality.Let‘s try some examples.Example:Transfer the contents of the truth table to the Karnaugh map above.Solution:The truth table contains two 1s. the K- map must have both of them. locatethe first 1 in the 2nd row of the truth table above.  note the truth table AB address Page 47NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017

 locate the cell in the K-map having the same address  place a 1 in that cellRepeat the process for the 1 in the last line of the truth table.Example:For the Karnaugh map in the above problem, write the Boolean expression.Solution is below.Solution:Look for adjacent cells, that is, above or to the side of a cell. Diagonal cellsare not adjacent. Adjacent cells will have one or more Boolean variables incommon.  Group (circle) the two 1s in the column  Find the variable(s) top and/or side which are the same for the group, Write this as the Boolean result. It is B in our case.  Ignore variable(s) which are not the same for a cell group. In our case A varies, is both 1 and 0, ignore Boolean A.  Ignore any variable not associated with cells containing 1s. B’ has no one‘s under it. Ignore B‘  Result Out = BThis might be easier to see by comparing to the Venn diagrams to the right,specifically the B column.Example:Write the Boolean expression for the Karnaugh map below.NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 48

Solution: (above)  Group (circle) the two 1’s in the row  Find the variable(s) which are the same for the group, Out = A’Example:For the Truth table below, transfer the outputs to the Karnaugh, then write theBoolean expression for the result.Solution:Transfer the 1s from the locations in the Truth table to the correspondinglocations in the K-map. Group (circle) the two 1‘s in the column under B=1 Group (circle) the two 1‘s in the row right of A=1 Write product term for first group = B Write product term for second group = A Write Sum-Of-Products of above two terms Output = A+BThe solution of the K-map in the middle is the simplest or lowest costsolution. A less desirable solution is at far right. After grouping the two 1s, wemake the mistake of forming a group of 1-cell. The reason that this is notdesirable is that:  The single cell has a product term of AB’ Page 49NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017

 The corresponding solution is Output = AB’ + B  This is not the simplest solutionThe way to pick up this single 1 is to form a group of two with the 1 to theright of it as shown in the lower line of the middle K-map, even thoughthis 1 has already been included in the column group (B). We are allowed tore-use cells in order to form larger groups. In fact, it is desirable because itleads to a simpler result.We need to point out that either of the above solutions, Output or WrongOutput, are logically correct. Both circuits yield the same output. It is a matterof the former circuit being the lowest cost solution.Example:Fill in the Karnaugh map for the Boolean expression below, then write theBoolean expression for the result.Solution: (above)The Boolean expression has three product terms. There will be a 1 enteredfor each product term. Though, in general, the number of 1s per product termvaries with the number of variables in the product term compared to the sizeof the K-map. The product term is the address of the cell where the 1 isentered. The first product term, A’B, corresponds to the 01 cell in the map.A 1 is entered in this cell. The other two P-terms are entered for a total ofthree 1sNext, proceed with grouping and extracting the simplified result as in theprevious truth table problem.Example:Simplify the logic diagram below.NTTF DIGITAL ELECTRONICS (Common for CP04 & CP15) _ 3rd Sem._ June 2017 Page 50