Eletro-X_VEGAS TURIS SKL-KBL (15341-1 91N85)

21 GFX & GPP, 85Ω 1 OF 7 GFX & GPP CLK, 85Ω GPU1A GEN2/GEN3 SCD1U16V2KX-3GP D GEN2/GEN3 SCD1U16V2KX-3GP C B AF30 PCIE_RX0P PCIE_TX0P AH30 PEG_RX_GPU_P0 C7601 1 2 SCD1U16V2KX-3GP PEG_RX_CPU_P0 16 A AE31 PCIE_RX0N PCIE_TX0N AG31 2 SCD1U16V2KX-3GP PEG_RX_CPU_N0 16 PEG_RX_GPU_N0 C7602 1 AE29 PCIE_RX1P PCIE_TX1P AG29 2 SCD1U16V2KX-3GP PEG_RX_CPU_P1 16 AD28 PCIE_RX1N PCIE_TX1N AF28 GEN2/GEN3 2 SCD1U16V2KX-3GP PEG_RX_CPU_N1 16 GEN2/GEN3 AD30 PCIE_RX2P PCIE_TX2P AF27 PEG_RX_GPU_P1 C7603 1 2 SCD1U16V2KX-3GP PEG_RX_CPU_P2 16 AC31 PCIE_RX2N PCIE_TX2N AF26 2 SCD1U16V2KX-3GP PEG_RX_CPU_N2 16 PEG_RX_GPU_N1 C7604 1 AC29 PCIE_RX3P PCIE_TX3P AD27 2 PEG_RX_CPU_P3 16 AB28 PCIE_RX3N PCIE_TX3N AD26 GEN2/GEN3 2 PEG_RX_CPU_N3 16 GEN2/GEN3 AB30 PCIE_RX4P PCIE_TX4P AC25 PEG_RX_GPU_P2 C7605 1 AA31 PCIE_RX4N PCIE_TX4N AB25 PEG_RX_GPU_N2 C7606 1 AA29 PCIE_RX5P PCIE_TX5P Y23 Y28 PCIE_RX5N PCIE_TX5N Y24 GEN2/GEN3 GEN2/GEN3 Y30 PCIE_RX6P PCIE_TX6P AB27 PEG_RX_GPU_P3 C7607 1 W 31 PCIE_RX6N PCIE_TX6N AB26 PEG_RX_GPU_N3 C7608 1 W 29 PCIE_RX7P PCIE_TX7P Y27 tro-XV28 PCIE_RX7N PCI EXPRESS INTERFACE PCIE_TX7N Y26 V30 NC#V30 NC#W 24 W 24 U31 NC#U31 NC#W 23 W 23 U29 NC#U29 NC#V27 V27 T28 NC#T28 NC#U26 U26 T30 NC#T30 NC#U24 U24 R31 NC#R31 NC#U23 U23 R29 NC#R29 NC#T26 T26 P28 NC#P28 NC#T27 T27 P30 NC#P30 NC#T24 T24 N31 NC#N31 NC#T23 T23 N29 NC#N29 NC#P27 P27 M28 NC#M28 NC#P26 P26 M30 NC#M30 NC#P24 P24 L31 NC#L31 NC#P23 P23 L29 NC#L29 NC#M27 M27 K30 NC#K30 NC#N26 N26 AK30 CLOCK AK32 PCIE_REFCLKP PCIE_REFCLKN CALIBRATION Y22 PCIE_CALR_TX 1K69R2F-2-GP 2 OPS 1 R7622 0D95V_VGA_S0 PCIE_CALR_TX AA22 PCIE_CALR_RX 1 R7618 T N10 TEST_PG PCIE_CALR_RX 1KR2F-3-GP 2 OPS AL27 PERST# Y JET-XT-S3-GP OPS <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title 076_GPU(1/5) PEG Size Project Name Rev <Project Name> Date: Monday, June 27, 2016 Sheet 76 of 105 21

5 4 3 5 OF 7 Main Func = dGPU GPU1E AA27 GND GND A3 1.8V and 0.95V for Clock AB24 GND GND A30 D AB32 GND GND AA13 1D8V_VGA_S0 AC24 GND GND AA16 AC26 GND GND AB10 R7704 GND AB15 AC27 GND GND AB6 12 21 21 AD25 GND GND AC9 0R0603-PAD-2-GP-U AD32 GND GND AD6 AE27 GND GND AD8 DY AF32 GND GND AE7 GND AG12 C AG27 GND GND AH10 SC GND AH28 AH32 GND GND B10 GND B12 K28 GND GND B14 0D95V_VGA_S0 K32 GND GND B16 R7705 L27 GND GND B18 M32 GND GND B20 12 N25 GND GND B22 0R0603-PAD-2-GP-U GND B24 N27 GND GND B26 P25 GND GND B6 P32 GND GND B8 GND C1 R27 GND GND C32 T25 GND GND E28 GND F10 C T32 GND GND F12 GPU1F U25 GND GND F14 U27 GND GND F16 GND F18 V32 GND GND F2 W25 GND GND F20 W26 GND GND F22 W27 GND GND F24 GND GND F26 Y25 GND F6 GND F8 Y32 GND GND G10 GND G27 M6 GND GND G31 N13 GND GND G8 GND H14 N16 GND GND GND H17 N18 GND GND H2 N21 GND GND H20 GND GND H6 P6 GND GND J27 P9 GND J31 GND K11 R12 GND GND K2 Elet R15 GND GND K22 GND K6 B R17 GND R20 GND T13 GND T16 GND T18 GND T21 GND T6 GND U15 GND U17 GND U20 GND GND U9 V13 GND V16 GND V18 GND TP7701 Y10 GND TP7702 Y15 GND TP7703 Y17 GND Y20 GND A R11 GND VSS_MECH A32 VSS_MECH1 1 T11 GND VSS_MECH AM1 VSS_MECH2 1 AA11 GND VSS_MECH AM32 VSS_MECH3 1 M12 GND N11 GND V11 GND JET-XT-S3-GP JET-XT OPS 4 OPS 5 3

21 GPU1G 7 OF 7 DP POW ER NC/DP POW ER resource AG15 NC_DP_VDDR#AG15 NC#AE11 AE11 AG16 NC_DP_VDDR#AG16 NC#AF11 AF11 DPLL_PVDD DPLL_PVDD AF16 NC_DP_VDDR#AF16 NC#AE13 AE13 D AG17 NC_DP_VDDR#AG17 NC#AF13 AF13 C 40mA AG18 NC_DP_VDDR#AG18 AG8 B AG19 NC_DP_VDDR#AG19 NC#AG8 AG10 A AF14 DP_VDDR NC#AG10 C7713 21 21 C7711 21 C7710 NC_DP_VDDC#AG20 SC10U6D3V3MX-GP SC1U10V2KX-1GP NC_DP_VDDC#AG21 SCD1U16V2KX-3GP NC_DP_VDDC#AF22 OPS NC_DP_VDDC#AG22 OPS AG20 DP_VDDC AF6 AF7 DPLL_VDDC DPLL_VDDC AG21 NC_DP_VSSR#AG14 NC#AF6 AF8 AF22 NC_DP_VSSR#AH14 NC#AF7 AF9 NC_DP_VSSR#AM14 NC#AF8 32mA AG22 NC_DP_VSSR#AM16 NC#AF9 AD14 NC_DP_VSSR#AM18 NC_DP_VSSR#AF23 C7715 C7714 AG14 NC_DP_VSSR#AG23 NC#AE1 AE1 C1U10V2KX-1GP SCD1U16V2KX-3GP AH14 NC_DP_VSSR#AM20 NC#AE3 AE3 AM14 NC_DP_VSSR#AM22 NC#AG1 AG1 OPS OPS AM16 NC_DP_VSSR#AM24 NC#AG6 AG6 AM18 NC_DP_VSSR#AF19 NC#AH5 AH5 F 6 OF 7 AF23 NC_DP_VSSR#AF20 NC#AF10 AF10 AG23 DP_VSSR NC#AG9 AG9 NC_VARY_BL AB11 AM20 NC#AH8 AH8 NC_DIGON AB12 AM22 NC_UPHYAB_DP_CALR NC#AM6 AM6 AM24 NC#AM8 AM8 AF19 JET-XT-S3-GP NC#AG7 AG7 AF20 NC#AG11 AG11 AE14 OPS NC_UPHYAB_TMDPA_TX0N AL15 BALL: AB11, AB12 NC_UPHYAB_TMDPA_TX0P AK14 R16 : NC AF17 MESO : VDDC NC_UPHYAB_TMDPA_TX1N AH16 NC_UPHYAB_TMDPA_TX1P AJ15 NC#AE10 AE10 NC_UPHYAB_TMDPA_TX2Ntro-X AL17 NC_UPHYAB_TMDPA_TX2P AK16 NC_UPHYAB_TMDPA_TX3N AH18 NC_UPHYAB_TMDPA_TX3P AJ17 NC_TXOUT_L3P AL19 NC_TXOUT_L3N AK18 TMDP NC_UPHYAB_TMDPB_TX0N AH20 <Core Design> NC_UPHYAB_TMDPB_TX0P AJ19 Wistron Corporation NC_UPHYAB_TMDPB_TX1N AL21 NC_UPHYAB_TMDPB_TX1P AK20 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, NC_UPHYAB_TMDPB_TX2N AH22 Taipei Hsien 221, Taiwan, R.O.C. NC_UPHYAB_TMDPB_TX2P AJ21 NC_UPHYAB_TMDPB_TX3N AL23 NC_UPHYAB_TMDPB_TX3P AK22 NC_TXOUT_U3P AK24 NC_TXOUT_U3N AJ23 Title 077_GPU (2/5) DIGITALOUT T-S3-GP Size Project Name Rev S Vegas SKL/KBL-U X00 Date: Friday, June 24, 2016 Sheet 77 of 105 21

5 43 Main Func = dGPU 81 DQA0_[31..0] D DQ Please MVREF drivers and Caps close to ASIC DDR3/GDDR3 Memory Stuff Option(R16) 82 DQA1_[31..0] C GDDR5 GDDR3 DDR3 MVDDQ 1.5V 1D35V 1.5V Ra 40.2R 40.2R 40.2R Rb 100R 100R 100R 1D5V_VGA_S0 1D5V_VGA_S0 Ra 2 12 1 R7817 Ra R78102 12 1 2 1 21 40D2R2F-GP 40D2R2F-GP 12 2 1 2 1 Elet OPS OPS MVREFDA MVREFSA OPS OPS SC1U10V2KX-1GP SC1U10V2KX-1GP Rb R7818 12 Rb R7814 100R2F-L1-GP-U 21 100R2F-L1-GP-U OPS C7805 OPS C7801 B Jet Setting R7809 1 OPS 2 120R2F-GP M Place all these componets very close to GPU (within 25mm) and keep all DRAM_RST_VGA1 components close to each other This basic topology should be used for DRAM_RST for DDR3/GDDR5 1D5V_VGA_S0 R7802 C7822 DY DY C7821 SCD1U16V2KX-3GP SCD1U 2K2R2J-2-GP DY 49D9R2F-GP OPS 10R2J-2-GP CLKTESTB_C R7804 CLKTESTA_C DRAM_RST_R R7803 81,82 DRAM_RST 12 1 2 DRAM_RST_VGA1 A OPS R7819 5K1R2F-2-GP C780221 21 R7821 R7820 SC120P50V2JN-1GP OPS 51D1R2F-GP 51D1R DY DY OPS 543

2 1 GPU1C 3 OF 7 DQA0_0 K27 GDDR5/DDR3 GDDR5/DDR3 K17 MAA0 81,82 ADD D DQA0_1 J29 J20 MAA1 81,82 C DQA0_2 H30 DQA0_0 MAA0_0 H23 MAA2 81,82 TP7801 B DQA0_3 H32 DQA0_1 MAA0_1 G23 MAA3 81,82 DQA0_4 G29 DQA0_2 MAA0_2 G24 MAA4 81,82 DM DQA0_5 F28 DQA0_3 MAA0_3 H24 MAA5 81,82 DQS DQA0_6 F32 DQA0_4 MAA0_4 J19 MAA6 81,82 DQA0_7 F30 DQA0_5 MAA0_5 K19 MAA7 81,82 Ctrl DQA0_8 C30 DQA0_6 MAA0_6 G20 MAA13 81,82 CLK DQA0_9 F27 DQA0_7 MAA0_7 L17 MAA15 81,82 CMD DQA0_10 A28 DQA0_8 MAA0_8 Ctrl, CS DQA0_11 C28 DQA0_9 MAA0_9 J14 MAA8 81,82 Ctrl DQA0_12 E27 DQA0_10 K14 CMD DQA0_13 G26 DQA0_11 MAA1_0 J11 MAA9 81,82 DQA0_14 D26 DQA0_12 MAA1_1 J13 DQA0_15 F25 DQA0_13 MAA1_2 H11 MAA10 81,82 DQA0_16 A25 DQA0_14 MAA1_3 G11 DQA0_17 C25 DQA0_15 MAA1_4 J16 MAA11 81,82 DQA0_18 E25 DQA0_16 MAA1_5 L15 DQA0_19 D24 DQA0_17 MAA1_6 G14 MAA12 81,82 DQA0_20 E23 DQA0_18 MAA1_7 L16 DQA0_21 F23 DQA0_19 MAA1_8 MAA_BA2 81,82 DQA0_22 D22 DQA0_20 MAA1_9 E32 DQA0_23 F21 DQA0_21 E30 MAA_BA0 81,82 DQA0_24 E21 DQA0_22 W CKA0_0 A21 DQA0_25 D20 DQA0_23 W CKA0#_0 C21 MAA_BA1 81,82 DQA0_26 F19 DQA0_24 E13 tro-X DQA0_27 A19 DQA0_25 W CKA0_1 D12 VSSRHA MAA14 81,82 1 MEMORY INTERFACEDQA0_28D18DQA0_26 W CKA0#_1 E3 DQA0_29 F17 DQA0_27 F4 DQMA0 81 DQA0_30 A17 DQA0_28 W CKA1_0 DQMA1 81 DQA0_31 C17 DQA0_29 W CKA1#_0 H28 DQMA2 81 DQA1_0 E17 DQA0_30 C27 DQMA3 81 DQA1_1 D16 DQA0_31 W CKA1_1 A23 DQMA4 82 DQA1_2 F15 DQA1_0 W CKA1#_1 E19 DQMA5 82 DQA1_3 A15 DQA1_1 E15 DQMA6 82 DQA1_4 D14 DQA1_2 EDCA0_0 D10 DQMA7 82 DQA1_5 F13 DQA1_3 EDCA0_1 D6 DQA1_6 A13 DQA1_4 EDCA0_2 G5 QSAP_0 81 DQA1_7 C13 DQA1_5 EDCA0_3 QSAP_1 81 DQA1_8 E11 DQA1_6 EDCA1_0 H27 QSAP_2 81 DQA1_9 A11 DQA1_7 EDCA1_1 A27 QSAP_3 81 DQA1_10 C11 DQA1_8 EDCA1_2 C23 QSAP_4 82 DQA1_11 F11 DQA1_9 EDCA1_3 C19 QSAP_5 82 DQA1_12 DQA1_10 C15 QSAP_6 82 DQA1_13 A9 DQA1_11 DDBIA0_0 E9 QSAP_7 82 DQA1_14 C9 DQA1_12 DDBIA0_1 C5 DQA1_15 F9 DQA1_13 DDBIA0_2 H4 QSAN_0 81 DQA1_16 D8 DQA1_14 DDBIA0_3 QSAN_1 81 DQA1_17 E7 DQA1_15 DDBIA1_0 L18 QSAN_2 81 DQA1_18 A7 DQA1_16 DDBIA1_1 K16 QSAN_3 81 DQA1_19 C7 DQA1_17 DDBIA1_2 QSAN_4 82 DQA1_20 F7 DQA1_18 DDBIA1_3 H26 QSAN_5 82 DQA1_21 A5 DQA1_19 H25 QSAN_6 82 DQA1_22 E5 DQA1_20 ADBIA0 QSAN_7 82 DQA1_23 C3 DQA1_21 ADBIA1 G9 DQA1_24 E1 DQA1_22 H9 ODTA0 81 DQA1_25 G7 DQA1_23 CLKA0 ODTA1 82 DQA1_26 G6 DQA1_24 CLKA0# G22 DQA1_27 G1 DQA1_25 G17 CLKA0 81 DQA1_28 G3 DQA1_26 CLKA1 CLKA0# 81 DQA1_29 J6 DQA1_27 CLKA1# G19 DQA1_30 J1 DQA1_28 G16 CLKA1 82 DQA1_31 J3 DQA1_29 RASA0# CLKA1# 82 J5 DQA1_30 RASA1# H22 MVREFDA DQA1_31 J22 RASA0# 81 MVREFSA K26 CASA0# RASA1# 82 J26 MVREFDA CASA1# G13 MEM_CALRP0 MVREFSA K13 CASA0# 81 J25 CSA0#_0 CASA1# 82 K25 NC#J25 CSA0#_1 K20 MEM_CALRP0 J17 CSA0#_0 81 CSA1#_0 CSA1#_1 G25 CSA1#_0 82 H10 1 L10 DRAM_RST# CKEA0 CKEA0 81 CKEA1 CKEA1 82 CLKTESTA K8 CLKTESTA CLKTESTB L7 CLKTESTB W EA0# W EA0# 81 W EA1# W EA1# 82 1 JET-XT-S3-GP U16V2KX-3GP OPS Debug only, for clock observation, if not needed, DNI 0 R2F-GP <Core Design> A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title 078_GPU (3/5) VRAM I/F Size Project Name Rev Vegas SKL/KBL-U Date: Monday, June 27, 2016 Sheet 78 of 105 21

543 Main Func = dGPU R16: DY GPU1B 2 OF 7 #3 MESO : 上上上上 RN7905 C 6 3D3V_VGA_S0 1D8V_VGA_S0 32 MESO_U1 8 4 MESO 1 MESO_U3 1 SMB_CLK_VGA_R NC#AF2 AF2 N R7903 2 DY 1 5K1R2F-2-GP TESTEN SMB_DATA_VGA_R SRN10KJ-5-GP PINs for debug NC#AF4 AF4 R7902 1 OPS 2 1KR2F-3-GP TESTEN 3D3V_VGA_S0 R7912 1 2 0R0402-PAD SMB_CLK_VGA N9 DBG_DATA16 DPA NC#AG3 AG3 XO_IN 19,24,85 DGPU_PWROK R7914 1 L9 DBG_DATA15 DPB NC#AG5 AG5 RN7904 32 XO_IN2 2 0R0402-PAD SMB_DATA_VGA AE9 DBG_DATA14 4 OPS 1 RN7902 Y11 DBG_DATA13 NC#AH3 AH3 OPS SRN4K7J-8-GP 3D3V_VGA_S0 AE8 DBG_DATA12 NC#AH1 AH1 AD9 DBG_DATA11 SRN10KJ-5-GP AC10 DBG_DATA10 NC#AK3 AK3 AD7 DBG_DATA9 NC#AK1 AK1 AC8 DBG_DATA8 DVO AC7 DBG_DATA7 NC#AK5 AK5 DY21R7942 AB9 DBG_DATA6 NC#AM3 AM3 10KR2J-3-GP AB8 DBG_DATA5 14 R7904 2DGPU_PWROK_R AB7 DBG_DATA4 NC#AK6 AK6 23 1 DY Q7903 AB4 DBG_DATA3 NC#AM5 AM5 G DY AB2 DBG_DATA2 D Y8 DBG_DATA1 NC#AJ7 AJ7 2N7002KDW-GP Y7 DBG_DATA0 NC#AH6 AH6 0R2J-2-GP NC#AK8 AK8 NC#AL7 AL7 D CLKREQ_PEG#0 18 18,24 SML1_SMBCLK 6 1 SMB_CLK_VGA_R S 18,24 SML1_SMBDATA 2 5 3 2N7002K-2-GP W6 NC#W6 V4 24 GPU_PWR_LEVEL OPS V6 NC#V6 U5 R7943 1 OPS 2 NC#V4 4 0R2J-2-GP AC6 NC#AC6 NC#U5 W3 AC5 NC#AC5 V2 Q7901 NC#W3 AA5 NC#AA5 NC#V2 Y4 SMB_DATA_VGA_R AA6 NC#AA6 DPC W5 NC#Y4 TP7918 NC#W5 AA3 R7938 Y2 NC#AA3 16K2R2F-GP NC#Y2 J8 MESO_U1 U1 NC#U1 NC#AA3 2 DY 1 MESO_U3 W1 NC#W1 NC#J8 3D3V_VGA_S0 1PLL_ANALOG_IN U3 NC#U3 NC#Y6 21 2 1 GPU_DPRSLP 1 TP7902 Y6 NC#AA1 AA1 1 R7937 2GPU_PWR_LEVEL_R Q7902 R7921 Circuit checklist G OPS OPS10KR2J-3-GP Test only, 0R0402-PAD Connect to GND through a 16.2-K resistor. D GPIO_5_AC_BATT I2C The resistor is not needed on production. S DY R7911 R1 SCL 2N7002K-2-GP 0R2J-2-GP R3 SDA U6 NC_R AM26 NC_R 1 TP7922 U10 AK26 T10 GENERAL PURPOSE I/O NC_AVSSN#AK26 R7941 GPU_DPRSLP_R 4K7R2J-2-GP U8 GPIO_0 2 MESO1 U7 AL25 Pre-PWROK METAL VID CODES T9 NC_GPIO_1 NC_G AJ25 T8 SMB_DATA_VGA T7 NC_GPIO_2 NC_AVSSN#AJ25 SMB_CLK_VGA P10 GPIO_5_AC_BATT P4 SMBDATA AH24 P2 AG25 SVC SVD Output Voltage 1 GPIO_8_ROMSO N6 SMBCLK NC_B 0 0 1.1 1 GPIO_9_ROMSI N5 0 1 1.0 1 GPIO_10_ROMSCK N3 GPIO_5_AC_BATT NC_AVSSN#AG25 1 0 0.9 Y9 1 1 0.8 85 TOPAZ_OCP N1 GPIO_6 DAC1 AH26 M4 AJ27 NC_VSYNC BALL: U10,T10,Y9,W10 TP7905 R6 NC_GPIO_7 NC_HSYNC R16: NC TP7906 W10 MESO : VDDC TP7901 M2 GPIO_8_ROMSO NC_VSYNC P8 P7 GPIO_9_ROMSI N8 AMD suggestion AK10 GPIO_10_ROMSCK AD22 R16 : DY AM10 MESO : 上上上上 N7 NC_GPIO_11 NC_RSET AG24 AE22 NC_GPIO_12 AE23 NC_GPIO_13 NC_AVDD AD23 JET_SVD NC_GPIO_14 NC_AVSSQ 1 GPIO16_VGA C TP7903 1 GPIO_17_THERMAL_INT GPIO_15_PWRCNTL_0 TP7923 JET_SVC GPIO_16 NC_VDD1DI TP7910 R7922 TP7919 1 GPIO_22_ROMCS# GPIO_17_THERMAL_INT NC_VSS1DI 2 OPS 1 TP7920 1 H_VID3 GPIO_19_CTF 1 H_VID4 NC_GPIO_18 10KR2J-3-GP GPIO_19_CTF FutureASIC/SEYMOUR/PARK GPIO_20_PWRCNTL_1 CEC_1 AM12 GPIO_21 AK12 AL11 GPIO_22_ROMCS# AJ11 MESO_SVD MESO_SVT R7919 1 2 0R0402-PAD JET_SVC GPIO_29 NC_SVI2#AK12 MESO_SVC R7920 1 85 VGA_SVC 2 0R0402-PAD JET_SVD GPIO_30 NC_SVI2#AL11 85 VGA_SVD CLKREQ# NC_SVI2#AJ11 PWR_VGA_CORE_VDDIO BALL: AB13, W9, AC14 TP7907 1 JTAG_TRST#_VGA L6 JTAG_TRST# R16: NC TP7908 1 JTAG_TDI_VGA L5 JTAG_TDI MESO : VDDC TP7911 1 JTAG_TCK_VGA L3 JTAG_TCK NC_GENLK_CLK AL13 TP7912 1 JTAG_TMS_VGA L1 JTAG_TMS NC_GENLK_VSYNC AJ13 TP7913 1 JTAG_TDO_VGA K4 JTAG_TDO TESTEN K7 TESTEN NC_SWAPLOCKA AG13 AF24 NC#AF24 NC_SWAPLOCKB AH12 12 R7940 12R7924 12R7923 10KR2J-3-GP AB13 NC_GENERICA 10KR2J-3-GP 10KR2J-3-GP W8 NC_GENERICB OPS W9 NC_GENERICC DY MESO W7 NC_GENERICD NC_GENERICE_HPD4 85 VGA_SVD R7944 1 MESO 2 0R2J-2-GP MESO_SVD AD10 NC#AJ9 PS_0 AC19 PS_0 #3 85 VGA_SVT R7945 1 MESO 2 0R2J-2-GP MESO_SVT AJ9 DBG_CNTL0 PS_1 AD19 PS_1 85 VGA_SVC R7946 1 MESO 2 0R2J-2-GP MESO_SVC AL9 PS_2 AE17 PS_2 NC_HPD1 PS_3 AE20 PS_3 12 12 12 TP7904 1 PX_EN AC14 PX_EN Elet AB16 R7925 R7934 R7939 10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP TS_A AE19 OPS MESO DY AC16 NC_DBG_VREFG PLL/CLOCK DDC/AUX AE6 BALL: AC11,AC13 AE5 R16: NC NC_DDC1CLK MESO : VDDC NC_DDC1DATA SVID PWR Sequencing NC_AUX1P AD2 PR8611 PC8607 / PR8612 PC8612 NC_AUX1N AD4 R16 R7919 R7920 0: Enable MLPS, disable GPIO PINSTRAP XTL_27M_X1_VGA AM28 1: Disable MLPS, enable GPIO PINSTRAP XTL_27M_X2_VGA AK28 NC_DDC2CLK AC11 B XTALIN NC_DDC2DATA AC13 3D3V_VGA_S0 XO_IN AC22 XTALOUT XO_IN2 AB22 NC_AUX2P AD13 XO_IN NC_AUX2N AD11 XO_IN2 NC#AD20 AD20 NC#AC20 AC20 DY2 12 1R7935 SEYMOUR/FutureASIC NC#AE16 AE16 2110KR2J-3-GP NC#AD16 AD16 GPU_DPLUS GPU_DMINUS T4 DPLUS THERMAL NC_DDCVGACLK AC1 MLPS_EN# T2 DMINUS NC_DDCVGADATA AC3 XTL_27M_X2_VGA C7903 1 OP2S SC5D6P50V2CN-1GP 1D8V_VGA_S0 13mA R5 X7901 AD17 R7901 23 R7936 AC17 GPIO28_FDO OPS 1MR2J-1-GP OPS 10KR2J-3-GP TSVDD 14 C7904 TSVSS OPS OPS SC1U10V2KX-1GP 12 XTAL-27MHZ-159-GP JET-XT-S3-GP OPS GPU thermal sen XTL_27M_X1_VGA C7901 1 OP2S SC5D6P50V2CN-1GP 3D3V_VGA_S0 3D3V_VG Note：： 21DY GPU_T8 C7501 and C7503 values determine CL value of the oscillation circuit. 21 If Negative Resistance is too low, that may cause crystal resonator stop oscillation or not easy C2615 C2616 to oscillate. SC10U6D3V3MX-GP SCD1U16V2KX-3GP If Drive Level is too high, that may cause crystal resonator abnormal oscillation or damaged the main body of quartz. GPU_DPLUS THM262 GPU_DMINUS A C2614 1 GPU T SC2200P50V2KX-2GP 2 21 3 VDD GPU T8 4 D+ A D- GPU_T_CRIT# T_CRIT# NCT7718W-GP 74.07718.0B 3D Both DXN and DXP Layout Note: width R2615 1GPU T8 2 GPU_T_CRIT_R routing 10 mil trace 0R2J-2-GP and 10 mil spacing. 543

2 1 3 AMD suggest Aperture Size = 256MB PS0 ~ PS3 Setting 11001 Cap Value (nF) Bits [5:4] R_pu (Ω) R_pd (Ω) Bits [3:1] 1D8V_VGA_S0 680 00 82 01 NC 4750 000 10 10 NC 11 8450 2000 001 4530 2000 010 8K45R2F-2-GP 2 12 1 R7926 21 6980 4990 011 OPS 4530 4990 100 3240 5620 101 PS_0 R_pu 3400 10000 110 4750 NC 111 R7927 OPS C7918 2KR2F-3-GP R_pd DY SCD082U16V2KX-GP Note: 0402 1% resistors are required. 1D8V_VGA_S0 11000 D C 8K45R2F-2-GP GEN2/GEN32 12 1 R7928 R_pu 21 PS_1 R7929 GEN2/GEN3 C7919 4K75R2F-1-GP DY SCD68U16V3KX-GP-U R_pd 680nF R7929 cgange to 2K ohm 1/21 11000 1D8V_VGA_S0 8K45R2F-2-GP 2 12 1DY R7930 21R_pu PS_2 R7931 C7920 4K75R2F-1-GP OPS DY SCD68U16V3KX-GP-U R_pd 680nF ## PS_3[3-1] => MEM_ID setting, need decide for AMD 1D8V_VGA_S0 3K24R2F-GP 2 12 1 21 VRAM R7932 tro-X PS_3 R_pu VRAM DY C7921 R7933 R_pd SCD01U50V2KX-1GP 5K62R2F-GP B Resistor PN/64.47515.6DL Capacitor 4.75Kohm: PN/64.84515.6DL 680nF: PN/78.68421.5BL 8.45Kohm: PN/64.20015.6DL PN/64.45315.6DL 82nF: PN/78.82321.2FL 2Kohm: PN/64.69815.6DL 10nF: PN/78.10324.L0L 4.53Kohm: PN/64.49915.6DL nsor 1GPU T8 2 18K7R2F-GP GPU_ALERT# 6.98Kohm: PN/64.32415.6DL 1GPU T8 2 2KR2F-3-GP GPU_T_CRIT# 4.99Kohm: PN/64.34015.6DL GA_S0 3.24Kohm: PN/64.56215.6DL PN/64.10025.6DL R2613 3.4Kohm: R2614 5.62Kohm: 10Kohm: T8 8 GPU_ALERT# SMB_CLK_VGA_R SCL 7 DY SMB_DATA_VGA_R SDA 6 5 DY ALERT# 21 GND C2617 SCD1U16V2KX-3GP P 21 B9 C2618 SCD1U16V2KX-3GP A D3V_VGA_S0 Q2605 G DY D PURE_HW_SHUTDOWN# 26,40 S R# <Core Design> 2N7002K-2-GP Wistron Corporation 84.2N702.J31 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, 2ND = 84.2N702.031 3rd = 84.07002.I31 Taipei Hsien 221, Taiwan, R.O.C. Title 079_GPU (4/5) GPIO/STRAP Size Date: Project Name Rev 105 Vegas SKL/KBL-U Monday, June 27, 2016 Sheet 79 of 2 1

5 4 3 Main Func = dGPU I C AMD schematic Review need GPU1D 10uF x 1, 2.2uFx5, 0.1uF x1, 0.01uF x1 1D5V_VGA_S0 1A MEM I/O D 21 21 21 C8001 21 21 C8003 21 C8009 21 21 C8004 H13 VDDR1 1D5V_VGA_S0 SC10U6D3V3MX-GP 21 SC1U10V2KX-1GP 21 SC1U10V2KX-1GP SC1U10V2KX-1GP H16 VDDR1 OPS 21 H19 VDDR1 OPS DY OPS J10 VDDR1 J23 VDDR1 21 21 C8042 C8005 C8006 C8014 SCD1U16V2KX-3GP J24 VDDR1 SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP SCD01U50V2KX-1GP C8007 VDDR1 DY J9 VDDR1 DY DY DY DY K10 VDDR1 K23 VDDR1 K24 VDDR1 VDDR1 K9 VDDR1 L11 VDDR1 L12 VDDR1 L13 VDDR1 L20 VDDR1 L21 L22 C8034 C8031 C8032 C8033 LEVEL SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP TRANSLATION OPS DY DY DY VDD_CT VDD_CT 1D8V_VGA_S0 13mA AA20 VDD_CT AA21 VDD_CT 21 21 C8017 AB20 SC1U10V2KX-1GP AB21 OPS 25mAC I/O 3D3V_VGA_S0 AA17 VDDR3 AA18 VDDR3 AB17 VDDR3 AB18 VDDR3 C8024 V12 NC_VDDR4#V12 SC1U10V2KX-1GP Y12 NC_VDDR4#Y12 U12 NC_VDDR4#U12 OPS 1D8V_VGA_S0 Memory phase lock loop power: Dedicated L8001 analogue power in for memory PLLs MPV18 1 OPS 2 MMZ1005S241C-GP 21 21 C8043 21 21 21 C8044 21 21 21C8045 2 1 EletPLL SC10U6D3V3MX-GP SC10U6D3V3MX-GP 21 SC1U10V2KX-1GP OPS OPS OPS MPV18 Engine phase loop power: Dedicated analogue 90mA L8 MPLL_PVDD power pin for engine PLL B 1D8V_VGA_S0 SPV18 SPV18 L8002 1 OPS 2 BLM15BD121SN1D-GP 75mA H7 C8053 C8054 SPLL_PVDD SC10U6D3V3MX-GP SC1U10V2KX-1GP OPS OPS SPV10 100mA H8 SPLL_VDDC J7 SPLL_PVSS 0D95V_VGA_S0 Engine phase loop power: Dedicated digital JET-XT-S3-GP power pin for engine PLL SPV10 L8003 1 OPS 2 BLM15BD121SN1D-GP C8055 SCD1U16V2KX-3GP SC1U10V2KX-1GP C8056 OPS OPS VGA_CORE A C8040 21 C8041 C8063 SC10U6D3V3MX-GP SC10U6D3V3MX-GP SC10U6D3V3MX-GP OPS OPS OPS 543

21 4 OF 7 1D8V_VGA_S0 0D95V_VGA_S0 POWER PCIE_PVDD AM30 0.1A C800821 21 21 21 21 2121 C8002 C8010 21DY21 C8016 PCIE 2.5A DY SC1U10V2KX-1GP 21 21 21 21SC10U6D3V3MX-GP SC10U6D3V3MX-GP SC10U6D3V3MX-GP NC#AB23 AB23 OPS OPS NC#AC23 AC23 21 D NC#AD24 AD24 21 21 21 C NC#AE24 AE24 B NC#AE25 AE25 NC#AE26 AE26 NC#AF25 AF25 NC#AG26 AG26 AMD schematic Review need 10uF x 2, 1uFx3, 0.1uF x2 0D95V_VGA_S0 PCIE_VDDC L23 C8011 C8012 21 C8013 21 C8015 21 C8057 PCIE_VDDC L24 SCD1U16V2KX-3GP SCD1U16V2KX-3GP 21 21 21SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP PCIE_VDDC L25 OPS OPS 21 PCIE_VDDC L26 OPS OPS OPS PCIE_VDDC M22 PCIE_VDDC N22 AMD ORB 10U x 6 LF145M 4.7U x 6 VGA_CORE PCIE_VDDC N23 2.2U x 16 1U x 20 PCIE_VDDC N24 PCIE_VDDC R22 PCIE_VDDC T22 PCIE_VDDC U22 PCIE_VDDC V22 CORE VDDC AA15 C8018 C8019 C8020 C8021 21 21 21 C8022 21 21 21 C8023 VDDC N15 SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP VDDC N17 VDDC R13 OPS OPS OPS OPS OPS OPS VDDC R16 VDDC R18 NC on JET VGA_CORE VDDC Y21 VDDC T12 AB13 U10 W9 Y9 W10 T10 AC14 AB12 AB11 AC11 AC13 VDDC T15 VDDC T17 C8025 C8026 C8027 C8028 C8029 C8030 VDDC T20 SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP VDDC U13 VDDC U16 OPS OPS OPS OPS OPS OPS VDDC U18 VDDC V21 VGA_CORE VDDC V15 tro-X VDDC V17 C8035 C8036 C8037 C8058 C8059 C8060 VDDC V20 SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP VDDC Y13 VDDC Y16 OPS OPS OPS OPS OPS OPS VDDC Y18 VDDC AA12 VDDC M11 VDDC N12 VDDC U11 VGA_CORE BIF_VDDC R21 0D95V_VGA_S0 21 21 BIF_VDDC U21 1.4A C8065 C8066 C8061 C8062 SC1U10V2KX-1GP SC22U6D3V3MX-1-GP SC1U10V2KX-1GP SC1U10V2KX-1GP OPS OPS OPS OPS ISOLATED 5A CORE I/O VDDCI M13 AMD ORB 10U x 2 LF145M 4.7U x 2 VGA_CORE VDDCI M15 1U x 3 1U x 3 VDDCI M16 0.1U x2 0.1U x 2 VDDCI M17 VDDCI M18 21 VDDCI M20 21 VDDCI M21 VDDCI N20 21 C8051 2 1 C8046 C8047 C8048 C8049 C8050 SCD1U16V2KX-3GP SC4D7U6D3V3KX-GPSCD1U16V2KX-3GPSC1U10V2KX-1GPSC1U10V2KX-1GP SC1U10V2KX-1GP OPS 21 21OPS C8052OPSOPS OPS SC4D7U6D3V3KX-GPVGA_CORE 21 OPS OPS <Core Design> A C8064 21 C8038 C8039 Wistron Corporation SC10U6D3V3MX-GP SC10U6D3V3MX-GP SC10U6D3V3MX-GP OPS OPS OPS 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Project Name 080_GPU (5/5) PWR/GND Rev <Project Name> Date: Thursday, June 16, 2016 Sheet 80 of 105 1 2

5 4 3 Main Func = Vram (DDR3L) 1D5V_VGA_S0 1D5V_VGA_S0 VRAM1 DQA0_[31..0] 78 B2 VDD DQ0 E3 DQA0_13 DQ1 B2 D9 VDD DQ1 F7 DQA0_12 D9 D G7 VDD DQ2 F2 DQA0_14 1D5V_VGA_S0 G7 K2 VDD DQ3 F8 DQA0_10 K2 C 1D5V_VGA_S0 K8 VDD DQ4 H3 DQA0_9 K8 78 N1 VDD DQ5 H8 DQA0_11 N1 78 N9 VDD DQ6 G2 DQA0_15 DQ2 N9 R1 VDD DQ7 H7 DQA0_8 R1 B R9 VDD DQ8 D7 DQA0_18 R9 DQ9 C3 DQA0_22 A1 VDDQ DQ10 C8 DQA0_16 A1 A8 VDDQ DQ11 C2 DQA0_21 A8 C1 VDDQ DQ12 A7 DQA0_19 C1 C9 VDDQ DQ13 A2 DQA0_23 C9 D2 VDDQ DQ14 B8 DQA0_17 D2 E9 VDDQ DQ15 A3 DQA0_20 E9 F1 VDDQ F1 H2 VDDQ LDQS F3 QSAP_1 78DQ1 H2 H9 VDDQ LDQS# G3 QSAN_1 78 H9 FBA_VREF_0 H1 VREFDQ UDQS C7 QSAP_2 78DQ2 FBA_VREF_0 H1 R7808 M8 VREFCA UDQS# B7 QSAN_2 78 R7811 M8 ZQ 78 1 OPS 2 FBA_ZQ0 L8 ODT K1 ODTA0 1 OPS 2FBA_ZQ1 L8 243R2F-2-GP L2 243R2F-2-GP N3 T2 P7 CS# CSA0#_0 78 78,82 MAA0 P3 J1 78,82 MAA1 N2 78,82 MAA0 N3 A0 RESET# J9 DRAM_RST 78,82 78,82 MAA2 P8 78,82 MAA1 P7 L1 78,82 MAA3 P2 78,82 MAA2 P3 A1 L9 78,82 MAA4 R8 78,82 MAA3 N2 M7 78,82 MAA5 R2 78,82 MAA4 P8 A2 NC#J1 T3 78,82 MAA6 T8 78,82 MAA5 P2 T7 78,82 MAA7 R3 78,82 MAA6 R8 A3 NC#J9 78,82 MAA8 L7 78,82 MAA7 R2 A9 78,82 MAA9 R7 78,82 MAA8 T8 A4 NC#L1 B3 78,82 MAA10 N7 78,82 MAA9 R3 E1 78,82 MAA11 78,82 MAA10 L7 A5 NC#L9 G8 MAA15 78,82 78,82 MAA12 78,82 MAA11 R7 J2 MAA13 78,82 78,82 MAA12 N7 A6 NC#M7 J8 MAA14 78,82 M1 M2 A7 NC#T3 M9 N8 P1 M3 A8 NC#T7 P9 T1 E7 A9 T9 D3 A10/AP B1 J7 B9 K7 A11 VSS D1 D8 K9 A12/BC# VSS E2 E8 L3 72.41K26.00U VSS F9 78,82 MAA_BA0 M2 K3 VSS G1 78,82 MAA_BA1 N8 78,82 MAA_BA0 J3 G9 78,82 MAA_BA2 M3 78,82 MAA_BA1 BA0 VSS 78,82 MAA_BA2 BA1 VSS DQ1 DQMA1 78 DQMA2 BA2 VSS 7DQ82 VSS E7 D3 VSS D7Q80 DQMA0 D7Q83 DQMA3 J7 LDM VSS K7 CLKA0 CKEA0 UDM OPS VSS CLKA0# K9 VSS 78 CKEA0 CLKA0 CK VSSQ 78 CLKA0# CK# VSSQ VSSQ 78 78 21 CKEA0 CKE VSSQ CKEA0 21 VSSQ W E# VSSQ 78 21W EA0# CAS# VSSQ 78 W EA0# L3 78 21 21CASA0#RAS#VSSQ78CASA0# K3 78 21 21RASA0#VSSQ78RASA0#J3 21 21 21 21CheckMT41K256M16HA-107G-E-GP 21 21 2 1 2 1 Elet 1D5V_VGA_S0 Place close VRAM2VDDQ ball DY DY OPS DY DY OPS Frame Buffer Patition A-Lower Half C8128 SC1U10V2KX-1GP 1D5V_VGA_S0 C8104 SC1U6D3V3KX-2GP C8111 SC1U6D3V3KX-2GP C8126 SC1U10V2KX-1GP C8102 SC1U6D3V3KX-2GP C8115 SC1U6D3V3KX-2GP OPS R7807 4K99R2F-L-GP FBA_VREF_0 1D5V_VGA_S0 Place close VRAM1 VDD ball C8147 OPS OPS R7801 DY DY DY DY DY OPS SCD1U16V2KX-3GP 4K99R2F-L-GP C8120 SC1U10V2KX-1GP A C8112 SC1U6D3V3KX-2GP C8116 SC1U6D3V3KX-2GP C8109 SC1U6D3V3KX-2GP C8106 SC1U6D3V3KX-2GP C8125 SC1U6D3V3KX-2GP 543

2 1 VRAM2 DQA0_[31..0] 78 VDD DQ0 E3 DQA0_3 DQ0 VDD DQ1 F7 DQA0_7 VDD DQ2 F2 DQA0_1 Place close VRAM1VDDQ ball D VDD DQ3 F8 DQA0_4 C VDD DQ4 H3 DQA0_2 DQ3 1D5V_VGA_S0 B VDD DQ5 H8 DQA0_5 VDD DQ6 G2 DQA0_0 0.1uF(X7R) VDD DQ7 H7 DQA0_6 K0402 ×4 VDD DQ8 D7 DQA0_29 DQ9 C3 DQA0_27 SCD1U16V2KX-3GP VDDQ DQ10 C8 DQA0_31 21 VDDQ DQ11 C2 DQA0_25 VDDQ DQ12 A7 DQA0_28 SCD1U16V2KX-3GP VDDQ DQ13 A2 DQA0_24 21 VDDQ DQ14 B8 DQA0_30 VDDQ DQ15 A3 DQA0_26 SCD1U16V2KX-3GP VDDQ 21 VDDQ LDQS F3 QSAP_0 78 DQ0 C8108 VDDQ LDQS# G3 QSAN_0 78 SCD1U16V2KX-3GP 21 DY C7 C8122 C8107 C8124 B7 DY DY OPS K1 VREFDQ UDQS QSAP_3 78 DQ3 VREFCA UDQS# L2 QSAN_3 78 ZQ T2 ODT ODTA0 78 J1 CS# J9 CSA0#_0 78 L1 A0 RESET# L9 DRAM_RST 78,82 M7 A1 T3 T7 A2 NC#J1 A9 A3 NC#J9 B3 Place close VRAM2 VDD ball E1 A4 NC#L1 G8 J2 A5 NC#L9 J8 MAA15 78,82 M1 MAA13 78,82 A6 NC#M7 M9 MAA14 78,82 1D5V_VGA_S0 0.1uF(X7R) P1 K0402 ×4 A7 NC#T3 P9 T1 A8 NC#T7 T9 A9 B1 SCD1U16V2KX-3GP B9 21 A10/AP D1 D8 SCD1U16V2KX-3GP A11 VSS E2 21 E8 A12/BC# VSS F9 SCD1U16V2KX-3GP G1 21 G9 SCD1U16V2KX-3GP 21 72.41K26.00U VSS C8103 C8105 C8119 C8121 VSS DY DY OPS DY BA0 VSS BA1 VSS BA2 VSS OPS VSS VSS LDM VSS tro-X UDM VSS VSS CK VSSQ R7805 R7810 CK# VSSQ VSSQ Single Rank, 40.2 Ohm = 64.40R25.6DL CKE VSSQ Dual Rank, 80.6 Ohm = 64.80R65.6DL VSSQ W E# VSSQ CAS# VSSQ RAS# VSSQ VSSQ MT41K256M16HA-107G-E-GP CLKA0 CLKA0# 21 R7806 2 12 1 40D2R2F-GP 1.0uF(X7R) 10uF(X5R) R7805 K0603 ×8 M0805 ×2 40D2R2F-GP DY Dual/Single Dual/Single C8114 CLKA0_CLKA0# OPS DY OPS C8146 SCD01U50V2KX-1GP C8117 SC10U6D3V3MX-GP C8113 SC1U6D3V3KX-2GP 21 Dual/Single C8110 SC10U6D3V3MX-GP SC1U10V2KX-1GP 21 21 21 21 21 10uF(X5R) 1.0uF(X7R) M0805 ×2 K0603 ×8 OPS DY DY DY C8129 C8123 SC10U6D3V3MX-GP C8127 <Core Design> SC1U6D3V3KX-2GP 21 A C8118 SC10U6D3V3MX-GP SC1U6D3V3KX-2GP 21 Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title GPU-VRAM1,2 (1/4) Size Document Number Rev A3 Date: Vegas SKL/KBL-U A00 Monday, June 27, 2016 Sheet 81 of 105 2 1

5 4 3 Main Func = Vram (DDR3L) 1D5V_VGA_S0 1D5V_VGA_S0 VRAM3 DQA1_[31..0] 78 B2 D9 B2 VDD DQ0 E3 DQA1_20 DQ6 G7 D9 VDD DQ1 F7 DQA1_16 K2 D G7 VDD DQ2 F2 DQA1_23 1D5V_VGA_S0 K8 K2 VDD DQ3 F8 DQA1_18 N1 C 1D5V_VGA_S0 K8 VDD DQ4 H3 DQA1_22 N9 78 N1 VDD DQ5 H8 DQA1_19 R1 78 N9 VDD DQ6 G2 DQA1_21 DQ4 R9 R1 VDD DQ7 H7 DQA1_17 B R9 VDD DQ8 D7 DQA1_2 A1 DQ9 C3 DQA1_6 A8 A1 VDDQ DQ10 C8 DQA1_0 C1 A8 VDDQ DQ11 C2 DQA1_5 C9 C1 VDDQ DQ12 A7 DQA1_1 D2 C9 VDDQ DQ13 A2 DQA1_4 E9 D2 VDDQ DQ14 B8 DQA1_3 F1 E9 VDDQ DQ15 A3 DQA1_7 H2 F1 VDDQ H9 H2 VDDQ LDQS F3 H9 VDDQ LDQS# G3 QSAP_6 78 DQ6 QSAN_6 78 C7 FBA_VREF_1 H1 B7 QSAP_4 M8 UDQS QSAN_4 78 R8203 UDQS# K1 78 L8 FBA_VREF_1 H1 VREFDQ ODTA1 DQ4 1 OPS 2 FBA_ZQ3 M8 VREFCA ODT L2 78 N3 R8205 ZQ T2 CSA1#_0 243R2F-2-GP P7 L8 DRAM_RST P3 1 OPS 2 FBA_ZQ2 J1 N2 J9 P8 243R2F-2-GP L1 78,81 MAA0 P2 L9 78,81 MAA1 R8 78,81 MAA0 N3 CS# M7 78 78,81 MAA2 R2 78,81 MAA1 P7 T3 78,81 78,81 MAA3 T8 78,81 MAA2 P3 A0 RESET# T7 78,81 MAA4 R3 78,81 MAA3 N2 78,81 MAA5 L7 78,81 MAA4 P8 A1 A9 78,81 MAA6 R7 78,81 MAA5 P2 B3 78,81 MAA7 N7 78,81 MAA6 R8 A2 NC#J1 E1 78,81 MAA8 78,81 MAA7 R2 G8 78,81 MAA9 78,81 MAA8 T8 A3 NC#J9 J2 78,81 MAA10 78,81 MAA9 R3 J8 78,81 MAA11 78,81 MAA10 L7 A4 NC#L1 M1 78,81 MAA12 78,81 MAA11 R7 M9 78,81 MAA12 N7 A5 NC#L9 P1 MAA15 78,81 P9 MAA13 78,81 M2 A6 NC#M7 T1 MAA14 78,81 N8 T9 M3 A7 NC#T3 B1 E7 A8 NC#T7 B9 D3 D1 A9 D8 J7 E2 K7 A10/AP E8 F9 K9 A11 VSS G1 G9 L3 A12/BC# VSS 78,81 MAA_BA0 M2 K3 78,81 MAA_BA1 N8 J3 72.41K26.00U VSS 78,81 MAA_BA2 M3 VSS 78,81 MAA_BA0 78,81 MAA_BA1 BA0 VSS 78,81 MAA_BA2 BA1 VSS DQ6 DQMA6 DQ478 DQMA4 BA2 VSS E7 D3 78 VSS DQ778 DQMA7 DQ578 DQMA5 J7 VSS K7 CLKA1 CKEA1 LDM VSS CLKA1# K9 UDM VSS 78 CKEA1 78 VSS 78 OPS CLKA1 21 CK VSSQ CLKA1# CKEA1 CKEA1 21CK# VSSQ VSSQ 78 21CKEVSSQ 21 21VSSQ 78 W EA1# 21 21W E#VSSQ 78 W EA1# L3 78 CASA1# 21 21CAS#VSSQ78CASA1# K3 78 RASA1# 21 21RAS#VSSQ78RASA1# J3 VSSQ 2 1 2 1 Elet MT41K256M16HA-107G-E-GP 1D5V_VGA_S0 Place close VRAM2VDDQ ball OPS DY DY OPS OPS DY Frame Buffer Patition A-Lower Half C8210 SC1U10V2KX-1GP 1D5V_VGA_S0 C8217 SC1U10V2KX-1GP C8216 SC1U6D3V3KX-2GP C8209 SC1U6D3V3KX-2GP C8207 SC1U10V2KX-1GP 1D5V_VGA_S0 Place close VRAM1 VDD ball OPS R8204 4K99R2F-L-GP FBA_VREF_1 DY DY DY OPS OPS DY A C8230 OPS OPS R8206 C8204 SCD1U16V2KX-3GP SC1U10V2KX-1GP 4K99R2F-L-GP C8220 SC1U10V2KX-1GP C8218 SC1U6D3V3KX-2GP C8201 SC1U6D3V3KX-2GP C8202 SC1U6D3V3KX-2GP 543

2 1 VRAM4 DQA1_[31..0] 78 Place close VRAM3VDDQ ball VDD DQ0 E3 DQA1_25 1D5V_VGA_S0 0.1uF(X7R) VDD DQ1 F7 DQA1_26 K0402 ×4 VDD DQ2 F2 DQA1_24 VDD DQ3 F8 DQA1_29 DQ7 SCD1U16V2KX-3GP VDD DQ4 H3 DQA1_27 21 VDD DQ5 H8 DQA1_30 VDD DQ6 G2 DQA1_28 SCD1U16V2KX-3GP VDD DQ7 H7 DQA1_31 21 VDD DQ8 D7 DQA1_15 DQ9 C3 DQA1_11 SCD1U16V2KX-3GP VDDQ DQ10 C8 DQA1_14 21 VDDQ DQ11 C2 DQA1_9 VDDQ DQ12 A7 DQA1_12 SCD1U16V2KX-3GP VDDQ DQ13 A2 DQA1_8 21 VDDQ DQ14 B8 DQA1_13 C8226 C8227 C8228 C8229 D VDDQ DQ15 A3 DQA1_10 C VDDQ DY OPS DY OPS B VDDQ LDQS F3 VDDQ LDQS# G3 DQ5 C7 QSAP_7 78 DQ7 B7 QSAN_7 78 Place close VRAM4VDDQ ball K1 QSAP_5 VREFDQ UDQS QSAN_5 78 DQ5 1D5V_VGA_S0 VREFCA UDQS# L2 78 ZQ T2 ODTA1 0.1uF(X7R) ODT 78 K0402 ×4 J1 CSA1#_0 CS# J9 DRAM_RST 78 SCD1U16V2KX-3GP L1 78,81 21 A0 RESET# L9 M7 SCD1U16V2KX-3GP A1 T3 21 C8223 C8225 T7 SCD1U16V2KX-3GPDY DY A9 21 B3 E1 SCD1U16V2KX-3GP G8 21 A2 NC#J1 J2 C8222 C8224 J8 A3 NC#J9 M1 DY DY M9 A4 NC#L1 P1 P9 A5 NC#L9 T1 MAA15 78,81 T9 MAA13 78,81 A6 NC#M7 MAA14 78,81 B1 A7 NC#T3 B9 D1 A8 NC#T7 D8 E2 A9 E8 F9 A10/AP G1 G9 A11 VSS A12/BC# VSS 72.41K26.00U VSS VSS BA0 VSS R7905 R7910 BA1 VSS BA2 VSS OPS VSS Single Rank, 40.2 Ohm VSS Dual Rank, 80.6 Ohm LDM VSS tro-X UDM VSS VSS CLKA1 CLKA1# CK VSSQ 21 CK# VSSQ 2 12 1 VSSQ R8201 R8202 CKE VSSQ 40D2R2F-GP 40D2R2F-GP VSSQ W E# VSSQ Dual/Single Dual/Single CAS# VSSQ RAS# VSSQ CLKA1_CLKA1# C8221 VSSQ SCD01U50V2KX-1GP MT41K256M16HA-107G-E-GP Dual/Single 1.0uF(X7R) 10uF(X5R) K0603 ×8 M0805 ×2 DY DY OPS DY C8211 C8213 C8214 SC1U6D3V3KX-2GP SC10U6D3V3MX-GP 21 C8215 SC1U6D3V3KX-2GP SC10U6D3V3MX-GP 21 C8212 SC1U6D3V3KX-2GP 21 21 21 21 10uF(X5R) 21 21 M0805 ×2 1.0uF(X7R) K0603 ×8 OPS DY DY C8205 OPS C8203 SC10U6D3V3MX-GP C8206 <Core Design> SC1U6D3V3KX-2GP 21 A C8219 SC10U6D3V3MX-GP SC1U6D3V3KX-2GP 21 Wistron Corporation C8208 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, SC1U6D3V3KX-2GP Taipei Hsien 221, Taiwan, R.O.C. Title GPU-VRAM3,4 (2/4) Size Document Number Rev A3 Date: Vegas SKL/KBL-U A00 Monday, June 27, 2016 Sheet 82 of 105 2 1

5 Elet43 D (Blanki C 43 B A 5

21 D C ing) tro-X B <Core Design> A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title GPU-VRAM5,6 (3/4) Size Document Number Rev A3 Vegas SKL/KBL-U A00 Date: Thursday, June 16, 2016 Sheet 83 of 105 21

5 Elet43 D (Blankin C 43 B A 5

21 D C tro-X ng) B <Core Design> A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title GPU-VRAM7,8 (4/4) Size Document Number Rev A3 Date: Vegas SKL/KBL-U A00 Thursday, June 16, 2016 Sheet 84 of 105 21

5 4 3 Main Func = dGPU power OPS DCBATOUT PW R_DCBATOUT_VGA_CORE2 10KR2J-3-GP PG8501 PR8501 12 PGOOD_NB 35 PHASE_NB 33 PR8502 GAP-CLOSE-PW R LGATE_NB 34 PWR_VGA_CORE_LGATE_NB 2 1 UGATE_NB 32 PWR_VGA_CORE_UGATE_LX_NB 2 1 10KR2J-3-GP PG8502 OPS 12 3D3V_VGA_S0 PR8503 1 2 10KR2F-2-GP OPS EN /D EM_VG A GAP-CLOSE-PW R PC8502 2 PG8503 12 1 SCD1U16V2KX-3GP OPS GAP-CLOSE-PW R PG8504 12 PR8546 1 2 0R2J-2-GP MESO PW R_VGA_CORE_VDDIO 1D8V_VGA_S0 PR8505 1 2 0R0402-PAD GAP-CLOSE-PW R PC8503 1 2 SC1KP50V2KX-1GP PG8505 D 3D3V_VGA_S0 12 OPS ISUMP_NB 40 PU8201_39 PU8201_36 GAP-CLOSE-PW R PG8506 12 5V_S5 GAP-CLOSE-PW R PU8501 ISUMN_NB 39 VSEN_NB 38 COMP_NB 36 BOOT_NB 31 FB_NB 37 PR8507 P PR8506 1 OPS 2 PW R_VGA_CORE_NTC_NB 1 NTC_NB BOOT2 30 PW R_VGA_CORE_BOOT2 1 OPS 2PW R_VGA_CORE__BOOT21_1O PR8508 100KR2F-L1-GP PW R_VGA_CORE_IMON_NB 2 IMON_NB UGATE2 29 PR8509 1 OPS 2 PW R_VGA_CORE_SVC 3 SVC PHASE2 28 2D2R3-1-U-GP PR8511 100KR2F-L1-GP PW R_VGA_CORE_VR_HOT# 4 VR_HOT# LGATE2 27 PR8512 PW R_VGA_CORE_SVD 5 SVD 26 PW R_VGA_CORE_UGATE2 SCD22U25V3KX 12 6 VDDIO VDDP 25 79 VGA_SVC PR8513 0R0402-PAD SVT VDD 24 PW R_VGA_CORE_PHASE2 79 TOPAZ_OCP PR8514 ENABLE 23 79 VGA_SVD 12 PWROK LGATE1 22 PW R_VGA_CORE_LGATE2 0R0402-PAD IMON PHASE1 21 PW R_VGA_CORE_VDDIO GND UGATE1 79 VGA_SVT 12 0R0402-PAD BOOT1 12 PW R_VGA_CORE_SVT 7 ISL62771H R T Z - G P- U PW R_VGA_CORE_VDD 0R0402-PAD PW R_VGA_CORE_ENABLE 8 PW R_VGA_CORE_LGATE1 PW R_VGA_CORE_PW ROK 9 74.62771.033 PW R_VGA_CORE_PHASE1 12 OPS PW R_VGA_CORE_UGATE1 0R0402-PAD PW R_VGA_CORE_BOOT1 PD8501 PW R_VGA_CORE_IMON 10 3D3V_VGA_S0 PR8515 20,86 DGPU_PW R_EN K DY AEN /D EM_VG A 21 1 OP2PSW R_VGA_CORE__BOOT1_1 C 41 2D2R3-1-U-GP SCD22U25 RB551VM-30TE-17-GP 21 86 EN /D EM_VG A PR8516 PC8511 11 NTC 2 12 1 133KR2F-GP SC1KP50V2KX-1GP 12 ISEN2 OPS OPS 13 ISEN1 14 ISUMP PE_GPIO1 is for 15 ISUMN PR8518 turning off PWR IC 16 VSEN 1KR2J-1-GP 17 RTN OPS 18 FB 19 COMP 20 PGOOD PWR_VGA_CORE_RTN PW R_VGA_CORE_PGOOD 1 PR8520 2 PWR_VGA_CORE_VSEN PW R_VGA_CORE_FB 0R0402-PAD PWR_VGA_CORE_ISUMN PWR_VGA_CORE_ISUMP PC8512 PWR_VGA_CORE_ISEN1 SC100P50V2JN-3GP PWR_VGA_CORE_ISEN2 OPS PWR_VGA_CORE_NTC 12 PR852 PR8524 PW R_VGA_CORE_COMP PC8514 OPS 2 OP 100KR2F-L1-GP 2 1 301R2F- OPS PR852 SC180P50V2JN-1GP PR8526 1 OPS 2OPS1PW R_VGA_CORE_FB2_R1 OPS 2 1K13R2F 33KR2F-GP PR852 1 OP 2KR2F 21 PC8515 Elet PR8528 SC330P50V2KX-3GP 32K4R2F-1-GP 21 DY 21 PC8517 PC8518 OPS OPS SCD22U10V2KX-1GP SCD22U10V2KX-1GP PR85291VGA_VSUM-2_1 1 OPS 2K61R2F-1-GP PR8530 1 2 PR8531 1 2 10R2J-2-GP OPS 0R0402-PAD 21 PR8532 21 21 VGA_VDD_RUN_FB_L 1 SCD1U25V2KX-GP B PC8522 PC8523 OPS TP8501 SCD022U16V2KX-3GP OPS 11KR2F-L-GPDY PC8501 2 1 SCD01U50V2KX-1GP OPS PC8524 PR8533 1DY 2 NTC-10K-29-GP-U SC330P50V2KX-3GP VGA_VDD_RUN_FB_H 1 OPS 1 PR8534 2 TP8502 0R0402-PAD PR8535 2 1 10R2J-2-GP OPS VGA PW R_VGA_CORE_VSUM- 2 1 OPS 2 PR8536 1K96R2F-1-GP PC8525 21 SCD1U25V2KX-GP OPS PW R_VGA_CORE_PW ROK PW R_VGA_CORE_PGOOD 3D3V_S5 100KR2J-1-GP PR8539 2 DY 1 PW R_VGA_CORE_EN_R# PQ8501 16 2N7002KDW -GP 25 34 12 VGA_CORE A DY PR8545 100R2J-2-GP DY EN /D EM_VG A PQ8206_3 543

21 DCBATOUT PW R_DCBATOUT_VGA_CORE1 PG8511 12 GAP-CLOSE-PW R PG8512 12 GAP-CLOSE-PW R Main source: 84.03660.037 PG8513 12 GAP-CLOSE-PW R PW R_DCBATOUT_VGA_CORE1 PG8514 12 PU8502 PU8503 PC8527 PC8526 F D MS3600- 02- R J K0215- C O LAY- G P F D MS3600- 02- R J K0215- C O LAY- G P OPS OPS GAP-CLOSE-PW R 2 SC4D7U25V5KX-GP PG8515 3 21 12 14 10 SC4D7U25V5KX-GP 9 21 7 21 86 21 5 12 2 SCD1U25V2KX-GPPC8528PC8529PC8530 D 3 SC10U25V5KX-GP C 4 SC10U25V5KX-GPOPS OPS OPS B 10 GAP-CLOSE-PW R 1 PG8516 7 12 695 BOM 6 5 GAP-CLOSE-PW R 8 ZZ.00215.037 ZZ.00215.037 5V_S5 PC8507 PR8510 OP2S 1R2F-GP TDC=34A OCP<??A X-GP tro-X 1 2 PW R_VGA_CORE_UGATE1 VGA_CORE 21 SC1U10V2KX-1GP OPS PC8508 OPS 12 PW R_VGA_CORE_PHASE1 PL8501 OPS PW R_VGA_CORE_LGATE1 12 IN D - D 33U H - 7- G P- U 68.R3310.201 PC8509 SC1U10V2KX-1GP 2 12 1 SE330U2VDM-4-GP SE330U2VDM-4-GP GAP-CLOSE-PWR-3-GP PWR_VGA_CORE_VO1 PG8508 PG8507 PWR_VGA_CORE_PH1 GAP-CLOSE-PWR-3-GP OPS PR8541 12 2D2R3J-2-GP 12 PT8507 21 21OPS DY PT8506 PC8510 PW R_VGA_SNUB1 OPS 11 2 PC8506 DY OPS SC330P50V2KX-3GP 5V3KX-GP PW R_VGA_CORE_ISUMP PR8517 79.33719.20C79.33719.20C PW R_VGA_CORE_ISEN1 DGPU_PW ROK 19,24,79 PW R_VGA_CORE_VSUM- 1 OPS 2 PC8513 3K65R2F-1-GP OPS 2 1R2F-GP PR8519 OPS 1 OPS 2 2 10KR2J-3-GP 10KR2F-2-GP PR8521 1 23 PW R_VGA_CORE_FB_R 2 OPS1 PS 1 SC1KP50V2KX-1GP PW R_VGA_CORE_ISEN2 PR8522 1 -GP PW R_VGA_CORE_VSEN 25 Main source: 84.03660.037 PW R_DCBATOUT_VGA_CORE2 S2 PW R_VGA_CORE_COMP_1 PC8516 PC8520 PC8532 F-1-GP 1 OPS2 PU8504 PU8505 OPS OPS 27 F D MS3600- 02- R J K0215- C O LAY- G P F D MS3600- 02- R J K0215- C O LAY- G P SC4D7U25V5KX-GP PS 2 21 2 F-3-GP 3 SC4D7U25V5KX-GP 14 21 10 21 9 21 7 12 SC330P50V2KX-3GP 86 SCD1U25V2KX-GPPC8519PC8531 PC8521 5 SC10U25V5KX-GP 2 SC10U25V5KX-GPOPS OPS OPS 3 1 4 10 659 BOM 7 8 6 5 ZZ.00215.037 ZZ.00215.037 A_CORE PW R_VGA_CORE_UGATE2 VGA_CORE 1 PR8544 2 PW R_VGA_CORE_PHASE2 PL8502 OPS 0R0402-PAD PW R_VGA_CORE_LGATE2 12 PR8542 2 12 1 IN D - D 33U H - 7- G P- U PC8534 PC8535 2D2R3J-2-GP 12 68.R3310.201 DY PG8509 PG8510 12 21 21 21 SC22U6D3V3MX-1-GPPT8508 OPS SC22U6D3V3MX-1-GP SE330U2VDM-4-GP PWR_VGA_CORE_VO2 GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP PWR_VGA_CORE_PH2 79.33719.20C OPS PW R_VGA_SNUB2 OPS PC8533 SC330P50V2KX-3GP DY PR8537 PW R_VGA_CORE_ISUMP 1 OPS 2 3K65R2F-1-GP PR8538 PW R_VGA_CORE_ISEN2 1 O2PS 10KR2F-2-GP A PW R_VGA_CORE_VSUM- PR8540 1 OPS 2 1R2F-GP <Core Design> PW R_VGA_CORE_ISEN1 PR8543 1 OPS 2 10KR2J-3-GP Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Document Number Sheet 85 of Rev A2 Monday, June 27, 2016 A00 D ate: 105 2 1

5 4 3 Main Func = dGPU GPU PWR Sequencing 3D3V_S0 to 3D3V_VGA_S0 Transfer 3D3V_VGAS0 => 0D95V_VGA_S0/1D8V_VGA_S0 3D3V_S0 3D3V_VGA_S0 => 1D5V_VGA_S0 3D3V_S5 PR8601 1 DY 2 0R2J-2-GP 25mA => VGA_CORE D OPS All the ASIC supplies must reach their respective nominal 3D3V_VGA_S0 SD voltages withing 20ms of the start of the ramp-up sequence, though a shorter ramp-up duration is preferred. The maximum 084.03419.0031 PQ8609 slew rate on all rails is 50mV/us. It is recommended that the 3.3V rail ramp up first. PC8603 21 PC8601 PJA3419-GP It is recommended that the 0.95V rail reach at least 90% of its DY 21 normal value no later than 2ms from the start of VDDC ramping 21 up. 21 PR8606 PR8619 16 G 100KR2J-1-GP OPS 100KR2J-1-GP SCD1U16V2KX-3GP 3.3V_RUN_VGA_1 1 2 SCD1U16V2KX-3GPPC8605 PC8604 DY DY SC22U6D3V5MX-2GPDY DY SC22U6D3V5MX-2GP 21 3.3V_ALW_1 DY PR8609 21 75R2F-2-GP 3D3V _V GA discharge PQ8604 25 34 2N7002KDW-GP OPS 20,85 DGPU_PWR_EN PR8661 2 DGPU_PWR_EN_R 1 High Activ e 21 OPS 10KR2J-3-GP OPS PC8602 SCD47U25V3KX-1GP C DCBAT OUT PWR_DCBAT OUT _1D35V PG8651 GAP-CLOSE-PWR-3-GP 12 3D3V_S5 PG8652 21 21 GAP-CLOSE-PWR-3-GP PC8655 OPS 12 SC1U10V2KX-L1-GP PC8656 MagLayer. 6.86 x 6.47 x 3.0mm SCD1U25V2KX-L-GP DCR: 5~5.5mOhm PR8674 0R0603-PAD-1-GP-U PWR_1D35V_BOOT 1 2PWR_1D35V_BOOT_A 1OPS2 PL8651 Idc :15.5A , Isat : 25A design current = 3.56A PU8651 IND-D68UH-36-GP-U 1D5V_VGA_S0 PWR_1D35V_VCC PWR_1D35V_VCC 17 OPS 6 PWR_1D35V_PH 1 OPS 2 15 19 VCC LX#6 20 68.R681A.10A DY B YP LX#19 PC8661 OPS PC8654 LX#20 21PC8657PC8658 PC8659 PC8660 21 PWR_DCBAT OUT _1D35V SC2D2U10V3KX-L-GP 2 I N#2 NC # 1 0 10 PWR_1D35V_PG 12 21OPSOPSOPSOPS 3 I N#3 NC # 1 2 12 PWR_1D35V_VCC 21 4 I N#4 NC # 1 6 16 PG8653 21 5 I N#5 GAP-CLOSE-PWR-3-GP B Elet 21 PWR_1D35V_EN 21 PWR_1D35V_BOOT PC8651 PWR_1D35V_PG 11 EN G ND 7 PWR_1V35V_ILMT 1 BS G ND 8 OPS OPS PC8652 PWR_1D35V_FB 9 PG G ND 18 SC22U6D3V5MX-L3-GP I LMT G ND 21 SC22U6D3V5MX-L3-GP 13 FB PWR_1D35V_FB_A SC22U6D3V5MX-L3-GP 14 SC22U6D3V5MX-L3-GP SC22U6D3V5MX-L3-GP SCD1U25V2KX-L-GP SC10U25V5KX-L-GP 2 12 1 PR8673 SY8286RAC-GP PC866221 PR8675 100KR2J-1-GP 074.08286.0B43 SC470P50V2KX-L-GP OPS OPS 24K9R2F-L-GP 3D3V_S5 1 OPS 2 T P8601 PG8654 VOUT=0.6*(1+(R1/R2)) T PAD14-OP-GP GAP-CLOSE-PWR-3-GP 11D35V-PG 1 2 PR8677 OPS PR8676 0R2J-2-GP 16K5R2F-2-GP PG8655 1 DY 2 PWR_1D35V_VCC GAP-CLOSE-PWR-3-GP 0D95V_VGA_S0_PG 21 12 21 PR8671 0R0402-PAD-1-GP EN rating 23V PR8672 EN Rising Threshold : 0.8V 1MR2J-1-GPOPS ILIM LOW , ILIM=6.5A D8602 ILIM FLOAT , ILIM=9.5A 2 ILIM HIGH , ILIM=12.5A 85 EN/DEM_VGA OPS 3 3.3V_RUN_VGA_1 PWR_1D35V_EN 1 BAT 54C-7-F-3-GP 75.00054.E7D A 2nd = 83.R2003.W81 3rd = 75.00054.A7D 4th = 83.R2003.V81 543

2 1 1D8V_VGA_S0 1D8V_S5 PQ8607 1D8V_VGA_S0 400m A DMP2130L-7-GP D OPS S D SCD1U16V2KX-3GP D G 21 21 SCD1U16V2KX-3GP 1D8V_VGA_EN#2 1 21 G 21 OPS PC8636 PC8635 OPS PR8650 10KR2J-3-GP DY PC8634 DY SC1U10V2KX-1GP PR8651 1 OPS 2 1D8V_VGA_EN_R# 2K2R2J-2-GP 84.02130.031 2nd = 84.00102.031 PR8603 1D8V_VGA_EN PQ8608 0D95V_VGA_EN 1 OPS 2 G OPS 1KR2J-1-GP PC8612 D 3rd = 84.03413.B31 OPS SCD22U10V2KX-1GP S 2N7002K-2-GP SYW232 for 0.95V_S5 C B PWR_0D95V_PVDD 3D3V_S5 PG8601 21 21 21 21 GAP-CLOSE-PWR PC8621 DY PC8622 PC8623 PG8602 OPS 21 GAP-CLOSE-PWR SC22U6D3V3MX-1-GPOPS SC22U6D3V3MX-1-GP PU8601 SC22P50V2JN-4GP Design Current =1.35A 3D3V_VGA_S0 5 NC#5 IN 3 SC1U10V2KX-1GP SC10U6D3V3MX-GP OPS 1 SC10U6D3V3MX-GP PWR_0D95V 0D95V_VGA_S0 2 OPS 8 SGND FB 6 PWR_0D95V_FB PL8601 PG8603 7 0D95V_VGA_S0_PG 1 OPS PC8624 12 21 4 P G ND PG PWR_0D95V_PHASE 2 9 P G ND LX 0D95V_VGA_EN_R GAP-CLOSE-PWR EN PG8604 PR8625 10KR2J-3-GP SYW232DFC-GP IND-1UH-281-GP 21R1 21 12 OPS 74.00232.033 PR8622 GAP-CLOSE-PWR 0D95V_VGA_EN 30K1R2F-L-GP OPS tro-X 1 PR8621 2 PC8625 PC8626 0R0402-PAD 21 21 21 PWR_0D95V_FB 21 DY PC8607 OPS OPS SCD1U16V2KX-3GP 0D95V_VGA_EN_R 2 D8601 PR8623 21OPSR2 OPS 3 3.3V_RUN_VGA_1 51K1R2F-GP 1D8V_VGA_EN 1 3D3V_S5 Close Pin1 BAT 54C-7-F-3-GP Vo=0.6x(1+R1/R2) 75.00054.E7D =0.6x(1+30.1/51.1) =0.953 2nd = 83.R2003.W81 OPS PR8624 3rd = 75.00054.A7D 10KR2J-3-GP 4th = 83.R2003.V81 0D95V_VGA_S0_PG For power down sequence 2015/02/09 modify 2015/02/09 modify A <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin T ai Wu Rd., Hsichih, T aipei Hsien 221, T aiwan, R.O.C. T itle GPU Discrete Power Size Document Number Rev A00 Custom Vegas SKL/KBL-U 105 Date: Monday, June 27, 2016 Sheet 86 of 21

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321 D C tro-X B <Core Design> Wistron Corporation A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Document Number Reserved Rev Size Vegas SKL/KBL-U A00 A4 Thursday, June 16, 2016 Sheet 87 of 105 Date: 321

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3 21 D ng) C 3 tro-X B <Core Design> Wistron Corporation A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Document Number Reserved Rev Size Vegas SKL/KBL-U A00 A4 Thursday, June 16, 2016 Sheet 88 of 105 Date: 21

5 4 3 Main Func = UnusedParts H1 H2 H3 H4 H5 H6 H7 H8 H9 HOLE335R178-GP HOLE335R178-GP HOLE335R178-GP HOLE335R178-GP HOLE335R178-GP HOLE335R178-GP HOLE335R178-GP HOLE335R178-GP HOLE335R115-G D ZZ.00PAD.7F1 ZZ.00PAD.7F1 ZZ.00PAD.7F1 ZZ.00PAD.7F1 ZZ.00PAD.7F1 ZZ.00PAD.7F1 ZZ.00PAD.7F1 ZZ.00PAD.7F1 ZZ.00PAD.D01 11 1 SPR5 1 1 1 1 1 1 1 1 1 1 1 SPR3 SPR4 SPRING-63-GP SPR1 SPR2 SPRING-43-GP-U SPRING-63-GP SPRING-63-GP SPRING-63-GP 34.4Y806.001 34.4Y806.001 Spring Spring Spring 34.4Y806.001 Spring Spring 34.4Y806.00134.15J03.001 C Main Func = EMI & RF Capacitors For RF solution DVT1 3/2 3D3V_S0 5V_S0 +VC Mind the voltage rating of the caps. FC9702 FC9703 FC9704 FC9706 F DCBATOUT DY DY 21 DY DY 21 21 21 Elet2 1 SCD1U25V2KX-GP SCD1U25V2KX-GP 21 EC9710 21 21 SCD1U25V2KX-GPEC9701EC9702EC9703EC9704 EC9708 EC9705 EC9706 EC9707 EC9709 SC1U10V2KX-1GP 21 21 SC1U10V2KX-1GP SCD1U25V2KX-GP SCD1U25V2KX-GP SC1U10V2KX-1GP 21 21 SC1U10V2KX-1GP SCD1U25V2KX-GP SCD1U25V2KX-GP SC1KP50V2KX-1GP 21 21 SC1KP50V2KX-1GP SCD1U25V2KX-GP 21 21 SCD1U25V2KX-GP SCD1U25V2KX-GP 21 21 SCD1U25V2KX-GP 21 21 SCD1U25V2KX-GP 21 EC9717 SC1KP50V2KX-1GPEC9711EC9712EC9713EC9716EC9715EC9714 SC1KP50V2KX-1GP SC1KP50V2KX-1GP B 1D2V_S3 EC8901 EC8902 EC8903 EC8904 EC8905 EC8906 EC8907 EC8908 EC8 21 21 SCD1U25V2KX-GP 21 21 21 21 21 21 21 21 21 21 21 5V_S0 SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP EC9720 EC9719 EC9718 EC9723 EC9721 EC9722 EC9724 DY DY DY DY DY DY 21 EC8911 EC8912 EC8913 EC8914 EC8915 21 DY 21 21 21 21 21 SC1U10V2KX-1GP SC1U10V2KX-1GP SCD1U25V2KX-GP 3D SC1U10V2KX-1GP SCD1U25V2KX-GP SC1U10V2KX-1GP SCD1U25V2KX-GP DY SC1U10V2KX-1GP SCD1U25V2KX-GP SC1U10V2KX-1GP SCD1U25V2KX-GP SC1U10V2KX-1GP A 543

21 H11 H14 H16 HT85BE95R29-U-5-GP H10 HT85B85X925R29-S-GP H12 H13 HT85B85X925R29-S-GP H15 H17 HOLE384X421R115-GP GP HOLE335R115-GP HOLE335R115-GP HOLE335R115-GP HOLE276R91-GP 1 ZZ.00PAD.D81 ZZ.00PAD.D81 D 1 C 1 1 1 1 1 21 1 21 1 1 ZZ.00PAD.D01 ZZ.00PAD.D01 ZZ.00PAD.D01 ZZ.00PAD.CZ1 ZZ.00PAD.D31 ZZ.SCREW.681 HS1 For acoustic noice STF236R128H101-2-GP DCBATOUT DCBATOUT 34.4YG18.101 PT8901 SE33U25VM-10-GPPT8902 Spring SE33U25VM-10-GP DY DY 79.33612.6CL 79.33612.6CL CCGT 1D5V_VGA_S0 AUD_AGND t2ro-1X 21 21 21 21 21 21 21 21 21 21 21 21 FC9707 FC9708 EC9727 EC9725 EC9726 EC9730 EC9728 EC9729 EC9731 DY DY DY DY DY DY DY DY DY EC9739 EC9744 EC9743 EC9745 SC1U10V2KX-1GP SC1U10V2KX-1GP DY DY DY DY SC1U10V2KX-1GP SC1KP50V2KX-1GP SC1U10V2KX-1GP SCD1U25V2KX-GP SC1U10V2KX-1GP SCD1U25V2KX-GP SC1U10V2KX-1GP SCD1U25V2KX-GP SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP B VGA_CORE DCBATOUT EC9741 EC9742 EC9747 EC9748 EC9749 EC9746 EC9750 EC9751 EC9752 EC9753 EC9740 21 21 21 8909 EC8910 21 21 21 21 DY 21 12 DY DY DY DY DY DY DY SCD1U25V2KX-GP 21 SCD1U25V2KX-GP 12 SCD1U25V2KX-GP 21 12 SCD1U25V2KX-GP SC1KP50V2KX-1GP SCD1U25V2KX-GP SCD1U25V2KX-GP SC1KP50V2KX-1GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP D3V_S0 5V_S5 EC9737 EC9735 EC9736 EC9738 EC9734 EC9732 EC9733 DY DY 21 <Core Design> A 21 21 21 21 21 21 Y DY DY DY DY SC1U10V2KX-1GP SC1U10V2KX-1GP Wistron Corporation SC1U10V2KX-1GP 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, SC1U10V2KX-1GP SC1U10V2KX-1GP Taipei Hsien 221, Taiwan, R.O.C. SC1U10V2KX-1GP SC1U10V2KX-1GP Title UNUSED PARTS/EMI Capacitors Size Document Number Rev A3 Vegas SKL/KBL-U A00 Date: Thursday, June 16, 2016 Sheet 89 of 105 1 2

5 Elet43 D (Blanking C 43 B A 5

3 21 D g) C 3 tro-X B <Core Design> Wistron Corporation A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Document Number Reserved Rev Size Vegas SKL/KBL-U A00 A4 Thursday, June 16, 2016 Sheet 90 of 105 Date: 21

5 4 3 SSID = TPM 3D3V_TPM_1 3D3V_TPM D C9103 SCD1U16V2KX-3GP 3D3V_S5 3D3V_TPM 3D3V_S0 R9108 TPM 1 DY 2 C9102 SCD1U16V2KX-3GP 0R3J-0-U-GP TPM 1 R9114 2 C9104 SCD1U16V2KX-3GP 0R0603-PAD TPM C9101 SC10U6D3V3MX-GP TPM C9105 SCD1U16V2KX-3GP TPM C9106 SC10U6D3V3MX-GP TPM 21 3D3V_S5 3D3V_TPM_1 U9101 21 1 R9110 21 10 VDD 21 2 21 19 VHIO 21 0R0603-PAD 24 VHIO C Elet 5 VSB 18,24,68 LPC_LAD[3..0] LPC_LAD[3..0] LPC_LAD0 R9103 0R2J1-2-GP 2 TPM LPC_LAD0_TPM 26 LAD0 LPC_LAD1 R9111 0R2J1-2-GP 2 TPM LPC_LAD1_TPM 23 LAD1 LPC_LAD2 R9112 0R2J1-2-GP 2 TPM LPC_LAD2_TPM 20 LAD2 LPC_LAD3 R9113 0R2J1-2-GP 2 TPM LPC_LAD3_TPM 17 LAD3 17,24,31,40,55,61,68,76 PLT_RST# TPM 0R0402-PAD1 R9117 2 PLT_RST#_TPM 16 LRES 18 PCI_CLK_LPC0 R9109 0R2J1-2-GP 2 CLK_PCI_LPC_TPM 21 LCLK 0R0402-PAD1 R9101 2 LPC_LFRAME#_TPM 22 LFRA 18,24,68 LPC_LFRAME# 0R0402-PAD1 R9102 2 SERIRQ_TPM 27 SERI 0R0402-PAD1 R9118 2SUS_STAT#/LPCPD#_TPM 28 LPCP 18,24 SERIRQ 18 SUS_STAT#/LPCPD# NPCT 071.0 B A 543

321 D 3D3V_S0 1 SDA/GPIO0 1 GPIO0_TPM R9106 1 DY 2 0R2J-2-GP GPIO1/SCL 2 GPIO1_TPM R9105 O GPX/GPIO2 6 GPIO2_TPM R9104 1 DY 2 0R2J-2-GP O GPIO3/BADD 9 GPIO3_TPM R9107 1 DY 2 0R2J-2-GP CLKRUN#/GPIO4/SINT# 15 1 DY 2 0R2J-2-GP CLKRUN#_TPM 1 2 7 CLKRUN# 18,24 C 8 PP TPM TEST 3 12 R9116 0R2J-2-GP NC#3 13 0/MISO TPM NC#12 14 1/MOSI NC#13 2/SPI_IRQ# RESERVED 4 3 11 tro-X 18 SET#/SPI_RST#/SRESET# GND 25 K/SCLK GND AME#/SCS# GND IRQ GND PD# T650JBAW X-GP 00650.0G0W B <Core Design> Wistron Corporation A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Document Number TPM Rev Size Vegas SKL/KBL-U A00 A4 Monday, June 27, 2016 Sheet 91 of 105 Date: 321

5 4 3 SSID = Finger Print R9203 1 USB_PN3_C 2 USB_PP3_C 16 USB_CPU_PN3 16 USB_CPU_PP3 0R0402-PAD For EMI Reserved D EC9201 DY EC9202 DY R9204 1 2 0R0402-PAD 1 2 USB_PP3_C 1 2 USB_PN3_C SC22P50V2JN-4GP SC22P50V2JN-4GP 3D3V_S0 Layout Note: 3D3V_S0 5V_S0 close to FPR1 C C9203 2 12 1 FPR R9205 10KR2J-3-GP R9202 21 DY R9201 SCD1U16V2KX-3GP FPR1 0R0402-PAD 210R2J-2-GP 7 1 DY 2 Reset_N Elet USB_PP3_C 3 FPR USB_PN3_C 4 FP_PW R 5 6 21 8 21 C9202 FPR C9201 FPR HRS-CON6-15-GP SC1U10V2KX-1GP 020.K0237.0006 B SCD1U16V2KX-3GP AFTE14P-GP AFTP8902 1 FP_PW R AFTE14P-GP AFTP8903 1 USB_PN3_C AFTE14P-GP AFTP8904 1 USB_PP3_C A 543

21 D C tro-X B <Core Design> A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Finger Print Size Document Number Rev A3 Vegas SKL/KBL-U A00 Date: Monday, June 27, 2016 Sheet 92 of 102 21

5 Elet43 D (Blanki C 43 B A 5

21 D C ing) tro-X B <Core Design> A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size (Reserved) Rev A3 Document Number A00 Vegas SKL/KBL-U Date: Thursday, June 16, 2016 Sheet 93 of 105 21

5 Elet43 D (Blanki C 43 B A 5

21 D C ing) tro-X B <Core Design> A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size (Reserved) Rev A3 Document Number A00 Vegas SKL/KBL-U Date: Thursday, June 16, 2016 Sheet 94 of 105 21

5 Elet43 D (Blanki C 43 B A 5

21 D C ing) tro-X B <Core Design> A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size (Reserved) Rev A3 Document Number A00 Vegas SKL/KBL-U Date: Thursday, June 16, 2016 Sheet 95 of 105 21

5 Elet43 D (Blanking) C 43 B A 5

321 D C tro-X B <Core Design> Wistron Corporation A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Document Number (Reserved) Rev Size Vegas SKL/KBL-U A00 A4 Thursday, June 16, 2016 Sheet 96 of 105 Date: 321

5 Elet43 D (Blanking) C 43 B A 5

321 D C tro-X B <Core Design> Wistron Corporation A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title LVDS_Switch Size Document Number Rev A4 Date: Vegas SKL/KBL-U A00 Thursday, June 16, 2016 Sheet 97 of 105 321

5 Elet43 D (Blanking C 43 B A 5

21 D C g) tro-X B <Core Design> A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title CRT_Switch Size Document Number Rev A3 Date: Vegas SKL/KBL-U A00 Thursday, June 16, 2016 Sheet 98 of 105 21

5 4 Elet3 3 D test point test point PCH_JTAG_TMS test point XDP_TMS test point PCH_JTAG_TDI 4 XDP_TDI XDP_TCLK XDP_TCK_JTAGX XDP_TDO_CPU PCH_JTAG_TDO C B A 5

321 D C tro-X B <Core Design> Wistron Corporation A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title CPU_XDP;PCH_XDP Size Document Number Rev A4 Vegas SKL/KBL-U A00 Date: Thursday, June 16, 2016 Sheet 99 of 105 321

5 43 CLK Block Diagram Intel C Haswell D SA_CLK0 DDR3L CK0 M_A_DIMA_CLK_DDR0 SA_CLK#0 M_A_DIMA_CLK_DDR#0 CK0# SA_CLK1 M_A_DIMA_CLK_DDR1 SA_CLK#1 DIMM1 M_A_DIMA_CLK_DDR#1 CK1 CK1# CK FBA_CLK0P C VRAM1 VGA CK# FBA_CLK0N N15V-GM-S-A2 CK FBA_CLK0P GB2-64 (23x23) CLK_PCIE_VGA# CLKOUT_PCIE_N4 CLK_PCIE_VGA CLKOUT_PCIE_P4 VRAM2 FBA_CLK0‧N ‧ FBA_CLK0 PEX_REFCLK# CK# FBA_CLK0# PEX_REFCLK CK FBA_CLK1P XTAL_IN 27MHZ_IN FBA_CLK1N VRAM3 X7601 Elet CK# FBA_CLK1P 27MHz CK FBA_CLK1‧N ‧ FBA_CLK1 XTAL_OUT 27MHZ_OUT FBA_CLK1# VRAM4 CK# B RTC_X1 RTCX1 X1901 RTC_X2 RTCX2 32.768KHz XTAL24_IN XTAL24_IN X1801 24MHz XTAL24_OUT XTAL24_OUT A 543

21 CPU D l/Broadwell ULT CLKOUT_PCIE_P2 CLK_PCIE_WLAN_P3 REFCLKP0 WLAN CLKOUT_PCIE_N2 CLK_PCIE_WLAN_N3 REFCLKN0 NGFF CLKOUT_PCIE_P3 CLK_PCIE_LAN_P4 LAN CLKOUT_PCIE_N3 CLK_PCIE_LAN_N4 RTL8106E/RTL8111G REFCLK_P C REFCLK_N LANXIN CKXTAL1 4 X3001 25MHz 4 tro-X LANXOUT CKXTAL2 RN2102 Audio Realtek HDA_BCLK/I2S0_SCLK HDA_BITCLK HDA_CODEC_BITCLK BITCLK ALC3223 SRN33J-5-GP-U B R5815 SUSCLK_NGFF NGFF 0R2J-2-GP SUS_CLK SUSCLK/GPIO62 ‧SUS_CLK_PCH R1710 SUS_CLK R2441 SUS_CLK_KBC KBC CLKOUT_LPC_1 0R2J-2-GP 0R2J-2-GP NPCE285P GPIO0/EXTCLK/F_SDIO3 CLK_PCI_KBC_R R1805 CLK_PCI_KBC 0R2J-2-GP LCLK/GPIOF5 CLKOUT_LPC_0 CLK_PCI_LPC_R R1804 CLK_PCI_LPC LPC 0R2J-2-GP CLKOUT_ITPXDP# Test Point CLKOUT_ITPXDP_P A <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title CLK Block Diagram Size Document Number Rev A2 Vegas SKL/KBL-U A00 Date: Thursday, June 16, 2016 Sheet 100 of 105 21

5 4 3 3 Change notes - Modify List DATE VERSON DATE Page 4 D C Elet B A 5