Eletro-X_VEGAS TURIS SKL-KBL (15341-1 91N85)

2 1 D OWNER C tro-X B <Core Design> A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Change History Rev Document Number Size A00 A3 Vegas SKL/KBL-U 105 Date: Thursday, June 16, 2016 Sheet 101 of 21

5 43 SKL-U/Y Timing Diagram for G3 to S0/M0 [Non Deep Sx Platform] KBL-U/Y Timing Diagram for G3 to S0/M0 [Non Deep Sx Platform] D C Elet For DDR4 power sequence 2D5V_S3 B 1D2V_S3 0D6V_S0 AMD GPU Power sequence 3D3V_VGAS0 => 0D95V_VGA_S0/1D8V_VGA_S0 => 1D5V_VGA_S0 => VGA_CORE 20ms All the ASIC supplies must reach their respective nominal voltages withing of the start of the ramp-up sequence, though a shorter ramp-up duration is preferred. The maximum slew rate on all rails is 50mV/us. It is recommended that the 3.3V rail ramp up first. It is recommended that the 0.95V rail reach at least 90% of its normal value no later than 2ms from the start of VDDC ramping up. 3D3V_VGA_S0 0D95V_VGA_S0/1D8V_VGA_S0 A 1D5V_VGA_S0 VGA_CORE 5 4 3

Tulip Skylake POWER 2 SEQUENCE DIAGRAM (NON Deep Sx 1 Red: Power Rail UP Platform) Orange: Output from KBC Light Blue: Output from CPU DC BT+ SI7121DN-T1-GE3 d a Battery +DC_IN Page43 3V_5V_EN Page43 Page43 V8P10-5300M3-86A AC a Adapter in SI7121DN-T1-GE3 Page43 Page43 AD+ EN1 EN2 e D 3D3V_S5 C B Charger DCBATOUT VIN TPS51225RUKR BQ24770RUYR DC/DC (3.3V/5V) ACOK 5V_S5 Page44 35 Page45 DDR_VTT_PG_CTRL Level SM_PGCNTL_R f b PWR_CHG_ACOK d 3D3V_AUX_S5 Shifter R2469 3V_5V_EN R2446 3V_5V_POK SIO_SLP_S4# Page45 Page24 PM_SLP_SUS# SIO_SLP_S3# SWITCH Page40 ALWON SLP_S4# SLP_S3# DDR_PG_CTL c KBC_PWRBTN# GPIO36 GPIO05 PSL_IN2# GPIO34 DPWROK 1 GPIO66 PCH_RSMRST# The DSW rails must be stable for at least PM_RSMRST# 10 ms before DSW_PWROK is asserted to PCH. GPIO20 SIO_PWRBTN# DSW_PWROK KBC ACAV_IN b MEC1404 f RSMRST# Skylake-U MCP 2 RSMRST_PWRGD# PSL_IN1# PWRBTN# h TBDDelay 10ms ALL_SYS_PWRGD and VR_RDY assert, GPIO36 delay 10ms; PCH_PWROK assert. GPIO57 RSMRST#_KBC: Delay 10 ms after receive AND 8b RSMRST_PWRGD# and PM_SLP_SUS#. RESET_OUT# SIO_SLP_S0# RSMRST#_KBC 10 PCH_PLTRST# GPIO107 PCH_PWROK SLP_S0# SUSWARN# PLTRST# ALL_SYS_PWRGD assert, PM_SUSWARN# SUSACK# 9 delay 10ms; PCH_PWROK assert. PROCPWRGD GPIO02 AND ALL_SYS_PWRGD i 7 GPIO81 It is recommended that SYS_PWROK be asserted after both PWROK assertion and processor core VR PWRGD assertion. PM_SLP_S4# GPIO44 8d H_VCCST_PWRGD ALL_SYS_PWRGD 3 GPIO01 VCCST_PWRGD 7 PM_SLP_S3# Level Shifter ALL_SYS_PWRGD 4 8c SYS_PWROK 74LVC1G07GW Page17 GPIO141 SYS_PWROK EXT_PWR_GATE# Page24 PWR_VDDQ_PG ALL_SYS_PWRGD assert, EXT_PWR_GATE# e 6 RSMRST_PWRGD# delay 100ms; SYS_PWROK assert. SLP_SUS# h DY 3D3V_S5 DS3 SIO_SLP_SUS# SVID Transanctions Vin EN SW 3D3V_S5_PCH PCH_ALW_ON SY6288C10CAC IMVP8 CPU SVID Rails (DS3) Page41 SA/Core/GT/GTx tro-X 6 PWR_VDDQ_PG VR_ON VR_RDY VR_READY 8a f 3V_5V_POK 0R 0402 RSMRST_PWRGD# g h g 1D8V_S5_PWROK 0R 0402 1D0V_S5_PWRGD DY0R 0402 3D3V_S5 5V_S5 3D3V_S5 1D0V_S5 5V_S5 Vin VCNTL 3V_5V_POK 3 4 5 IN 1D5V_S0 f SIO_SLP_S4# +V1.00U_CPU(VCCST) SIO_SLP_S3# 1D8V_S5 Vin VDD Out EN Vout 1D8V_S5_PWROK g APL5930KAI EN SW TLV70215DBVR PGOOD EN Page54 M5938ARD1U Page54 Page40 1D8V_S5 +V1.8A_SIP 0R PWR_DCBATOUT_1D0V 1D0V_S5 VIN 1D0V_PWR 3 3D3V_S5 4a Vin SIO_SLP_S4# 2D5V_S3 3V_5V_POK LX 1D0V_S5_PWRGD Vin f g LX PWR_2D5V_PG M5938ARD1U5 SIO_SLP_S3# +VCCIO +VCCSTG EN SY8208DQNC 4b EN SW EN 0R 0402 PGOOD APL5930KAI Page53 PGOOD Page54 Page40 1D0V_PWR VCCPRIM_CORE 0R 5V_S5 3D3V_S5 4b PWR_2D5V_PG S5 1D2V_S3 4c Vin1 Vin2 SIO_SLP_S3# RT8231AGQW 0D6V_S0 5 SIO_SLP_S3# G5016KD1U VOut1 5V_S0 5 PWR_VDDQ_PG 3D3V_S0 S3 EN VOut2 6 PGOOD Page40 Page51 A a b c de f g h i 1 2 3a 4 4a 4b 5 6 7 8 8a 8b 9 10 <Core Des ign> Wistron Corporation 2 1 F, 8 8 , Se c.1 , H s in Ta i Wu R d ., H s ich ih , Ta ip e i H s ie n 2 2 1 , Ta iw a n , R .O.C . Ti tl e Power Sequence Rev A00 S i ze Docum ent Num ber A0 105 Vegas SKL/KBL-U D a te : Th u rs d a y, Ju n e 1 6 , 2 0 1 6 Sheet 102 of 21

543 Adapter DCBATOUT VR_EN RT8231AGQW EN(S5) 2D5V_PWROK NCP81208MNTXG EN EN(S3) SIO_SLP_S3# Charger NCP81382MNTXG NCP81382MNTX D ISL88739 Battery BT+ 1D2V_S3 0D6V_S0 VCC_CORE +VCCGT S5_ENABLE TPS51225RUKR EN Boost 3D3V_PWR 5V_PWR 5V_S5 Circuit USB_PWR_EN# EN PM_SLP_S3# PM_SLP_S3# EN C SY6288DAAC x 2 5V_S0 USB20_VCCA TPS22966DPUR EN USB30_VCCC 0 ohm 15V_S5 APL593 1D8V_S 3D3V_S0 ODD_PWR_5V RT9724GB DGPU_PWR_EN EN AO3419L LCDVDD 3D3V_VGA_S0 Elet B Regul A 543

21 VR_EN EN/DEM_VGA 0D95V_VGA_S0_PG 3V_5V_POK EN AOZ2262QI-10 EN EN EN NCP81382MNTXG ISL62771HRTZ SY8288RAC-GP +VCCSA_VR XG D VGA_CORE 1D5V_VGA_S0 3V_5V_POK 3D3V_S5 PM_LAN_ENABLE C EN SIO_SLP_S4# EN 30KAI EN DMP2130L S5 APL5930KAI 3D3V_LAN_S5 2D5V_S3 tro-X 1D0V_S5 M5938ARD1U TPS22961DNYT 0 ohm +V1.00U_CPU V_EDRAM_EOPIO_R +VCCPRIM_CORE B 0 ohm 0 ohm +V_EOPIO_VR +V_EDRAM_VR TPS22961DNYT Power Shape +VCCIO 0 ohm 0 ohm lator LDO Switch +VCCMPHYGTAON_1P0_LS_SIP +VCCSTG A <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Power Block Diagram Size Document Number Rev A2 Vegas SKL/KBL-U A00 Date: Thursday, June 16, 2016 Sheet 103 of 105 21

A B C PCH SMBus Block Diagram 3D3V_S0 KB ‧ 1 3D3V_S5_PCH 3D3V_S0 SMS ‧ ‧ SRN10KJ-5-GP MEC14 2 SRN2K2J-1-GP 2N7002SPT SMBus Address:0xA0/0xA1 GPIO73/SCL2 GPIO74/SDA2 DIMM 1 SMBus Address SMBCLK MEM_SMBCLK ‧ ‧PCH_SMBCLK SCL 0x94/0x95/0x9 SMBDATA MEM_SMBDATA ‧ ‧ PCH_SMBDATA SDA GPIO16 SMBus Address:0xA0/0xA1 DIMM 2 SCL SDA 3D3V_S5_PCH PCH_SMBCLK TPAD ‧ PCH_SMBDATA SRN2K2J-1-GP SCL SDA SML0CLK SML0_CLK SML0DATA SML0_DATA SMBus Address:0x58/0x59 PCH_SMBCLK PTN3355 PCH_SMBDATA VDDA33_DP TMS (Janus Only) SMBus Address:0xC0H/0x40H PCH 3D3V_S0 3D3V_S5_PCH ‧ SMBus Address:0x98/0x99 3D3V_S0 SRN2K2J-8-GP Thermal‧THM_SML1_CLK SCL GPU T8 ‧ SRN2K2J-8-GP NCT7718W‧THM_SML1_DATA SDL SML1CLK ‧ ‧SML1_SMBCLK ‧ ‧THM_SML1_CLK SCL Thermal SML1DATA ‧ ‧ ‧THM_SML1_DATA SDL NCT7718W ‧ SML1_SMBDATA Elet SMBus Address:0x82/0x83 SMBus Address:0x98/0x99 2N7002SPT 3D3V_VGA_S0 ‧ SRN4K7J-8-GP 3D3V_VGA_S0 dGPU 3‧ SMB_CLK_VGA ‧ I2CS_SCL SMB_DATA_VGA ‧ I2CS_SDA SMBus Address:0x9E/0x9F 3D3V_S0 3D3V_S0 5V_S0 ‧ ‧ ‧ SRN2K2J-1-GP SRN2K2J-1-GP DDPB_CTRLCLK ‧CPU_DP1_CTRL_CLK ‧‧ DDC_CLK_HDMI ‧ HDMI CONN DDPB_CTRLDATA ‧ CPU_DP1_CTRL_DATA DDC_DATA_HDMI ‧ 2N7002DW-1-GP 4 ABC

DE BC SMBus Block Diagram TP_VDD ‧ SRN10KJ-5-GP TouchPad Conn. 1 PS2_DAT0 DAT_TP_SIO ‧ DAT_TP_SIO TPDATA PS2_CLK0 CLK_TP_SIO ‧ CLK_TP_SIO TPCLK 3D3V_AUX_KBC ‧ SRN4K7J-8-GP SRN33J-7-GP Battery Conn. SMB01_CLK18 ‧‧SMBCLK1 PBAT_SMBCLK1 CLK_SMB SMB01_DATA18 PBAT_SMBDAT1 ‧ ‧SMBDA1 DAT_SMB SMBus address:16 SC HPA02224RGRR 404 SCL SDA SMBus address:12 2 s: 96/0x97 tro-X 3 CMP_VOUT1 CMP_VOUT1 ‧ 0R2J-2-GP 66/CMP_VREF1/UART_CLK LCD_TST_EN ‧ LCD_TST_EN DY 0R2J-2-GP H_PROCHOT_EC LCD_TST ‧ 4 <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title SMBUS Block Diagram Rev Size Document Number A00 A2 Vegas SKL/KBL-U 105 D ate: Thursday, June 16, 2016 Sheet 104 of D E

AB C Thermal Block Diagram 1 3D3V_S5_PCH 3D3V_S0 PAGE28 D+ NCT7718_DXP PCH M SC2200P50V2KX-2GP Thermal D- NCT7718_DXN NCT7718 Place ne PWM CORE SDA SML1DATA/GPIO74 ‧ ‧‧SML1_DATA ‧THM_SML1_DATA SML1CLK/GPIO75 2N7002 ‧THM_SML1_CLK ‧‧ ‧SML1_CLK SCL MMBT3904-3-GP T8 SML1_DATA 3D3V_S0 T_CRIT# THERM_SYS_SHDN# 2N7002 PURE_HW_SHUTDOWN# SML1_CLK D ‧ PAGE20 S PCH_PWROK 2 G Put under CPU(T8 HW shutdown) PAGE27 GPIO74 PAGE86 GPIO73 KBC MEC1404 2N7002 SMB_CLK_VGA_R I2CS_SCL VGA SMB_DATA_VGA_R I2CS_SDA GPIO94 GPIO4 MESO-LE Elet GPIO56 GB2-64 (23x23) FAN1_DAC_1 FAN_TACH1 3 TACH 5V FAN VIN FAN_VCC1 VIN VSET VOUT FAN CONTROL APL5606AKI PAGE28 4 ABC

DE Audio Block Diagram MMBT3904-3-GP SPKR_L+ SPEAKER 1 SPKR_L- 2 ear CPU SPKR_R- HP MIC E SPKR_R+ COMBO EN 3V/5V Codec Digital ALC3246 MIC AUD_HP1_JACK_L AUD_HP1_JACK_R SLEEVE RING2 tro-X GPIO0/DMIC_DATA DMIC_DATA_R R2714 DMIC_DATA GPIO1/DMIC_CLK DMIC_CLK_R DMIC_CLK 0R2J-2-GP R2716 0R2J-2-GP 3 <Core Design> 4 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Thermal/Audio Block Diagram Rev Document Number A00 Custom Vegas SKL/KBL-U Date: Thursday, June 16, 2016 Sheet 105 of 105 DE