TTL_Databook

MC54 / 74F538 GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54, 74 4.5 5.0 5.5 V TA Operating Ambient Temperature Range 54 – 55 25 125 °C 74 0 25 70 IOH Output Current — High 54, 74 – 3.0 mA IOL Output Current — Low 54, 74 24 mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter Min Typ Max Unit Test Conditions VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage VIL 2.4 VIK Input LOW Voltage 2.7 0.8 V Guaranteed Input LOW Voltage VOH Input Clamp Diode Voltage – 60 – 1.2 V VCC = MIN, IIN = – 18 mA VOL 54, 74 V IOH = – 3.0 mA VCC = 4.5 V IOZH 74 IOZL Output HIGH Voltage IIH V IOH = – 3.0 mA VCC = 4.75 V IIL Output LOW Voltage 0.5 V IOL = 24 mA VCC = MIN IOS ICCZ Output OFF Current — HIGH 50 µA VOUT = 2.7 V VCC = MAX Output OFF Current — LOW – 50 µA VOUT = 0.5 V VCC = MAX Input HIGH Current 20 µA VCC = MAX, VIN = 2.7 V 0.1 mA VCC = MAX, VIN = 7.0 V Input LOW Current – 0.6 mA VCC = MAX, VIN = 0.5 V Output Short Circuit Current (Note 2) –150 mA VCC = MAX, VOUT = 0 V Power Supply Current 37 56 mA VCC = MAX: A0 – A2, E1, E2 = GND OE1, OE2, E3, E4, P = HIGH AC CHARACTERISTICS Symbol Parameter 54 / 74F 54F 74F Unit ns tPLH Propagation Delay TA = + 25°C TA = –55 to +125′C TA = 0 to 70°C ns tPHL An to On VCC = + 5.0 V VCC = 5.0 V ± 10% VCC = 5.0 V ± 10% ns tPLH Propagation Delay CL = 50 pF CL = 50 pF CL = 50 pF tPHL E1 or E2 to On Min Typ Max Min Max Min Max tPLH Propagation Delay tPHL E3 or E4 to On 4.0 11 13 4.0 17 4.0 14 3.0 7.5 12.5 3.0 16.5 3.0 13.5 tPLH Propagation Delay tPHL P to On 4.0 8.5 12 3.5 15 3.5 13 3.0 6.5 12 3.0 14.5 3.0 12.5 tPZH Output Enable Time tPZL OE1 or OE2 to On 6.5 11 12.5 5.5 15.5 5.5 13.5 4.0 10 12.5 3.5 15 3.5 13 tPHZ Output Disable Time tPLZ OE1 or OE2 to On 4.5 11.5 15 4.0 18.5 4.0 16.5 3.5 11 11.5 3.5 12.5 3.5 12 2.5 5.5 9.5 2.0 13 2.0 11 4.0 9.0 13.5 4.0 16 4.0 15 1.0 4.0 6.0 1.0 8.0 1.0 7.0 1.0 5.0 8.5 1.0 10.5 1.0 9.5 FAST AND LS TTL DATA 4-210

MC54 / 74F538 TRUTH TABLE INPUTS OUTPUTS FUNCTION OE1 OE2 E1 E2 E3 E4 A2 A1 A0 O0 O1 O2 O3 O4 O5 O6 O7 High Impedance H X X XXX X XXZZZZ Z ZZZ X H X XXX X XXZZZZ Z ZZZ Disable L L H XXX X XX Outputs Equal P Input Active HIGH L L X HXX X XX Output L L X XLX X XX (P = L) L L X XXL X XX Active LOW L L L LHH L L LHL L L L L L L Output L L L LHH L LHLHL L L L L L (P = H) L L L LHH L HL L LHL L L L L L L L LHH L HHL L LH L L L L H = HIGH Voltage Level L = LOW Voltage Level L L L LHH H L L L L L L H L L L X = Don’t Care L L L LHH H LHL L L L L HL L Z = High Impedance L L L LHH H HL L L L L L LHL L L L LHH H HHL L L L L L LH L L L LHH L L L LHHH H HHH L L L LHH L LHHLHH H HHH L L L LHH L HLHHLH H HHH L L L LHH L HHHHHL H HHH L L L LHH H L LHHHH L HHH L L L LHH H LHHHHH H LHH L L L LHH H HLHHHH H HLH L L L LHH H HHHHHH H HHL FAST AND LS TTL DATA 4-211

MC54/74F539 DUAL 1-OF-4 DECODER DUAL 1-OF-4 DECODER WITH 3-STATE OUTPUTS WITH 3-STATE OUTPUTS The MC54 / 74F539 contains two independent decoders. Each accepts two FAST™ SCHOTTKY TTL Address (A0 – A1) input signals and decodes them to select one of four mutually exclusive outputs. A polarity control input (P) determines whether the 20 J SUFFIX outputs are active HIGH (P = L) or active LOW (P = H). An active LOW input 1 CERAMIC Enable (E) is available for data demultiplexing; data is routed to the selected CASE 732-03 output in non-inverted form in the active LOW mode or in inverted form in the 20 active HIGH mode. A HIGH Signal on the active LOW Output Enable (OE) 1 N SUFFIX input forces the 3-state outputs to the high impedance state. PLASTIC • Demultiplexing Capability 20 CASE 738-03 • 3-State Outputs 1 • Two Completely Independent 1-of-4 Decoders DW SUFFIX • Input Clamp Diodes Limit High Speed Termination Effects SOIC • ESD Protection > 4000 Volts CASE 751D-03 CONNECTION DIAGRAM DIP (TOP VIEW) VCC O3b A1b A0b Eb Ea OEa Pa O0a O1a ORDERING INFORMATION 20 19 18 17 16 15 14 13 12 11 MC54FXXXJ Ceramic 1 2 3 4 5 6 7 8 9 10 MC74FXXXN Plastic O2b O1b O0b Pb OEb A0a A1a O3a O2a GND MC74FXXXDW SOIC LOGIC DIAGRAM (1/2 SHOWN) LOGIC SYMBOL A1 13 6 7 A0 P A0 A1 15 E E DECODER a P 14 OE OE O0 O1 O2 O3 O0 O1 O2 O3 12 11 9 8 VCC = PIN 20 Please note that this diagram is provided only for the understanding of logic operations and 4 17 18 GND = PIN 10 should not be used to estimate propagation delays. P A0 A1 16 E DECODER b 5 OE O0 O1 O2 O3 3 2 1 19 FAST AND LS TTL DATA 4-212

MC54 / 74F539 GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54, 74 4.5 5.0 5.5 V TA Operating Ambient Temperature Range 54 – 55 25 125 °C 74 0 25 70 IOH Output Current — High 54, 74 – 3.0 mA IOL Output Current — Low 54, 74 24 mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter Min Typ Max Unit Test Conditions VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage VIL Input LOW Voltage 0.8 V Guaranteed Input LOW Voltage VIK Input Clamp Diode Voltage – 1.2 V VCC = MIN, IIN = – 18 mA 54, 74 2.4 V IOH = – 3.0 mA VCC = 4.5 V 74 2.7 VOH Output HIGH Voltage V IOH = – 3.0 mA VCC = 4.75 V VOL Output LOW Voltage 0.5 V IOL = 24 mA VCC = MIN IOZH Output OFF Current — HIGH 50 µA VOUT = 2.7 V VCC = MAX IOZL Output OFF Current — LOW – 50 µA VOUT = 0.5 V VCC = MAX IIH Input HIGH Current 20 µA VCC = MAX, VIN = 2.7 V 0.1 mA VCC = MAX, VIN = 7.0 V IIL Input LOW Current – 0.6 mA VCC = MAX, VIN = 0.5 V IOS Output Short Circuit Current (Note 2) – 60 –150 mA VCC = MAX, VOUT = 0 V ICCZ Power Supply Current 40 60 mA VCC = MAX, A0 , A1, E = GND OE, P = HIGH AC CHARACTERISTICS Symbol Parameter 54 / 74F 54F 74F Unit ns tPLH Propagation Delay TA = + 25°C TA = –55 to +125°C TA = 0 to 70°C ns tPHL An to On VCC = + 5.0 V VCC = 5.0 V ± 10% VCC = 5.0 V ± 10% ns ns tPLH Propagation Delay CL = 50 pF CL = 50 pF CL = 50 pF tPHL E to On ns Min Typ Max Min Max Min Max tPLH Propagation Delay tPHL P to On 3.5 12.5 3.0 18.5 3.0 13.5 3.0 12.5 2.5 16 2.5 13 tPLH Propagation Delay tPHL P to On 3.0 11 2.5 14 3.0 12 3.0 11 3.0 13.5 3.0 11.5 tPZH Output Enable Time tPZL OE to On 4.0 9.5 3.5 12.5 3.5 10.5 3.5 9.5 3.0 11.5 3.0 10 tPHZ Output Disable Time tPLZ OE to On 5.0 14.5 4.0 19.5 4.0 15.5 3.0 9.0 3.0 11.5 3.0 9.5 2.5 7.5 2.0 10.5 2.0 8.5 4.0 10 3.5 13.5 3.5 11.5 1.5 6.0 1.0 7.5 1.0 6.5 2.0 8.0 1.5 9.5 1.5 8.5 FAST AND LS TTL DATA 4-213

MC54 / 74F539 TRUTH TABLE (each half) Inputs Outputs Function OE E A1 A0 O0 O1 O2 O3 High Impedance HXXX Z Z Z Z Disable LHXX On = P Active HIGH Output L L L LHL L L (P = L) L L LHLHL L L LHL L LHL Active LOW L LHHL L LH Output (P = H) L L L L LHHH L L LHHLHH H = HIGH Voltage Level L LHLHHLH L = LOW Voltage Level L LHHHHHL X = Don’t Care Z = High Impedance FAST AND LS TTL DATA 4-214

OCTAL REGISTERED MC74F543 TRANSCEIVER, NON-INVERTING, 3-STATE OCTAL REGISTERED TRANSCEIVER, The MC74F543 Octal Registered Transceivers contain two sets of data NON-INVERTING, 3-STATE flowing in either direction. Separate Latch Enable (LEAB, LEBA) and Enable FAST™ SCHOTTKY TTL (OEAB, OEBA) inputs are provided for each register to permit independent 24 N SUFFIX 1 PLASTIC control of inputting and outputting in either direction of data flow. The CASE 724-03 MC74F543 has a noninverting data path. The A outputs are guaranteed to sink 20 mA while the B outputs are rated for 64 mA. • Combines 74F245 and 74F373 Type Functions in One Chip • 8-Bit Octal Transceiver • Non-Inverting • Back-to-Back Registers for Storage • Separate Controls for Data Flow in Each Direction • Glitchless Outputs During 3-State Power Up or Power Down Operation • High Impedance Outputs in Power Off State • A Outputs Sink 24 mA and Source 3.0 mA • B Outputs Sink 64 mA and Source 15 mA • See F544 for Inverting Version • ESD Protection > 4000 Volts VCC EBA B0 PIN ASSIGNMENT B7 LEAB OEAB 24 DW SUFFIX 24 23 22 B1 B2 B3 B4 B5 B6 15 14 13 1 SOIC 21 20 19 18 17 16 CASE 751E-03 ORDERING INFORMATION MC74FXXXN Plastic MC74FXXXDW SOIC 1 2 3 4 5 6 7 8 9 10 11 12 LEBA OEBA A0 A1 A2 A3 A4 A5 A6 A7 EAB GND GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 74 4.5 5.0 5.5 V TA Operating Ambient Temperature Range IOH Output Current — High 74 0 25 70 °C IOL Output Current — Low 74 – 3.0 / – 15 mA 74 24 / 64 mA FAST AND LS TTL DATA 4-215

MC74F543 FUNCTION TABLE Inputs OEXX EXX LEXX Data Outputs Status HXXX Z Outputs disabled LHL l Z Outputs disabled Z Data latched LHL h LLH l L Data latched L LHh H LLLL L Transparent L L LH H H = HIGH voltage level: h = HIGH state must be present one set-up time before the LOW-to-HIGH transition of LEXX or EXX (XX = AB or BA): L = LOW Voltage Level: I = LOW state must be present one set-up time before the LOW-to-HIGH transition of LEXX or EXX (XX = AB or BA): X = Don’t care: Z = HIGH impedance state. FUNCTIONAL DESCRIPTION transition of the LEAB signal puts the A latches in the storage The MC74F543 contains two sets of eight D-type latches, mode and their outputs no longer change with the A inputs. With EAB and OEAB both LOW, the 3-State B output buffers with separate input and controls for each set. For data flow are active and reflects the data present at the output of the A from A to B, for example, the A-to-B Enable (EAB) Input must latches. Control of data flow from B to A is similar, but using be LOW in order to enter data from A0 – A7 or take data from the EBA, LEBA, and OEBA inputs. B0 – B7, as indicated in the Function Table. With EAB LOW, a LOW signal on the A-to-B Latch Enable (LEAB) input makes the A-to-B latches transparent; a subsequent LOW-to-HIGH DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter Min Typ Max Unit Test Conditions VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage VIL V VIK Input LOW Voltage 0.8 V Guaranteed Input LOW Voltage VOH Input Clamp Diode Voltage –0.73 – 1.2 V VCC = MIN, IIN = – 18 mA VOL 2.4 V VCC = 4.5 V IIH V VCC = 4.75 V A0 – A7 74 V IOH = – 3.0 mA IIL mA Output HIGH Voltage 2.7 3.4 µA B0 – B7 74 2.0 IOH = – 15 mA VCC = 4.5 V mA Output LOW Voltage A0 – A7 74 0.35 0.5 IOL = 24 mA VCC = MIN B0 – B7 74 0.4 0.55 IOL = 64 mA I/O Pins 1.0 VCC = MAX, VIN = 5.5 V Input HIGH Current 100 VCC = MAX, VIN = 7.0 V 20 Control Pins VCC = MAX, VIN = 2.7 V Input LOW Current EAB, EBA – 1.2 VCC = MAX, VIN = 0.5 V Other Inputs – 0.6 IOZH Off-State Output Current, 70 µA VCC = MAX VOUT = 2.7 V IOZL High-Level Voltage Applied 1.0 mA VOUT = 5.5 V Off-State Output Current, – 600 µA VCC = MAX, VOUT = 0.5 V Low-Level Voltage Applied An Outputs – 60 –150 mA VCC = MAX, VOUT = 0 V IOS Output Short Circuit Current (Note 2) –225 Bn Outputs – 100 ICCH 70 100 ICC Total Supply Current ICCL 95 125 mA VCC = MAX ICCZ 95 125 NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device type. 2. Not more than one output should be shorted at a time, nor for more than 1 second. FAST AND LS TTL DATA 4-216

MC74F543 AC ELECTRICAL CHARACTERISTICS Symbol Parameter 74F 74F Unit TA = 0°C to + 70°C MHz fMAX Maximum Clock Frequency TA = + 25°C VCC = + 5.0 V ± 10% ns VCC = + 5.0 V ns tPLH Propagation Delay CL = 50 pF ns tPHL Transparent Mode CL = 50 pF Min Max ns An to Bn or Bn to An 70 tPLH Min Typ Max ns tPHL Propagation Delay 3.0 8.5 tPLH LEBA to An 70 100 3.0 7.5 tPHL Propagation Delay 3.0 5.5 7.5 4.5 12.5 tPZH LEAB to Bn 3.0 5.0 6.5 4.5 12.5 tPZL Output Enable Time to 4.5 8.5 11 4.5 12.5 tPHZ OEBA or OEAB to An or Bn 4.5 8.5 11 4.5 12.5 tPLZ EBA or EAB to An or Bn 4.5 8.5 11 3.0 10 Output Disable Time to 4.5 8.5 11 4.0 12 OEBA or OEAB to An or Bn EBA or EAB to An or Bn 3.0 7.0 9.0 2.5 9.0 4.0 7.5 10.5 2.0 8.5 2.5 6.0 8.0 2.0 5.5 7.5 AC OPERATING REQUIREMENTS Symbol Parameter 74F 74F Unit ns ts(H) Setup Time, HIGH or LOW TA = + 25°C TA = 0°C to + 70°C ns ts(L) An or Bn to LEBA or LEAB VCC = + 5.0 V VCC = + 5.0 V ± 10% ns th(H) Hold Time, HIGH or LOW CL = 50 pF CL = 50 pF th(L) An to Bn to LEBA or LEAB Min Typ Max Min Typ Max tw(L) Latch Enable, B to A 3.0 3.5 Pulse Width, LOW 3.0 3.5 3.0 3.5 3.0 3.5 8.0 9.0 FAST AND LS TTL DATA 4-217

MC74F543 LOGIC DIAGRAM DQ DETAIL A B0 LE QD B1 A0 LE B2 B3 A1 DETAIL A X 7 B4 A2 B5 A3 B6 A4 B7 A5 A6 A7 OEBA EBA OEAB LEAB LEBA EAB NOTE: Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. FAST AND LS TTL DATA 4-218

OCTAL REGISTERED MC74F544 TRANSCEIVER, INVERTING, 3-STATE OCTAL REGISTERED TRANSCEIVER, INVERTING, The MC74F544 Octal Registered Transceivers contain two sets of D-Type latches for temporary storage of data flowing in either direction. Separate 3-STATE Latch Enable (LEAB, LEBA) and Enable (OEAB, OEBA) inputs are provided FAST™ SCHOTTKY TTL for each register to permit independent control of inputting and outputting in either direction of data flow. The MC74F544 has an inverting data path. The 24 N SUFFIX A outputs are guaranteed to sink 24 mA while the B outputs are rated for 1 PLASTIC 64 mA. CASE 724-03 • Combines 74F245 and 74F373 Type Functions in One Chip DW SUFFIX • 8-Bit Octal Transceiver SOIC • Inverting • Back-to-Back Registers for Storage CASE 751E-03 • Separate Controls for Data Flow in Each Direction • Glitchless Outputs During 3-State Power Up or Power Down Operation • High Impedance Outputs in Power Off State • A Outputs Sink 24 mA and Source 3.0 mA • B Outputs Sink 64 mA and Source 15 mA • See F543 for Noninverting Version • ESD Protection > 4000 Volts 24 1 VCC EBA B0 PIN ASSIGNMENT B7 LEAB OEAB ORDERING INFORMATION 24 23 22 B1 B2 B3 B4 B5 B6 15 14 13 21 20 19 18 17 16 MC74FXXXN Plastic MC74FXXXDW SOIC 1 2 3 4 5 6 7 8 9 10 11 12 LEBA OEBA A0 A1 A2 A3 A4 A5 A6 A7 EAB GND GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC DC Supply Voltage 74 4.5 5.0 5.5 V TA Operating Ambient Temperature Range IOH Output Current — High 74 0 25 70 °C IOL Output Current — Low 74 — — – 3.0 / – 15 mA 74 — — 24 / 64 mA FAST AND LS TTL DATA 4-219

MC74F544 FUNCTION TABLE Inputs OEXX EXX LEXX Data Outputs Status HXXX Z Outputs disabled XHXX Z Outputs disabled L↑L l Z Outputs disabled Z Data latched L↑Lh LL↑ l H LL↑h L Data latched LLLL H Transparent L L LH L L LHX NC Hold H = HIGH voltage level: h = HIGH state must be present one set-up time before the LOW-to-HIGH transition of LEXX or EXX (XX = AB or BA): L = LOW voltage level: l = LOW state must be present one set-up time before the LOW-to-HIGH transition of LEXX or EXX (XX = AB or BA): X = Don’t care: Z = HIGH impedance state: NC = No Change. FUNCTIONAL DESCRIPTION transition of the LEAB signal puts the A latches in the storage The MC74F544 contains two sets of eight D-type latches, mode and their outputs no longer change with the A inputs. With EAB and OEAB both LOW, the 3-State B output buffers with separate input and controls for each set. For data flow are active and reflect the inverted data present at the output from A to B, for example, the A-to-B Enable (EAB) input must of the A latches. Control of data flow from B to A is similar, but be LOW in order to enter data from A0 – A7 or take data from using the EBA, LEBA, and OEBA inputs. B0 – B7, as indicated in the Function Table. With EAB LOW, a LOW signal on the A-to-B latch enable (LEAB) input makes the A-to-B latches transparent; a subsequent LOW-to-HIGH DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Symbol Parameter Limits Unit Test Conditions Min Typ Max (Note 1) VIH Input HIGH Voltage 2.0 — — V Guaranteed Input HIGH Voltage VIL V VIK Input LOW Voltage — — 0.8 V Guaranteed Input LOW Voltage VOH Input Clamp Diode Voltage — – 0.73 – 1.2 V VCC = MIN, IIN = – 18 mA VOL A0 – A7 74 2.4 — — V IOH = – 3.0 mA VCC = 4.5 V IIH V VCC = 4.75 V Output HIGH Voltage 2.7 3.4 — V mA B0 – B7 74 2.0 — — µA IOH = – 15 mA VCC = 4.5 V µA Output LOW Voltage A0 – A7 74 — 0.35 0.5 µA IOL = 24 mA VCC = MIN B0 – B7 74 — 0.4 0.55 IOL = 64 mA I/O Pins — — 1.0 VCC = MAX, VIN = 5.5 V Input HIGH Current Control Pins — — 100 VCC = MAX, VIN = 7.0 V Control Pins — — 20 VCC = MAX, VIN = 2.7 V I/O Pins — — 70 IIL Input LOW Current EAB, EBA — — – 1.2 mA VCC = MAX, VIN = 0.5 V Other Inputs — — – 0.6 IOZH Off-State Output Current — — 70 µA VCC = MAX, VOUT = 2.7 V IOZL VCC = MAX, VOUT = 0.5 V Off-State Output Current, — — – 600 µA Low-Level Voltage Applied IOS Output Short Circuit Current (Note 2) An Outputs – 60 — –150 mA VCC = MAX, VOUT = 0 V Bn Outputs – 100 — –225 ICCH — 70 105 ICC Total Supply Current ICCL — 95 130 mA VCC = MAX ICCZ — 95 125 NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device type. 2. Not more than one output should be shorted at a time, nor for more than 1 second. FAST AND LS TTL DATA 4-220

MC74F544 AC ELECTRICAL CHARACTERISTICS Symbol Parameter 74F 74F Unit TA = + 25°C TA = 0 °C to + 70°C ns tPLH Propagation Delay VCC = + 5.0 V VCC = + 5.0 V ± 10% ns tPHL Transparent Mode CL = 50 pF ns An to Bn or Bn to An Min Typ Max CL = 50 pF ns tPLH Min Max tPHL Propagation Delay 2.0 — 9.5 ns tPLH LEBA to An 2.0 — 6.5 2.0 10.5 tPHL 2.0 7.5 Propagation Delay 6.0 — 13 tPZH LEAB to Bn 4.0 — 9.5 6.0 14.5 tPZL 4.0 10.5 Output Enable Time 6.0 — 13 tPHZ OEBA or OEAB to An or Bn 4.0 — 9.5 6.0 14.5 tPLZ EBA or EAB to An or Bn 4.0 10.5 3.0 — 9.0 Output Disable Time 4.0 — 10.5 3.0 10 OEBA or OEAB to An or Bn 4.0 12 EBA or EAB to An or Bn 1.5 — 8.0 1.5 — 7.5 1.5 9.0 1.5 8.5 AC OPERATING REQUIREMENTS 74F 74F Symbol Parameter TA = + 25°C TA = 0°C to + 70°C Unit VCC = + 5.0 V VCC = + 5.0 V ± 10% ns ts(H) Setup Time, HIGH or LOW ns ts(L) An or Bn to LEBA or LEAB CL = 50 pF CL = 50 pF ns th(H) Hold Time, HIGH or LOW Min Typ Max Min Typ Max th(L) An to Bn to LEBA or LEAB 3.0 — — 3.0 — — tw(L) Latch Enable, B to A 3.0 — — 3.0 — — Pulse Width, LOW 3.0 — — 3.0 — — 3.0 — — 3.0 — — 6.0 — — 7.5 — — FAST AND LS TTL DATA 4-221

MC74F544 LOGIC DIAGRAM DQ DETAIL A B0 LE D A0 Q LE A1 B1 A2 B2 A3 B3 A4 DETAIL A X 7 B4 A5 B5 A6 B6 A7 B7 OEBA EBA OEAB LEBA LEAB EAB NOTE: Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. FAST AND LS TTL DATA 4-222

4-BIT BIDIRECTIONAL COUNTERS MC54/74F568 (WITH 3-STATE OUTPUTS) MC54/74F569 The MC54/ 74F568 and MC54/74F569 are fully synchronous, reversible 4-BIT counters with 3-state outputs. The F568 is a BCD decade counter; the F569 BIDIRECTIONAL is a binary counter. They feature preset capability for programmable opera- tion, carry lookahead for easy cascading, and a U/D input to control the direc- COUNTERS tion of counting. For maximum flexibility there are both synchronous and mas- (WITH 3-STATE OUTPUTS) ter asynchronous reset inputs as well as both Clocked Carry (CC) and Terminal Count (TC) outputs. All state changes except Master Reset are initi- FAST™ SCHOTTKY TTL ated by the rising edge of the clock. A HIGH signal on the Output Enable (OE) input forces the output buffers into the high impedance state but does not pre- 20 J SUFFIX vent counting, resetting or parallel loading. 1 CERAMIC CASE 732-03 • 4-Bit Bidirectional Counting 20 F568 Decade Counter 1 N SUFFIX F569 Binary Counter PLASTIC 20 CASE 738-03 • Synchronous Counting and Loading 1 • Lookahead Carry Capability for Easy Cascading DW SUFFIX • Preset Capability for Programmable Operation SOIC • 3-State Outputs for Bus Organized Systems • Master Reset (MR) Overrides All Other Inputs CASE 751D-03 • Synchronous Reset (SR) Overrides Counting and Parallel Loading VCC TC CONNECTION DIAGRAM PE 20 19 CC OE O0 O1 O2 O3 CET 11 18 17 16 15 14 13 12 ORDERING INFORMATION MC54FXXXJ Ceramic MC74FXXXN Plastic MC74FXXXDW SOIC 1 2 3 4 5 6 7 8 9 10 U/D CP P0 P1 P2 P3 CEP MR SR GND LOGIC SYMBOL 11 3 4 5 6 PE P0 P1 P2 P3 1 U/D 7 CEP CC 18 12 CET TC 19 2 CP 17 OE MR SR O0 O1 O2 O3 8 9 16 15 14 13 FAST AND LS TTL DATA 4-223

MC54/74F568 • MC54/74F569 Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54, 74 4.5 5.0 5.5 V TA Operating Ambient Temperature Range 54 – 55 25 125 IOH °C IOL 74 0 25 70 Output Current — High 54, 74 – 3.0 mA Output Current — Low 54, 74 24 mA FUNCTIONAL DESCRIPTION od is the CP to TC delay of the first stage plus the CEP to CP setup time of the last stage. The TC output is subject to decod- The F568 counts modulo-10 in the BCD (8421) sequence. ing spikes due to internal race conditions and is therefore not From state 9 (HLLH) it will increment to 0 (LLLL) in the Up recommended for use as a clock or asynchronous reset for mode; in Down mode it will decrement from 0 to 9.The F569 flip-flops, registers or counters. For such applications, the counts in the modulo-16 binary sequence. From state 15 it will Clocked Carry (CC) output is provided. The CC output is nor- increment to state 0 in the Up mode; in the Down mode it will mally HIGH. When CEP, CET, and TC are LOW, the CC output decrement from 0 to 15. The clock inputs of all flip-flops are will go LOW when the clock next goes LOW and will stay LOW driven in parallel through a clock buffer. All state changes (ex- until the clock goes HIGH again, as shown in the CC Truth cept due to Master Reset) occur synchronously with the LOW- Table. When the Output Enable (OE) is LOW, the parallel data to-HIGH transition of the Clock Pulse (CP) input signal. outputs O0–O3 are active and follow the flip-flop Q outputs. A HIGH signal on OE forces O0–O3 to the High Z state but does The circuits have five fundamental modes of operation, in not prevent counting, loading or resetting. order of precedence: asynchronous reset, synchronous reset, parallel load, count and hold. Five control inputs — Master Re- LOGIC EQUATIONS: set (MR), Synchronous Reset (SR), Parallel Enable (PE), Count Enable Parallel (CEP) and Count Enable Trickle (CET) Count Enable = CEP⋅CET⋅PE — plus the Up/Down (U/D) input, determine the mode of op- Up (’F568): TC = Q0⋅Q1⋅Q2⋅Q3⋅(Up)⋅CET eration, as shown in the Mode Select Table. A LOW signal on MR overrides all other inputs and asynchronously forces the (’F569): TC = Q0⋅Q1⋅Q2⋅Q3⋅(Up)⋅CET flip-flop Q outputs LOW. A LOW signal on SR overrides count- Down (Both): TC = Q0⋅Q1⋅Q2⋅Q3⋅(Down)⋅CET ing and parallel loading and allows the Q outputs to go LOW on the next rising edge of CP. A LOW signal on PE overrides CC TRUTH TABLE counting and allows information on the Parallel Data (Pn) in- puts to be loaded into the flip-flops on the next rising edge of Inputs Output CP. With MR, SR and PE HIGH, CEP and CET permit counting when both are LOW. Conversely, a HIGH signal on either CEP SR PE CEP CET TC* CP CC or CET inhibits counting. LXX X X X H The F568 and F569 use edge-triggered flip-flops and XLX X X X H changing the SR, PE, CEP , CET or U/D inputs when the CP XXH X X X H is in either state does not cause errors, provided that the rec- XXX H X X H ommended setup and hold times, with respect to the rising XXX X H X H edge of CP, are observed. HHL L L Two types of outputs are provided as overflow/underflow in- * = TC is generated internally X = Don’t Care dicators. The Terminal Count (TC) output is normally HIGH L = LOW Voltage Level = Low Pulse and goes LOW providing CET is LOW, when the counter H = HIGH Voltage Level reaches zero in the Down mode, or reaches maximum (9 for the F568,15 for the F569) in the Up mode. TC will then remain FUNCTION TABLE LOW until a state change occurs, whether by counting or pre- setting, or until U/D or CET is changed. To implement synchro- Inputs nous multistage counters, the connections between the TC Operating Mode output and the CEP and CET inputs can provide either slow or fast carry propagation. Figure A shows the connections for MR SR PE CEP CET U/D CP simple ripple carry, in which the clock period must be longer than the CP to TC delay of the first stage, plus the cumulative L X X X X X X Asynchronous reset CET to TC delays of the intermediate stages, plus the CET to CP setup time of the last stage. This total delay plus setup time hlXX X X ↑ Synchronous reset sets the upper limit on clock frequency. For faster clock rates, the carry lookahead connections shown in Figure B are rec- h h l X X X ↑ Parallel load ommended. In this scheme the ripple delay through the inter- mediate stages commences with the same clock that causes hhh l l h ↑ Count up the first stage to tick over from max to min in the Up mode, or (increment) min to max in the Down mode, to start its final cycle. Since this final cycle takes 10 (F568) or 16 (F569) clocks to complete, hhh l l l ↑ Count down there is plenty of time for the ripple to progress through the in- (decrement) termediate stages. The critical timing that limits the clock peri- h HH H X XX h HH X Hold (do nothing) H XX H = HIGH voltage level h = HIGH voltage level one setup prior to the Low-to-High Clock transition L = LOW voltage level l = LOW voltage level one setup prior to the Low-to-High clock transition X = Don’t care ↑ = Low-to-High clock transition FAST AND LS TTL DATA 4-224

MC54/74F568 LOGIC DIAGRAMS MC54/74F569 P3 P0 P1 P2 P3 P0 P1 P2 PE PE CEP CEP CET CET T LD T LD MC54/74F568 • MC54/74F569 DETAIL A DETAIL A FAST AND LS TTL DATA 4-225 AT AT TC AF TC AF CC ENF CC ENF LD T BT LD T BT U/D UP BF DETAIL A DETAIL A U/D UP BF DETAIL A DETAIL A DN DN SR UP CP SR UP CP DN DN CP ENF CP ENF CD Q SR CD Q SR CP CP CP CP J CP K J CP K CD CD QQ QQ SR SR DETAIL A Q CD DETAIL A Q CD MR MR OE OE O0 O1 O2 O3 O0 O1 O2 O3 Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.

MC54/74F568 • MC54/74F569 Figure A. Multistage Counter with Ripple Carry COUNT CET TC CET TC CET TC CET TC CET CP CP TO ALL STAGES Figure B. Multistage Counter with Lookahead Carry COUNT CET TC CEP CEP CEP CEP CP CP L CET TC CET TC CET TC CET TO ALL STAGES DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Symbol Parameter Limits Unit Test Conditions Min Typ Max VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for All Inputs VIL Input LOW Voltage 0.8 V Guaranteed Input LOW Voltage for All Inputs VIK Input Clamp Diode Voltage – 1.2 V VCC = MIN, IIN = – 18 mA VOH VOL Output HIGH Voltage 54, 74 2.4 3.3 V IOH = – 3.0 mA VCC = 4.5 V IOZH 74 2.7 IOZL 3.3 V IOH = – 3.0 mA VCC = 4.75 V IIH Output LOW Voltage 0.3 0.5 V IOL = 24 mA VCC = MIN IIL Output OFF Current — HIGH 50 µA VOUT = 2.7 V VCC = MAX Output OFF Current — LOW – 50 µA VOUT = 0.5 V VCC = MAX 20 VIN = 2.7 V Input HIGH Current µA VCC = MAX VIN = 7.0 V 100 Input LOW Current –1.2 mA VCC = MAX, VIN = 0.5 V PE, CET –0.6 Others IOS Output Short Circuit Current (Note 2) – 60 –150 mA VOUT = 0 V VCC = MAX ICC Power Supply Current 67 mA VCC = MAX (ALL Outputs OFF) NOTES: 1. For conditions such as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device type. 2. Not more than one output should be shorted at a time, nor for more than 1 second. FAST AND LS TTL DATA 4-226

MC54/74F568 • MC54/74F569 STATE DIAGRAMS MC54/74F568 MC54/74F569 0123 01234 15 5 10 15 13 14 6 94 11 14 13 7 876 5 12 12 11 10 9 8 COUNT DOWN COUNT UP COUNT DOWN COUNT UP AC CHARACTERISTICS Symbol Parameter 54 / 74F 54F 74F Unit MHz fmax Maximum Clock Frequency TA = + 25°C TA = – 55 to + 125°C TA = 0 to + 70°C ns VCC = + 5.0 V VCC = 5.0 V ± 10% VCC = 5.0 V ± 10% ns tPLH Propagation Delay ns tPHL CP to On (PE HIGH or LOW) CL = 50 pF CL = 50 pF CL = 50 pF ns Min Max ns tPLH Propagation Delay Min Max Min Max ns tPHL CP to TC 100 ns 60 85 ns tPLH Propagation Delay 3.0 8.5 ns tPHL CET to TC 4.0 11.5 3.0 10.5 3.0 9.5 ns 4.0 14 4.0 13 tPLH Propagation Delay 5.5 15.5 tPHL U/D to TC (′F568) 4.0 11 5.5 18.5 5.5 17.5 4.0 13.5 4.0 12.5 tPLH Propagation Delay 2.5 6.0 tPHL U/D to TC (′F569) 2.5 8.0 2.5 8.0 2.5 7.0 2.5 10 2.5 9.0 tPLH Propagation Delay 3.5 11 tPHL CP to CC 4.0 16 3.5 13.5 3.5 12.5 4.0 19 4.0 18 tPLH Propagation Delay 3.5 11 tPHL CEP, CET to CC 4.0 10.5 3.5 13.5 3.5 12.5 4.0 13 4.0 12 tPHL Propagation Delay 2.5 7.0 MR to On 2.0 6.0 2.5 9.0 2.5 8.0 tPZH 2.0 8.0 2.0 7.0 tPZL Output Enable Time 2.5 6.5 OE to On 4.0 11 2.5 8.5 2.5 7.5 tPHZ 4.0 13.5 4.0 12.5 tPLZ Output Disable Time 5.0 13 OE to On 5.0 15.5 5.0 14.5 2.5 7.0 3.0 8.0 2.5 9.0 2.5 8.0 3.0 10 3.0 9.0 1.5 6.5 2.0 6.0 1.5 8.5 1.5 7.5 2.0 8.0 2.0 7.0 FAST AND LS TTL DATA 4-227

MC54/74F568 • MC54/74F569 AC OPERATING REQUIREMENTS Symbol Parameter 54 / 74F 54F 74F Unit ns ts(H) Setup Time, HIGH or LOW TA = + 25°C TA = – 55°C to + 125°C TA = 0°C to + 70°C ts(L) Pn to CP VCC = + 5.0 V VCC = 5.0 V ± 10% VCC = 5.0 V ± 10% ns Hold Time, HIGH or LOW Min Max Min Max th(H) Pn to CP Min Max ns th(L) Setup Time, HIGH or LOW 4.0 5.5 ns CEP or CET to CP 4.0 5.5 4.5 ns ts(H) 4.5 ns ts(L) Hold Time, HIGH or LOW 3.0 3.5 ns CEP or CET to CP 3.0 3.5 3.5 ns th(H) 3.5 ns th(L) Setup Time, HIGH or LOW 5.0 7.0 ns PE to CP 5.0 7.0 6.0 ts(H) 6.0 ts(L) Hold Time, HIGH or LOW 0 0 PE to CP 0 0 0 th(H) 0 th(L) Setup Time, HIGH or LOW 8.0 10 U/D to CP (F568) 8.0 10 9.0 ts(H) 9.0 ts(L) Setup Time, HIGH or LOW 0 0 U/D to CP (F569) 0 0 0 ts(H) 0 ts(L) Hold Time, HIGH or LOW 11 13.5 U/D to CP 16.5 18.5 12.5 th(H) 17.5 th(L) Setup Time, HIGH or LOW 11 13.5 SR to CP 7.0 10 12.5 ts(H) 8.0 ts(L) Hold Time, HIGH or LOW 0 0 SR to CP 0 0 0 th(H) 0 th(L) CP Pulse Width HIGH or LOW 10 12 8.0 10.5 11 tw(H) MR Pulse Width, LOW 9.5 tw(L) 0 0 MR Recovery Time 0 0 0 tw(L) 0 4.0 6.0 trec 6.0 8.0 4.5 6.5 4.5 6.0 5.0 6.0 8.0 7.0 FAST AND LS TTL DATA 4-228

MC74F574 OCTAL D-TYPE FLIP-FLOP OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS WITH 3-STATE OUTPUTS The MC74F574 is a high-speed, low-power octal D-type flip-flop featuring FAST™ SCHOTTKY TTL separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. A buffered clock (CP) and Output Enable (OE) are common to 20 J SUFFIX all flip-flops. 1 CERAMIC CASE 732-03 This device is functionally identical to the F374 except for the pinouts. 20 • Broadside Pinout Version of F374 1 N SUFFIX • Edge-Triggered D-Type Inputs PLASTIC • Buffered Positive Edge-Triggered Clock 20 CASE 738-03 • 3-State Outputs for Bus Oriented Applications 1 • ESD Protection > 4000 Volts DW SUFFIX SOIC PIN ASSIGNMENT CASE 751D-03 VCC O0 O1 O2 O3 O4 O5 O6 O7 CP 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 OE D0 D1 D2 D3 D4 D5 D6 D7 GND LOGIC SYMBOL 23 4 5 6 78 9 D0 D1 D2 D3 D4 D5 D6 D7 ORDERING INFORMATION 11 CP MC74FXXXJ Ceramic MC74FXXXN Plastic MC74FXXXDW SOIC 1 OE O0 O1 O2 O3 O4 O5 O6 O7 19 18 17 16 15 14 13 12 GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC DC Supply Voltage 74 4.5 5.0 5.5 V TA Operating Ambient Temperature Range IOH Output Current — High 74 0 25 70 °C 74 — — 3.0 mA IOL Output Current — Low 74 — — 24 mA FAST AND LS TTL DATA 4-229

MC74F574 FUNCTION TABLE Internal Outputs Operating Mode Register Inputs Q0–Q7 Load and read register L L Hold OE CP Dn H H Disable outputs L↑ l L↑h NC NC L↑X Dn Z X Z H ↑ Dn HXX H = HIGH voltage level h = HIGH voltage level one set-up time prior to the Low-to-High clock transition L = LOW voltage level l = LOW voltage level one set-up time prior to the Low-to-High clock transition NC = No change X = Don’t care Z = High impedance “off” state ↑ = Low-to-High clock transition ↑ = Not a Low-to-High clock transition FUNCTIONAL DESCRIPTION The MC74F574 consists of eight edge-triggered flip-flops on the LOW-to-HIGH Clock (CP) transition. With the Output with individual D-type inputs and 3-state true outputs. The Enable (OE) LOW, the contents of the eight flip-flops are avail- buffered clock and buffered Output Enable are common to all able at the outputs. When the OE is HIGH, the outputs go to flip-flops. The eight flip-flops will store the state of their individ- the high impedance state. Operation of the OE input does not ual D inputs that meet the setup and hold times requirements affect the state of the flip-flops. DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Symbol Parameter Limits Unit Test Conditions Min Typ Max (Note 1) VIH Input HIGH Voltage 2.0 — — V Guaranteed Input HIGH Voltage VIL Input LOW Voltage — — 0.8 V Guaranteed Input LOW Voltage VIK Input Clamp Diode Voltage — — – 1.2 V VCC = MIN, IIN = – 18 mA VOH Output HIGH Voltage 2.4 — — V VCC = MIN 2.7 — — IOH = – 3.0 mA V VCC = 4.75 V VOL Output LOW Voltage — — 0.5 V IOL = 24 mA VCC = MIN — — 20 VCC = MAX, VIN = 2.7 V IIH Input HIGH Current — — 100 µA VCC = MAX, VIN = 7.0 V IIL Input LOW Current — — – 0.6 mA VCC = MAX, VIN = 0.5 V IOZH Output Off Current — HIGH — — 50 µA VCC = MAX, VOUT = 2.7 V IOZL Output Off Current — LOW — — –50 µA VCC = MAX, VOUT = 0.5 V IOS Output Short Circuit Current (Note 2) – 60 — –150 mA VCC = MAX, VOUT = 0 V ICCZ Power Supply Current — 55 86 mA VCC = MAX Dn – GND; (All Outputs OFF) OE = 4.5 V NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device type. 2. Not more than one output should be shorted at a time, nor for more than 1 second. FAST AND LS TTL DATA 4-230

MC74F574 LOGIC DIAGRAM D0 D1 D2 D3 D4 D5 D6 D7 CP CP D CP D CP D CP D CP D CP D CP D CP D QQ QQ QQ QQ QQ QQ QQ QQ OE O2 O3 O4 O5 O6 O7 O0 O1 AC ELECTRICAL CHARACTERISTICS 54 / 74F 74F TA = + 25°C TA = 0°C to + 70°C VCC = + 5.0 V VCC = +5.0 V ± 10% CL = 50 pF CL = 50 pF Symbol Parameter Min Typ Max Min Max Unit Maximum Clock Frequency MHz fMAX Propagation Delay 100 — — 70 — ns CP to On tPLH 2.5 — 8.5 2.5 8.5 ns tPHL Output Enable Time 2.5 — 8.5 2.5 8.5 ns tPZH Output Disable Time 3.0 — 9.0 2.5 10.0 tPZL 3.0 — 9.0 2.5 10.0 tPHZ 1.5 — 5.5 1.5 6.5 tPLZ 1.0 — 5.5 1.0 6.5 AC OPERATING CHARACTERISTICS 54 / 74F 74F TA = + 25°C TA = 0°C to + 70°C VCC = + 5.0 V VCC = +5.0 V ± 10% CL = 50 pF CL = 50 pF Symbol Parameter Min Typ Max Min Typ Max Unit ns ts(H) Setup Time, HIGH or LOW 2.5 — — 2.5 — — ns ts(L) Dn to CP 2.0 — — 3.0 — — ns th(H) Hold Time, HIGH to LOW 2.0 — — 2.0 — — th(L) Dn to CP 2.0 — — 2.0 — — tw(H) CP Pulse Width 5.0 — — 5.0 — — tw(L) HIGH or LOW 5.0 — — 5.0 — — FAST AND LS TTL DATA 4-231

MC74F579 8-BIT BIDIRECTIONAL 8-BIT BIDIRECTIONAL BINARY COUNTER (3-STATE) BINARY COUNTER (3-STATE) The MC74F579 is a fully synchronous 8-stage up/down counter with multi- FAST™ SCHOTTKY TTL plexed 3-state I/O ports for bus-oriented applications. It features a preset capability for programmable operation, carry look-ahead for easy cascading 20 J SUFFIX and a U/D input to control the direction of counting. All state changes, except 1 CERAMIC for the case of asynchronous reset, are initiated by the rising edge of the clock. CASE 732-03 TC output is not recommended for use as a clock or asynchronous reset due 20 to the possibility of decoding spikes. 1 N SUFFIX PLASTIC • Multiplexed 3-State I/O Ports For Bus-oriented Applications 20 CASE 738-03 • Built-In Cascading Carry Capability 1 • Count Frequency 115 MHz Typ DW SUFFIX • Supply Current 100 mA Typ SOIC • Fully Synchronous Operation • U/D Pin to Control Direction of Counting CASE 751D-03 • Separate Pins for Master Reset and Synchronous Reset • Center Power Pins to Reduce Effects of Package Inductance • See F269 for 24-Pin Separate I/O Port Version • See F779 for 16-Pin Version • ESD Protection > 4000 Volts PIN ASSIGNMENT MR SR CEP CET VCC TC U/D PE CS OE 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 ORDERING INFORMATION CP I/O0 I/O1 I/O2 I/O3 GND I/O4 I/O5 I/O6 I/O7 MC74FXXXJ Ceramic LOGIC SYMBOL MC74FXXXN Plastic 13 12 20 19 14 MC74FXXXDW SOIC PE CS MR SR U/D 1 CP 18 CEP TC 15 17 CET 11 OE I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 2345 6 78 9 GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 4.5 5.0 5.5 V TA Operating Ambient Temperature Range 0 25 70 °C IOH Output Current — High TC –1.0 mA IOL Output Current — Low I/On –3.0 TC 20 mA I/On 24 FAST AND LS TTL DATA 4-232

MC74F579 FUNCTION TABLE MR SR CS PE CEP CET U/D OE CP Function X I/O0 to I/O7 in Hi-Z (PE disabled) X XH X X X XX X I/O0 to I/O7 in Hi-Z X Flip-Flop outputs appear on I/O lines X XL H X X XH X Asynchronous reset for all flip-flops ↑ Synchronous reset for all flip-flops X XL H X X XL ↑ Parallel load all flip-flops ↑ Hold L XX X X X XX ↑ Hold (TC held high) ↑ Count up H LXX X X XX ↑ Count down H HL L X X XX H H (not LL) H X X X H H (not LL) X H X X H H (not LL) L L H X H H (not LL) L L L X H = High voltage level L = Low voltage level X = Don’t care ↑ = Low-to-High clock transition (not LL) = CS and PE should never both be low voltage at the same time DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Symbol Parameter 74F Unit Test Conditions Min Typ (2) Max (Note 1) 2.5 IOH = – 1.0 mA VCC = 4.5 V TC V VIL = MAX VOH Output HIGH Voltage 2.7 3.4 VIH = MIN VCC = 4.75 V 3.3 2.4 3.3 IOH = – 3.0 mA VCC = 4.5 V I/On V VIL = MAX 2.7 VIH = MIN VCC = 4.75 V VOL Output LOW Voltage TC 0.35 0.5 IOL = 20 mA VCC = 4.5 V VIK Input Clamp Diode Voltage I/On –0.73 V VIL = MAX – 1.2 VIH = MIN IIH Input HIGH Current I/On 1.0 IOL = 24 mA others 100 I/On 70 V VCC = 4.5 V, IIN = – 18 mA others 20 mA VIN = 5.5 V µA VCC = 5.5 V VIN = 7.0 V µA VCC = 5.5 V, VIN = 2.7 V IIL Input LOW Current Except –0.6 mA VCC = 5.5 V, VIN = 0.5 V IOZH I/On 70 IOZL OFF-State Current –600 µA VCC = 5.5 V VOUT = 2.7 V High-Level Voltage Applied I/On VOUT = 0.5 V OFF-State Current Low-Level Voltage Applied IOS Output Short Circuit Current (Note 3) – 60 –80 –150 mA VCC = MAX, VOUT = 0 V ICCH 95 135 ICC Total Supply Current (total) ICCL 105 145 mA VCC = MAX ICCZ 105 150 NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under guaranteed operating conditions for the applicable device type. 2. All typical values are at VCC = 5.0 V, TA = 25°C. 3. Not more than one output should be shorted at a time. For IOS testing, the use of high-speed test apparatus and/or sample-and-hold techniques are prefer- able in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a HIGH output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be per- formed last. FAST AND LS TTL DATA 4-233

MC74F579 AC ELECTRICAL CHARACTERISTICS 74F 74F TA = + 25°C TA = 0°C to + 70°C VCC = + 5.0 V VCC = +5.0 V ± 10% CL = 50 pF CL = 50 pF Min Max Symbol Parameter Min Typ Max Unit 80 MHz fMAX Maximum Clock Frequency 100 ns Propagation Delay 5.0 11.5 ns tPLH CP to I/On 5.0 10.5 5.0 11.5 ns tPHL 5.0 10.5 ns Propagation Delay 4.5 11 ns tPLH CP to TC 4.5 10 5.0 11 ns tPHL 5.5 10 ns Propagation Delay 3.5 9.0 ns tPLH U/D to TC 3.5 8.0 4.5 9.0 ns tPHL 4.5 8.0 Propagation Delay 3.5 8.5 tPLH CET to TC 3.5 7.0 3.5 8.5 tPHL 3.5 8.0 Propagation Delay 5.0 11 tPHL MR to I/On 5.0 10 4.5 11.5 tPZH Output Enable Time to HIGH or 4.5 10.5 6.0 11.5 tPZL LOW Level CS, PE to I/On 6.5 10.5 3.0 9.0 tPHZ Output Disable Time to HIGH or 3.0 7.5 4.0 11 tPLZ LOW Level CS, PE to I/On 4.0 9.5 4.0 9.5 tPZH Output Enable Time to HIGH or 4.0 8.5 5.0 10.5 tPZL LOW Level OE to I/On 6.0 9.5 1.0 6.5 tPHZ Output Disable Time to HIGH or 1.0 6.0 2.5 8.0 tPLZ LOW Level OE to I/On 2.5 7.0 AC SETUP REQUIREMENTS 74F 74F TA = + 25°C TA = 0°C to + 70°C VCC = + 5.0 V VCC = +5.0 V ± 10% CL = 50 pF CL = 50 pF Min Typ Max Symbol Parameter Min Typ Max Unit 4.0 ns ts(H) Setup Time, HIGH or LOW 3.0 4.0 ts(L) I/On to CP 3.0 ns Hold Time, HIGH or LOW 1.0 th(H) I/On to CP 1.0 1.0 ns th(L) 1.0 Setup Time, HIGH or LOW 10 ns ts(H) PE, SR or CS to CP 9.5 10 ts(L) 9.5 ns Hold Time, HIGH or LOW 0 th(H) PE, SR or CS to CP 0 0 ns th(L) 0 ns Setup Time, HIGH or LOW 5.5 ns ts(H) CET, CEP to CP 5.0 10.5 ns ts(L) 9.0 Hold Time, HIGH or LOW 0 th(H) CET, CEP to CP 0 0 th(L) 0 CP Pulse Width 6.0 tw 4.5 MR Pulse Width 4.5 tw(L) 3.5 MR Recovery Time 4.5 trec 4.0 FAST AND LS TTL DATA 4-234

MC74F579 LOGIC DIAGRAM SR CPMR PE LOAD CONTROL DETAIL A CE OE I/O0 DETAIL A I/O1 I/O2 DETAIL A DETAIL A I/O3 DETAIL A I/O4 DETAIL A I/O5 DETAIL A I/O6 I/O7 DOWN UP DETAIL A U/D CEP TOGGLE TC CET CP MR DATA MR DQ LOAD CP Q Q Q Detail A FAST AND LS TTL DATA 4-235

OCTAL BUS TRANSCEIVER MC74F620 WITH 3-STATE OUTPUTS MC74F623 (INVERTING AND NONINVERTING) OCTAL BUS TRANSCEIVER The MC74F620 is an octal bus transceiver featuring inverting 3-state bus- WITH 3-STATE OUTPUTS compatible outputs in both send and receive directions. The BN outputs are capable of sinking 64 mA and sourcing up to 15 mA, providing very good ca- (INVERTING AND NONINVERTING) pacitive drive characteristics. The MC74F623 is a non-inverting version of the MC74F620. These octal bus transceivers are designed for asynchronous FAST™ SCHOTTKY TTL two-way communication between data busses. The control function imple- mentation allows for maximum flexibility in timing. These devices allow data 20 J SUFFIX transmission from the A bus to the B bus or from B bus to A bus, depending 1 CERAMIC upon the logic levels at the Enable inputs (OEBA and OEAB). The Enable in- CASE 732-03 puts can be used to disable the device so that the busses are effectively iso- 20 lated. The dual-enable configuration gives the MC74F620 and MC74F623 the 1 N SUFFIX capability to store data by the simultaneous enabling of OEBA and OEAB. PLASTIC Each output reinforces its input in this transceiver configuration. Thus, when 20 CASE 738-03 both control inputs are enabled and all other data sources to the two sets of 1 the bus lines are at high impedance, both sets of bus lines (16 in all) will remain DW SUFFIX at their last states. SOIC • High Impedance NPN base inputs for reduced loading (70 µA in High CASE 751D-03 and Low states) • Ideal for Applications which Require High Output drive and minimal bus loading • Octal Bidirectional Bus Interface • 3-State Buffer Outputs Sink 64 mA and Source 15 mA • – F620 Inverting – F623 Noninverting • ESD Protection > 4000 Volts ORDERING INFORMATION MC74FXXXJ Ceramic MC74FXXXN Plastic MC74FXXXDW SOIC PIN ASSIGNMENTS VCC OEBA B0 B1 B2 B3 B4 B5 B6 B7 VCC OEBA B0 B1 B2 B3 B4 B5 B6 B7 20 19 18 17 16 15 14 13 12 11 20 19 18 17 16 15 14 13 12 11 F620 F623 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 OEAB A0 A1 A2 A3 A4 A5 A6 A7 GND OEAB A0 A1 A2 A3 A4 A5 A6 A7 GND FAST AND LS TTL DATA 4-236

MC74F620 • MC74F623 LOGIC SYMBOLS 2 3 4 5 6 7 89 2 3 4 5 6 7 89 A0 A1 A2 A3 A4 A5 A6 A7 A0 A1 A2 A3 A4 A5 A6 A7 1 OEAB 1 OEAB 19 OEBA F620 19 OEBA F623 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 18 17 16 15 14 13 12 11 18 17 16 15 14 13 12 11 FUNCTION TABLE Inputs Operating Modes OEBA OEAB F620 F623 LL B data to A bus B data to A bus HH A data to B bus A data to B bus HL Z Z LH B data to A bus B data to A bus A data to B bus A data to B bus H = HIGH voltage level: L = LOW voltage level: X = Don’t care: Z = High impedance “off” state GUARANTEED OPERATING RANGES Symbol Parameter An Outputs 74 Limits Unit DC Supply Voltage Bn Outputs 74 Min Typ Max V VCC Operating Ambient Temperature Range An Outputs 74 4.5 5.0 5.5 °C TA Output Current  High Bn Outputs 74 mA IOH Output Current  High 74 0 25 70 mA IOH Output Current  Low 74 — — –3.0 mA IOL Output Current  Low — — –15 mA IOL — — 24 — — 64 FAST AND LS TTL DATA 4-237

MC74F620 • MC74F623 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Symbol Parameter Limits Test Conditions Min Typ (Note 1) Max Unit VIH Input HIGH Voltage 2.0 — — V Guaranteed as a HIGH Signal VIL Input LOW Voltage — — 0.8 V Guaranteed as a LOW Signal VIK Input Clamp Diode Voltage — — –1.2 V VCC = MIN, IIN = –18 mA 74 2.4 3.3 — V IOH = –3.0 mA VCC = 4.5 V An 2.7 3.3 — V IOH = –3.0 mA VCC = 4.75 V 74 VOH Output HIGH Voltage 74 2.4 3.4 — V IOH = –3.0 mA VCC = 4.5 V Bn 74 2.7 3.4 — V IOH = –3.0 mA VCC = 4.75 V 74 2.0 — — V IOH = –15.0 mA VCC = 4.5 V VOL Output LOW Voltage An 74 — 0.35 0.50 V IOL = 24 mA VCC = MIN VOL Output LOW Voltage Bn 74 — — 0.55 V IOL = 64 mA VCC = MIN IOZH + IIH Output Off Current HIGH — — 70 µA VCC = MAX VOUT = 2.7 V IOZL + IIL Output Off Current LOW — — –70 µA VCC = MAX VOUT = 0.5 V OEBA, OEAB — — 20 µA VCC = MAX, VIN = 2.7 V IIH Input HIGH Current OEBA, OEAB — — 100 µA VCC = 0 V, VIN = 7.0 V Others — — 1.0 mA VCC = MAX, VIN = 5.5 V IIL Input LOW Current Non I/O Pins — — –20 µA VCC = MAX, VIN = 0.5 V IOS Output Short Circuit Current A0–A7 –60 — –150 (Note 2) B0–B7 –100 — –225 mA VCC = MAX, VOUT = GND ICCH — — 92 Vout = HIGH ICC Power Supply Current F620 ICCL — — 110 mA Vout = LOW VCC = MAX ICCZ — — 92 Vout = HIGH Z ICC Power Supply Current F623 — — 120 mA VCC = MAX NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device type. 2. Not more than one output should be shorted at a time, nor for more than 1 second. FAST AND LS TTL DATA 4-238

MC74F620 • MC74F623 F620 LOGIC DIAGRAMS F623 19 19 OEBA OEBA 1 1 OEAB OEAB 2 18 2 18 A0 B0 A0 B0 3 17 3 17 A1 B1 A1 B1 4 16 4 16 A2 B2 A2 B2 5 15 5 15 A3 B3 A3 B3 6 14 6 14 A4 B4 A4 B4 7 13 7 13 A5 B5 A5 B5 8 12 8 12 A6 B6 A6 B6 9 11 9 11 A7 B7 A7 B7 FAST AND LS TTL DATA 4-239

MC74F620 • MC74F623 AC ELECTRICAL CHARACTERISTICS For F620 74F 74F Symbol Parameter TA = +25°C TA = 0°C to +70°C Unit VCC = +5.0 V VCC = +5.0 V ±10% ns tPLH Propagation Delay ns tPHL An to Bn and Bn to An CL = 50 pF CL = 50 pF ns ns tPZH Output Enable Time Min Typ Max Min Typ Max ns tPZL to High or Low level, OEBA to An 2.5 — 6.5 2.0 — 7.5 tPHZ Output Disable Time 1.0 — 4.5 1.0 — 5.0 tPLZ to High or Low level, OEBA to An 3.0 — 10.5 2.5 — 11.5 tPZH Output Enable Time 4.0 — 10.5 3.5 — 11.5 tPZL to High or Low level, OEAB to Bn 2.5 — 7.5 2.0 — 8.0 tPHZ Output Disable Time 1.5 — 7.0 1.0 — 7.5 tPLZ to High or Low level, OEAB to Bn 3.5 — 10.5 3.5 — 11.5 4.5 — 10.0 4.0 — 11.0 3.0 — 9.5 2.5 — 10.5 3.0 — 9.5 1.5 — 10.5 AC ELECTRICAL CHARACTERISTICS For F623 74F 74F Symbol Parameter TA = +25°C TA = 0°C to +70°C Unit VCC = +5.0 V VCC = +5.0 V ±10% ns tPLH Propagation Delay ns tPHL An to Bn CL = 50 pF CL = 50 pF ns ns tPLH Propagation Delay Min Typ Max Min Typ Max ns tPHL Bn to An ns 2.0 — 5.5 2.0 — 6.5 tPZH Output Enable Time 3.0 — 7.0 2.5 — 7.5 tPZL to High or Low level, OEBA to An 2.0 — 6.0 2.0 — 6.5 tPHZ Output Disable Time 3.0 — 7.0 2.5 — 7.5 tPLZ to High or Low level, OEBA to An 3.5 — 10.5 3.5 — 12.0 tPZH Output Enable Time 5.0 — 10.0 tPZL to High or Low level, OEAB to Bn 5.0 — 9.5 1.5 — 7.5 tPHZ Output Disable Time 1.5 — 6.5 1.5 — 7.0 tPLZ to High or Low level, OEAB to Bn 1.5 — 6.5 3.5 — 11.5 3.5 — 10.0 4.5 — 9.5 4.5 — 9.0 3.0 — 10.0 2.0 — 10.0 3.0 — 8.5 4.0 — 9.0 FAST AND LS TTL DATA 4-240

MC74F640 OCTAL BUS TRANSCEIVER, INVERTING WITH 3-STATE OUTPUTS The MC74F640 is an octal transceiver featuring inverting 3-state bus com- OCTAL BUS TRANSCEIVER, INVERTING WITH patible outputs in both transmit and receive directions. The B port outputs are 3-STATE OUTPUTS capable of sinking 64 mA and sourcing 15 mA, providing very good capacitive FAST™ SCHOTTKY TTL drive characteristics. The device features an Output Enable (OE) input for 20 J SUFFIX 1 CERAMIC easy cascading and Transmit/Receive (T/R) input for direction control. The CASE 732-03 3-state outputs, B0–B7, have been designed to prevent output bus loading if the power is removed from the device. • High-Impedance NPN Base Inputs for Reduced Loading (70 µA in High and Low States) • Ideal for Applications which Require High-Output Drive and Minimal Bus Loading • Inverting Version of F245 • Octal Bidirectional Bus Interface • 3-State Buffer Outputs Sink 64 mA and Source 15 mA • ESD Sensitive — 4000 V HBM VCC OE PIN ASSIGNMENT B7 20 N SUFFIX 20 19 11 1 PLASTIC B0 B1 B2 B3 B4 B5 B6 CASE 738-03 18 17 16 15 14 13 12 20 DW SUFFIX 1 SOIC CASE 751D-03 1 2 3 4 5 6 7 8 9 10 ORDERING INFORMATION T/R A0 A1 A2 A3 A4 A5 A6 A7 GND MC74FXXXJ Ceramic FUNCTION TABLE MC74FXXXN Plastic MC74FXXXDW SOIC Inputs H = High Voltage Level L = Low Voltage Level OE T/R Outputs X = Don’t Care LOGIC SYMBOL Z = High Impedance “Off” State 23 4 567 8 9 L L Bus B data to Bus A L H Bus A data to Bus B A0 A1 A2 A3 A4 A5 A6 A7 H XZ 1 T/R 19 OE B0 B1 B2 B3 B4 B5 B6 B7 18 17 16 15 14 13 12 11 FAST AND LS TTL DATA 4-241

MC74F640 GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit 4.5 5.0 5.5 V VCC DC Supply Voltage An Outputs 74 0 25 70 °C TA Operating Ambient Temperature Range Bn Outputs 74 mA IOH Output Current — High An Outputs 74 –3.0 mA IOH Output Current — High Bn Outputs 74 –15 mA IOL Output Current — Low 74 24 mA 74 64 IOL Output Current — Low DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Symbol Parameter Limits Unit Test Conditions1 Min Typ Max VIH Input HIGH Voltage 2.0 V Guaranteed as a HIGH Signal VIL Input LOW Voltage VIK Input Clamp Diode Voltage 0.8 V Guaranteed as a LOW Signal VOH Output HIGH Voltage –1.2 V VCC = MIN, IIN = –18 mA VOL Output LOW Voltage 74 2.4 3.3 V IOH = –3.0 mA VCC = 4.5 V VOL Output LOW Voltage 74 IOZH + IIH Output Off Current HIGH An 74 2.7 3.3 V IOH = –3.0 mA VCC = 4.75 V IOZL + IIL Output Off Current LOW 74 Bn 74 2.4 3.4 V IOH = –3.0 mA VCC = 4.5 V IIH Input HIGH Current 74 An 74 2.7 3.4 V IOH = –3.0 mA VCC = 4.75 V IIL Input LOW Current Bn IOS Output Short Circuit Current2 2.0 V IOH = –15 mA VCC = 4.5 V OE, T/R OE, T/R 0.35 0.5 V IOL = 24 mA VCC = MIN Others OE, T/R 0.55 V IOL = 64 mA VCC = MIN A0 – A7 B0 – B7 70 µA VCC = MAX VOUT = 2.7 V – 70 µA VCC = MAX VOUT = 0.5 V 40 µA VCC = MAX, VIN = 2.7 V 100 µA VCC = 0 V, VIN = 7.0 V 1.0 mA VCC = MAX, VIN = 5.5 V – 40 µA VCC = MAX, VIN = 0.5 V – 60 –150 –100 – 225 mA VCC = MAX, VOUT = GND ICCH 85 Vout = HIGH T/R = 4.5 V ICC Power Supply Current ICCL 120 mA Vout = LOW VCC = MAX T/R = 0 V ICCZ 100 OE = 4.5 V Vout = HIGH Z NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device type. 2. Not more than one output should be shorted at a time, nor for more than 1 second. FAST AND LS TTL DATA 4-242

MC74F640 LOGIC DIAGRAM A0 A1 A2 A3 A4 A5 A6 A7 23456 78 9 OE 19 18 17 16 15 14 13 12 11 1 B0 B1 B2 B3 B4 B5 B6 B7 T/R VCC = PIN 20 GND = PIN 10 AC ELECTRICAL CHARACTERISTICS 74F 74F TA = +25°C TA = 0°C to +70°C VCC = +5.0 V VCC = +5.0 V ±10% CL = 50 pF CL = 50 pF RL = 500 Ω RL = 500 Ω Symbol Parameter Min Typ Max Min Typ Max Unit ns tPLH Propagation Delay 2.0 7.0 2.0 8.0 ns tPHL An to Bn, Bn to An 1.0 5.0 1.0 5.5 ns tPZH Output Enable Time 3.5 11 3.5 13 tPZL to High or Low Level 6.0 11 6.0 12 tPHZ Output Disable Time 1.5 8.0 1.5 9.0 tPLZ to High or Low Level 1.0 7.0 1.0 7.5 FAST AND LS TTL DATA 4-243

Product Preview MC54/74F646 MC54/74F648 OCTAL TRANSCEIVER/REGISTER WITH 3-STATE OUTPUTS OCTAL TRANSCEIVER/REGISTER WITH 3-STATE OUTPUTS These devices consist of bus transceiver circuits with 3-state D-type FAST™ SCHOTTKY TTL flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B 24 J SUFFIX bus will be clocked into the registers as the appropriate clock pin goes to a 1 CERAMIC high logic level. Output Enable (OE) and DIR pins are provided to control the CASE 758-01 transceiver function. In the transceiver mode, data present at the high 24 impedance port may be stored in either the A or the B register or in both. The 1 N SUFFIX select controls can multiplex stored and real-time (transparent mode) data. PLASTIC The direction control determines which bus will receive data when the enable CASE 724-03 OE is Active LOW. In the isolation mode (OE HIGH), A data may be stored in the B register and/or B data may be stored in the A register. • Independent Registers for A and B • Multiplexed Real-Time and Stored Data • Choice of True (F646) and Inverting (F648) Data Paths • 3-State Outputs PIN ASSIGNMENTS VCC CPBA SBA OE B0 B1 B2 B3 B4 B5 B6 B7 24 23 22 21 20 19 18 17 16 15 14 13 F646 1 2 3 4 5 6 7 8 9 10 11 12 24 DW SUFFIX CPAB SAB DIR A0 A1 A2 A3 A4 A5 A6 A7 GND 1 SOIC VCC CPBA SBA OE B0 B1 B2 B3 B4 B5 B6 B7 CASE 751E-03 24 23 22 21 20 19 18 17 16 15 14 13 F648 ORDERING INFORMATION MC54FXXXJ Ceramic 1 2 3 4 5 6 7 8 9 10 11 12 MC74FXXXN Plastic CPAB SAB DIR A0 A1 A2 A3 A4 A5 A6 A7 GND MC74FXXXDW SOIC LOGIC SYMBOLS 4 5 6 7 8 9 10 11 4 5 6 7 8 9 10 11 1 CPAB A0 A1 A2 A3 A4 A5 A6 A7 1 CPAB A0 A1 A2 A3 A4 A5 A6 A7 2 SAB 2 SAB 3 DIR F646 3 DIR F648 23 CPBA 23 CPBA 22 SBA 22 SBA 21 OE B0 B1 B2 B3 B4 B5 B6 B7 21 OE B0 B1 B2 B3 B4 B5 B6 B7 20 19 18 17 16 15 14 13 20 19 18 17 16 15 14 13 This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. FAST AND LS TTL DATA 4-244

MC54/74F646 • MC54/74F648 FUNCTION TABLE Inputs Data I/O* Operation/Function CPAB CPBA A0–A7 B0–B7 OE bar DIR SAB SBA H X H or L H or L X X Input Input Isolation HX ↑ X X X Input Input Store An Data in A Register HX X HX ↑ ↑ X X Input Input Store Bn Data in B Register ↑ X X Input Input Store An/Bn Data in A/B Register LH X X L X Input Output An to Bn — Real Time (Transparent Mode) LH ↑ X L X Input Output Store An Data in A Register L H H or L X H X Input Output A Register to Bn (Stored Mode) LH ↑ X H X Input Output Clock An Data to Bn and into A Register LL X X X L Output Input Bn to An — Real Time (Transparent Mode) LL X ↑ X L Output Input Store Bn Data in B Register L L X H or L X H Output Input B Register to An (Stored Mode) LL X ↑ X H Output Input Clock An Data to Bn and into B Register *The data output function may be enabled or disabled by various signals at the OE bar and DIR inputs. Data input functions are always enabled; i.e., data at the *bus pins will be stored on every low-to-high transition of the appropriate clock inputs. H = HIGH voltage level L = LOW voltage level X = Don’t Care ↑ = Low-to-High transition GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC DC Supply Voltage 54, 74 4.5 5.0 5.5 V TA Operating Ambient Temperature Range 54 –55 25 125 °C 74 0 25 70 IOH Output Current  High 54 — — –12 mA 74 — — –15 IOL Output Current  Low 54 — — 48 mA 74 — — 64 FAST AND LS TTL DATA 4-245

MC54/74F646 • MC54/74F648 LOGIC DIAGRAM F646 OE DIR CPBA SBA SAB CPAB 1 OF 8 CHANNELS A0 C0 B0 D0 D0 C0 TO 7 OTHER CHANNELS FAST AND LS TTL DATA 4-246

MC54/74F646 • MC54/74F648 LOGIC DIAGRAM F648 OE DIR CPBA SBA SAB CPAB 1 OF 8 CHANNELS A0 C0 B0 D0 D0 C0 TO 7 OTHER CHANNELS FAST AND LS TTL DATA 4-247

MC54/74F646 • MC54/74F648 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Symbol Parameter Limits Test Conditions Min Typ Max Unit (Note 1) VIH Input HIGH Voltage 2.0 — — V Guaranteed as a HIGH Signal VIL Input LOW Voltage — — 0.8 V Guaranteed as a LOW Signal VIK Input Clamp Diode Voltage — — –1.2 V VCC = MIN, IIN = –18 mA 54/74 2.4 — — V IOH = –3.0 mA VCC = 4.5 V VOH Output HIGH Voltage An, Bn 74 2.7 — — V IOH = –3.0 mA VCC = 4.75 V 54 2.0 — — V IOH = –12.0 mA VCC = 4.5 V 74 2.0 — — V IOH = –15.0 mA VCC = 4.5 V 54 — — 0.55 V IOL = 48 mA VCC = MIN VOL Output LOW Voltage An, Bn 74 — — 0.55 V IOL = 64 mA VCC = MIN Non I/O Pins — — 20 µA VCC = MAX, VIN = 2.7 V IIH Input HIGH Current Non I/O Pins — — 100 µA VCC = MAX, VIN = 7.0 V I/O (Aa, Bn) — — 1.0 mA VCC = MAX, VIN = 5.5 V IIL Input LOW Current Non I/O Pins — — –600 µA VCC = MAX, VIN = 0.5 V IIH + IOZH Output Leakage Current I/O (An, Bn) — — 70 µA VCC = MAX VOUT = 2.7 V IIL + IOZL Output Leakage Current I/O (An, Bn) — — –650 µA VCC = MAX, VOUT = 0.5 V IOS Output Short Circuit Current (Note 2) –100 — –225 mA VCC = MAX, VOUT = GND ICCH — — 135 Vout = HIGH ICC Power Supply Current ICCL — — 150 mA Vout = LOW VCC = MAX ICCZ — — 150 Vout = HIGH Z NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device type. 2. Not more than one output should be shorted at a time, nor for more than 1 second. FAST AND LS TTL DATA 4-248

MC54/74F646 • MC54/74F648 AC ELECTRICAL CHARACTERISTICS Symbol Parameter 54/74F 54F 74F Unit MHz fMAX Maximum Clock Frequency TA = +25°C TA = –55°C to +125°C TA = 0°C to +70°C VCC = +5.0 V VCC = +5.0 V ±10% VCC = +5.0 V ±10% ns tPLH Propagation Delay ns tPHL Clock to Bus CL = 50 pF CL = 50 pF CL = 50 pF ns RL = 500 Ω RL = 500 Ω RL = 500 Ω ns tPLH Propagation Delay ns tPHL Bus to Bus (F646) Min Max Min Max Min Max ns ns tPLH Propagation Delay 100 — 75 — 90 — ns tPHL Bus to Bus (F648) 2.0 7.0 2.0 8.5 2.0 8.0 tPLH Propagation Delay 2.0 8.0 2.0 9.5 2.0 9.0 tPHL SBA or SAB to An or Bn 1.0 7.0 1.0 8.0 1.0 7.5 tPZH Output Enable Time 1.0 6.5 1.0 8.0 1.0 7.0 tPZL OE to An or Bn 1.0 7.0 1.0 10.0 1.0 7.5 tPHZ Output Disable Time 1.0 6.5 1.0 9.0 1.0 7.0 tPLZ OE to An or Bn 2.0 7.5 2.0 10.0 2.0 9.0 tPZH Output Enable Time 2.0 7.5 2.0 10.0 2.0 9.0 tPZL DIR to An or Bn 2.0 7.0 2.0 9.5 2.0 8.5 tPHZ Output Disable Time 2.0 7.0 2.0 9.5 2.0 8.5 tPLZ DIR to An or Bn 1.0 7.0 1.0 9.5 1.0 8.5 2.0 7.0 2.0 9.5 2.0 8.5 2.0 7.0 2.0 9.5 2.0 8.5 2.0 7.0 2.0 9.5 2.0 8.5 1.0 7.0 1.0 9.5 1.0 8.5 2.0 7.0 2.0 9.5 2.0 8.5 AC OPERATING REQUIREMENTS Symbol Parameter 54/74F 54F 74F Unit ns ts(H) Setup Time, HIGH or LOW TA = +25°C TA = –55°C to +125°C TA = 0°C to +70°C ts(L) Bus to Clock VCC = +5.0 V VCC = +5.0 V ±10% VCC = +5.0 V ±10% ns th(H) Hold Time, HIGH or LOW CL = 50 pF CL = 50 pF CL = 50 pF ns th(L) Bus to Clock RL = 500 Ω RL = 500 Ω RL = 500 Ω tw(H) Clock Pulse Width Min Max Min Max Min Max tw(L) HIGH or LOW 4.0 — 5.0 — 5.0 — 4.0 — 5.0 — 5.0 — 0.0 — 0.0 — 0.0 — 0.0 — 0.0 — 0.0 — 4.0 — 4.0 — 4.0 — 5.0 — 5.0 — 5.0 — FAST AND LS TTL DATA 4-249

OCTAL BIDIRECTIONAL MC74F657A,B TRANSCEIVER WITH 8-BIT PARITY GENERATOR CHECKER OCTAL BIDIRECTIONAL (3-STATE OUTPUTS) TRANSCEIVER WITH 8-BIT PARITY The MC74F657A and MC74F657B are Octal Bidirectional Transceivers GENERATOR CHECKER with an 8-bit parity Generator/Checker and 3-state outputs. (3-STATE OUTPUTS) FAST™ SCHOTTKY TTL The A and B options are faster versions of the F657 and contain eight non- inverting buffers with 3-state outputs and an 8-bit parity generator/checker. 24 J SUFFIX These devices are intended for bus-oriented applications. The buffers have 1 CERAMIC a guaranteed current sinking capability of 24 mA at the A ports and 64 mA at CASE 758-01 the B ports. The Transmit/Receiver (T/R) input determines the direction of the data flow through the bidirectional transceivers. Transmit (active HIGH) en- 24 N SUFFIX ables data from A ports to B ports; Receive (active LOW) enables data from 1 PLASTIC B ports to A ports. CASE 724-03 • High-Impedance NPN Base Input for Reduced Loading (20 µA in 24 1 DW SUFFIX HIGH and LOW States) SOIC • Ideal in Applications Where High Output Drive and Light Bus Loading CASE 751E-03 are Required (IIL is 20 µA versus Fast std of 600 µA) • Combines F245 and F280A Functions in One Package • 3-State Outputs • B Outputs, PARITY, ERROR, Sink 64 mA and Source 15 mA • 15 mA Source Current • Input Diodes for Termination Effects • Glitchless Outputs During Power Up and Power Down • High Impedance Outputs During Power Off • ESD Protection > 4000 Volts PIN ASSIGNMENT OE B0 B1 B2 B3 GND GND B4 B5 B6 B7 PARITY 24 23 22 21 20 19 18 17 16 15 14 13 ORDERING INFORMATION 1 2 3 4 5 6 7 8 9 10 11 12 MC74FXXXAJ/BJ Ceramic T/R A0 A1 A2 A3 A4 VCC A5 A6 A7 ODD/ ERROR MC74FXXXAN/BN Plastic MC74FXXXADW/BDW SOIC EVEN LOGIC SYMBOL 2 3 4 5 6 8 9 10 A0 A1 A2 A3 A4 A5 A6 A7 1 T/R PARITY 13 24 OE ERROR 12 11 EVEN/ODD B0 B1 B2 B3 B4 B5 B6 B7 23 22 21 20 17 16 15 14 FAST AND LS TTL DATA 4-250

MC74F657A, B GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit 74 4.5 5.0 5.5 V VCC Supply Voltage TA 74 0 25 70 °C Operating Ambient Temperature Range 74 –3.0/–15 mA 74 24/64 mA IOH Output Current — High IOL Output Current — Low FUNCTION TABLE OE Inputs Input/Output Error Outputs Number of L T/R Even/Odd Parity Z Outputs Mode Inputs That are High L Z L HH H H Transmit 0, 2, 4, 6, 8 L HL L L Transmit L LH H L Receive L LH L H Receive LL H Receive LL L Receive Number of Inputs Input/Output Outputs Inputs That are High Outputs Mode OE T/R Even/Odd Parity Error Transmit 1, 3, 5, 7 LH H L Z Transmit LH L H Z Receive LL H H L Receive LL H L H Receive LL L H H Receive LL L L L Z Don’t Care HX X Z Z H = HIGH Voltage Level; L = LOW Voltage Level; X = Don’t Care; Z = HIGH impedance state. FAST AND LS TTL DATA 4-251

MC74F657A, B DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter Min Typ Max Unit Test Conditions VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage VIL V Guaranteed Input LOW Voltage VIK Input LOW Voltage 0.8 V VCC = MIN, IIN = –18 mA VOH Input Clamp Diode Voltage –0.73 –1.2 VCC = 4.5 V V IOH = –3.0 mA All Outputs 74 2.4 VCC = 4.75 V Output HIGH Voltage B0–B7 2.7 3.4 PARITY, 74 2.0 V IOH = –15 mA VCC = 4.5 V ERROR VOL Output LOW Voltage A0–A7 74 0.35 0.5 V IOL = 24 mA 74 0.4 0.55 VCC = MIN B0–B7 PARITY, V IOL = 64 mA ERROR IIH Input HIGH Current T/R, OE, EVEN/ODD 100 µA VCC = 0 V, VIN = 7.0 V A0–A7 2.0 VCC = 5.5 V, VIN = 5.5 V B0–B7, PARITY mA EVEN/ODD T/R, OE 1.0 VCC = 5.5 V, VIN = 5.5 V 20 µA VCC = MAX, VIN = 2.7 V 40 IIL Input LOW Current EVEN/ODD –20 T/R, OE µA VCC = MAX, VIN = 0.5 V –40 IIH Off-State Current HIGH A0–A7 70 VCC = MAX, VOUT = 2.7 V +IOZH Level Voltage Applied B0–B7 µA IIL PARITY +IOZL Off-State Current LOW –70 VCC = MAX, VOUT = 0.5 V Level Voltage Applied ERROR IOZH 50 VCC = MAX, VOUT = 2.7 V Off-State Output Current, µA IOZL High-Level Voltage Applied –50 VCC = MAX, VOUT = 0.5 V Off-State Output Current, Low-Level Voltage Applied IOS Output Short Circuit An Outputs –60 –150 Current (Note 2) –100 mA VCC = MAX, VOUT = 0 V PARITY, Bn Outputs, ERROR –225 ICCH 90 135 ICC Total Supply Current ICCL 106 150 mA VCC = MAX ICCZ 98 145 NOTES: 1. For conditions shown as MIN or MAX, use appropriate value specified under recommended operating conditions for the applicable device type. 2. Not more than one output should be shorted at one time, nor for more than 1 second. FAST AND LS TTL DATA 4-252

MC74F657A, B F657A AC ELECTRICAL CHARACTERISTICS Symbol Parameter 74F 74F Unit ns tPLH Propagation Delay TA = +25°C TA = 0°C to +70°C ns tPHL An to Bn or Bn to An VCC = +5.0 V VCC = +5.0 V ± 10% ns Propagation Delay ns tPLH An to PARITY CL = 50 pF CL = 50 pF ns tPHL Propagation Delay Min Typ Max Min Max ns EVEN/ODD to PARITY, ERROR ns tPLH 2.0 7.0 2.0 7.5 tPHL Propagation Delay 2.0 7.0 2.0 7.5 Bn to ERROR tPLH Propagation Delay 6.0 13 5.5 14 tPHL PARITY to ERROR 6.5 13 6.5 14 tPLH Output Enable Time 4.5 10.5 4.5 11 tPHL to HIGH or LOW Level 4.5 10.5 4.5 11.5 tPZH Output Disable Time 7.0 18 6.5 19 tPZL from HIGH or LOW Level 7.0 18 6.5 19 tPHZ 8.0 14 7.0 15 tPLZ 7.0 14 7.0 15 3.0 8.0 3.0 9.0 4.0 9.0 4.0 10 2.0 7.5 2.0 8.0 2.0 6.0 2.0 6.5 F657B AC ELECTRICAL CHARACTERISTICS Symbol Parameter 74F 74F Unit ns tPLH Propagation Delay TA = +25°C TA = 0°C to +70°C ns tPHL An to Bn or Bn to An VCC = +5.0 V VCC = +5.0 V ± 10% ns Propagation Delay ns tPLH An to PARITY CL = 50 pF CL = 50 pF ns tPHL Propagation Delay Min Typ Max Min Max ns EVEN/ODD to PARITY, ERROR ns tPLH 2.0 6.0 2.0 6.5 tPHL Propagation Delay 2.0 6.0 2.0 6.5 Bn to ERROR tPLH Propagation Delay 4.5 11.5 4.5 13 tPHL PARITY to ERROR 4.5 11.5 4.5 13 tPLH Output Enable Time 2.0 7.5 2.0 8.5 tPHL to HIGH or LOW Level 2.0 7.5 2.0 8.5 tPZH Output Disable Time 4.0 15 3.5 16 tPZL from HIGH or LOW Level 4.0 15 3.5 16 tPHZ 5.0 11 4.0 12 tPLZ 5.0 11 4.0 12 2.0 7.0 2.0 8.0 2.0 7.0 2.0 8.0 2.0 6.0 2.0 6.5 2.0 6.0 2.0 6.5 FAST AND LS TTL DATA 4-253

MC74F657A, B LOGIC DIAGRAM T/R OE A0 B0 A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 EVEN/ODD PARITY ERROR FAST AND LS TTL DATA 4-254

MC74F779 8-BIT BIDIRECTIONAL 8-BIT BIDIRECTIONAL BINARY COUNTER (3-STATE) BINARY COUNTER (3-STATE) 16 J SUFFIX The MC74F779 is a fully synchronous 8-stage up/down counter with multi- 1 CERAMIC plexed 3-state I/O ports for bus-oriented applications. All control functions CASE 620-09 (hold, count up, count down, synchronous load) are controlled by two mode 16 pins (S0, S1). The device also features carry look-ahead for easy cascading. 1 N SUFFIX All state changes are initiated by the rising edge of the clock. PLASTIC CASE 648-08 When CET is High the data outputs are held in their current state and TC is held high. The TC output is not recommended for use as a clock or asynch- ronous reset due to the possibility of decoding spikes. • Multiplexed 3-State I/O Ports For Bus-oriented Applications • Built-In Look-Ahead Carry Capability • Count Frequency 145 MHz Typ • Supply Current 90 mA Typ • Fully Synchronous Operation • Separate Pins for Master Reset and Synchronous Reset • Center Power Pins to Reduce Effects of Package Inductance • See F269 for 24-Pin Separate I/O Port Version • See F579 for 20-Pin Version • ESD Protection > 4000 Volts PIN ASSIGNMENT I/O0 CP CET VCC TC S0 S1 OE 16 15 14 13 12 11 10 9 16 D SUFFIX 1 SOIC CASE 751B-03 1 2 3 4 56 78 ORDERING INFORMATION I/O1 I/O2 I/O3 GND I/O4 I/O5 I/O6 I/O7 LOGIC SYMBOL MC74FXXXJ Ceramic 11 10 MC74FXXXN Plastic MC74FXXXD SOIC S0 S1 14 CET TC 12 15 CP 9 OE I/O0–I/O7 TC I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O0–I/O7 2345 6 789 TC GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 74 4.5 5.0 5.5 V TA Operating Ambient Temperature Range 74 74 0 25 70 °C IOH Output Current — High 74 –3.0 mA –1.0 IOL Output Current — Low 24 mA 20 FAST AND LS TTL DATA 4-255

MC74F779 FUNCTION TABLE S1 S0 CET OE CP Operating Mode X X X H X I/Oa to I/Oh in Hi-Z X X X L X Flip-flop outputs appear on I/O lines L L X H ↑ Parallel load all flip-flops (not LL) H X ↑ Hold (TC held High) H L L X ↑ Count up L H L X ↑ Count Down H = High voltage level L = Low voltage level X = Don’t care ↑ = Low-to-High clock transition (not LL) = S1 and S2 should never be Low voltage level at the same time in the hold mode only. DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) 74F Symbol Parameter Typ Unit Test Conditions Min (Note 2) Max (Note 1) 2.5 IOH= –1.0 mA VCC = 4.5 V TC V VIL = MAX VOH Output HIGH Voltage 2.7 3.4 VIH = MIN VCC = 4.75 V 3.3 2.4 3.3 IOH = –3.0 mA VCC = 4.5 V I/On V VIL= MAX 2.7 VIH = MIN VCC = 4.75 V TC IOL = 20 mA VCC = 4.5 V VOL Output LOW Voltage 0.35 0.5 V VIL = MAX I/On IOL = 24 mA VIH = MIN VIK Input Clamp Diode Voltage –0.73 –1.2 V VCC = 4.5 V, IIN = –18 mA IIH Input HIGH Current I/On 1.0 mA VIN = 5.5 V others 100 µA VCC = 5.5 V VIN = 7.0 V I/On others 70 µA VCC = 5.5 V, VIN = 2.7 V 20 IIL Input LOW Current Except –0.6 mA VCC = 5.5 V, VIN = 0.5 V IOZH I/On IOZL OFF-State Current 70 VOUT = 2.7 V High-Level Voltage Applied I/On VOUT = 0.5 V µA VCC = 5.5 V OFF-State Current –600 Low-Level Voltage Applied IOS Output Short Circuit Current (Note 3) –60 –80 –150 mA VCC = MAX, VOUT = 0 V ICCH 82 116 ICC Total Supply Current (total) ICCL 91 128 mA VCC = MAX ICCZ 97 136 NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under guaranteed operating conditions for the applicable device type. 2. All typical values are at VCC = 5.0 V, TA = 25°C. 3. Not more than one output should be shorted at a time. FAST AND LS TTL DATA 4-256

MC74F779 AC ELECTRICAL CHARACTERISTICS Symbol Parameter 74F 74F Unit MHz fMAX Maximum Clock Frequency TA = +25°C TA = 0°C to +70°C VCC = +5.0 V VCC = +5.0 V ±10% ns tPLH Propagation Delay tPHL CP to I/On CL = 50 pF CL = 50 pF ns tPLH Propagation Delay Min Typ Max Min Max ns tPHL CP to TC 125 80 ns tPLH Propagation Delay tPHL CET to TC 4.5 10.5 4.5 11 ns 5.5 10.5 5.5 11 tPZH Enable Time from tPZL High or Low Level 4.5 9.0 4.5 10 4.5 9.0 4.5 10 tPHZ Disable Time from tPLZ High or Low Level 3.0 6.5 2.5 7.5 3.0 7.5 2.5 8.0 2.5 7.0 2.5 8.0 4.5 9.0 4.5 9.5 1.0 6.5 1.0 8.0 1.0 7.0 1.0 8.0 AC SETUP REQUIREMENTS Symbol Parameter 74F 74F Unit ns ts(H) Set-up time, HIGH or LOW TA = +25°C TA = 0°C to +70°C ns ts(L) I/On to CP VCC = +5.0 V VCC = +5.0 V ±10% ns Hold time, HIGH or LOW ns th(H) I/On to CP CL = 50 pF CL = 50 pF ns th(L) Set-up time, HIGH or LOW ns CET to CP Min Typ Max Min Typ Max ns ts(H) ts(L) Hold time, HIGH or LOW 5.0 5.0 CET to CP 5.0 5.0 th(H) th(L) Set-up time, HIGH or LOW 1.0 2.0 Sn to CP 1.0 2.0 ts(H) Hold time, HIGH or LOW ts(L) Sn to CP 5.0 5.0 5.5 6.0 th(H) Clock Pulse Width th(L) 0 0 0 0 tw(H) tw(L) 8.0 8.5 8.0 8.5 0 0 0 0 4.0 4.0 4.0 4.0 FAST AND LS TTL DATA 4-257

MC74F779 LOGIC DIAGRAM S0 LOAD CONTROL CP S1 UP DOWN OE DETAIL A I/O0 DETAIL A I/O1 DETAIL A I/O2 DETAIL A I/O3 DETAIL A I/O4 DETAIL A I/O5 DETAIL A I/O6 I/O7 TOGGLE DETAIL A CET Detail A TC DATA LOAD CP Q MR Q DQ CP Q FAST AND LS TTL DATA 4-258

MOTOROLA Order this document from Logic Marketing SEMICONDUCTOR TECHNICAL DATA Clock Driver MC74F803 Quad DĆType FlipĆFlop CLOCK DRIVER QUAD With Matched Propagation Delays D-TYPE FLIP-FLOP WITH MATCHED PROPAGATION The MC74F803 is a high-speed, low-power, quad D-type flip-flop featuring separate D-type inputs, and inverting outputs with closely matched propaga- DELAYS tion delays. With a buffered clock (CP) input that is common to all flip-flops, the F803 is useful in high-frequency systems as a clock driver, providing multi- J SUFFIX ple outputs that are synchronous. Because of the matched propagation de- CERAMIC lays, the duty cycles of the output waveforms in a clock driver application are CASE 632-08 symmetrical within 1.0 to 1.5 nanoseconds. 14 • Edge-Triggered D-Type Inputs 1 • Buffered Positive Edge-Triggered Clock • Matched Outputs for Synchronous Clock Driver Applications • Outputs Guaranteed for Simultaneous Switching Pinout: 14-Lead Plastic (Top View) VCC NC O3 D3 D2 O2 CP 14 13 12 11 10 9 8 1234567 14 N SUFFIX GND NC O0 D0 D1 O1 GND 1 PLASTIC CASE 646-06 14 1 D SUFFIX SOIC CASE 751A-03 GUARANTEED OPERATION RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 4.5 5.0 5.5 V TA Operating Ambient 0 25 70 °C LOGIC SYMBOL Temperature Range 4 5 10 11 IOH Output Current — High — — –20 mA D0 D1 D2 D3 IOL Output Current — Low — — 24 mA 8 CP LOGIC DIAGRAM O0 O1 O2 O3 D0 D1 D2 D3 3 6 9 12 CP VCC = PIN 14 CP D CP D CP D CP D GND = PINS 1 AND 7 Q Q Q Q NC = PINS 2 AND 13 O0 O1 O2 O3 11/93 REV 3 © Motorola, Inc. 1994