TTL_Databook

SN54 / 74LS137 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Symbol Parameter Limits Unit Test Conditions Min Typ Max VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for All Inputs 54 0.7 Guaranteed Input LOW Voltage for VIL Input LOW Voltage 0.8 V All Inputs 74 VIK Input Clamp Diode Voltage – 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA VOH Output HIGH Voltage 54 2.5 3.5 V VCC = MIN, IOH = MAX, VIN = VIH 74 2.7 3.5 V or VIL per Truth Table VOL Output LOW Voltage 54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN, 74 0.35 0.5 V IOL = 8.0 mA VIN = VIL or VIH per Truth Table IIH Input HIGH Current 20 µA VCC = MAX, VIN = 2.7 V 0.1 mA VCC = MAX, VIN = 7.0 V IIL Input LOW Current – 0.4 mA VCC = MAX, VIN = 0.4 V IOS Short Circuit Current (Note 1) – 20 –100 mA VCC = MAX ICC Power Supply Current 18 mA VCC = MAX Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (VCC = 5.0 V, TA = 25°C) Symbol Parameter Levels of Limits Unit Test Conditions Propagation Delay Time, A, B, C to Y Delay ns tPLH Propagation Delay Time, A, B, C to Y Min Typ Max ns VCC = 5.0 V tPHL Propagation Delay Time, Enable G2 to Y 2 ns CL = 15 pF Propagation Delay Time, Enable G1 to Y 4 11 17 ns tPLH Propagation Delay Time, Enable GL to Y 25 38 ns tPHL 3 3 16 24 tPLH 19 29 tPHL 2 2 13 21 tPLH 16 27 tPHL 3 3 14 21 tPLH 18 27 tPHL 3 4 18 27 25 38 AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V) Symbol Parameter Min Limits Max Unit Test Conditions Pulse Width — Enable at GL 15 Typ ns VCC = 5.0 V tW Setup Time, A, B, C 10 ns ts Hold Time, A, B, C 10 ns th FAST AND LS TTL DATA 5-129

1-OF-8 DECODER/ SN54/74LS138 DEMULTIPLEXER 1-OF-8 DECODER / The LSTTL / MSI SN54 / 74LS138 is a high speed 1-of-8 Decoder / DEMULTIPLEXER Demultiplexer. This device is ideally suited for high speed bipolar memory chip select address decoding. The multiple input enables allow parallel ex- LOW POWER SCHOTTKY pansion to a 1-of-24 decoder using just three LS138 devices or to a 1-of-32 decoder using four LS138s and one inverter. The LS138 is fabricated with the J SUFFIX Schottky barrier diode process for high speed and is completely compatible CERAMIC with all Motorola TTL families. CASE 620-09 • Demultiplexing Capability 16 • Multiple Input Enable for Easy Expansion 1 • Typical Power Dissipation of 32 mW • Active Low Mutually Exclusive Outputs • Input Clamp Diodes Limit High Speed Termination Effects CONNECTION DIAGRAM DIP (TOP VIEW) VCC O0 O1 O2 O3 O4 O5 O6 16 15 14 13 12 11 10 9 NOTE: 16 N SUFFIX The Flatpak version 1 PLASTIC has the same pinouts CASE 648-08 (Connection Diagram) as the Dual In-Line Package. 1 2 3 4 56 78 A0 A1 A2 E1 E2 E3 O7 GND PIN NAMES LOADING (Note a) D SUFFIX SOIC HIGH LOW 16 1 CASE 751B-03 A0 – A2 Address Inputs 0.5 U.L. 0.25 U.L. ORDERING INFORMATION E1, E2 Enable (Active LOW) Inputs 0.5 U.L. 0.25 U.L. E3 Enable (Active HIGH) Input 0.5 U.L. 0.25 U.L. SN54LSXXXJ Ceramic O0 – O7 Active LOW Outputs (Note b) 10 U.L. 5 (2.5) U.L. SN74LSXXXN Plastic SN74LSXXXD SOIC NOTES: a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) Temperature Ranges. LOGIC DIAGRAM LOGIC SYMBOL A2 A1 A0 E1 E2 E3 123 456 32 1 45 6 VCC = PIN 16 GND = PIN 8 12 3 = PIN NUMBERS A0 A1 A2 E O0 O1 O2 O3 O4 O5 O6 O7 15 14 13 12 11 10 9 7 VCC = PIN 16 GND = PIN 8 7 9 10 11 12 13 14 15 O7 O6 O5 O4 O3 O2 O1 O0 FAST AND LS TTL DATA 5-130

SN54 / 74LS138 FUNCTIONAL DESCRIPTION pansion of the device to a 1-of-32 (5 lines to 32 lines) decoder with just four LS138s and one inverter. (See Figure a.) The LS138 is a high speed 1-of-8 Decoder/Demultiplexer The LS138 can be used as an 8-output demultiplexer by fabricated with the low power Schottky barrier diode process. using one of the active LOW Enable inputs as the data input and the other Enable inputs as strobes. The Enable inputs The decoder accepts three binary weighted inputs (A0, A1, A2) which are not used must be permanently tied to their appropri- and when enabled provides eight mutually exclusive active ate active HIGH or active LOW state. LOW Outputs (O0 – O7). The LS138 features three Enable in- puts, two active LOW (E1, E2) and one active HIGH (E3). All outputs will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel ex- TRUTH TABLE INPUTS OUTPUTS E1 E2 E3 A0 A1 A2 O0 O1 O2 O3 O4 O5 O6 O7 HXXXXXHHHHHHH H XHXXXXHHHHHHH H XX L XXXHHHHHHH H L LHL L L LHHHHHH H L LHHL LHLHHHHH H L LHLHLHHLHHHH H L LHHHLHHHLHHH H L LHL LHHHHHLHH H L LHHLHHHHHHLH H L LHLHHHHHHHHL H L LHHHHHHHHHHH L H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care A0 A1 A2 LS04 A3 123 123 123 A4 H 123 A0 A1 A2 E A0 A1 A2 E A0 A1 A2 E A0 A1 A2 E LS138 LS138 LS138 LS138 O0 O1 O2 O3 O4 O5 O6 O7 O0 O1 O2 O3 O4 O5 O6 O7 O0 O1 O2 O3 O4 O5 O6 O7 O0 O1 O2 O3 O4 O5 O6 O7 O0 O31 Figure a FAST AND LS TTL DATA 5-131

SN54 / 74LS138 GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 4.5 5.0 5.5 V 74 4.75 5.0 5.25 TA Operating Ambient Temperature Range 54 – 55 25 125 °C 74 0 25 70 IOH Output Current — High 54, 74 – 0.4 mA IOL Output Current — Low 54 4.0 mA 74 8.0 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Symbol Parameter Limits Unit Test Conditions Min Typ Max VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for All Inputs 54 0.7 Guaranteed Input LOW Voltage for VIL Input LOW Voltage 0.8 V All Inputs 74 VIK Input Clamp Diode Voltage 54 – 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA VOH Output HIGH Voltage 74 2.5 3.5 2.7 3.5 V VCC = MIN, IOH = MAX, VIN = VIH V or VIL per Truth Table VOL Output LOW Voltage 54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN, 74 0.35 0.5 V IOL = 8.0 mA VIN = VIL or VIH per Truth Table IIH Input HIGH Current 20 µA VCC = MAX, VIN = 2.7 V 0.1 mA VCC = MAX, VIN = 7.0 V IIL Input LOW Current – 0.4 mA VCC = MAX, VIN = 0.4 V IOS Short Circuit Current (Note 1) – 20 –100 mA VCC = MAX ICC Power Supply Current 10 mA VCC = MAX Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C) Symbol Parameter Levels of Limits Unit Test Conditions Delay ns tPLH Propagation Delay Min Typ Max ns VCC = 5.0 V tPHL Address to Output 2 ns CL = 15 pF 2 13 20 ns tPLH Propagation Delay 27 41 tPHL Address to Output 3 3 18 27 tPLH Propagation Delay E1 or E2 26 39 tPHL Enable to Output 2 2 12 18 tPLH Propagation Delay E3 21 32 tPHL Enable to Output 3 3 17 26 25 38 VIN 1.3 V AC WAVEFORMS 1.3 V 1.3 V VOUT tPHL 1.3 V VIN 1.3 V tPLH tPHL tPLH 1.3 V 1.3 V VOUT 1.3 V Figure 1 Figure 2 FAST AND LS TTL DATA 5-132

DUAL 1-OF-4 DECODER/ SN54/74LS139 DEMULTIPLEXER DUAL 1-OF-4 DECODER / The LSTTL/MSI SN54/74LS139 is a high speed Dual 1-of-4 Decoder /De- DEMULTIPLEXER multiplexer. The device has two independent decoders, each accepting two inputs and providing four mutually exclusive active LOW Outputs. Each LOW POWER SCHOTTKY decoder has an active LOW Enable input which can be used as a data input for a 4-output demultiplexer. Each half of the LS139 can be used as a function J SUFFIX generator providing all four minterms of two variables. The LS139 is CERAMIC fabricated with the Schottky barrier diode process for high speed and is CASE 620-09 completely compatible with all Motorola TTL families. 16 • Schottky Process for High Speed 1 • Multifunction Capability • Two Completely Independent 1-of-4 Decoders • Active Low Mutually Exclusive Outputs • Input Clamp Diodes Limit High Speed Termination Effects • ESD > 3500 Volts CONNECTION DIAGRAM DIP (TOP VIEW) N SUFFIX VCC Eb AOb A1b O0b O1b O2b O3b PLASTIC 16 15 14 13 12 11 10 9 CASE 648-08 NOTE: 16 The Flatpak version 1 has the same pinouts (Connection Diagram) as the Dual In-Line Package. 1 2 3 4 56 78 16 D SUFFIX Ea A0a A1a O0a O1a O2a O3a GND 1 SOIC CASE 751B-03 PIN NAMES LOADING (Note a) HIGH LOW A0, A1 Address Inputs 0.5 U.L. 0.25 U.L. ORDERING INFORMATION E Enable (Active LOW) Input 0.5 U.L. 0.25 U.L. Active LOW Outputs (Note b) 10 U.L. 5 (2.5) U.L. SN54LSXXXJ Ceramic O0 – O3 SN74LSXXXN Plastic SN74LSXXXD SOIC NOTES: a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. LOGIC SYMBOL b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) Temperature Ranges. LOGIC DIAGRAM Ea A0a A1a Eb A0b A1b 1 23 15 14 13 1 23 15 14 13 E A0 A1 E A0 A1 DECODER a DECODER b O0 O1 O2 O3 O0 O1 O2 O3 VCC = PIN 16 456 7 12 11 10 9 GND = PIN 8 = PIN NUMBERS VCC = PIN 16 GND = PIN 8 45 6 7 12 11 10 9 O0a O1a O2a O3a O0b O1b O2b O3b FAST AND LS TTL DATA 5-133

SN54 / 74LS139 FUNCTIONAL DESCRIPTION demultiplexer application. Each half of the LS139 generates all four minterms of two The LS139 is a high speed dual 1-of-4 decoder/demultiplex- er fabricated with the Schottky barrier diode process. The variables. These four minterms are useful in some applica- device has two independent decoders, each of which accept tions, replacing multiple gate functions as shown in Fig. a, and two binary weighted inputs (A0, A1) and provide four mutually thereby reducing the number of packages required in a logic exclusive active LOW outputs (O0 – O3). Each decoder has an network. active LOW Enable (E). When E is HIGH all outputs are forced HIGH. The enable can be used as the data input for a 4-output TRUTH TABLE EE O0 A0 O0 A0 O1 INPUTS OUTPUTS A1 A1 O2 O3 E A0 A1 O0 O1 O2 O3 EE A0 O1 A0 HXXHHH H A1 A1 L L L LHH H LHLHLH H EE L LHHHL H A0 O2 A0 L HHHHH L A1 A1 H = HIGH Voltage Level EE L = LOW Voltage Level A0 O3 A0 X = Don’t Care A1 A1 Figure a GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 4.5 5.0 5.5 V 74 4.75 5.0 5.25 TA Operating Ambient Temperature Range 54 – 55 25 125 °C 74 0 25 70 IOH Output Current — High 54, 74 – 0.4 mA IOL Output Current — Low 54 4.0 mA 74 8.0 FAST AND LS TTL DATA 5-134

SN54 / 74LS139 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Symbol Parameter Limits Unit Test Conditions Min Typ Max VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for All Inputs 54 0.7 Guaranteed Input LOW Voltage for VIL Input LOW Voltage 0.8 V All Inputs 74 VIK Input Clamp Diode Voltage – 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA VOH Output HIGH Voltage 54 2.5 3.5 V VCC = MIN, IOH = MAX, VIN = VIH 74 2.7 3.5 V or VIL per Truth Table VOL Output LOW Voltage 54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN, 74 0.35 0.5 V IOL = 8.0 mA VIN = VIL or VIH per Truth Table IIH Input HIGH Current 20 µA VCC = MAX, VIN = 2.7 V 0.1 mA VCC = MAX, VIN = 7.0 V IIL Input LOW Current – 0.4 mA VCC = MAX, VIN = 0.4 V IOS Short Circuit Current (Note 1) – 20 –100 mA VCC = MAX ICC Power Supply Current 11 mA VCC = MAX Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C) Symbol Parameter Levels of Limits Unit Test Conditions Delay ns tPLH Propagation Delay Min Typ Max ns VCC = 5.0 V tPHL Address to Output 2 ns CL = 15 pF 2 13 20 tPLH Propagation Delay 22 33 tPHL Address to Output 3 3 18 29 tPLH Propagation Delay 25 38 tPHL Enable to Output 2 2 16 24 21 32 VIN 1.3 V AC WAVEFORMS 1.3 V 1.3 V VOUT tPHL 1.3 V VIN 1.3 V tPLH tPHL tPLH 1.3 V 1.3 V VOUT 1.3 V Figure 1 Figure 2 FAST AND LS TTL DATA 5-135

SN54/74LS145 1-OF-10 DECODER/DRIVER 1-OF-10 DECODER / DRIVER OPEN-COLLECTOR OPEN-COLLECTOR The SN54 / 74LS145, 1-of-10 Decoder/Driver, is designed to accept BCD LOW POWER SCHOTTKY inputs and provide appropriate outputs to drive 10-digit incandescent displays. All outputs remain off for all invalid binary input conditions. It is J SUFFIX designed for use as indicator/relay drivers or as an open-collector logic circuit CERAMIC driver. Each of the high breakdown output transistors will sink up to 80 mA of CASE 620-09 current. Typical power dissipation is 35 mW. This device is fully compatible with all TTL families. 16 • Low Power Version of 54 / 74145 1 • Input Clamp Diodes Limit High Speed Termination Effects CONNECTION DIAGRAM DIP (TOP VIEW) VCC P0 P1 P2 P3 Q9 Q8 Q7 16 15 14 13 12 11 10 9 16 N SUFFIX 1 PLASTIC CASE 648-08 1 2 3 4 56 78 Q0 Q1 Q2 Q3 Q4 Q5 Q6 GND PIN NAMES LOADING (Note a) D SUFFIX SOIC HIGH LOW 16 1 CASE 751B-03 P0, P1, P2, P3 BCD Inputs 0.5 U.L. 0.25 U.L. Q0 to Q9 Outputs (Note b) Open Collector 15 (7.5) U.L. NOTES: ORDERING INFORMATION a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 15 U.L. for Commercial (74) SN54LSXXXJ Ceramic SN74LSXXXN Plastic Temperature Ranges. SN74LSXXXD SOIC LOGIC DIAGRAM INPUTS P2 P3 LOGIC SYMBOL P0 P1 15 14 13 12 P0 P1 P2 P3 INPUT INVERTERS Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 1 2 3 4 5 6 7 9 10 11 0 0 1 1 2 2 33 VCC = PIN 16 DECODE/DRIVER GND = PIN 8 GATES Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 OUTPUTS FAST AND LS TTL DATA 5-136

SN54 / 74LS145 TRUTH TABLE INPUTS OUTPUTS P3 P2 P1 P0 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 L L L L LHHHHHHHHH L L LHHLHHHHHHHH L LHLHHLHHHHHHH L LHHHHHLHHHHHH LHL LHHHHLHHHHH L H L HHHHHH L HHHH L HH L HHHHHH L HHH L HHHHHHHHHH L HH HL L LHHHHHHHHLH HL LHHHHHHHHHHL H L H L HHHHHHHHHH H L HHHHHHHHHHHH HHL LHHHHHHHHHH HH L HHHHHHHHHHH HHH L HHHHHHHHHH HHHHHHHHHHHHHH H = HIGH Voltage Level L = LOW Voltage Level GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 4.5 5.0 5.5 V 74 4.75 5.0 5.25 TA Operating Ambient Temperature Range 54 – 55 25 125 °C 74 0 25 70 VOH Output Voltage — High 54, 74 15 V IOL Output Current — Low 54 12 mA 74 24 FAST AND LS TTL DATA 5-137

SN54 / 74LS145 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Symbol Parameter Limits Unit Test Conditions Min Typ Max VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for All Inputs 54 0.7 Guaranteed Input LOW Voltage for VIL Input LOW Voltage 0.8 V All Inputs 74 VIK Input Clamp Diode Voltage – 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA IOH Output HIGH Current 250 54, 74 0.25 0.4 µA VCC = MIN, VOH = MAX VOL Output LOW Voltage 54, 74 0.35 0.5 2.3 3.0 V IOL = 12 mA VCC = VCC MIN, IIH 74 20 V IOL = 24 mA VIN = VIL or VIH IIL 54, 74 0.1 V IOL = 80 mA per Truth Table ICC – 0.4 Input HIGH Current 13 µA VCC = MAX, VIN = 2.7 V mA VCC = MAX, VIN = 7.0 V Input LOW Current mA VCC = MAX, VIN = 0.4 V Power Supply Current mA VCC = MAX, VIN = GND AC CHARACTERISTICS (TA = 25°C) Symbol Parameter Limits Unit Test Conditions ns tPHL Propagation Delay Min Typ Max VCC = 5.0 V tPLH Pn Input to Qn Output CL = 45 pF 50 50 AC WAVEFORMS VIN 1.3 V 1.3 V VIN 1.3 V 1.3 V VOUT tPHL tPLH VOUT tPHL tPLH 1.3 V 1.3 V 1.3 V 1.3 V Figure 1 Figure 2 FAST AND LS TTL DATA 5-138

10-LINE-TO-4-LINE SN54/74LS147 AND 8-LINE-TO-3-LINE SN54/74LS148 PRIORITY ENCODERS SN54/74LS748 The SN54 / 74LS147 and the SN54 / 74LS148 are Priority Encoders. They 10-LINE-TO-4-LINE provide priority decoding of the inputs to ensure that only the highest order AND 8-LINE-TO-3-LINE data line is encoded. Both devices have data inputs and outputs which are PRIORITY ENCODERS active at the low logic level. LOW POWER SCHOTTKY The LS147 encodes nine data lines to four-line (8-4-2-1) BCD. The implied decimal zero condition does not require an input condition because zero is J SUFFIX encoded when all nine data lines are at a high logic level. CERAMIC CASE 620-09 The LS148 encodes eight data lines to three-line (4-2-1) binary (octal). By providing cascading circuitry (Enable Input EI and Enable Output EO) octal 16 expansion is allowed without needing external circuitry. 1 The SN54 / 74LS748 is a proprietary Motorola part incorporating a built-in N SUFFIX deglitcher network which minimizes glitches on the GS output. The glitch PLASTIC occurs on the negative going transition of the EI input when data inputs 0 – 7 CASE 648-08 are at logical ones. The only dc parameter differences between the LS148 and the LS748 are that (1) Pin 10 (input 0) has a fan-in of 2 on the LS748 versus a fan-in of 1 on the LS148; (2) Pins 1, 2, 3, 4, 11, 12 and 13 (inputs 1, 2, 3, 4, 5, 6, 7) have a fan-in of 3 on the LS748 versus a fan-in of 2 on the LS148. The only ac difference is that tPHL from EI to EO is changed from 40 to 45 ns. SN54 / 74LS147 16 (TOP VIEW) 1 OUTPUT INPUTS OUTPUT VCC NC D 3 2 1 9 A 16 D SUFFIX 16 15 14 13 12 11 10 9 1 SOIC CASE 751B-03 D 32 1 9 ORDERING INFORMATION 4A SN54LSXXXJ Ceramic 5 678C B SN74LSXXXN Plastic SN74LSXXXD SOIC 1 2 3 4 56 78 4 5 6 7 8 C B GND INPUTS OUTPUTS SN54 / 74LS148 SN54 / 74LS748 (TOP VIEW) OUTPUTS 3 INPUTS OUTPUT 13 21 0 A0 VCC EO GS 12 11 10 9 16 15 14 EO GS 3 2 1 0 4 A0 5 6 7 EI A2 A1 1 2 3 4 56 78 4 5 6 7 E1 A2 A1 GND INPUTS OUTPUTS FAST AND LS TTL DATA 5-139

SN54/74LS147 • SN54/74LS148 • SN54/74LS748 SN54 / 74LS147 SN54 / 74LS148 FUNCTION TABLE SN54 / 74LS748 FUNCTION TABLE INPUTS OUTPUTS INPUTS OUTPUTS 1 2 3 4 5 6 7 8 9 DCBA EI 0 1 2 3 4 5 6 7 A2 A1 A0 GS EO HH HHH HHHH HH HH HX XXXXXXX H H H H H XX XXX XXXL LHHL L H HHHHHHH H H H H L XX X XX XX LH LH HH L X XXXXXXL L L L L H XX XXX X L HHHL L L L X XXXXXLH L L H L H XX XXX LHHHHL LH L X XXXX LHH L H L L H XX XX L HHHHHL HL L X XXX LHHH L H H L H XX X LHHHHHHL HH L X XX LHHHH H L L L H XX L HHHHHHHH L L L X X LHHHHH H L H L H X L HHHHHHHHH LH L X LHHHHHH H H L L H L H HHH HH HH HH H L L L HHHHHHH H H H L H H = HIGH Logic Level, L = LOW Logic Level, X = Irrelevant FUNCTIONAL BLOCK DIAGRAMS 1 (11) (9) A (10) (15) (12) 0 EO (7) B 2 (11) (14) (13) (6) 1 GS C 3 (12) (8) (1) 2 A0 4 (13) (7) 5 (2) 3 A1 (3) 4 (1) (6) 6 A2 7 (4) (2) (14) D 5 (5) 8 (3) 9 (10) 6 (4) 7 (5) EI SN54 / 74LS147 SN54 / 74LS148 FAST AND LS TTL DATA 5-140

SN54/74LS147 • SN54/74LS148 • SN54/74LS748 FUNCTIONAL BLOCK DIAGRAMS (continued) G31 0(10) G2 G13 (15) 1(11) G9 EO 2(12) 3(13) G3 (14) 4 (1) GS G4 (2) G10 G29 5 (9) 6 (3) G5 A0 G11 (4) G18 7 G6 G12 (7) A1 (5) G23 EI G7 (6) G8 A2 G1 G28 SN54 / 74LS748 FAST AND LS TTL DATA 5-141

SN54/74LS147 • SN54/74LS148 • SN54/74LS748 GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 4.5 5.0 5.5 V 74 4.75 5.0 5.25 TA Operating Ambient Temperature Range 54 – 55 25 125 °C 74 0 25 70 IOH Output Current — High 54, 74 – 0.4 mA IOL Output Current — Low 54 4.0 mA 74 8.0 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Symbol Parameter Limits Unit Test Conditions VIH Input HIGH Voltage Min Typ Max V Guaranteed Input HIGH Voltage for 2.0 All Inputs 54 0.7 Guaranteed Input LOW Voltage for VIL Input LOW Voltage 0.8 V All Inputs 74 VIK Input Clamp Diode Voltage 54 – 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA VOH Output HIGH Voltage 74 2.5 3.5 2.7 3.5 V VCC = MIN, IOH = MAX, VIN = VIH V or VIL per Truth Table VOL Output LOW Voltage 54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN, 74 0.35 0.5 V IOL = 8.0 mA VIN = VIL or VIH per Truth Table Input HIGH Current 20 All Others Input 0 (LS748) 40 µA VCC = MAX, VIN = 2.7 V Inputs 1 – 7 (LS148) 40 IIH Inputs 1 – 7 (LS748) 60 All Others Input 0 (LS748) 0.1 Inputs 1 – 7 (LS148) Inputs 1 – 7 (LS748) 0.2 mA VCC = MAX, VIN = 7.0 V 0.2 0.3 Input LOW Current – 0.4 mA VCC = MAX, VIN = 0.4 V – 0.8 All Others – 0.8 – 1.2 IIL Input 0 (LS748) Inputs 1 – 7 (LS148) Inputs 1 – 7 (LS748) IOS Short Circuit Current (Note 1) – 20 – 100 mA VCC = MAX ICCH Power Supply Current Output HIGH 17 mA VCC = MAX, All Inputs = 4.5 V ICCL Output LOW 20 mA VCC = MAX, Inputs 7 & E1 = GND All Other Inputs = 4.5 V Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. FAST AND LS TTL DATA 5-142

SN54/74LS147 • SN54/74LS148 • SN54/74LS748 AC CHARACTERISTICS (VCC = 5.0 V, TA = 25°C) SN54 / 74LS147 Symbol From To Waveform Limits Unit Test Conditions (Input) (Output) Min Typ Max ns tPLH In-phase tPHL Any Any output 12 18 CL = 15 pF, tPLH 12 18 RL = 2.0 kΩ tPHL Any Any Out-of-phase 21 33 ns output 15 23 Unit Test Conditions SN54 / 74LS148 Limits ns SN54 / 74LS748 Min Typ Max ns Symbol From To Waveform 14 18 (Input) (Output) 15 25 ns tPLH 1 thru 7 In-phase 20 36 CL = 15 pF, tPHL 1 thru 7 A0, A1, or A2 output 16 29 tPLH 0 thru 7 7.0 18 ns RL = 2.0 kΩ tPHL 0 thru 7 A0, A1, or A2 Out-of-phase 25 40 tPLH 35 55 ns tPHL EI output 9.0 21 tPLH EI 16 25 ns tPHL Out-of-phase 12 25 tPLH EI EO output 12 17 ns (LS148) tPHL 14 36 (LS748) tPLH In-phase 12 21 tPHL GS output 28 40 tPLH 30 45 tPHL A0, A1, or A2 In-phase output In-phase GS output EO In-phase output FAST AND LS TTL DATA 5-143

SN54/74LS151 8-INPUT MULTIPLEXER 8-INPUT MULTIPLEXER LOW POWER SCHOTTKY The TTL / MSI SN54 / 74LS151 is a high speed 8-input Digital Multiplexer. It provides, in one package, the ability to select one bit of data from up to eight J SUFFIX sources. The LS151 can be used as a universal function generator to CERAMIC generate any logic function of four variables. Both assertion and negation CASE 620-09 outputs are provided. • Schottky Process for High Speed 16 • Multifunction Capability 1 • On-Chip Select Logic Decoding • Fully Buffered Complementary Outputs • Input Clamp Diodes Limit High Speed Termination Effects CONNECTION DIAGRAM DIP (TOP VIEW) VCC I4 I5 I6 I7 S0 S1 S2 16 15 14 13 12 11 10 9 16 N SUFFIX 1 PLASTIC CASE 648-08 1 2 3 4 56 78 D SUFFIX I3 I2 I1 I0 Z Z E GND SOIC 16 CASE 751B-03 1 PIN NAMES LOADING (Note a) ORDERING INFORMATION SN54LSXXXJ Ceramic SN74LSXXXN Plastic SN74LSXXXD SOIC HIGH LOW S0 – S2 Select Inputs 0.5 U.L. 0.25 U.L. LOGIC SYMBOL E Enable (Active LOW) Input 0.5 U.L. 0.25 U.L. Multiplexer Inputs 0.5 U.L. 0.25 U.L. 7 4 3 2 1 15 14 13 12 I0 – I7 Multiplexer Output (Note b) 10 U.L. 5 (2.5) U.L. Z Complementary Multiplexer Output 10 U.L. 5 (2.5) U.L. Z (Note b) NOTES: 11 E I0 I1 I2 I3 I4 I5 I6 I7 a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. S0 b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) 10 S1 Temperature Ranges. 9 S2 ZZ 65 VCC = PIN 16 GND = PIN 8 FAST AND LS TTL DATA 5-144

LOGIC DIAGRAM SN54 / 74LS151 9 I0 I1 I2 I3 I4 I5 I6 I7 S2 4 3 2 1 15 14 13 12 10 S1 S0 11 7 E VCC = PIN 16 65 GND = PIN 8 ZZ = PIN NUMBERS FUNCTIONAL DESCRIPTION Z = E ⋅ (I0 ⋅ S0 ⋅ S1 ⋅ S2 + ⋅ I1 ⋅ S0 ⋅ S1 ⋅ S2 + I2 ⋅ S0 ⋅ S1 ⋅ S2 + I3 ⋅ S0 ⋅ S1 ⋅ S2 + I4 ⋅ S0 ⋅ S1 ⋅ S2 + I5 ⋅ S0 ⋅ S1 ⋅ S2 + I6 ⋅ S0 The LS151 is a logical implementation of a single pole, 8-position switch with the switch position controlled by the ⋅ S1 ⋅ S2 + I7 ⋅ S0 ⋅ S1 ⋅ S2). state of three Select inputs, S0, S1, S2. Both assertion and The LS151 provides the ability, in one package, to select negation outputs are provided. The Enable input (E) is active LOW. When it is not activated, the negation output is HIGH from eight sources of data or control information. By proper and the assertion output is LOW regardless of all other inputs. The logic function provided at the output is: manipulation of the inputs, the LS151 can provide any logic function of four variables and its negation. TRUTH TABLE E S2 S1 S0 I0 I1 I2 I3 I4 I5 I6 I7 Z Z HXXXXXXXXXXXHL L L L L LXXXXXXXHL L L L LHXXXXXXXLH L L LHXLXXXXXXHL L L LHXHXXXXXXLH L LHLXXLXXXXXHL L LHLXXHXXXXXLH L LHHXXX L XXXXHL L LHHXXXHXXXX LH LHL LXXXXLXXXHL LHL LXXXXHXXXLH L H L HXXXXX L XXH L L H L HXXXXXHXX L H LHHL XXXXXX L XHL LHHL XXXXXXHX LH LHHHXXXXXXX LHL L HHHX X X X X X XH L H H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care FAST AND LS TTL DATA 5-145

SN54 / 74LS151 GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 4.5 5.0 5.5 V 74 4.75 5.0 5.25 TA Operating Ambient Temperature Range 54 – 55 25 125 °C 74 0 25 70 IOH Output Current — High 54, 74 – 0.4 mA IOL Output Current — Low 54 4.0 mA 74 8.0 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Symbol Parameter Limits Unit Test Conditions Min Typ Max VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for All Inputs 54 0.7 V Guaranteed Input LOW Voltage for VIL Input LOW Voltage 74 0.8 All Inputs VIK Input Clamp Diode Voltage 54 – 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA VOH Output HIGH Voltage 74 2.5 3.5 2.7 3.5 V VCC = MIN, IOH = MAX, VIN = VIH V or VIL per Truth Table VOL Output LOW Voltage 54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN, 74 0.35 0.5 V IOL = 8.0 mA VIN = VIL or VIH per Truth Table IIH Input HIGH Current 20 µA VCC = MAX, VIN = 2.7 V 0.1 mA VCC = MAX, VIN = 7.0 V IIL Input LOW Current – 0.4 mA VCC = MAX, VIN = 0.4 V IOS Short Circuit Current (Note 1) – 20 – 100 mA VCC = MAX ICC Power Supply Current 10 mA VCC = MAX Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C) Limits Symbol Parameter Min Typ Max Unit Test Conditions tPLH Propagation Delay 27 43 ns tPHL Select to Output Z 18 30 tPLH Propagation Delay 14 23 ns tPHL Select to Output Z 20 32 tPLH Propagation Delay 26 42 ns VCC = 5.0 V tPHL Enable to Output Z 20 32 CL = 15 pF tPLH Propagation Delay 15 24 ns tPHL Enable to Output Z 18 30 tPLH Propagation Delay 20 32 ns tPHL Data to Output Z 16 26 tPLH Propagation Delay 13 21 ns tPHL Data to Output Z 12 20 AC WAVEFORMS VIN 1.3 V 1.3 V VIN 1.3 V 1.3 V VOUT tPHL tPLH VOUT 1.3 V 1.3 V tPHL tPLH 1.3 V 1.3 V Figure 1 Figure 2 FAST AND LS TTL DATA 5-146

DUAL 4-INPUT MULTIPLEXER SN54/74LS153 The LSTTL / MSI SN54 / 74LS153 is a very high speed Dual 4-Input DUAL 4-INPUT MULTIPLEXER Multiplexer with common select inputs and individual enable inputs for each LOW POWER SCHOTTKY section. It can select two bits of data from four sources. The two buffered outputs present data in the true (non-inverted) form. In addition to multiplexer operation, the LS153 can generate any two functions of three variables. The LS153 is fabricated with the Schottky barrier diode process for high speed and is completely compatible with all Motorola TTL families. • Multifunction Capability • Non-Inverting Outputs • Separate Enable for Each Multiplexer • Input Clamp Diodes Limit High Speed Termination Effects CONNECTION DIAGRAM DIP (TOP VIEW) J SUFFIX CERAMIC VCC Eb S0 I3b I2b I1b I0b Zb CASE 620-09 16 15 14 13 12 11 10 9 16 NOTE: 1 The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 1 2 3 4 56 78 16 N SUFFIX Ea S1 I3a I2a I1a I0a Za GND 1 PLASTIC CASE 648-08 PIN NAMES LOADING (Note a) HIGH LOW S0 Common Select Input 0.5 U.L. 0.25 U.L. 16 D SUFFIX E Enable (Active LOW) Input 0.5 U.L. 0.25 U.L. 1 SOIC Multiplexer Inputs 0.5 U.L. 0.25 U.L. I0, I1 Multiplexer Output (Note b) 10 U.L. 5 (2.5) U.L. CASE 751B-03 Z NOTES: ORDERING INFORMATION a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) SN54LSXXXJ Ceramic SN74LSXXXN Plastic Temperature Ranges. SN74LSXXXD SOIC LOGIC DIAGRAM I3a S1 S0 I0b I1b I2b I3b Eb Ea I0a I1a I2a 32 14 10 11 12 13 15 1 65 4 LOGIC SYMBOL 1 6 5 4 3 10 11 12 13 15 Ea I0a I1a I2a I3a I0b I1b I2b I3b Eb 14 S0 2 Sa Za Zb 79 VCC = PIN 16 VCC = PIN 16 GND = PIN 8 GND = PIN 8 79 = PIN NUMBERS Za Zb FAST AND LS TTL DATA 5-147

SN54 / 74LS153 FUNCTIONAL DESCRIPTION Za = Ea ⋅ (I0a ⋅ S1 ⋅ S0 + I1a ⋅ S1 ⋅ S0 + I2a ⋅ S1 ⋅ S0 + I3a ⋅ S1 ⋅ S0) The LS153 is a Dual 4-input Multiplexer fabricated with Low Zb = Eb ⋅ (I0b ⋅ S1 ⋅ S0 + I1b ⋅ S1 ⋅ S0 + I2b ⋅ S1 ⋅ S0 + Power, Schottky barrier diode process for high speed. It can I3b ⋅ S1 ⋅ S0) select two bits of data from up to four sources under the control of the common Select Inputs (S0, S1). The two 4-input multi- The LS153 can be used to move data from a group of regis- plexer circuits have individual active LOW Enables (Ea, Eb) ters to a common output bus. The particular register from which can be used to strobe the outputs independently. When which the data came would be determined by the state of the the Enables (Ea, Eb) are HIGH, the corresponding outputs (Za, Select Inputs. A less obvious application is a function genera- Zb) are forced LOW. tor. The LS153 can generate two functions of three variables. This is useful for implementing highly irregular random logic. The LS153 is the logic implementation of a 2-pole, 4-posi- tion switch, where the position of the switch is determined by the logic levels supplied to the two Select Inputs. The logic equations for the outputs are shown below. SELECT INPUTS TRUTH TABLE I3 OUTPUT S0 S1 E INPUTS (a or b) X Z X X XH I0 I1 I2 X L L LL X L L LL XXX X H H LL LXX X L H LL HXX X H L HL XLX L L L HL XHX H H H HL XXL L H HL XXH H XXX H = HIGH Voltage Level XXX L = LOW Voltage Level X = Don’t Care GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 4.5 5.0 5.5 V 74 4.75 5.0 5.25 TA Operating Ambient Temperature Range 54 – 55 25 125 °C 74 0 25 70 IOH Output Current — High 54, 74 – 0.4 mA IOL Output Current — Low 54 4.0 mA 74 8.0 FAST AND LS TTL DATA 5-148

SN54 / 74LS153 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Symbol Parameter Limits Unit Test Conditions Min Typ Max VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for All Inputs 54 0.7 Guaranteed Input LOW Voltage for VIL Input LOW Voltage 0.8 V All Inputs 74 VIK Input Clamp Diode Voltage – 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA VOH Output HIGH Voltage 54 2.5 3.5 V VCC = MIN, IOH = MAX, VIN = VIH 74 2.7 3.5 V or VIL per Truth Table VOL Output LOW Voltage 54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN, 74 0.35 0.5 V IOL = 8.0 mA VIN = VIL or VIH per Truth Table IIH Input HIGH Current 20 µA VCC = MAX, VIN = 2.7 V 0.1 mA VCC = MAX, VIN = 7.0 V IIL Input LOW Current – 0.4 mA VCC = MAX, VIN = 0.4 V IOS Short Circuit Current (Note 1) – 20 – 100 mA VCC = MAX ICC Power Supply Current 10 mA VCC = MAX Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C) Symbol Parameter Limits Unit Test Conditions ns tPLH Propagation Delay Min Typ Max ns Figure 2 tPHL Data to Output ns 10 15 Figure 1 VCC = 5.0 V tPLH Propagation Delay 17 26 Figure 2 CL = 15 pF tPHL Select to Output 19 29 tPLH Propagation Delay 25 38 tPHL Enable to Output 16 24 21 32 AC WAVEFORMS VIN 1.3 V 1.3 V VIN 1.3 V 1.3 V VOUT tPHL tPLH VOUT tPHL tPLH 1.3 V 1.3 V 1.3 V 1.3 V Figure 1 Figure 2 FAST AND LS TTL DATA 5-149

DUAL 1-OF-4 DECODER/ SN54/74LS155 DEMULTIPLEXER SN54/74LS156 The SN54 / 74LS155 and SN54 / 74LS156 are high speed Dual 1-of-4 DUAL 1-OF-4 DECODER / Decoder/Demultiplexers. These devices have two decoders with common DEMULTIPLEXER 2-bit Address inputs and separate gated Enable inputs. Decoder “a” has an Enable gate with one active HIGH and one active LOW input. Decoder “b” has LS156-OPEN-COLLECTOR two active LOW Enable inputs. If the Enable functions are satisfied, one LOW POWER SCHOTTKY output of each decoder will be LOW as selected by the address inputs. The LS156 has open collector outputs for wired-OR (DOT-AND) decoding and J SUFFIX function generator applications. CERAMIC CASE 620-09 The LS155 and LS156 are fabricated with the Schottky barrier diode process for high speed and are completely compatible with all Motorola TTL 16 families. 1 • Schottky Process for High Speed • Multifunction Capability 16 N SUFFIX • Common Address Inputs 1 PLASTIC • True or Complement Data Demultiplexing CASE 648-08 • Input Clamp Diodes Limit High Speed Termination Effects • ESD > 3500 Volts 16 D SUFFIX 1 SOIC CONNECTION DIAGRAM DIP (TOP VIEW) VCC Eb Eb A0 O3b O2b O1b O0b CASE 751B-03 16 15 14 13 12 11 10 9 ORDERING INFORMATION NOTE: The Flatpak version SN54LSXXXJ Ceramic has the same pinouts SN74LSXXXN Plastic (Connection Diagram) as SN74LSXXXD SOIC the Dual In-Line Package. 1 2 3 4 56 78 Ea Ea A1 O3a O2a O1a O0a GND PIN NAMES LOADING (Note a) LOGIC SYMBOL 1 2 13 3 14 15 HIGH LOW A0, A1 Address Inputs 0.5 U.L. 0.25 U.L. E A0 A0 E Ea, Eb Enable (Active LOW) Inputs 0.5 U.L. 0.25 U.L. DECODER a A1 DECODER b Ea Enable (Active HIGH) Input 0.5 U.L. 0.25 U.L. A1 O0 – O3 Active LOW Outputs (Note b) 10 U.L. 5 (2.5) U.L. 012 3 0 123 NOTES: 765 4 9 10 11 12 a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) Temperature Ranges. The HIGH level drive for the LS156 must be established by an external resistor. VCC = PIN 16 GND = PIN 8 FAST AND LS TTL DATA 5-150

SN54/74LS155 • SN54/74LS156 LOGIC DIAGRAM Ea Ea A0 A1 Eb Eb 12 13 3 14 15 VCC = PIN 16 7 6 5 4 9 10 11 12 GND = PIN 8 O0a O1a O2a O3a O0b O1b O2b O3b = PIN NUMBERS FUNCTIONAL DESCRIPTION AND the minterm functions by tying outputs together. Any number of terms can be wired-AND as shown below. The LS155 and LS156 are Dual 1-of-4 Decoder/Demulti- f = (E + A0 + A1) ⋅ (E + A0 + A1) ⋅ (E + A0 + A1) ⋅ plexers with common Address inputs and separate gated (E + A0 + A1) Enable inputs. When enabled, each decoder section accepts where E = Ea + Ea; E = Eb + Eb the binary weighted Address inputs (A0, A1) and provides four EE O0 mutually exclusive active LOW outputs (O0 – O3). If the Enable A0 O0 A0 O1 requirements of each decoder are not met, all outputs of that A1 A1 O2 O3 decoder are HIGH. EE A0 O1 A0 Each decoder section has a 2-input enable gate. The A1 A1 enable gate for Decoder “a” requires one active HIGH input EE and one active LOW input (Ea•Ea). In demultiplexing applica- A0 O2 A0 tions, Decoder “a” can accept either true or complemented A1 A1 data by using the Ea or Ea inputs respectively. The enable gate EE for Decoder “b” requires two active LOW inputs (Eb•Eb). The A0 O3 A0 LS155 or LS156 can be used as a 1-of-8 Decoder/Demulti- A1 A1 plexer by tying Ea to Eb and relabeling the common connection Figure a as (A2). The other Eb and Ea are connected together to form the common enable. The LS155 and LS156 can be used to generate all four minterms of two variables. These four minterms are useful in some applications replacing multiple gate functions as shown in Fig. a. The LS156 has the further advantage of being able to TRUTH TABLE ADDRESS ENABLE “a” OUTPUT “a” ENABLE “b” OUTPUT “b” A0 A1 Ea Ea O0 O1 O2 O3 Eb Eb O0 O1 O2 O3 X X L X H H HH H X H H H H X X X H H H HH X H H H H H L L H L L H HH L L L H H H H L H L H L HH L L H L H H L H H L H H LH L L H H L H H H H L H H HL L L H H H L H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care FAST AND LS TTL DATA 5-151

SN54 / 74LS155 GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 4.5 5.0 5.5 V 74 4.75 5.0 5.25 TA Operating Ambient Temperature Range 54 – 55 25 125 °C 74 0 25 70 IOH Output Current — High 54, 74 – 0.4 mA IOL Output Current — Low 54 4.0 mA 74 8.0 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Symbol Parameter Limits Unit Test Conditions VIH Input HIGH Voltage Min Typ Max V Guaranteed Input HIGH Voltage for 2.0 All Inputs 54 0.7 Guaranteed Input LOW Voltage for VIL Input LOW Voltage 0.8 V All Inputs 74 VIK Input Clamp Diode Voltage 54 – 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA VOH Output HIGH Voltage 74 2.5 3.5 2.7 3.5 V VCC = MIN, IOH = MAX, VIN = VIH V or VIL per Truth Table VOL Output LOW Voltage 54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN, 74 0.35 0.5 V IOL = 8.0 mA VIN = VIL or VIH per Truth Table IIH Input HIGH Current 20 µA VCC = MAX, VIN = 2.7 V 0.1 mA VCC = MAX, VIN = 7.0 V IIL Input LOW Current – 0.4 mA VCC = MAX, VIN = 0.4 V IOS Short Circuit Current (Note 1) – 20 – 100 mA VCC = MAX ICC Power Supply Current 10 mA VCC = MAX Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C) Symbol Parameter Limits Unit Test Conditions ns tPLH Propagation Delay Min Typ Max ns Figure 1 tPHL Address, Ea or Eb to Output ns 10 15 Figure 2 VCC = 5.0 V tPLH Propagation Delay 19 30 Figure 1 CL = 15 pF tPHL Address to Output 17 26 tPLH Propagation Delay 19 30 tPHL Ea to Output 18 27 18 27 AC WAVEFORMS VIN 1.3 V 1.3 V VIN 1.3 V 1.3 V VOUT tPHL tPLH VOUT tPHL tPLH 1.3 V 1.3 V 1.3 V 1.3 V Figure 1 Figure 2 FAST AND LS TTL DATA 5-152

SN54 / 74LS156 GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 4.5 5.0 5.5 V 74 4.75 5.0 5.25 TA Operating Ambient Temperature Range 54 – 55 25 125 °C 74 0 25 70 VOH Output Voltage — High 54, 74 5.5 V IOL Output Current — Low 54 4.0 mA 74 8.0 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Symbol Parameter Limits Unit Test Conditions Min Typ Max VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for All Inputs 54 0.7 Guaranteed Input LOW Voltage for VIL Input LOW Voltage 0.8 V All Inputs 74 VIK Input Clamp Diode Voltage – 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA IOH Output HIGH Current 54, 74 100 µA VCC = MIN, VOH = MAX VOL Output LOW Voltage 54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN, 74 0.35 0.5 V IOL = 8.0 mA VIN = VIL or VIH per Truth Table IIH Input HIGH Current 20 µA VCC = MAX, VIN = 2.7 V 0.1 mA VCC = MAX, VIN = 7.0 V IIL Input LOW Current – 0.4 mA VCC = MAX, VIN = 0.4 V ICC Power Supply Current 10 mA VCC = MAX AC CHARACTERISTICS (TA = 25°C) Symbol Parameter Limits Unit Test Conditions ns tPLH Propagation Delay Min Typ Max ns Figure 1 VCC = 5.0 V tPHL Address, Ea or Eb to Output ns Figure 2 25 40 Figure 1 CL = 15 pF tPLH Propagation Delay 34 51 RL = 2.0 kΩ tPHL Address to Output 31 46 tPLH Propagation Delay 34 51 tPHL Ea to Output 32 48 32 48 AC WAVEFORMS VIN 1.3 V 1.3 V VIN 1.3 V 1.3 V VOUT tPHL tPLH VOUT tPHL tPLH 1.3 V 1.3 V 1.3 V 1.3 V Figure 1 Figure 2 FAST AND LS TTL DATA 5-153

QUAD 2-INPUT MULTIPLEXER SN54/74LS157 The LSTTL / MSI SN54 / 74LS157 is a high speed Quad 2-Input Multiplexer. QUAD 2-INPUT MULTIPLEXER Four bits of data from two sources can be selected using the common Select LOW POWER SCHOTTKY and Enable inputs. The four buffered outputs present the selected data in the true (non-inverted) form. The LS157 can also be used to generate any four J SUFFIX of the 16 different functions of two variables. The LS157 is fabricated with the CERAMIC Schottky barrier diode process for high speed and is completely compatible CASE 620-09 with all Motorola TTL families. 16 • Schottky Process for High Speed 1 • Multifunction Capability • Non-Inverting Outputs N SUFFIX • Input Clamp Diodes Limit High Speed Termination Effects PLASTIC • Special Circuitry Ensures Glitch Free Multiplexing CASE 648-08 • ESD > 3500 Volts CONNECTION DIAGRAM DIP (TOP VIEW) VCC E I0c I1c Zc I0d I1d Zd 16 15 14 13 12 11 10 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 1 2 3 4 56 78 16 S I0a I1d Za I0b I1b Zb GND 1 PIN NAMES LOADING (Note a) HIGH LOW D SUFFIX SOIC S Common Select Input 1.0 U.L. 0.5 U.L. 16 Enable (Active LOW) Input 1.0 U.L. 0.5 U.L. 1 CASE 751B-03 E Data Inputs from Source 0 0.5 U.L. 0.25 U.L. Data Inputs from Source 1 0.5 U.L. 0.25 U.L. ORDERING INFORMATION I0a – I0d Multiplexer Outputs (Note b) 10 U.L. 5 (2.5) U.L. I1a – I1d SN54LSXXXJ Ceramic Za – Zd SN74LSXXXN Plastic SN74LSXXXD SOIC NOTES: a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) Temperature Ranges. LOGIC DIAGRAM I0a I1a I0b I1b I0c I1c I0d I1d E S LOGIC SYMBOL 15 2 3 5 6 14 13 11 10 2 3 5 6 14 13 11 10 15 1 E I0a I1a I0b I1b I0c I1c I0d I1d VCC = PIN 16 1S GND = PIN 8 4 7 12 9 = PIN NUMBERS Za Zb Zc Zd Za Zb Zc Zd 4 7 12 9 FAST AND LS TTL DATA VCC = PIN 16 5-154 GND = PIN 8

SN54 / 74LS157 FUNCTIONAL DESCRIPTION Za = E ⋅ (I1a ⋅ S + I0a ⋅ S) Zb = E ⋅ (I1b ⋅ S + I0b ⋅ S) Zc = E ⋅ (I1c ⋅ S + I0c ⋅ S) Zd = E ⋅ (I1d ⋅ S + I0d ⋅ S) The LS157 is a Quad 2-Input Multiplexer fabricated with the Schottky barrier diode process for high speed. It selects four A common use of the LS157 is the moving of data from two bits of data from two sources under the control of a common groups of registers to four common output busses. The partic- Select Input (S). The Enable Input (E) is active LOW. When E ular register from which the data comes is determined by the is HIGH, all of the outputs (Z) are forced LOW regardless of all state of the Select Input. A less obvious use is as a function other inputs. generator. The LS157 can generate any four of the 16 different functions of two variables with one variable common. This is The LS157 is the logic implementation of a 4-pole, useful for implementing highly irregular logic. 2-position switch where the position of the switch is deter- mined by the logic levels supplied to the Select Input. The logic equations for the outputs are: TRUTH TABLE ENABLE SELECT INPUTS OUTPUT INPUT Z E S I0 I1 L H X XX L L H XL H L H XH L L L LX H L L HX H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 4.5 5.0 5.5 V 74 4.75 5.0 5.25 TA Operating Ambient Temperature Range 54 – 55 25 125 °C 74 0 25 70 IOH Output Current — High 54, 74 – 0.4 mA IOL Output Current — Low 54 4.0 mA 74 8.0 FAST AND LS TTL DATA 5-155

SN54 / 74LS157 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Symbol Parameter Limits Unit Test Conditions Min Typ Max VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for All Inputs 54 0.7 Guaranteed Input LOW Voltage for VIL Input LOW Voltage 0.8 V All Inputs 74 VIK Input Clamp Diode Voltage 54 – 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA VOH Output HIGH Voltage 74 2.5 3.5 2.7 3.5 V VCC = MIN, IOH = MAX, VIN = VIH V or VIL per Truth Table VOL Output LOW Voltage 54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN, 74 0.35 0.5 V IOL = 8.0 mA VIN = VIL or VIH per Truth Table Input HIGH Current 20 µA VCC = MAX, VIN = 2.7 V 40 I0, I1 IIH E, S 0.1 mA VCC = MAX, VIN = 7.0 V 0.2 I0, I1 E, S Input LOW Current – 0.4 mA VCC = MAX, VIN = 0.4 V – 0.8 IIL I0, I1 E, S IOS Short Circuit Current (Note 1) – 20 – 100 mA VCC = MAX ICC Power Supply Current 16 mA VCC = MAX Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C) Symbol Parameter Limits Unit Test Conditions ns tPLH Propagation Delay Min Typ Max ns Figure 2 tPHL Data to Output ns 9.0 14 Figure 1 VCC = 5.0 V tPLH Propagation Delay 9.0 14 CL = 15 pF tPHL Enable to Output 13 20 Figure 2 tPLH Propagation Delay 14 21 tPHL Select to Output 15 23 18 27 AC WAVEFORMS VIN 1.3 V 1.3 V VIN 1.3 V 1.3 V VOUT tPHL tPLH VOUT tPHL tPLH 1.3 V 1.3 V 1.3 V 1.3 V Figure 1 Figure 2 FAST AND LS TTL DATA 5-156

QUAD 2-INPUT MULTIPLEXER SN54/74LS158 The LSTTL / MSI SN54L / 74LS158 is a high speed Quad 2-input Multiplex- QUAD 2-INPUT MULTIPLEXER er. It selects four bits of data from two sources using the common Select and LOW POWER SCHOTTKY Enable inputs. The four buffered outputs present the selected data in the inverted form. The LS158 can also generate any four of the 16 different J SUFFIX functions of two variables. The LS158 is fabricated with the Schottky barrier CERAMIC diode process for high speed and is completely compatible with all Motorola CASE 620-09 TTL families. 16 • Schottky Process for High Speed 1 • Multifunction Capability • Inverted Outputs N SUFFIX • Input Clamp Diodes Limit High Speed Termination Effects PLASTIC • ESD > 3500 Volts CASE 648-08 • Special Circuitry Ensures Glitch Free Multiplexing CONNECTION DIAGRAM DIP (TOP VIEW) VCC E I0c I1c Zc I0d I1d Zd 16 15 14 13 12 11 10 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 1 2 3 4 56 78 16 S I0a I1a Za I0b I1b Zb GND 1 PIN NAMES LOADING (Note a) HIGH LOW D SUFFIX SOIC S Common Select Input 1.0 U.L. 0.5 U.L. 16 Enable (Active LOW) Input 1.0 U.L. 0.5 U.L. 1 CASE 751B-03 E Data Inputs from Source 0 0.5 U.L. 0.25 U.L. Data Inputs from Source 1 0.5 U.L. 0.25 U.L. ORDERING INFORMATION I0a – I0d Inverted Outputs (Note b) 10 U.L. 5 (2.5) U.L. I1a – I1d SN54LSXXXJ Ceramic Za – Zd SN74LSXXXN Plastic SN74LSXXXD SOIC NOTES: a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) Temperature Ranges. LOGIC DIAGRAM I0a I1a I0b I1b I0c I1c I0d I1d E S LOGIC SYMBOL 15 2 3 5 6 14 13 11 10 2 3 5 6 14 13 11 10 15 1 E I0a I1a I0b I1b I0c I1c I0d I1d VCC = PIN 16 1S GND = PIN 8 4 7 12 9 = PIN NUMBERS Za Zb Zc Zd Za Zb Zc Zd 4 7 12 9 FAST AND LS TTL DATA VCC = PIN 16 5-157 GND = PIN 8

SN54 / 74LS158 FUNCTIONAL DESCRIPTION mined by the logic levels supplied to the Select Input. A common use of the LS158 is the moving of data from two The LS158 is a Quad 2-input Multiplexer fabricated with the Schottky barrier diode process for high speed. It selects four groups of registers to four common output busses. The bits of data from two sources under the control of a common particular register from which the data comes is determined by Select Input (S) and presents the data in inverted form at the the state of the Select Input. A less obvious use is as a function four outputs. The Enable Input (E) is active LOW. When E is generator. The LS158 can generate four functions of two HIGH, all of the outputs (Z) are forced HIGH regardless of all variables with one variable common. This is useful for other inputs. implementing gating functions. The LS158 is the logic implementation of a 4-pole, 2-position switch where the position of the switch is deter- TRUTH TABLE ENABLE SELECT INPUTS OUTPUT INPUT Z E S I0 I1 H H X XX H L L LX L L L HX H L H XL L L H XH H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 4.5 5.0 5.5 V 74 4.75 5.0 5.25 TA Operating Ambient Temperature Range 54 – 55 25 125 °C 74 0 25 70 IOH Output Current — High 54, 74 – 0.4 mA IOL Output Current — Low 54 4.0 mA 74 8.0 FAST AND LS TTL DATA 5-158

SN54 / 74LS158 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Symbol Parameter Limits Unit Test Conditions Min Typ Max VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for All Inputs 54 0.7 Guaranteed Input LOW Voltage for VIL Input LOW Voltage 0.8 V All Inputs 74 VIK Input Clamp Diode Voltage – 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA VOH Output HIGH Voltage 54 2.5 3.5 V VCC = MIN, IOH = MAX, VIN = VIH 74 2.7 3.5 V or VIL per Truth Table VOL Output LOW Voltage 54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN, 74 0.35 0.5 V IOL = 8.0 mA VIN = VIL or VIH per Truth Table Input HIGH Current 20 µA VCC = MAX, VIN = 2.7 V 40 I0, I1 IIH E, S 0.1 mA VCC = MAX, VIN = 7.0 V 0.2 I0, I1 E, S Input LOW Current – 0.4 mA VCC = MAX, VIN = 0.4 V – 0.8 IIL I0, I1 E, S IOS Short Circuit Current (Note 1) – 20 – 100 mA VCC = MAX 8.0 mA VCC = MAX ICC Power Supply Current All inputs at 4.5 V. All outputs open. ICC Power Supply Current 11 mA VCC = MAX All other input combinations. All outputs open. Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C) Symbol Parameter Limits Unit Test Conditions ns tPLH Propagation Delay Min Typ Max ns Figure 2 tPHL Data to Output ns 7.0 12 Figure 1 VCC = 5.0 V tPLH Propagation Delay 10 15 CL = 15 pF tPHL Enable to Output 11 17 Figure 2 tPLH Propagation Delay 18 24 tPHL Select to Output 13 20 16 24 AC WAVEFORMS VIN 1.3 V 1.3 V VIN 1.3 V 1.3 V VOUT tPHL tPLH VOUT tPHL tPLH 1.3 V 1.3 V 1.3 V 1.3 V Figure 1 Figure 2 FAST AND LS TTL DATA 5-159

BCD DECADE COUNTERS/ SN54/74LS160A 4-BIT BINARY COUNTERS SN54/74LS161A SN54/74LS162A The LS160A / 161A / 162A / 163A are high-speed 4-bit synchronous count- SN54/74LS163A ers. They are edge-triggered, synchronously presettable, and cascadable MSI building blocks for counting, memory addressing, frequency division and BCD DECADE COUNTERS / other applications. The LS160A and LS162A count modulo 10 (BCD). The 4-BIT BINARY COUNTERS LS161A and LS163A count modulo 16 (binary.) LOW POWER SCHOTTKY The LS160A and LS161A have an asynchronous Master Reset (Clear) input that overrides, and is independent of, the clock and all other control inputs. The LS162A and LS163A have a Synchronous Reset (Clear) input that overrides all other control inputs, but is active only during the rising clock edge. BCD (Modulo 10) Binary (Modulo 16) Asynchronous Reset LS160A LS161A J SUFFIX CERAMIC Synchronous Reset LS162A LS163A CASE 620-09 • Synchronous Counting and Loading 16 • Two Count Enable Inputs for High Speed Synchronous Expansion 1 • Terminal Count Fully Decoded • Edge-Triggered Operation 16 N SUFFIX • Typical Count Rate of 35 MHz 1 PLASTIC • ESD > 3500 Volts CASE 648-08 CONNECTION DIAGRAM DIP (TOP VIEW) VCC TC Q0 Q1 Q2 Q3 CET PE NOTE: 16 D SUFFIX 16 15 14 13 12 11 10 9 The Flatpak version 1 SOIC has the same pinouts 12 3 4 56 78 (Connection Diagram) as CASE 751B-03 *R CP P0 P1 P2 P3 CEP GND the Dual In-Line Package. ORDERING INFORMATION *MR for LS160A and LS161A *SR for LS162A and LS163A SN54LSXXXJ Ceramic SN74LSXXXN Plastic SN74LSXXXD SOIC PIN NAMES LOADING (Note a) LOGIC SYMBOL 934 56 HIGH LOW PE Parallel Enable (Active LOW) Input 1.0 U.L. 0.5 U.L. 7 PE P0 P1 P2 P3 Parallel Inputs 0.5 U.L. 0.25 U.L. CEP P0 – P3 Count Enable Parallel Input 0.5 U.L. 0.25 U.L. CEP Count Enable Trickle Input 1.0 U.L. 10 CET TC 15 Clock (Active HIGH Going Edge) Input 0.5 U.L. 0.5 U.L. CET Master Reset (Active LOW) Input 0.5 U.L. 0.25 U.L. 2 CP Synchronous Reset (Active LOW) Input 1.0 U.L. 0.25 U.L. *R Q0 Q1 Q2 Q3 CP Parallel Outputs (Note b) 10 U.L. Terminal Count Output (Note b) 10 U.L. 0.5 U.L. MR 5 (2.5) U.L. 5 (2.5) U.L. SR Q0 – Q3 TC NOTES: 1 14 13 12 11 a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) VCC = PIN 16 GND = PIN 8 Temperature Ranges. *MR for LS160A and LS161A *SR for LS162A and LS163A FAST AND LS TTL DATA 5-160

SN54/74LS160A • SN54/74LS161A SN54/74LS162A • SN54/74LS163A STATE DIAGRAM 4 LS161A • LS163A LOGIC EQUATIONS LS160A • LS162A 5 01234 6 Count Enable = CEP • CET • PE 0123 7 15 5 TC for LS160A & LS162A = CET • Q0 • Q1 • Q2 • Q3 8 TC for LS161A & LS163A = CET • Q0 • Q1 • Q2 • Q3 15 14 6 Preset = PE • CP + (rising clock edge) Reset = MR (LS160A & LS161A) 14 13 7 Reset = SR • CP + (rising clock edge) Reset = (LS162A & LS163A) 13 12 11 10 9 8 NOTE: 12 11 10 9 The LS160A and LS162A can be preset to any state, but will not count beyond 9. If preset to state 10, 11, 12, 13, 14, or 15, it will return to its normal sequence within two clock pulses. FUNCTIONAL DESCRIPTION the Binary counters). Note that TC is fully decoded and will, therefore, be HIGH only for one count state. The LS160A / 161A / 162A / 163A are 4-bit synchronous counters with a synchronous Parallel Enable (Load) feature. The LS160A and LS162A count modulo 10 following a The counters consist of four edge-triggered D flip-flops with binary coded decimal (BCD) sequence. They generate a TC the appropriate data routing networks feeding the D inputs. All output when the CET input is HIGH while the counter is in state changes of the Q outputs (except due to the asynchronous 9 (HLLH). From this state they increment to state 0 (LLLL). If Master Reset in the LS160A and LS161A) occur as a result of, loaded with a code in excess of 9 they return to their legitimate and synchronous with, the LOW to HIGH transition of the sequence within two counts, as explained in the state Clock input (CP). As long as the set-up time requirements are diagram. States 10 through 15 do not generate a TC output. met, there are no special timing or activity constraints on any of the mode control or data inputs. The LS161A and LS163A count modulo 16 following a binary sequence. They generate a TC when the CET input is Three control inputs — Parallel Enable (PE), Count Enable HIGH while the counter is in state 15 (HHHH). From this state Parallel (CEP) and Count Enable Trickle (CET) — select the they increment to state 0 (LLLL). mode of operation as shown in the tables below. The Count Mode is enabled when the CEP, CET, and PE inputs are HIGH. The Master Reset (MR) of the LS160A and LS161A is When the PE is LOW, the counters will synchronously load the asynchronous. When the MR is LOW, it overrides all other data from the parallel inputs into the flip-flops on the LOW to input conditions and sets the outputs LOW. The MR pin should HIGH transition of the clock. Either the CEP or CET can be never be left open. If not used, the MR pin should be tied used to inhibit the count sequence. With the PE held HIGH, a through a resistor to VCC, or to a gate output which is LOW on either the CEP or CET inputs at least one set-up time permanently set to a HIGH logic level. prior to the LOW to HIGH clock transition will cause the existing output states to be retained. The AND feature of the The active LOW Synchronous Reset (SR) input of the two Count Enable inputs (CET • CEP) allows synchronous LS162A and LS163A acts as an edge-triggered control input, cascading without external gating and without delay accu- overriding CET, CEP and PE, and resetting the four counter mulation over any practical number of bits or digits. flip-flops on the LOW to HIGH transition of the clock. This simplifies the design from race-free logic controlled reset The Terminal Count (TC) output is HIGH when the Count circuits, e.g., to reset the counter synchronously after Enable Trickle (CET) input is HIGH while the counter is in its reaching a predetermined value. maximum count state (HLLH for the BCD counters, HHHH for MODE SELECT TABLE *SR PE CET CEP Action on the Rising Clock Edge ( ) LX X X RESET (Clear) *For the LS162A and X LOAD (Pn → Qn) *LS163A only. HL X H COUNT (Increment) X H = HIGH Voltage Level HH H L NO CHANGE (Hold) L = LOW Voltage Level X = Don’t Care HH L NO CHANGE (Hold) HH X FAST AND LS TTL DATA 5-161

SN54/74LS160A • SN54/74LS161A SN54/74LS162A • SN54/74LS163A GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 4.5 5.0 5.5 V 74 4.75 5.0 5.25 TA Operating Ambient Temperature Range 54 – 55 25 125 °C 74 0 25 70 IOH Output Current — High 54, 74 – 0.4 mA IOL Output Current — Low 54 4.0 mA 74 8.0 LS160A and LS161A DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Symbol Parameter Limits Unit Test Conditions Min Typ Max VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for All Inputs 54 0.7 Guaranteed Input LOW Voltage for VIL Input LOW Voltage 0.8 V All Inputs 74 VIK Input Clamp Diode Voltage 54 – 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA VOH Output HIGH Voltage 74 2.5 3.5 2.7 3.5 V VCC = MIN, IOH = MAX, VIN = VIH V or VIL per Truth Table VOL Output LOW Voltage 54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN, 74 0.35 0.5 V IOL = 8.0 mA VIN = VIL or VIH per Truth Table Input HIGH Current 20 µA VCC = MAX, VIN = 2.7 V MR, Data, CEP, Clock 40 IIH PE, CET 0.1 mA VCC = MAX, VIN = 7.0 V MR, Data, CEP, Clock 0.2 PE, CET Input LOW Current – 0.4 mA VCC = MAX, VIN = 0.4 V – 0.8 IIL MR, Data, CEP, Clock PE, CET IOS Short Circuit Current (Note 1) – 20 – 100 mA VCC = MAX Power Supply Current 31 mA VCC = MAX 32 ICC Total, Output HIGH Total, Output LOW Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. FAST AND LS TTL DATA 5-162

SN54/74LS160A • SN54/74LS161A SN54/74LS162A • SN54/74LS163A LS162A and LS163A DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Symbol Parameter Limits Unit Test Conditions Min Typ Max VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for All Inputs 54 0.7 Guaranteed Input LOW Voltage for VIL Input LOW Voltage 74 0.8 V All Inputs VIK Input Clamp Diode Voltage – 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA VOH Output HIGH Voltage 54 2.5 3.5 V VCC = MIN, IOH = MAX, VIN = VIH 74 2.7 3.5 V or VIL per Truth Table VOL Output LOW Voltage 54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN, 74 0.35 0.5 V IOL = 8.0 mA VIN = VIL or VIH per Truth Table Input HIGH Current 20 µA VCC = MAX, VIN = 2.7 V Data, CEP, Clock 40 IIH PE, CET, SR 0.1 mA VCC = MAX, VIN = 7.0 V Data, CEP, Clock 0.2 PE, CET, SR Input LOW Current – 0.4 mA VCC = MAX, VIN = 0.4 V – 0.8 IIL Data, CEP, Clock, PE, SR CET IOS Short Circuit Current (Note 1) – 20 – 100 mA VCC = MAX Power Supply Current 31 mA VCC = MAX 32 ICC Total, Output HIGH Total, Output LOW Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C) Symbol Parameter Limits Unit Test Conditions MHz fMAX Maximum Clock Frequency Min Typ Max VCC = 5.0 V ns CL = 15 pF tPLH Propagation Delay 25 32 tPHL Clock to TC ns 20 35 tPLH Propagation Delay 18 35 ns tPHL Clock to Q ns 13 24 tPLH Propagation Delay 18 27 tPHL CET to TC 9.0 14 tPHL MR or SR to Q 9.0 14 20 28 FAST AND LS TTL DATA 5-163

SN54/74LS160A • SN54/74LS161A SN54/74LS162A • SN54/74LS163A AC SETUP REQUIREMENTS (TA = 25°C) Symbol Parameter Limits Unit Test Conditions Min Typ Max ns VCC = 5.0 V tWCP Clock Pulse Width Low 25 ns 20 ns tW MR or SR Pulse Width 20 ns 25 ns ts Setup Time, other* ns 3 ns ts Setup Time PE or SR 0 15 th Hold Time, data th Hold Time, other trec Recovery Time MR to CP *CEP, CET or DATA DEFINITION OF TERMS nition. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from LOW to SETUP TIME (ts) — is defined as the minimum time required HIGH and still be recognized. for the correct logic level to be present at the logic input prior to the clock transition from LOW to HIGH in order to be recog- RECOVERY TIME (trec) — is defined as the minimum time re- nized and transferred to the outputs. quired between the end of the reset pulse and the clock transi- tion from LOW to HIGH in order to recognize and transfer HOLD TIME (th) — is defined as the minimum time following HIGH Data to the Q outputs. the clock transition from LOW to HIGH that the logic level must be maintained at the input in order to ensure continued recog- AC WAVEFORMS tW(H) tW(L) MR 1.3 V tW CP 1.3 V 1.3 V OTHER CONDITIONS: trec OTHER CONDITIONS: tPHL PE = MR (SR) = H 1.3 V PE = L P0 = P1 = P2 = P3 = H tPLH CEP = CET = H CP tPHL Q0 ⋅ Q1 ⋅ Q2 ⋅ Q3 Q 1.3 V 1.3 V 1.3 V Figure 1. Clock to Output Delays, Count Figure 2. Master Reset to Output Delay, Master Reset Frequency, and Clock Pulse Width Pulse Width, and Master Reset Recovery Time FAST AND LS TTL DATA 5-164

SN54/74LS160A • SN54/74LS161A SN54/74LS162A • SN54/74LS163A AC WAVEFORMS (continued) COUNT ENABLE TRICKLE INPUT CET 1.3 V 1.3 V TO TERMINAL COUNT OUTPUT DELAYS TC tPLH tPHL The positive TC pulse occurs when the outputs are in the 1.3 V 1.3 V (Q0 • Q1 • Q2 • Q3) state for the LS160 and LS162 and the (Q0 • Q1 • Q2 • Q3) state for the LS161 and LS163. Figure 3 OTHER CONDITIONS: CP = PE = CEP = MR = H CLOCK TO TERMINAL COUNT DELAYS CP 1.3 V 1.3 V 1.3 V tPLH tPHL The positive TC pulse is coincident with the output state TC 1.3 V 1.3 V (Q0 • Q1 • Q2 • Q3) state for the LS161 and LS163 and (Q0 • Q1 • Q2 • Q3) for the LS161 and LS163. Figure 4 OTHER CONDITIONS: PE = CEP = CET = MR = H SETUP TIME (ts) AND HOLD TIME (th) CP 1.3 V 1.3 V FOR PARALLEL DATA INPUTS ts(H) th(H) = 0 ts(L) P0 • P1 • P2 • P3 th(L) = 0 The shaded areas indicate when the input is permitted to 1.3 V 1.3 V 1.3 V change for predictable output performance. Q0 • Q1 • Q2 • Q3 Figure 5 OTHER CONDITIONS: PE = L, MR = H SETUP TIME (ts) AND HOLD TIME (th) FOR COUNT ENABLE (CEP) AND (CET) AND PARALLEL ENABLE (PE) INPUTS The shaded areas indicate when the input is permitted to change for predictable output performance. CP 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V ts(L) ts(L) th (L) = 0 ts(H) th(H) = 0 CP th(L) = 0 th(L) = 0 SR or PE ts(H) th(H) = 0 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V HOLD CEP ts(L) PARALLEL LOAD COUNT MODE ts(H) th(H) = 0 (See Fig. 5) (See Fig. 7) 1.3 V CET 1.3 V COUNT Q RESPONSE TO PE 1.3 V RESET COUNT OR LOAD HOLD Q RESPONSE TO SR Q OTHER CONDITIONS: PE = H, MR = H Figure 6 Figure 7 FAST AND LS TTL DATA 5-165

SN54/74LS164 SERIAL-IN PARALLEL-OUT SERIAL-IN PARALLEL-OUT SHIFT REGISTER SHIFT REGISTER The SN54 / 74LS164 is a high speed 8-Bit Serial-In Parallel-Out Shift Regis- LOW POWER SCHOTTKY ter. Serial data is entered through a 2-Input AND gate synchronous with the LOW to HIGH transition of the clock. The device features an asynchronous J SUFFIX Master Reset which clears the register setting all outputs LOW independent of CERAMIC the clock. It utilizes the Schottky diode clamped process to achieve high CASE 632-08 speeds and is fully compatible with all Motorola TTL products. • Typical Shift Frequency of 35 MHz 14 • Asynchronous Master Reset 1 • Gated Serial Data Input • Fully Synchronous Data Transfers 14 N SUFFIX • Input Clamp Diodes Limit High Speed Termination Effects 1 PLASTIC • ESD > 3500 Volts CASE 646-06 CONNECTION DIAGRAM DIP (TOP VIEW) 14 D SUFFIX 1 SOIC VCC Q7 Q6 Q5 Q4 MR CP 14 13 12 11 10 9 8 CASE 751A-02 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 1234567 A B Q0 Q1 Q2 Q3 GND ORDERING INFORMATION SN54LSXXXJ Ceramic SN74LSXXXN Plastic SN74LSXXXD SOIC PIN NAMES LOADING (Note a) HIGH LOW A, B Data Inputs 0.5 U.L. 0.25 U.L. LOGIC SYMBOL CP Clock (Active HIGH Going Edge) Input 0.5 U.L. 0.25 U.L. MR Master Reset (Active LOW) Input 0.5 U.L. 0.25 U.L. 1A LS164 Q0 – Q7 Outputs (Note b) 10 U.L. 5 (2.5) U.L. 2 B 8-BIT SHIFT REGISTER NOTES: 8 CP a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. MR Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) Temperature Ranges. 9 3 4 5 6 10 11 12 13 VCC = PIN 14 GND = PIN 7 FAST AND LS TTL DATA 5-166

SN54 / 74LS164 LOGIC DIAGRAM A DQ DQ DQ DQ DQ DQ DQ DQ CD CD CD CD CD CD CD CD 1 2 B 8 CP MR 9 VCC = PIN 14 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 3 4 5 6 10 11 12 13 GND = PIN 7 = PIN NUMBERS FUNCTIONAL DESCRIPTION Each LOW-to-HIGH transition on the Clock (CP) input shifts The LS164 is an edge-triggered 8-bit shift register with seri- data one place to the right and enters into Q0 the logical AND al data entry and an output from each of the eight stages. Data of the two data inputs (A•B) that existed before the rising clock is entered serially through one of two inputs (A or B); either of edge. A LOW level on the Master Reset (MR) input overrides these inputs can be used as an active HIGH Enable for data entry through the other input. An unused input must be tied all other inputs and clears the register asynchronously, forcing HIGH, or both inputs connected together. all Q outputs LOW. MODE SELECT — TRUTH TABLE OPERATING INPUTS B OUTPUTS MODE MR A X Q0 Q1–Q7 LX L L–L Reset (Clear) Shift H I I L q0 – q6 H I h L q0 – q6 H h I L q0 – q6 H h h H q0 – q6 L (l) = LOW Voltage Levels H (h) = HIGH Voltage Levels X = Don’t Care qn = Lower case letters indicate the state of the referenced input or output one qn = set-up time prior to the LOW to HIGH clock transition. GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit V VCC Supply Voltage 54 4.5 5.0 5.5 74 4.75 5.0 5.25 °C TA Operating Ambient Temperature Range 54 – 55 25 125 mA 74 0 25 70 mA IOH Output Current — High 54, 74 – 0.4 IOL Output Current — Low 54 4.0 74 8.0 FAST AND LS TTL DATA 5-167

SN54 / 74LS164 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter Min Typ Max Unit Test Conditions VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for All Inputs VIL Input LOW Voltage 54 0.7 Guaranteed Input LOW Voltage for 74 0.8 V All Inputs VIK Input Clamp Diode Voltage – 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA VOH Output HIGH Voltage 54 2.5 3.5 VCC = MIN, IOH = MAX, VIN = VIH 74 or VIL per Truth Table V 2.7 3.5 54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN, 74 0.35 0.5 VOL Output LOW Voltage VIN = VIH or VIL V IOL = 8.0 mA per Truth Table IIH Input HIGH Current 20 µA VCC = MAX, VIN = 2.7 V 0.1 mA VCC = MAX, VIN = 7.0 V mA VCC = MAX, VIN = 0.4 V IIL Input LOW Current – 0.4 mA VCC = MAX mA VCC = MAX IOS Short Circuit Current (Note 1) – 20 –100 ICC Power Supply Current 27 Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C) Symbol Parameter Limits Unit Test Conditions fMAX Min Typ Max MHz Maximum Clock Frequency 25 36 VCC = 5.0 V tPHL ns CL = 15 pF Propagation Delay 24 36 tPLH MR to Output Q ns tPHL 17 27 Propagation Delay 21 32 Clock to Output Q AC SETUP REQUIREMENTS (TA = 25°C) Symbol Parameter Limits Unit Test Conditions CP, MR Pulse Width Min Typ Max ns VCC = 5.0 V tW Data Setup Time 20 ns ts Data Hold Time 15 ns th MR to Clock Recovery Time 5.0 ns trec 20 FAST AND LS TTL DATA 5-168

SN54 / 74LS164 AC WAVEFORMS *The shaded areas indicate when the input is permitted to change for predictable output performance. I/fmax MR 1.3 V tW 1.3 V 1.3 V 1.3 V 1.3 V tW trec CP 1.3 V tPHL tPLH CP Q 1.3 V tPHL 1.3 V Q CONDITIONS: MR = H 1.3 V Figure 1. Clock to Output Delays Figure 2. Master Reset Pulse Width, and Clock Pulse Width Master Reset to Output Delay and Master Reset to Clock Recovery Time 1/fmax tW CP 1.3 V 1.3 V 1.3 V 1.3 V ts(H) th(H) ts(L) th(L) D * 1.3 V 1.3 V 1.3 V 1.3 V Q 1.3 V 1.3 V Figure 3. Data Setup and Hold Times FAST AND LS TTL DATA 5-169

8-BIT PARALLEL-TO-SERIAL SN54/74LS165 SHIFT REGISTER 8-BIT PARALLEL-TO-SERIAL The SN54 / 74LS165 is an 8-bit parallel load or serial-in register with SHIFT REGISTER complementary outputs available from the last stage. Parallel inputing occurs asynchronously when the Parallel Load (PL) input is LOW. With PL HIGH, LOW POWER SCHOTTKY serial shifting occurs on the rising edge of the clock; new data enters via the Serial Data (DS) input. The 2-input OR clock can be used to combine two independent clock sources, or one input can act as an active LOW clock enable. CONNECTION DIAGRAM DIP (TOP VIEW) J SUFFIX VCC CP2 P3 P2 P1 P0 DS Q7 CERAMIC 16 15 14 13 12 11 10 9 CASE 620-09 NOTE: 16 The Flatpak version 1 has the same pinouts (Connection Diagram) as the Dual In-Line Package. 123 4 56 78 N SUFFIX PL CP1 P4 P5 P6 P7 Q7 GND PLASTIC CASE 648-08 16 1 PIN NAMES LOADING (Note a) HIGH LOW CP1, CP2 Clock (LOW-to-HIGH Going Edge) Inputs 0.5 U.L. 0.25 U.L. 16 D SUFFIX DS Serial Data Input 0.5 U.L. 0.25 U.L. 1 SOIC PL Asynchronous Parallel Load (Active LOW) 1.5 U.L. 0.75 U.L. CASE 751B-03 P0 – P7 Input Q7 Parallel Data Inputs 0.5 U.L. 0.25 U.L. ORDERING INFORMATION Q7 Serial Output from Last State (Note b) 10 U.L. 5 (2.5) U.L. Complementary Output (Note b) 10 U.L. 5 (2.5) U.L. SN54LSXXXJ Ceramic SN74LSXXXN Plastic NOTES: SN74LSXXXD SOIC a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) Temperature Ranges. TRUTH TABLE LOGIC SYMBOL CP Q1 CONTENTS Q6 Q7 RESPONSE 1 11 12 13 14 3 4 5 6 PL P1 Q2 Q3 Q4 Q5 P6 P7 Parallel Entry 1 2 Q0 Q0 Q5 Q6 Right Shift Q1 P2 P3 P4 P5 Q6 Q7 No Change L X X P0 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Right Shift Q1 Q2 Q3 Q4 Q5 Q6 Q7 No Change HL DS Q1 Q2 Q3 Q4 PL P0 P1 P2 P3 P4 P5 P6 P7 Q2 Q3 Q4 Q5 DS Q7 HH Q0 10 9 H L DS 2 15 H H Q0 CP Q7 7 H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial VCC = PIN 16 GND = PIN 8 FAST AND LS TTL DATA 5-170

LOGIC DIAGRAM SN54 / 74LS165 45 6 P5 P6 P7 10 DS 11 12 13 14 3 2 CP1 P0 P1 P2 P3 P4 15 CP2 1 PL PRESET PRESET PRESET PRESET PRESET PRESET PRESET PRESET 9 S Q0 S Q1 S Q2 S Q3 S Q4 S Q5 S Q6 S Q7 7 VCC = PIN 16 CP CP CP CP CP CP CP CP GND = PIN 8 R CLQ0 R CLQ1 R CLQ2 R CLQ3 R CLQ4 R CLQ5 R CLQ6 R CLQ7 = PIN NUMBERS FUNCTIONAL DESCRIPTION applying a HIGH signal. To avoid double clocking, however, the inhibit signal should only go HIGH while the clock is HIGH. The SN54/74LS165 contains eight clocked master/slave Otherwise, the rising inhibit signal will cause the same RS flip-flops connected as a shift register, with auxiliary gating response as a rising clock edge. The flip-flops are to provide overriding asynchronous parallel entry. Parallel edge-triggered for serial operations. The serial input data can data enters when the PL signal is LOW. The parallel data can change at any time, provided only that the recommended change while PL is LOW, provided that the recommended set- setup and hold times are observed, with respect to the rising up and hold times are observed. edge of the clock. For clock operation, PL must be HIGH. The two clock inputs perform identically; one can be used as a clock inhibit by GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 4.5 5.0 5.5 V 74 4.75 5.0 5.25 TA Operating Ambient Temperature Range 54 – 55 25 125 °C 74 0 25 70 IOH Output Current — High 54, 74 – 0.4 mA IOL Output Current — Low 54 4.0 mA 74 8.0 FAST AND LS TTL DATA 5-171

SN54 / 74LS165 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter Min Typ Max Unit Test Conditions VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for All Inputs 54 0.7 Guaranteed Input LOW Voltage for VIL Input LOW Voltage 0.8 V All Inputs 74 VIK Input Clamp Diode Voltage 54 – 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA VOH Output HIGH Voltage 74 2.5 3.5 2.7 3.5 V VCC = MIN, IOH = MAX, VIN = VIH V or VIL per Truth Table VOL Output LOW Voltage 54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN, 74 0.35 0.5 V IOL = 8.0 mA VIN = VIL or VIH per Truth Table Input HIGH Current 20 µA VCC = MAX, VIN = 2.7 V Other Inputs 60 IIH PL Input 0.1 mA VCC = MAX, VIN = 7.0 V Other Inputs 0.3 PL Input Input LOW Current – 0.4 mA VCC = MAX, VIN = 0.4 V – 1.2 IIL Other Inputs PL Input IOS Short Circuit Current (Note 1) – 20 – 100 mA VCC = MAX ICC Power Supply Current 36 mA VCC = MAX Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C) Symbol Parameter Limits Unit Test Conditions MHz fMAX Maximum Input Clock Frequency Min Typ Max VCC = 5.0 V ns CL = 15 pF tPLH Propagation Delay 25 35 tPHL PL to Output ns 22 35 tPLH Propagation Delay 22 35 ns tPHL Clock to Output 27 40 ns tPLH Propagation Delay 28 40 tPHL P7 to Q7 14 25 tPLH Propagation Delay 21 30 tPHL P7 to Q7 21 30 16 25 FAST AND LS TTL DATA 5-172

SN54 / 74LS165 AC SETUP REQUIREMENTS (TA = 25°C) Symbol Parameter Min Limits Max Unit Test Conditions Typ ns VCC = 5.0 V ns tW CP Clock Pulse Width 25 ns ns tW PL Pulse Width 15 ns ns ts Parallel Data Setup Time 10 ns ts Serial Data Setup Time 20 ts CP1 to CP2 Setup Time1 30 th Hold Time 0 trec Recovery Time, PL to CP 45 1 The role of CP1, and CP2 in an application may be interchanged. DEFINITION OF TERMS: recognition. A negative hold time indicates that the correct logic level may be released prior to the clock transition from SETUP TIME (ts) — is defined as the minimum time required LOW-to-HIGH and still be recognized. for the correct logic level to be present at the logic input prior to the clock transition from LOW-to-HIGH in order to be recog- RECOVERY TIME (trec) — is defined as the minimum time nized and transferred to the outputs. required between the end of the PL pulse and the clock transition from LOW-to-HIGH in order to recognize and HOLD TIME (th) — is defined as the minimum time following transfer loaded Data to the Q outputs. the clock transition from LOW-to-HIGH that the logic level must be maintained at the input in order to ensure continued AC WAVEFORMS CP1 ts 1/fmax 1.3 V PL 1.3 V tW CP2 1.3 V tW 1.3 V tPLH 1.3 V 1.3 V Q7 OR Q7 tPHL tPLH Q7 OR Q7 tPHL 1.3 V 1.3 V 1.3 V Figure 1 Figure 2 Pn 1.3 V 1.3 V PL 1.3 V 1.3 V PL OR CP ts(H) th(H) ts(L) th(L) tW trec 1.3 V 1.3 V CP 1.3 V Figure 3 Figure 4 FAST AND LS TTL DATA 5-173

SN54/74LS166 8-BIT SHIFT REGISTERS 8-BIT SHIFT REGISTERS LOW POWER SCHOTTKY The SN54L/ 74LS166 is an 8-Bit Shift Register. Designed with all inputs buffered, the drive requirements are lowered to one 54 / 74LS standard load. J SUFFIX By utilizing input clamping diodes, switching transients are minimized and CERAMIC system design simplified. CASE 620-09 The LS166 is a parallel-in or serial-in, serial-out shift register and has a 16 complexity of 77 equivalent gates with gated clock inputs and an overriding 1 clear input. The shift/load input establishes the parallel-in or serial-in mode. When high, this input enables the serial data input and couples the eight 16 N SUFFIX flip-flops for serial shifting with each clock pulse. Synchronous loading occurs 1 PLASTIC on the next clock pulse when this is low and the parallel data inputs are CASE 648-08 enabled. Serial data flow is inhibited during parallel loading. Clocking is done on the low-to-high level edge of the clock pulse via a two input positive NOR gate, which permits one input to be used as a clock enable or clock inhibit function. Clocking is inhibited when either of the clock inputs are held high, holding either input low enables the other clock input. This will allow the system clock to be free running and the register stopped on command with the other clock input. A change from low-to-high on the clock inhibit input should only be done when the clock input is high. A buffered direct clear input overrides all other inputs, including the clock, and sets all flip-flops to zero. • Synchronous Load • Direct Overriding Clear • Parallel to Serial Conversion PARALLEL PARALLEL INPUTS 16 D SUFFIX 1 SOIC SHIFT/ INPUT OUTPUT VCC LOAD H QH G F E CLEAR CASE 751B-03 16 15 14 13 12 11 10 9 SHIFT/ H QH GF E LOAD SERIAL INPUT CLEAR ORDERING INFORMATION A BC D CLOCK CK SN54LSXXXJ Ceramic INHIBIT SN74LSXXXN Plastic SN74LSXXXD SOIC 1 2345 6 78 AB CD SERIAL CLOCK CLOCK GND INPUT PARALLEL INPUTS INHIBIT FUNCTION TABLE INPUTS INTERNAL OUTPUTS SHIFT/ CLOCK PARALLEL OUTPUT CLEAR LOAD QH INHIBIT CLOCK SERIAL A...H QA QB LX L HX XXX X L L QH0 HL QA0 QB0 HH L LX X h HH a b QGn HX L ↑ X a...h H QAn QGn L QAn QH0 L ↑H X QA0 QB0 L↑L X H↑X X FAST AND LS TTL DATA 5-174

SN54 / 74LS166 Typical Clear, Shift, Load, Inhibit, and Shift Sequences CLOCK CLOCK INIHIBIT CLEAR SERIAL INPUT SHIFT/LOAD A H L B C H L PARALLEL D INPUTS H E L F H G H H SERIAL SHIFT INHIBIT H H L H L H L H OUTPUT QH SERIAL SHIFT CLEAR LOAD CLEAR (9) (1) SERIAL INPUT (15) SHIFT/LOAD A (2) RS CK QA (3) B RS CK QB (4) C RS CK QC (5) RS D CK QD (10) E (11) RS F CK QE RS CK QF (12) RS G CK QG (14) H RS CK (7) CLOCK (13) QH (6) CLOCK INHIBIT FAST AND LS TTL DATA 5-175

SN54 / 74LS166 GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 4.5 5.0 5.5 V 74 4.75 5.0 5.25 TA Operating Ambient Temperature Range 54 – 55 25 125 °C 74 0 25 70 IOH Output Current — High 54, 74 – 0.4 mA IOL Output Current — Low 54 4.0 mA 74 8.0 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter Min Typ Max Unit Test Conditions VIH Input HIGH Voltage 2.0 Guaranteed Input HIGH Voltage for V All Inputs 54 0.7 Guaranteed Input LOW Voltage for VIL Input LOW Voltage 74 0.8 V All Inputs VIK Input Clamp Diode Voltage 54 – 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA VOH Output HIGH Voltage 74 2.5 3.5 2.7 3.5 V VCC = MIN, IOH = MAX, VIN = VIH V or VIL per Truth Table VOL Output LOW Voltage 54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN, 74 0.35 0.5 V IOL = 8.0 mA VIN = VIL or VIH per Truth Table IIH Input HIGH Current 20 µA VCC = MAX, VIN = 2.7 V 0.1 mA VCC = MAX, VIN = 7.0 V IIL Input LOW Current – 0.4 mA VCC = MAX, VIN = 0.4 V IOS Short Circuit Current (Note 1) – 20 – 100 mA VCC = MAX ICC Power Supply Current 38 mA VCC = MAX Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. FAST AND LS TTL DATA 5-176

SN54 / 74LS166 TEST TABLE FOR SYNCHRONOUS INPUTS DATA INPUT SHIFT/LOAD OUTPUT TESTED FOR TEST H 0V QH at tn+1 4.5 V QH at tn+8 Serial Input AC WAVEFORMS CLEAR INPUT tw(clear) 3V Vref Vref 0V tn tn + 1 (SEE NOTE 1) tn tn + 1 3V 0V CLOCK INPUT Vref Vref Vref Vref 3V Vref tsu th tsu th 0V tw(clock) Vref Vref VOH DATA tPHL VOL INPUT (clear-Q) tPLH tPHL (SEE TEST (CLK-Q) (CLK-Q) TABLE) Vref Vref OUTPUT Q Vref NOTE 1. tn = bit time before clocking transition NOTE 1. tn+1 = bit time after one clocking transition NOTE 1. tn+8 = bit time after eight clocking transition NOTE 1. LS166 Vref = 1.3 V. AC CHARACTERISTICS (TA = 25°C) Symbol Parameter Limits Unit Test Conditions Maximum Clock Frequency Min Typ Max MHz VCC = 5.0 V fMAX Clear to Output 25 35 CL = 15 pF tPHL ns tPLH Clock to Output 19 30 Test Conditions tPHL ns VCC = 5.0 V 23 35 24 35 AC SETUP REQUIREMENTS (TA = 25°C) Symbol Parameter Limits Unit Clock Clear Pulse Width Min Typ Max ns tW Mode Control Setup Time 30 ns ts Data Setup Time 30 ns ts Hold Time, Any Input 20 ns th 15 FAST AND LS TTL DATA 5-177

BCD DECADE/MODULO SN54/74LS168 16 BINARY SYNCHRONOUS SN54/74LS169 BI-DIRECTIONAL COUNTERS BCD DECADE / MODULO The SN54 / 74LS168 and SN54 / 74LS169 are fully synchronous 4-stage 16 BINARY SYNCHRONOUS up/down counters featuring a preset capability for programmable operation, BI-DIRECTIONAL COUNTERS carry lookahead for easy cascading and a U / D input to control the direction of counting. The SN54 / 74LS168 counts in a BCD decade (8, 4, 2, 1) LOW POWER SCHOTTKY sequence, while the SN54 / 74LS169 operates in a Modulo 16 binary sequence. All state changes, whether in counting or parallel loading, are J SUFFIX initiated by the LOW-to-HIGH transition of the clock. CERAMIC CASE 620-09 • Low Power Dissipation 100 mW Typical • High-Speed Count Frequency 30 MHz Typical 16 • Fully Synchronous Operation 1 • Full Carry Lookahead for Easy Cascading • Single Up / Down Control Input • Positive Edge-Trigger Operation • Input Clamp Diodes Limit High-Speed Termination Effects CONNECTION DIAGRAM DIP (TOP VIEW) 16 N SUFFIX 1 PLASTIC VCC TC Q0 Q1 Q2 Q3 CET PE CASE 648-08 16 15 14 13 12 11 10 9 NOTE: 16 D SUFFIX The Flatpak version 1 SOIC has the same pinouts (Connection Diagram) as CASE 751B-03 the Dual In-Line Package. 1234 56 78 ORDERING INFORMATION U/D CP P0 P1 P2 P3 CEP GND PIN NAMES LOADING (Note a) SN54LSXXXJ Ceramic SN74LSXXXN Plastic SN74LSXXXD SOIC HIGH LOW CEP Count Enable Parallel (Active LOW) Input 0.5 U.L. 0.25 U.L. LOGIC SYMBOL 93 4 5 6 CET Count Enable Trickle (Active LOW) Input 1.0 U.L. 0.5 U.L. CP Clock Pulse (Active positive going edge) Input 0.5 U.L. 0.25 U.L. PE Parallel Enable (Active LOW) Input 0.5 U.L. 0.25 U.L. U/D Up-Down Count Control Input 0.5 U.L. 0.25 U.L. P0–P3 Parallel Data Inputs 0.5 U.L. 0.25 U.L. 1 PE P0 P1 P2 P3 Q0–Q3 Flip-Flop Outputs 10 U.L. 5 (2.5) U.L. U/D TC Terminal Count (Active LOW) Output 10 U.L. 5 (2.5) U.L. 7 CEP TC 15 10 CET NOTES: 2 CP a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. Q0 Q1 Q2 Q3 b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) b. Temperature Ranges. 14 13 12 11 VCC = PIN 16 GND = PIN 8 FAST AND LS TTL DATA 5-178