TTL_Databook

SN54 / 74LS76A GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 4.5 5.0 5.5 V 74 4.75 5.0 5.25 TA Operating Ambient Temperature Range 54 – 55 25 125 °C 74 0 25 70 IOH Output Current — High 54, 74 – 0.4 mA IOL Output Current — Low mA 54 4.0 74 8.0 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter Min Typ Max Unit Test Conditions VIH Input HIGH Voltage Guaranteed Input HIGH Voltage for 2.0 V All Inputs VIL Input LOW Voltage 54 0.7 Guaranteed Input LOW Voltage for 74 0.8 V All Inputs VIK Input Clamp Diode Voltage – 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA VOH Output HIGH Voltage 54 2.5 3.5 V VCC = MIN, IOH = MAX, VIN = VIH 74 2.7 3.5 V or VIL per Truth Table VOL Output LOW Voltage 54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN, 74 0.35 0.5 V IOL = 8.0 mA VIN = VIL or VIH per Truth Table IIH Input HIGH Current J, K 20 Clear 60 µA VCC = MAX, VIN = 2.7 V Clock 80 J, K 0.1 Clear 0.3 mA VCC = MAX, VIN = 7.0 V Clock 0.4 IIL Input LOW Current J, K – 0.4 mA VCC = MAX, VIN = 0.4 V Clear, Clock – 0.8 IOS Short Circuit Current (Note 1) – 20 –100 mA VCC = MAX 6.0 mA VCC = MAX ICC Power Supply Current Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. Unit Test Conditions MHz VCC = 5.0 V AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V) CL = 15 pF ns Limits ns Symbol Parameter Min Typ Max fMAX Maximum Clock Frequency 30 45 Clock, Clear, Set to Output 15 20 tPLH 15 20 tPHL AC SETUP REQUIREMENTS (TA = 25°C) Symbol Parameter Limits Unit Test Conditions Clock Pulse Width High Min Typ Max ns VCC = 5.0 V tW Clear Set Pulse Width 20 ns tW Setup Time 25 ns ts Hold Time 20 ns th 0 FAST AND LS TTL DATA 5-79

SN54/74LS83A 4-BIT BINARY FULL ADDER 4-BIT BINARY FULL ADDER WITH FAST CARRY WITH FAST CARRY The SN54 / 74LS83A is a high-speed 4-Bit binary Full Adder with internal LOW POWER SCHOTTKY carry lookahead. It accepts two 4-bit binary words (A1 – A4, B1 – B4) and a Carry Input (C0). It generates the binary Sum outputs ∑1 – ∑4) and the Carry J SUFFIX Output (C4) from the most significant bit. The LS83A operates with either CERAMIC active HIGH or active LOW operands (positive or negative logic). The CASE 620-09 SN54 / 74LS283 is recommended for new designs since it is identical in function with this device and features standard corner power pins. CONNECTION DIAGRAM DIP (TOP VIEW) B4 Σ4 C4 C0 GND B1 A1 Σ1 16 15 14 13 12 11 10 9 NOTE: 16 The Flatpak version has the 1 same pinouts (Connection Diagram) as the Dual In-Line Package. 12 3 4 56 78 N SUFFIX A4 Σ3 A3 B3 VCC Σ2 B2 A2 PLASTIC CASE 648-08 PIN NAMES LOADING (Note a) 16 1 HIGH LOW A1 – A4 Operand A Inputs 1.0 U.L. 0.5 U.L. 16 D SUFFIX B1 – B4 Operand B Inputs 1.0 U.L. 0.5 U.L. 1 SOIC Carry Input 0.5 U.L. 0.25 U.L. C0 Sum Outputs (Note b) 10 U.L. 5 (2.5) U.L. CASE 751B-03 Σ1 – Σ4 Carry Output (Note b) 10 U.L. 5 (2.5) U.L. C4 NOTES: a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) ORDERING INFORMATION Temperature Ranges. LOGIC DIAGRAM SN54LSXXJ Ceramic SN74LSXXN Plastic A3 B3 SN74LSXXD SOIC C0 A1 B1 A2 B2 34 A4 B4 VCC = PIN 5 GND = PIN 12 13 10 11 87 1 16 = PIN NUMBERS LOGIC SYMBOL 10 11 8 7 3 4 1 16 B1 A2 B2 A3 B3 A4 B4 13 C0 C4 14 ∑1∑2 ∑3∑4 C4 9 6 2 15 14 C1 C2 C3 96 2 15 14 ∑1 ∑2 ∑3 ∑4 C4 FAST AND LS TTL DATA 5-80

SN54 / 74LS83A FUNCTIONAL DESCRIPTION The LS83A adds two 4-bit binary words (A plus B) plus the incoming carry. The binary sum appears on the sum outputs (∑1 – ∑4) and outgoing carry (C4) outputs. C0 + (A1+B1)+2(A2+B2)+4(A3+B3)+8(A4+B4) = ∑1+2∑2+4∑3+8∑4+16C4 Where: (+) = plus Due to the symmetry of the binary add function the LS83A can be used with either all inputs and outputs active HIGH (positive logic) or with all inputs and outputs active LOW (negative logic). Note that with active HIGH Inputs, Carry Input can not be left open, but must be held LOW when no carry in is intended. Example: Logic Levels C0 A1 A2 A3 A4 B1 B2 B3 B4 ∑1 ∑2 ∑3 ∑4 C4 Active HIGH L L H L HH L L H H H L L H Active LOW 0 01 0 11 0 0 1 1 1 0 0 1 (10+9 = 19) 1 10 1 00 1 1 0 0 0 1 1 0 (carry+5+6 = 12) Interchanging inputs of equal weight does not affect the operation, thus C0, A1, B1, can be arbitrarily assigned to pins 10, 11, 13, etc. FUNCTIONAL TRUTH TABLE C (n–1) An Bn ∑n Cn L LLL L L L LHH L L HLH H L HHL L H LLH H H LHL H H HLL H H HHH C1 — C3 are generated internally C0 — is an external input C4 — is an output generated internally GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 4.5 5.0 5.5 V 74 4.75 5.0 5.25 TA Operating Ambient Temperature Range 54 – 55 25 125 °C 74 0 25 70 IOH Output Current — High 54, 74 – 0.4 mA IOL Output Current — Low 54 4.0 mA 74 8.0 FAST AND LS TTL DATA 5-81

SN54 / 74LS83A DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Symbol Parameter Limits Unit Test Conditions Min Typ Max VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for All Inputs 54 0.7 Guaranteed Input LOW Voltage for VIL Input LOW Voltage 0.8 V All Inputs 74 VIK Input Clamp Diode Voltage 54 – 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA VOH Output HIGH Voltage 74 2.5 3.5 2.7 3.5 V VCC = MIN, IOH = MAX, VIN = VIH V per Truth Table VOL Output LOW Voltage 54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN, 74 0.35 0.5 V IOL = 8.0 mA VIN = VIL or VIH per Truth Table Input HIGH Current 20 µA VCC = MAX, VIN = 2.7 V 40 C0 IIH A or B 0.1 mA VCC = MAX, VIN = 7.0 V 0.2 C0 A or B Input LOW Current – 0.4 mA VCC = MAX, VIN = 0.4 V – 0.8 IIL C0 A or B IOS Output Short Circuit Current (Note 1) – 20 –100 mA VCC = MAX ICC Power Supply Current 39 mA VCC = MAX All Inputs Grounded 34 All Inputs at 4.5 V, Except B 34 All Inputs at 4.5 V Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C) Symbol Parameter Limits Unit Test Conditions ns tPLH Propagation Delay, C0 Input Min Typ Max ns VCC = 5.0 V tPHL to any Σ Output ns CL = 15 pF 16 24 ns Figures 1 and 2 tPLH Propagation Delay, Any A or 15 24 tPHL B Input to Σ Outputs 15 24 tPLH Propagation Delay, C0 Input 15 24 tPHL to C4 Output 11 17 tPLH Propagation Delay, Any A or 15 22 tPHL B Input to C4 Output 11 17 12 17 AC WAVEFORMS VIN 1.3 V 1.3 V VIN 1.3 V 1.3 V VOUT tPHL tPLH VOUT tPLH tPHL 1.3 V 1.3 V 1.3 V 1.3 V Figure 1 Figure 2 FAST AND LS TTL DATA 5-82

SN54/74LS85 4-BIT MAGNITUDE 4-BIT MAGNITUDE COMPARATOR COMPARATOR LOW POWER SCHOTTKY The SN54 / 74LS85 is a 4-Bit Magnitude Camparator which compares two 4-bit words (A, B), each word having four Parallel Inputs (A0 – A3, B0 – B3); A3, J SUFFIX B3 being the most significant inputs. Operation is not restricted to binary CERAMIC codes, the device will work with any monotonic code. Three Outputs are CASE 620-09 provided: “A greater than B” (OA > B), “A less than B” (OA < B), “A equal to B” (OA = B). Three Expander Inputs, IA > B, IA < B, IA = B, allow cascading without 16 external gates. For proper compare operation, the Expander Inputs to the 1 least significant position must be connected as follows: IA < B= IA > B = L, IA = B = H. For serial (ripple) expansion, the OA > B, OA < B and OA = B Outputs are 16 N SUFFIX connected respectively to the IA > B, IA < B, and IA = B Inputs of the next most 1 PLASTIC significant comparator, as shown in Figure 1. Refer to Applications section of CASE 648-08 data sheet for high speed method of comparing large words. The Truth Table on the following page describes the operation of the SN54 / 74LS85 under all possible logic conditions. The upper 11 lines describe the normal operation under all conditions that will occur in a single device or in a series expansion scheme. The lower five lines describe the operation under abnormal conditions on the cascading inputs. These conditions occur when the parallel expansion technique is used. • Easily Expandable • Binary or BCD Comparison • OA > B, OA < B, and OA = B Outputs Available CONNECTION DIAGRAM DIP (TOP VIEW) 16 D SUFFIX 1 SOIC VCC A3 B2 A2 A1 B1 A0 B0 16 15 14 13 12 11 10 9 CASE 751B-03 NOTE: ORDERING INFORMATION The Flatpak version has the same pinouts (Connection SN54LSXXJ Ceramic Diagram) as the Dual In-Line SN74LSXXN Plastic Package. SN74LSXXD SOIC 1 2 3 4 56 78 B3 IA<B IA=B IA>B OA>B OA=B OA<B GND LOGIC SYMBOL PIN NAMES LOADING (Note a) 10 12 13 15 9 11 14 1 HIGH LOW A0 A1 A2 A3 B0 B1 B2 B3 A0 – A3, B0 – B3 Parallel Inputs 1.5 U.L. 0.75 U.L. 4 IA>B OA>B 5 IA = B A = B Expander Inputs 1.5 U.L. 0.75 U.L. IA < B, IA > B A < B, A > B, Expander Inputs 0.5 U.L. 0.25 U.L. 2 IA<B OA<B 7 OA > B A Greater Than B Output (Note b) 10 U.L. 5 (2.5) U.L. OA < B B Greater Than A Output (Note b) 10 U.L. 5 (2.5) U.L. 3 IA=B OA=B 6 OA = B A Equal to B Output (Note b) 10 U.L. 5 (2.5) U.L. VCC = PIN 16 NOTES: GND = PIN 8 a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) Temperature Ranges. FAST AND LS TTL DATA 5-83

SN54 / 74LS85 LOGIC DIAGRAM A3 (15) B3 (1) (13) (5) A2 OA>B B2 (6) (14) OA=B A<B (2) (7) A=B OA<B (3) A>B (4) (12) A1 B1 (11) (10) A0 B0 (9) TRUTH TABLE COMPARING INPUTS CASCADING OUTPUTS INPUTS A3,B3 A2,B2 A1,B1 A0,B0 IA>B IA<B IA=B OA>B OA<B OA=B H = HIGH Level L = LOW Level A3>B3 X X X X X X H L L X = IMMATERIAL A3<B3 X X X L H L A3=B3 X X X X X X H L L A3=B3 X X X L H L A3=B3 A2>B2 X X X X X H L L A3=B3 A2<B2 X X X L H L A3=B3 A2=B2 X X X X X H L L A3=B3 A2=B2 X X X L H L A3=B3 A2=B2 A1>B1 X H L L H L L A3=B3 A2=B2 A1<B1 L H L L H L A3=B3 A2=B2 A1=B1 X X X H L L H A3=B3 A2=B2 A1=B1 H H L L L L A3=B3 A2=B2 A1=B1 A0>B0 L L L H H L A2=B2 A1=B1 A0<B0 A2=B2 A1=B1 A0=B0 A1=B1 A0=B0 A1=B1 A0=B0 A0=B0 A0=B0 GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 4.5 5.0 5.5 V 74 4.75 5.0 5.25 TA Operating Ambient Temperature Range 54 – 55 25 125 °C 74 0 25 70 IOH Output Current — High 54, 74 – 0.4 mA IOL Output Current — Low 54 4.0 mA 74 8.0 FAST AND LS TTL DATA 5-84

SN54 / 74LS85 A0 A1 A2 A3 B0 B1 B2 B3 A n3 A n2 A n1 An B n3 B n2 B n1 Bn A0 A1 A2 A3 B0 B1 B2 B3 A0 A1 A2 A3 B0 B1 B2 B3 L IA > B OA > B IA > B OA > B A>B A<B L IA < B SN54/74LS85 OA < B IA < B SN54/74LS85 OA < B A=B H IA = B OA = B IA = B OA = B L = LOW LEVEL H = HIGH LEVEL Figure 1. Comparing Two n-Bit Words APPLICATIONS Figure 2 shows a high speed method of comparing two 24-bit words with only two levels of device delay. With the technique shown in Figure 1, six levels of device delay result when comparing two 24-bit words. The parallel technique can be expanded to any number of bits, see Table 1. Table 1 WORD LENGTH NUMBER OF PKGS. NOTE: 1 – 4 Bits 1 The SN54/74LS85 can be used as a 5-bit comparator 5 – 24 Bits 2–6 25 – 120 Bits 8 – 31 only when the outputs are used to drive the A0–A3 and B0–B3 inputs of another SN54/74LS85 as shown in Figure 2 in positions #1, 2, 3, and 4. (LSB) INPUTS (MSB) A0 A1 A2 A3 B0 B1 B2 B3 A20 A21 A22 A23 B20 B21 B22 B23 A19 A0 A1 A2 A3 B0 B1 B2 B3 B19 A0 A1 A2 A3 B0 B1 B2 B3 L IA > B IA > B OA > B OA > B L L IA < B #5 OA < B IA < B #1 OA < B H IA = B OA = B IA = B OA = B NC INPUTS A5 A6 A7 A8 B5 B6 B7 B8 A10 A11 A12 A13 B10 B11 B12 B13 A15 A16 A17 A18 B15 B16 B17 B18 A0 A1 A2 A3 B0 B1 B2 B3 A0 A1 A2 A3 B0 B1 B2 B3 A0 A1 A2 A3 B0 B1 B2 B3 A4 IA > B OA > B A9 IA > B OA > B A14 IA > B OA > B B4 IA < B #4 OA < B B9 IA < B #3 OA < B B14 IA < B #2 OA < B L IA = B OA = B NC L IA = B OA = B NC L IA = B OA = B NC A0 A1 A2 A3 B0 B1 B2 B3 OUTPUTS IA > B OA > B IA < B #6 OA < B IA = B OA = B MSB = MOST SIGNIFICANT BIT LSB = LEAST SIGNIFICANT BIT L = LOW LEVEL H = HIGH LEVEL NC = NO CONNECTION Figure 2. Comparison of Two 24-Bit Words FAST AND LS TTL DATA 5-85

SN54 / 74LS85 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Symbol Parameter Limits Unit Test Conditions Min Typ Max VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for All Inputs 54 0.7 Guaranteed Input LOW Voltage for VIL Input LOW Voltage 0.8 V All Inputs 74 VIK Input Clamp Diode Voltage 54 – 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA VOH Output HIGH Voltage 74 2.5 3.5 2.7 3.5 V VCC = MIN, IOH = MAX, VIN = VIH V or VIL per Truth Table VOL Output LOW Voltage 54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN, 74 0.35 0.5 V IOL = 8.0 mA VIN = VIL or VIH per Truth Table Input HIGH Current 20 µA VCC = MAX, VIN = 2.7 V A < B, A > B 60 IIH Other Inputs 0.1 mA VCC = MAX, VIN = 7.0 V A < B, A > B 0.3 Other Inputs Input LOW Current – 0.4 mA VCC = MAX, VIN = 0.4 V – 1.2 IIL A < B, A > B Other Inputs IOS Output Short Circuit Current (Note 1) – 20 –100 mA VCC = MAX ICC Power Supply Current 20 mA VCC = MAX Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V) Limits Symbol Parameter Min Typ Max Unit Test Conditions ns tPLH Any A or B to A < B, A > B 24 36 ns VCC = 5.0 V tPHL 20 30 ns CL = 15 pF ns tPLH Any A or B to A = B 27 45 ns tPHL 23 45 tPLH A < B or A = B to A > B 14 22 tPHL 11 17 tPLH A = B to A = B 13 20 tPHL 13 26 tPLH A > B or A = B to A < B 14 22 tPHL 11 17 AC WAVEFORMS VIN 1.3 V 1.3 V VIN 1.3 V 1.3 V VOUT tPHL tPLH VOUT tPHL tPLH 1.3 V 1.3 V 1.3 V 1.3 V Figure 3 Figure 4 FAST AND LS TTL DATA 5-86

SN54/74LS86 QUAD 2-INPUT EXCLUSIVE OR GATE QUAD 2-INPUT EXCLUSIVE OR GATE LOW POWER SCHOTTKY VCC 9 8 14 13 12 11 10 J SUFFIX CERAMIC CASE 632-08 1234567 14 GND 1 14 N SUFFIX 1 PLASTIC CASE 646-06 TRUTH TABLE IN OUT AB Z D SUFFIX SOIC LL L 14 LH H 1 CASE 751A-02 HL H HH L ORDERING INFORMATION SN54LSXXJ Ceramic SN74LSXXN Plastic SN74LSXXD SOIC GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 4.5 5.0 5.5 V 74 4.75 5.0 5.25 TA Operating Ambient Temperature Range 54 – 55 25 125 °C 74 0 25 70 IOH Output Current — High 54, 74 – 0.4 mA IOL Output Current — Low 54 4.0 mA 74 8.0 FAST AND LS TTL DATA 5-87

SN54 / 74LS86 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter Min Typ Max Unit Test Conditions VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for All Inputs 54 0.7 Guaranteed Input LOW Voltage for VIL Input LOW Voltage 74 0.8 V All Inputs VIK Input Clamp Diode Voltage – 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA VOH Output HIGH Voltage 54 2.5 3.5 V VCC = MIN, IOH = MAX, VIN = VIH 74 2.7 3.5 V or VIL per Truth Table VOL Output LOW Voltage 54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN, 74 0.35 0.5 V IOL = 8.0 mA VIN = VIL or VIH per Truth Table IIH Input HIGH Current 40 µA VCC = MAX, VIN = 2.7 V 0.2 mA VCC = MAX, VIN = 7.0 V IIL Input LOW Current – 0.8 mA VCC = MAX, VIN = 0.4 V IOS Short Circuit Current (Note 1) – 20 –100 mA VCC = MAX ICC Power Supply Current 10 mA VCC = MAX Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C) Symbol Parameter Limits Unit Test Conditions ns tPLH Propagation Delay, Min Typ Max ns VCC = 5.0 V tPHL Other Input LOW CL = 15 pF 12 23 tPLH Propagation Delay, 10 17 tPHL Other Input HIGH 20 30 13 22 FAST AND LS TTL DATA 5-88

DECADE COUNTER; SN54/74LS90 DIVIDE-BY-TWELVE COUNTER; SN54/74LS92 4-BIT BINARY COUNTER SN54/74LS93 The SN54 / 74LS90, SN54 / 74LS92 and SN54 / 74LS93 are high-speed DECADE COUNTER; 4-bit ripple type counters partitioned into two sections. Each counter has a di- DIVIDE-BY-TWELVE COUNTER; vide-by-two section and either a divide-by-five (LS90), divide-by-six (LS92) or divide-by-eight (LS93) section which are triggered by a HIGH-to-LOW transi- 4-BIT BINARY COUNTER tion on the clock inputs. Each section can be used separately or tied together (Q to CP) to form BCD, bi-quinary, modulo-12, or modulo-16 counters. All of LOW POWER SCHOTTKY the counters have a 2-input gated Master Reset (Clear), and the LS90 also has a 2-input gated Master Set (Preset 9). J SUFFIX CERAMIC • Low Power Consumption . . . Typically 45 mW CASE 632-08 • High Count Rates . . . Typically 42 MHz • Choice of Counting Modes . . . BCD, Bi-Quinary, Divide-by-Twelve, 14 1 Binary • Input Clamp Diodes Limit High Speed Termination Effects PIN NAMES LOADING (Note a) HIGH LOW N SUFFIX PLASTIC CP0 Clock (Active LOW going edge) Input to 0.5 U.L. 1.5 U.L. CASE 646-06 ÷2 Section CP1 0.5 U.L. 2.0 U.L. 14 Clock (Active LOW going edge) Input to 1 CP1 ÷5 Section (LS90), ÷6 Section (LS92) 0.5 U.L. 1.0 U.L. MR1, MR2 Clock (Active LOW going edge) Input to MS1, MS2 ÷8 Section (LS93) 0.5 U.L. 0.25 U.L. 14 D SUFFIX Q0 0.5 U.L. 0.25 U.L. 1 SOIC Q1, Q2, Q3 Master Reset (Clear) Inputs 10 U.L. 5 (2.5) U.L. 10 U.L. 5 (2.5) U.L. CASE 751A-02 Master Set (Preset-9, LS90) Inputs Output from ÷2 Section (Notes b & c) ORDERING INFORMATION Outputs from ÷5 (LS90), ÷6 (LS92), ÷8 (LS93) Sections (Note b) NOTES: SN54LSXXJ Ceramic a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. SN74LSXXN Plastic b. The Output LOW drive factor is 2.5 U.L. for Military, (54) and 5 U.L. for commercial (74) SN74LSXXD SOIC b. Temperature Ranges. c. The Q0 Outputs are guaranteed to drive the full fan-out plus the CP1 input of the device. d. To insure proper operation the rise (tr) and fall time (tf) of the clock must be less than 100 ns. LS90 LOGIC SYMBOL LS93 67 LS92 14 CP0 12 14 CP0 1 CP1 1 CP1 MS MR Q0 Q1 Q2 Q3 14 CP0 MR Q0 Q1 Q2 Q3 12 1 CP1 12 2 3 12 9 8 11 6 7 12 11 9 8 VCC = PIN 5 MR Q0 Q1 Q2 Q3 VCC = PIN 5 GND = PIN 10 GND = PIN 10 NC = PIN 4, 6, 7, 13 12 NC = PINS 2, 3, 4, 13 2 3 12 9 8 11 VCC = PIN 5 GND = PIN 10 NC = PINS 4, 13 FAST AND LS TTL DATA 5-89

SN54/74LS90 • SN54/74LS92 • SN54/74LS93 LOGIC DIAGRAM CONNECTION DIAGRAM DIP (TOP VIEW) LS90 6 J SD Q J SD Q J SD Q R SD Q CP1 1 14 CP0 CP CP CP CP MR1 2 13 NC MS1 K CD Q K CD Q K CD Q S CD Q MR2 3 MS2 7 12 Q0 12 98 11 NC 4 11 Q3 14 10 GND Q0 Q1 Q2 Q3 VCC 5 9 Q1 CP0 MS1 6 8 Q2 MS2 7 1 NC = NO INTERNAL CONNECTION CP1 NOTE: 2 The Flatpak version has the same pinouts (Connection Diagram) as MR1 the Dual In-Line Package. MR2 3 = PIN NUMBERS VCC = PIN 5 GND = PIN 10 LOGIC DIAGRAM CONNECTION DIAGRAM DIP (TOP VIEW) LS92 14 JQ JQ JQ JQ CP1 1 14 CP0 CP CP CP CP NC 2 13 NC CP0 K CD Q K CD Q K CD Q K CD Q NC 3 NC 4 12 Q0 1 12 11 9 8 VCC 5 11 Q1 MR1 6 10 GND CP1 Q0 Q1 Q2 Q3 MR2 7 9 Q2 8 Q3 6 MR1 MR2 7 = PIN NUMBERS NC = NO INTERNAL CONNECTION VCC = PIN 5 NOTE: GND = PIN 10 The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. LOGIC DIAGRAM CONNECTION DIAGRAM DIP (TOP VIEW) LS93 14 JQ JQ JQ JQ CP1 1 14 CP0 CP CP CP CP MR1 2 13 NC CP0 K CD Q K CD Q K CD Q K CD Q MR2 3 12 Q0 1 NC 4 11 Q3 VCC 5 10 GND CP1 9 Q1 NC 6 8 Q2 2 MR1 NC 7 MR2 3 12 9 8 11 Q0 Q1 Q2 Q3 = PIN NUMBERS NC = NO INTERNAL CONNECTION VCC = PIN 5 NOTE: GND = PIN 10 The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. FAST AND LS TTL DATA 5-90

SN54/74LS90 • SN54/74LS92 • SN54/74LS93 FUNCTIONAL DESCRIPTION C. Divide-By-Two and Divide-By-Five Counter — No external interconnections are required. The first flip-flop is used as a The LS90, LS92, and LS93 are 4-bit ripple type Decade, binary element for the divide-by-two function (CP0 as the Divide-By-Twelve, and Binary Counters respectively. Each input and Q0 as the output). The CP1 input is used to obtain device consists of four master/slave flip-flops which are binary divide-by-five operation at the Q3 output. internally connected to provide a divide-by-two section and a divide-by-five (LS90), divide-by-six (LS92), or divide-by-eight LS92 (LS93) section. Each section has a separate clock input which initiates state changes of the counter on the HIGH-to-LOW A. Modulo 12, Divide-By-Twelve Counter — The CP1 input clock transition. State changes of the Q outputs do not occur must be externally connected to the Q0 output. The CP0 in- simultaneously because of internal ripple delays. Therefore, put receives the incoming count and Q3 produces a sym- decoded output signals are subject to decoding spikes and metrical divide-by-twelve square wave output. should not be used for clocks or strobes. The Q0 output of each device is designed and specified to drive the rated B. Divide-By-Two and Divide-By-Six Counter —No external fan-out plus the CP1 input of the device. interconnections are required. The first flip-flop is used as a binary element for the divide-by-two function. The CP1 in- A gated AND asynchronous Master Reset (MR1 • MR2) is put is used to obtain divide-by-three operation at the Q1 provided on all counters which overrides and clocks and and Q2 outputs and divide-by-six operation at the Q3 out- resets (clears) all the flip-flops. A gated AND asynchronous put. Master Set (MS1 • MS2) is provided on the LS90 which overrides the clocks and the MR inputs and sets the outputs to LS93 nine (HLLH). A. 4-Bit Ripple Counter — The output Q0 must be externally Since the output from the divide-by-two section is not connected to input CP1. The input count pulses are applied internally connected to the succeeding stages, the devices to input CP0. Simultaneous divisions of 2, 4, 8, and 16 are may be operated in various counting modes. performed at the Q0, Q1, Q2, and Q3 outputs as shown in the truth table. LS90 B. 3-Bit Ripple Counter— The input count pulses are applied A. BCD Decade (8421) Counter — The CP1 input must be ex- to input CP1. Simultaneous frequency divisions of 2, 4, and ternally connected to the Q0 output. The CP0 input receives 8 are available at the Q1, Q2, and Q3 outputs. Independent the incoming count and a BCD count sequence is pro- use of the first flip-flop is available if the reset function coin- duced. cides with reset of the 3-bit ripple-through counter. B. Symmetrical Bi-quinary Divide-By-Ten Counter — The Q3 output must be externally connected to the CP0 input. The input count is then applied to the CP1 input and a divide-by- ten square wave is obtained at output Q0. FAST AND LS TTL DATA 5-91

SN54/74LS90 • SN54/74LS92 • SN54/74LS93 LS90 LS92 AND LS93 MODE SELECTION MODE SELECTION RESET / SET INPUTS OUTPUTS RESET OUTPUTS INPUTS MR1 MR2 MS1 MS2 Q0 Q1 Q2 Q3 MR1 MR2 Q0 Q1 Q2 Q3 HH LX LL LL HHXL LL LL HH LL LL X X HH HL LH LH Count L X LX HL Count X L XL Count LL Count L XXL Count X L LX Count H = HIGH Voltage Level Count L = LOW Voltage Level H = HIGH Voltage Level X = Don’t Care L = LOW Voltage Level X = Don’t Care LS90 LS92 LS93 BCD COUNT SEQUENCE TRUTH TABLE TRUTH TABLE OUTPUT OUTPUT OUTPUT Q0 Q1 Q2 Q3 COUNT Q0 Q1 Q2 Q3 COUNT COUNT Q0 Q1 Q2 Q3 0 LL LL 0 LL LL 0 LL LL 1 HL LL 1 HL LL 1 HL LL 2 LH LL 2 LH LL 2 LH LL 3 HH LL 3 HH L L 3 HH LL 4 LL HL 4 LL HL 4 LL HL 5 HL HL 5 HL HL 5 HL HL 6 LH HL 6 LL LH 6 LH HL 7 HH HL 7 HL LH 7 HH HL 8 LL LH 8 LH LH 8 LL LH 9 HL LH 9 HH LH 9 HL LH 10 L L H H 10 LH LH NOTE: Output Q0 is connected to Input 11 H L H H 11 HH LH CP1 for BCD count. 12 LL HH 13 HL HH NOTE: Output Q0 is connected to Input 14 LH HH CP1. 15 HH HH NOTE: Output Q0 is connected to Input CP1. FAST AND LS TTL DATA 5-92

SN54/74LS90 • SN54/74LS92 • SN54/74LS93 GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 4.5 5.0 5.5 V 74 4.75 5.0 5.25 TA Operating Ambient Temperature Range 54 – 55 25 125 °C 74 0 25 70 IOH Output Current — High 54, 74 – 0.4 mA IOL Output Current — Low 54 4.0 mA 74 8.0 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter Min Typ Max Unit Test Conditions VIH Input HIGH Voltage Guaranteed Input HIGH Voltage for 2.0 V All Inputs 54 0.7 Guaranteed Input LOW Voltage for VIL Input LOW Voltage 74 0.8 V All Inputs VIK Input Clamp Diode Voltage – 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA VOH Output HIGH Voltage 54 2.5 3.5 V VCC = MIN, IOH = MAX, VIN = VIH 74 2.7 3.5 V or VIL per Truth Table VOL Output LOW Voltage 54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN, 74 0.35 0.5 V IOL = 8.0 mA VIN = VIL or VIH per Truth Table IIH Input HIGH Current 20 µA VCC = MAX, VIN = 2.7 V 0.1 mA VCC = MAX, VIN = 7.0 V Input LOW Current – 0.4 MS, MR – 2.4 mA VCC = MAX, VIN = 0.4 V – 3.2 IIL CP0 CP1 (LS90, LS92) – 1.6 CP1 (LS93) IOS Short Circuit Current (Note 1) – 20 –100 mA VCC = MAX ICC Power Supply Current 15 mA VCC = MAX Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. FAST AND LS TTL DATA 5-93

SN54/74LS90 • SN54/74LS92 • SN54/74LS93 AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V, CL = 15 pF) Limits LS90 LS92 LS93 Symbol Parameter Min Typ Max Min Typ Max Min Typ Max Unit fMAX CP0 Input Clock Frequency 32 32 32 MHz CP1 Input Clock Frequency fMAX Propagation Delay, 16 16 16 MHz CP0 Input to Q0 Output tPLH 10 16 10 16 10 16 ns tPHL CP0 Input to Q3 Output 12 18 12 18 12 18 tPLH CP1 Input to Q1 Output 32 48 32 48 46 70 ns tPHL 34 50 34 50 46 70 tPLH 10 16 10 16 10 16 ns tPHL 14 21 14 21 14 21 tPLH CP1 Input to Q2 Output 21 32 10 16 21 32 ns tPHL 23 35 14 21 23 35 CP1 Input to Q3 Output 21 32 34 51 ns tPLH MS Input to Q0 and Q3 Outputs 21 32 23 35 34 51 ns tPHL MS Input to Q1 and Q2 Outputs 23 35 ns MR Input to Any Output 26 40 26 40 ns tPLH 20 30 tPHL 26 40 tPHL 26 40 AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V) Limits LS90 LS92 LS93 Symbol Parameter Min Max Min Max Min Max Unit tW CP0 Pulse Width 15 15 15 ns tW CP1 Pulse Width 30 30 30 ns tW MS Pulse Width 15 ns tW MR Pulse Width 15 15 15 ns trec Recovery Time MR to CP 25 25 25 ns RECOVERY TIME (trec) is defined as the minimum time required between the end of the reset pulse and the clock transition from HIGH-to-LOW in order to recognize and transfer HIGH data to the Q outputs AC WAVEFORMS *CP 1.3 V 1.3 V 1.3 V tW tPLH tPHL 1.3 V Q 1.3 V Figure 1 *The number of Clock Pulses required between the tPHL and tPLH measurements can be determined from the appropriate Truth Tables. MR & MS 1.3 V 1.3 V MS 1.3 V 1.3 V tW trec tW trec CP CP tPLH tPHL 1.3 V 1.3 V Q0 • Q3 Q 1.3 V (LS90) 1.3 V Figure 2 Figure 3 FAST AND LS TTL DATA 5-94

SN54/74LS95B 4-BIT SHIFT REGISTER 4-BIT SHIFT REGISTER LOW POWER SCHOTTKY The SN54/74LS95B is a 4-Bit Shift Register with serial and parallel synchronous operating modes. The serial shift right and parallel load are acti- J SUFFIX vated by separate clock inputs which are selected by a mode control input. CERAMIC The data is transferred from the serial or parallel D inputs to the Q outputs CASE 632-08 synchronous with the HIGH to LOW transition of the appropriate clock input. The LS95B is fabricated with the Schottky barrier diode process for high speed and is completely compatible with all Motorola TTL families. • Synchronous, Expandable Shift Right • Synchronous Shift Left Capability • Synchronous Parallel Load • Separate Shift and Load Clock Inputs • Input Clamp Diodes Limit High Speed Termination Effects CONNECTION DIAGRAM DIP (TOP VIEW) 14 1 VCC Q0 Q1 Q2 Q3 CP1 CP2 NOTE: 14 13 12 11 10 9 8 The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line 14 N SUFFIX Package. 1 PLASTIC CASE 646-06 VCC = PIN 14 GND = PIN 7 1234567 D SUFFIX DS P0 P1 P2 P3 S GND SOIC 14 CASE 751A-02 1 PIN NAMES LOADING (Note a) HIGH LOW ORDERING INFORMATION S Mode Control Input 0.5 U.L. 0.25 U.L. SN54LSXXJ Ceramic Serial Data Input 0.5 U.L. 0.25 U.L. SN74LSXXN Plastic DS Parallel Data Inputs 0.5 U.L. 0.25 U.L. SN74LSXXD SOIC P0 – P3 Serial Clock (Active LOW Going Edge) Input 0.5 U.L. 0.25 U.L. CP1 Parallel Clock (Active LOW Going Edge) Input 0.5 U.L. 0.25 U.L. CP2 Parallel Outputs (Note b) 10 U.L. 5 (2.5) U.L. Q0 – Q3 NOTES: a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) Temperature Ranges. GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 4.5 5.0 5.5 V 74 4.75 5.0 5.25 TA Operating Ambient Temperature Range 54 – 55 25 125 °C 74 0 25 70 IOH Output Current — High 54, 74 – 0.4 mA IOL Output Current — Low 54 4.0 mA 74 8.0 FAST AND LS TTL DATA 5-95

SN54 / 74LS95B 6 LOGIC DIAGRAM P2 P3 S P0 P1 4 5 1 23 DS 9 R RRR CP1 8 CP2 VCC = PIN 14 SQ SQ SQ SQ GND = PIN 7 13 12 11 10 = PIN NUMBERS Q0 Q1 Q2 Q3 FUNCTIONAL DESCRIPTION HIGH to LOW transition on enabled CP1 transfers the data from Serial input (DS) to Q0 and shifts the data in Q0 to Q1, Q1 The LS95B is a 4-Bit Shift Register with serial and parallel to Q2, and Q2 to Q3 respectively (right-shift). A left-shift is ac- complished by externally connecting Q3 to P2, Q2 to P1, and synchronous operating modes. It has a Serial (DS) and four Q1 to P0, and operating the LS95B in the parallel mode (S = Parallel (P0 – P3) Data inputs and four Parallel Data outputs HIGH). (Q0 – Q3). The serial or parallel mode of operation is controlled by a Mode Control input (S) and two Clock Inputs (CP1) and For normal operation, S should only change states when (CP2). The serial (right-shift) or parallel data transfers occur synchronous with the HIGH to LOW transition of the selected both Clock inputs are LOW. However, changing S from LOW clock input. to HIGH while CP2 is HIGH, or changing S from HIGH to LOW while CP1 is HIGH and CP2 is LOW will not cause any changes When the Mode Control input (S) is HIGH, CP2 is enabled. A on the register outputs. HIGH to LOW transition on enabled CP2 transfers parallel data from the P0 – P3 inputs to the Q0 – Q3 outputs. When the Mode Control input (S) is LOW, CP1 is enabled. A MODE SELECT — TRUTH TABLE INPUTS OUTPUTS OPERATING MODE S CP1 CP2 DS Pn Q0 Q1 Q2 Q3 Shift L X I X L q0 q1 q2 Parallel Load L X h X H q0 q1 q2 Mode Change HX X Pn P0 P1 P2 P3 L L XX No Change L L XX No Change H L XX No Change H L XX Undetermined L H XX Undetermined L H XX No Change H H XX Undetermined H H XX No Change L = LOW Voltage Level H = HIGH Voltage Level X = Don’t Care I = LOW Voltage Level one set-up time prior to the HIGH to LOW clock transition. h = HIGH Voltage Level one set-up time prior to the HIGH to LOW clock transition. Pn = Lower case letters indicate the state of the referenced input (or output) one set-up time prior to the Pn = HIGH to LOW clock transition. FAST AND LS TTL DATA 5-96

SN54 / 74LS95B DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter Min Typ Max Unit Test Conditions VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for All Inputs 54 0.7 Guaranteed Input LOW Voltage for VIL Input LOW Voltage 74 0.8 V All Inputs VIK Input Clamp Diode Voltage – 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA VOH Output HIGH Voltage 54 2.5 3.5 V VCC = MIN, IOH = MAX, VIN = VIH 74 2.7 3.5 V or VIL per Truth Table VOL Output LOW Voltage 54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN, 74 0.35 0.5 V IOL = 8.0 mA VIN = VIL or VIH per Truth Table IIH Input HIGH Current 20 µA VCC = MAX, VIN = 2.7 V 0.1 mA VCC = MAX, VIN = 7.0 V IIL Input HIGH Current – 0.4 mA VCC = MAX, VIN = 0.4 V IOS Short Circuit Current (Note 1) – 20 –100 mA VCC = MAX ICC Power Supply Current 21 mA VCC = MAX Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V) Symbol Parameter Limits Unit Test Conditions Maximum Clock Frequency Min Typ Max MHz fMAX 25 36 VCC = 5.0 V CP to Output ns CL = 15 pF tPLH 18 27 ns tPHL 21 32 AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V) Symbol Parameter Limits Unit Test Conditions CP Pulse Width Min Typ Max ns VCC = 5.0 V tW Data Setup Time 20 ns ts Data Hold Time 20 ns th Mode Control Setup Time 20 ns ts Mode Control Hold Time 20 ns th 20 FAST AND LS TTL DATA 5-97

SN54 / 74LS95B DESCRIPTION OF TERMS the clock transition from HIGH to LOW that the logic level must be maintained at the input in order to ensure continued recog- SETUP TIME(ts) —is defined as the minimum time required nition. A negative HOLD TIME indicates that the correct logic for the correct logic level to be present at the logic input prior to level may be released prior to the clock transition from HIGH to the clock transition from HIGH to LOW in order to be recog- LOW and still be recognized. nized and transferred to the outputs. HOLD TIME (th) — is defined as the minimum time following AC WAVEFORMS The shaded areas indicate when the input is permitted to change for predictable output performance. D 1.3 V 1.3 V 1.3 V 1.3 V CP1 or CP2 th(L) 1.3 V ts(H) th(H) Q ts(L) l/fmax *The Data Input is 1.3 V 1.3 V 1.3 V tW (DS for CP1) or (Pn for CP2). tPHL tPLH 1.3 V Figure 1 (H → L ONLY) (L → H ONLY) (L → H ONLY) S 1.3 V 1.3 V STABLE ts(H) ts(L) ts(H) ts(L) th(L OR H) th(L) CP1 1.3 V 1.3 V 1.3 V 1.3 V tW ts(L) ts(H) th(H) CP2 1.3 V 1.3 V 1.3 V 1.3 V tW Figure 2 FAST AND LS TTL DATA 5-98

DUAL JK NEGATIVE SN54/74LS107A EDGE-TRIGGERED FLIP-FLOP DUAL JK NEGATIVE The SN54 / 74LS107A is a Dual JK Flip-Flop with individual J, K, Direct EDGE-TRIGGERED FLIP-FLOP Clear and Clock Pulse inputs. Output changes are initiated by the HIGH-to-LOW transition of the clock. A LOW signal on CD input overrides the LOW POWER SCHOTTKY other inputs and makes the Q output LOW. The SN54 / 74LS107A is the same as the SN54 / 74LS73A but has corner power pins. CONNECTION DIAGRAM DIP (TOP VIEW) J SUFFIX CERAMIC VCC CD1 CP1 K2 CD2 CP2 J2 CASE 632-08 14 13 12 11 10 9 8 14 1 NOTE: N SUFFIX The Flatpak version has the PLASTIC same pinouts (Connection CASE 646-06 Diagram) as the Dual In-Line Package. 1234567 14 J1 Q1 Q1 K1 Q2 Q2 GND 1 LOGIC SYMBOL 2 14 D SUFFIX 1 1 SOIC CASE 751A-02 1J Q3 8J Q5 12 CP 9 CP ORDERING INFORMATION 4K Q2 11 KQ 6 SN54LSXXXJ Ceramic CD SN74LSXXXN Plastic SN74LSXXXD SOIC CD 13 10 VCC = PIN 14 GND = PIN 7 GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 4.5 5.0 5.5 V 74 4.75 5.0 5.25 TA Operating Ambient Temperature Range 54 – 55 25 125 °C 74 0 25 70 IOH Output Current — High 54, 74 – 0.4 mA IOL Output Current — Low 54 4.0 mA 74 8.0 FAST AND LS TTL DATA 5-99

SN54 / 74LS107A DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter Min Typ Max Unit Test Conditions VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for All Inputs VIL Input LOW Voltage 54 0.7 Guaranteed Input LOW Voltage for 74 0.8 V All Inputs VIK Input Clamp Diode Voltage – 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA VOH Output HIGH Voltage 54 2.5 3.5 V VCC = MIN, IOH = MAX, VIN = VIH 74 2.7 3.5 V or VIL per Truth Table VOL Output LOW Voltage 54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN, 74 0.35 0.5 V IOL = 8.0 mA VIN = VIL or VIH per Truth Table IIH Input HIGH Current J, K 20 Clear 60 µA VCC = MAX, VIN = 2.7 V Clock 80 J, K 0.1 Clear 0.3 mA VCC = MAX, VIN = 7.0 V Clock 0.4 IIL Input LOW Current J, K – 0.4 mA VCC = MAX, VIN = 0.4 V Clear and Clock – 0.8 IOS Short Circuit Current (Note 1) – 20 –100 mA VCC = MAX ICC Power Supply Current 6.0 mA VCC = MAX Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V) Symbol Parameter Limits Unit Test Conditions Maximum Clock Frequency Min Typ Max MHz fMAX 30 45 VCC = 5.0 V Propagation Delay, ns CL = 15 pF tPLH Clock to Output 15 20 ns tPHL 15 20 AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V) Symbol Parameter Limits Unit Test Conditions Clock Pulse Width Min Typ Max ns VCC = 5.0 V tW Clear Pulse Width 20 ns tW Setup Time 25 ns ts Hold Time 20 ns th 0 FAST AND LS TTL DATA 5-100

SN54/74LS109A DUAL JK POSITIVE DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS109A consists of two high speed completely independent LOW POWER SCHOTTKY transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop by simply connecting the J and K pins together. LOGIC DIAGRAM SET (SD) Q J SUFFIX 5(11) 6(10) CERAMIC CASE 620-09 CLEAR (CD) Q 1(15) 7(9) 16 CLOCK 1 4(12) N SUFFIX J PLASTIC 2(14) CASE 648-08 K 3(13) 16 1 16 D SUFFIX 1 SOIC CASE 751B-03 MODE SELECT — TRUTH TABLE OPERATING MODE INPUTS OUTPUTS ORDERING INFORMATION SD CD J KQQ SN54LSXXXJ Ceramic Set LHXXHL SN74LSXXXN Plastic Reset (Clear) SN74LSXXXD SOIC *Undetermined HLXXLH Load “1” (Set) Hold L L XXHH Toggle Load “0” (Reset) HHh hHL HH l h q q HHh l q q LOGIC SYMBOL HH l l LH * Both outputs will be HIGH while both SD and CD are LOW, but the output states 5 11 are unpredictable if SD and CD go HIGH simultaneously. 2 J SD Q 6 14 J SD Q 10 H, h = HIGH Voltage Level 9 L, I = LOW Voltage Level 4 CP 12 CP X = Don’t Care l, h (q) = Lower case letters indicate the state of the referenced input (or output) 3 K CD Q 7 13 K CD Q l, h (q) = one set-up time prior to the LOW to HIGH clock transition. 1 15 VCC = PIN 16 GND = PIN 8 FAST AND LS TTL DATA 5-101

SN54 / 74LS109A GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 4.5 5.0 5.5 V 74 4.75 5.0 5.25 TA Operating Ambient Temperature Range 54 – 55 25 125 °C 74 0 25 70 IOH Output Current — High 54, 74 – 0.4 mA IOL Output Current — Low 54 4.0 mA 74 8.0 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter Min Typ Max Unit Test Conditions VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for All Inputs VIL Input LOW Voltage 54 0.7 Guaranteed Input LOW Voltage for VIK Input Clamp Diode Voltage 74 0.8 V All Inputs VOH Output HIGH Voltage – 0.65 – 1.5 54 2.5 3.5 V VCC = MIN, IIN = – 18 mA 74 2.7 3.5 V VCC = MIN, IOH = MAX, VIN = VIH V or VIL per Truth Table VOL Output LOW Voltage 54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN, 74 0.35 0.5 V IOL = 8.0 mA VIN = VIL or VIH per Truth Table Input HIGH Current 20 µA VCC = MAX, VIN = 2.7 V J, K, Clock 40 mA VCC = MAX, VIN = 7.0 V IIH Set, Clear 0.1 J, K, Clock 0.2 Set, Clear Input LOW Current – 0.4 mA VCC = MAX, VIN = 0.4 V – 0.8 IIL J, K, Clock mA VCC = MAX Set, Clear mA VCC = MAX IOS Output Short Circuit Current (Note 1) – 20 – 100 ICC Power Supply Current 8.0 Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V) Limits Symbol Parameter Min Typ Max Unit Test Conditions MHz fMAX Maximum Clock Frequency 25 33 VCC = 5.0 V Clock, Clear, Set to Output 13 25 ns CL = 15 pF tPLH 25 40 ns tPHL AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V) Symbol Parameter Min Limits Max Unit Test Conditions tW Clock High Clear, Set Pulse Width 25 Typ ns VCC = 5.0 V ts Data Setup Time — HIGH 20 ns th Data Setup Time — LOW 20 ns 5.0 ns Hold time FAST AND LS TTL DATA 5-102

DUAL JK NEGATIVE SN54/74LS112A EDGE-TRIGGERED FLIP-FLOP DUAL JK NEGATIVE The SN54 / 74LS112A dual JK flip-flop features individual J, K, clock, and EDGE-TRIGGERED FLIP-FLOP asynchronous set and clear inputs to each flip-flop. When the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the LOW POWER SCHOTTKY J and K inputs may be allowed to change when the clock pulse is HIGH and the bistable will perform according to the truth table as long as minimum set-up and hold time are observed. Input data is transferred to the outputs on the negative-going edge of the clock pulse. LOGIC DIAGRAM (Each Flip-Flop) J SUFFIX CERAMIC CASE 620-09 16 1 Q Q 16 N SUFFIX 5(9) 6(7) 1 PLASTIC CASE 648-08 CLEAR (CD) SET (SD) 15(14) 4(10) J 3(11) K 2(12) 1(13) D SUFFIX CLOCK (CP) SOIC 16 CASE 751B-03 1 MODE SELECT — TRUTH TABLE ORDERING INFORMATION INPUTS OUTPUTS SN54LSXXXJ Ceramic SN74LSXXXN Plastic KQQ SN74LSXXXD SOIC OPERATING MODE SD CD J XHL LOGIC SYMBOL XLH Set LH X XHH 4 10 Reset (Clear) HL X hqq *Undetermined LL X h LH 3 J SD Q 5 11 J SD Q 9 Toggle HH h l HL Load “0” (Reset) HH l l qq 1 CP 13 CP Load “1” (Set) HH h 2 K CD Q 6 12 K CD Q Hold HH l * Both outputs will be HIGH while both SD and CD are LOW, but the output states 7 are unpredictable if SD and CD go HIGH simultaneously. 15 14 H, h = HIGH Voltage Level L, I = LOW Voltage Level VCC = PIN 16 X = Don’t Care GND = PIN 8 l, h (q) = Lower case letters indicate the state of the referenced input (or output) l, h (q) = one set-up time prior to the HIGH to LOW clock transition. FAST AND LS TTL DATA 5-103

SN54 / 74LS112A GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 4.5 5.0 5.5 V 74 4.75 5.0 5.25 TA Operating Ambient Temperature Range 54 – 55 25 125 °C 74 0 25 70 IOH Output Current — High 54, 74 – 0.4 mA IOL Output Current — Low 54 4.0 mA 74 8.0 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter Min Typ Max Unit Test Conditions VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for All Inputs VIL Input LOW Voltage 54 0.7 Guaranteed Input LOW Voltage for VIK 74 0.8 V All Inputs VOH VOL Input Clamp Diode Voltage – 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA IIH Output HIGH Voltage 54 2.5 3.5 V VCC = MIN, IOH = MAX, VIN = VIH 74 2.7 3.5 V or VIL per Truth Table IIL Output LOW Voltage 54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN, 74 0.35 0.5 VIN = VIL or VIH V IOL = 8.0 mA per Truth Table Input HIGH Current J, K 20 Set, Clear 60 µA VCC = MAX, VIN = 2.7 V Clock 80 J, K 0.1 Set, Clear 0.3 mA VCC = MAX, VIN = 7.0 V Clock 0.4 Input LOW Current J, K – 0.4 mA VCC = MAX, VIN = 0.4 V Clear, Set, Clk – 0.8 IOS Short Circuit Current (Note 1) – 20 – 100 mA VCC = MAX mA VCC = MAX ICC Power Supply Current 6.0 Unit Test Conditions Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. MHz VCC = 5.0 V CL = 15 pF AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V) ns ns Limits Symbol Parameter Min Typ Max fMAX Maximum Clock Frequency 30 45 15 20 tPLH Propagation Delay, Clock 15 20 tPHL Clear, Set to Output AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V) Symbol Parameter Min Limits Max Unit Test Conditions Clock Pulse Width High 20 Typ ns VCC = 5.0 V tW Clear, Set Pulse Width 25 ns tW Setup Time 20 ns ts Hold Time 0 ns th FAST AND LS TTL DATA 5-104

DUAL JK NEGATIVE SN54/74LS113A EDGE-TRIGGERED FLIP-FLOP DUAL JK NEGATIVE The SN54 / 74LS113A offers individual J, K, set, and clock inputs. These EDGE-TRIGGERED FLIP-FLOP monolithic dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K LOW POWER SCHOTTKY inputs may be allowed to change when the clock pulse is HIGH and the bistable will perform according to the truth table as long as minimum setup times are observed. Input data is transferred to the outputs on the negative-going edge of the clock pulse. LOGIC DIAGRAM (Each Flip-Flop) J SUFFIX CERAMIC CASE 632-08 14 1 Q Q 14 N SUFFIX 5(9) 6(8) 1 PLASTIC CASE 646-06 J SET (SD) 3(11) 4(10) K 2(12) 1(13) D SUFFIX CLOCK (CP) SOIC 14 CASE 751A-02 1 MODE SELECT — TRUTH TABLE ORDERING INFORMATION INPUTS OUTPUTS SN54LSXXXJ Ceramic QQ SN74LSXXXN Plastic OPERATING MODE SN74LSXXXD SOIC SD J K Set L XXH L LOGIC SYMBOL Toggle Hh h q q Load “0” (Reset) H l hLH 4 10 Load “1” (Set) Hh l HL Hold Hl l qq H, h = HIGH Voltage Level 3 J SD Q 5 11 J SD Q 9 L, I = LOW Voltage Level X = Don’t Care 1 CP 13 CP l, h (q) = Lower case letters indicate the state of the referenced input (or output) l, h (q) = one set-up time prior to the HIGH to LOW clock transition. 2K Q 6 12 K Q8 VCC = PIN 14 GND = PIN 7 FAST AND LS TTL DATA 5-105

SN54 / 74LS113A GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 4.5 5.0 5.5 V 74 4.75 5.0 5.25 TA Operating Ambient Temperature Range 54 – 55 25 125 °C 74 0 25 70 IOH Output Current — High 54, 74 – 0.4 mA IOL Output Current — Low 54 4.0 mA 74 8.0 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Symbol Parameter Limits Unit Test Conditions Min Typ Max VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for All Inputs VIL Input LOW Voltage 54 0.7 Guaranteed Input LOW Voltage for 0.8 V All Inputs 74 VIK Input Clamp Diode Voltage – 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA VOH Output HIGH Voltage 54 2.5 3.5 V VCC = MIN, IOH = MAX, VIN = VIH 74 2.7 3.5 V or VIL per Truth Table VOL Output LOW Voltage 54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN, 74 0.35 0.5 V IOL = 8.0 mA VIN = VIL or VIH per Truth Table J, K 20 60 µA VCC = MAX, VIN = 2.7 V Set 80 Clock 0.1 0.3 mA VCC = MAX, VIN = 7.0 V IIH Input HIGH Current J, K 0.4 Set Clock IIL Input LOW Current J, K – 0.4 mA VCC = MAX, VIN = 0.4 V Set, Clock – 0.8 IOS Short Circuit Current (Note 1) – 20 – 100 mA VCC = MAX ICC Power Supply Current 6.0 mA VCC = MAX Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V) Limits Symbol Parameter Min Typ Max Unit Test Conditions MHz fMAX Maximum Clock Frequency 30 45 VCC = 5.0 V 15 20 ns CL = 15 pF tPLH Propagation Delay, Clock 15 20 ns tPHL Set to Output AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V) Symbol Parameter Min Limits Max Unit Test Conditions Clock Pulse Width High 20 Typ ns VCC = 5.0 V tW Set Pulse Width 25 ns tW Setup Time 20 ns ts Hold Time 0 ns th FAST AND LS TTL DATA 5-106

DUAL JK NEGATIVE SN54/74LS114A EDGE-TRIGGERED FLIP-FLOP DUAL JK NEGATIVE The SN54 / 74LS114A offers common clock and common clear inputs and EDGE-TRIGGERED FLIP-FLOP individual J, K, and set inputs. These monolithic dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be LOW POWER SCHOTTKY accepted. The logic level of the J and K inputs may be allowed to change when the clock pulse is HIGH and the bistable will perform according to the truth table as long as minimum set-up times are observed. Input data is transferred to the outputs on the negative-going edge of the clock pulse. LOGIC DIAGRAM (Each Flip-Flop) Q Q 14 J SUFFIX 5(9) 6(8) 1 CERAMIC CASE 632-08 CLEAR (CD) 4(10) 14 TO SET (SD) 1 N SUFFIX OTHER K PLASTIC FLIP-FLOP J CASE 646-06 2(12) 3(11) 13 CLOCK (CP) 14 D SUFFIX 1 SOIC CASE 751A-02 MODE SELECT — TRUTH TABLE ORDERING INFORMATION INPUTS OUTPUTS SN54LSXXXJ Ceramic SN74LSXXXN Plastic OPERATING MODE SD CD J KQQ SN74LSXXXD SOIC Set LH X XHL LOGIC SYMBOL Reset (Clear) HL X XLH *Undetermined LL X XHH 4 10 Toggle HH h hqq Load “0” (Reset) HH l h LH J SD Q 11 SD Q Load “1” (Set) HH h l HL CP J Hold HH l l qq K CD Q * Both outputs will be HIGH while both SD and CD are LOW, but the output states 3 5 9 are unpredictable if SD and CD go HIGH simultaneously. 13 8 CP H, h = HIGH Voltage Level 2 6 12 K CD Q L, I = LOW Voltage Level X = Don’t Care 1 l, h (q) = Lower case letters indicate the state of the referenced input (or output) l, h (q) = one set-up time prior to the HIGH to LOW clock transition. VCC = PIN 14 GND = PIN 7 FAST AND LS TTL DATA 5-107

SN54 / 74LS114A GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 4.5 5.0 5.5 V 74 4.75 5.0 5.25 TA Operating Ambient Temperature Range 54 – 55 25 125 °C 74 0 25 70 IOH Output Current — High 54, 74 – 0.4 mA IOL Output Current — Low 54 4.0 mA 74 8.0 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Symbol Parameter Limits Unit Test Conditions VIH Input HIGH Voltage Min Typ Max V Guaranteed Input HIGH Voltage for 2.0 All Inputs VIL Input LOW Voltage 54 0.7 Guaranteed Input LOW Voltage for VIK 74 0.8 V All Inputs VOH VOL Input Clamp Diode Voltage – 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA IIH Output HIGH Voltage 54 2.5 3.5 V VCC = MIN, IOH = MAX, VIN = VIH 74 2.7 3.5 V or VIL per Truth Table Output LOW Voltage 54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN, 74 0.35 0.5 V IOL = 8.0 mA VIN = VIL or VIH per Truth Table J, K 20 Set Clear 60 µA VCC = MAX, VIN = 2.7 V Clock 120 J, K 160 Set Input HIGH Current Clear 0.1 Clock 0.3 mA VCC = MAX, VIN = 7.0 V 0.6 0.8 J, K – 0.4 IIL Input LOW Current Set – 0.8 mA VCC = MAX, VIN = 0.4 V Clear, Clock – 1.6 IOS Output Short Circuit Current (Note 1) – 20 – 100 mA VCC = MAX ICC Power Supply Current 6.0 mA VCC = MAX Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V) Limits Symbol Parameter Min Typ Max Unit Test Conditions MHz fMAX Maximum Clock Frequency 30 45 VCC = 5.0 V ns CL = 15 pF tPLH Propagation Delay, Clock, 15 20 ns tPHL Clear, Set to Output 15 20 AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V) Symbol Parameter Min Limits Max Unit Test Conditions Typ tW Clock Pulse Width High 20 ns tW Clear, Set Pulse Width 25 ns ts Setup Time 20 ns VCC = 5.0 V th Hold Time 0 ns FAST AND LS TTL DATA 5-108

SN54/74LS122 SN54/74LS123 RETRIGGERABLE MONOSTABLE RETRIGGERABLE MONOSTABLE MULTIVIBRATORS MULTIVIBRATORS These dc triggered multivibrators feature pulse width control by three meth- LOW POWER SCHOTTKY ods. The basic pulse width is programmed by selection of external resistance and capacitance values. The LS122 has an internal timing resistor that allows J SUFFIX the circuits to be used with only an external capacitor. Once triggered, the ba- CERAMIC sic pulse width may be extended by retriggering the gated low-level-active (A) CASE 620-09 or high-level-active (B) inputs, or be reduced by use of the overriding clear. N SUFFIX • Overriding Clear Terminates Output Pulse PLASTIC • Compensated for VCC and Temperature Variations CASE 648-08 • DC Triggered from Active-High or Active-Low Gated Logic Inputs • Retriggerable for Very Long Output Pulses, up to 100% Duty Cycle D SUFFIX • Internal Timing Resistors on LS122 SOIC SN54 / 74LS123 (TOP VIEW) 16 CASE 751B-03 (SEE NOTES 1 THRU 4) 1 J SUFFIX 1 Rext/ 1 2 16 CERAMIC 1 CASE 632-08 VCC Cext Cext 1Q 2Q CLR 2B 2A 9 16 16 15 14 13 12 11 10 1 Q CLR 14 CLR Q Q 1 Q 1 2 3 4 56 78 14 N SUFFIX 1A 1B 1 1Q 2Q 2 2 GND 1 PLASTIC CASE 646-06 CLR Cext Rext/ 14 Cext 1 D SUFFIX SOIC SN54 / 74LS122 (TOP VIEW) (SEE NOTES 1 THRU 4) CASE 751A-02 Rext/ VCC Cext NC Cext NC Rint Q 14 13 12 11 10 9 8 Rint Q CLR Q 123 4567 A1 A2 B1 B2 CLR Q GND NC — NO INTERNAL CONNECTION. NOTES: ORDERING INFORMATION 1. An external timing capacitor may be connected between Cext and Rext/Cext (positive). SN54LSXXXJ Ceramic 2. To use the internal timing resistor of the LS122, connect Rint to VCC. SN74LSXXXN Plastic 3. For improved pulse width accuracy connect an external resistor between Rext/Cext and SN74LSXXXD SOIC VCC with Rint open-circuited. 4. To obtain variable pulse widths, connect an external variable resistance between Rint/Cext and VCC. FAST AND LS TTL DATA 5-109

SN54/74LS122 • SN54/74LS123 LS122 LS123 FUNCTIONAL TABLE FUNCTIONAL TABLE INPUTS OUTPUTS INPUTS OUTPUTS CLEAR A1 A2 B1 B2 QQ CLEAR A B Q Q L XXXX LH L X X LH X HHXX LH X H X LH X XXLX LH X X L LH X XXXL LH H L↑ H L X ↑H H ↓H H L XH↑ ↑ LH H XL ↑H H X L H↑ H H ↓ HH H ↓ ↓HH H ↓ HHH ↑ L XHH ↑ X L HH TYPICAL APPLICATION DATA separate power supplies are used for VCC and VRC. If VCC is tied to VRC, Figure 7 shows how K will vary with VCC and The output pulse tW is a function of the external compo- temperature. Remember, the changes in Rext and Cext with nents, Cext and Rext or Cext and Rint on the LS122. For values temperature are not calculated and included in the graph. of Cext ≥ 1000 pF, the output pulse at VCC = 5.0 V and VRC = 5.0 V (see Figures 1, 2, and 3) is given by As long as Cext ≥ 1000 pF and 5K ≤ Rext ≤ 260K (SN74LS122 / 123) or 5K ≤ Rext ≤ 160 K (SN54LS122 / 123), tW = K Rext Cext where K is nominally 0.45 the change in K with respect to Rext is negligible. If Cext is on pF and Rext is in kΩ then tW is in nanoseconds. If Cext ≤ 1000 pF the graph shown on Figure 8 can be used The Cext terminal of the LS122 and LS123 is an internal to determine the output pulse width. Figure 9 shows how K will connection to ground, however for the best system perfor- change for Cext ≤ 1000 pF if VCC and VRC are connected to the mance Cext should be hard-wired to ground. same power supply. The pulse width tW in nanoseconds is Care should be taken to keep Rext and Cext as close to the approximated by monostable as possible with a minimum amount of inductance tW = 6 + 0.05 Cext (pF) + 0.45 Rext (kΩ) Cext + 11.6 Rext between the Rext/Cext junction and the Rext/Cext pin. Good In order to trim the output pulse width, it is necessary to groundplane and adequate bypassing should be designed include a variable resistor between VCC and the Rext/Cext pin into the system for optimum performance to insure that no or between VCC and the Rext pin of the LS122. Figure 10, 11, and 12 show how this can be done. Rext remote should be kept false triggering occurs. as close to the monostable as possible. It should be noted that the Cext pin is internally connected Retriggering of the part, as shown in Figure 3, must not to ground on the LS122 and LS123, but not on the LS221. occur before Cext is discharged or the retrigger pulse will not Therefore, if Cext is hard-wired externally to ground, substitu- have any effect. The discharge time of Cext in nanoseconds is tion of a LS221 onto a LS123 socket will cause the LS221 to guaranteed to be less than 0.22 Cext (pF) and is typically 0.05 Cext (pF). become non-functional. For the smallest possible deviation in output pulse widths The switching diode is not needed for electrolytic capaci- from various devices, it is suggested that Cext be kept tance application and should not be used on the LS122 and ≥ 1000 pF. LS123. To find the value of K for Cext ≥ 1000 pF, refer to Figure 4. Variations on VCC or VRC can cause the value of K to change, as can the temperature of the LS123, LS122. Figures 5 and 6 show the behavior of the circuit shown in Figures 1 and 2 if FAST AND LS TTL DATA 5-110

SN54/74LS122 • SN54/74LS123 GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit 4.5 V VCC Supply Voltage 54 4.75 5.0 5.5 °C 74 – 55 5.0 5.25 mA TA Operating Ambient Temperature Range 0 mA 54 25 125 kΩ IOH Output Current — High 74 5.0 25 70 IOL Output Current — Low 5.0 pF 54, 74 – 0.4 Rext External Timing Resistance 54 4.0 Cext External Capacitance 74 8.0 Rext / Cext Wiring Capacitance at Rext / Cext Terminal 54 180 74 260 54, 74 No Restriction 54, 74 50 WAVEFORMS RETRIGGER PULSE (See Application Data) B INPUT Q OUTPUT tW OUTPUT WITHOUT RETRIGGER EXTENDING PULSE WIDTH B INPUT CLEAR INPUT CLEAR PULSE Q OUTPUT OUTPUT WITHOUT CLEAR PULSE OVERRIDING THE OUTPUT PULSE FAST AND LS TTL DATA 5-111

SN54/74LS122 • SN54/74LS123 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter Min Typ Max Unit Test Conditions VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for All Inputs VIL Input LOW Voltage 54 0.7 Guaranteed Input LOW Voltage for 74 0.8 V All Inputs VIK Input Clamp Diode Voltage – 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA VOH Output HIGH Voltage 54 2.5 3.5 V VCC = MIN, IOH = MAX, VIN = VIH 74 V or VIL per Truth Table 2.7 3.5 VOL Output LOW Voltage 54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN, 74 0.35 0.5 VIN = VIL or VIH V IOL = 8.0 mA per Truth Table IIH Input HIGH Current 20 µA VCC = MAX, VIN = 2.7 V 0.1 mA VCC = MAX, VIN = 7.0 V mA VCC = MAX, VIN = 0.4 V IIL Input LOW Current – 0.4 mA VCC = MAX –100 IOS Short Circuit Current (Note 1) – 20 mA VCC = MAX 11 ICC Power Supply Current LS122 20 LS123 Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V) Symbol Parameter Min Limits Max Unit Test Conditions 4.0 Typ 33 tPLH Propagation Delay, A to Q 23 45 ns tPHL Propagation Delay, A to Q 32 44 Cext = 0 23 56 CL = 15 pF tPLH Propagation Delay, B to Q 34 45 tPHL Propagation Delay, B to Q 28 27 ns 20 200 Rext = 5.0 kΩ tPLH Propagation Delay, Clear to Q 116 5.0 RL = 2.0 kΩ tPHL Propagation Delay, Clear to Q 4.5 ns tW min A or B to Q tWQ A to B to Q ns Cext = 1000 pF, Rext = 10 kΩ, µs CL = 15 pF, RL = 2.0 kΩ AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V) Symbol Parameter Min Limits Max Unit Test Conditions tW Pulse Width 40 Typ ns FAST AND LS TTL DATA 5-112

SN54/74LS122 • SN54/74LS123 VCC VRC VCC VCC VRC VCC Rext Rext Cext 0.1 µF Cext VCC 0.1 µF Pout Cext Rext/ Q Pout Cext Rext/ VCC CLR Cext Cext Q B2 B1 LS122 CLR B 1/2 LS123 A2 Pin Q Pin A1 GND Q A GND 51 Ω 51 Ω Figure 1 Figure 2 Pin Pout tW EXTERNAL CAPACITANCE, Cext ( µF) RETRIGGER Figure 3 10 5K ≤ Rext ≤ 260K 1 0.1 0.01 0.001 0.3 0.35 0.4 0.45 0.5 0.55 K Figure 4 FAST AND LS TTL DATA 5-113

SN54/74LS122 • SN54/74LS123 0.55 0.55 0.55 VRC = 5 V VCC = 5 V Cext = 1000 pF Cext = 1000 pF Cext = 1000 pF 0.5 0.5 0.5 – 55°C 0°C – 55°C K 0°C K – 55°C 25°C K 70°C 0.45 0°C 125°C 25°C 25°C 70°C 0.45 0.45 0.4 70°C 125°C 125°C 0.4 0.4 0.35 5 5.5 0.35 5 5.5 0.35 5 5.5 4.5 VCC 4.5 VRC 4.5 VCC = VRC Figure 5. K versus VCC Figure 6. K versus VRC Figure 7. K versus VCC and VRC 100000 10000 Rext = 260 kΩ Rext = 160 kΩ t W, OUTPUT PULSE WIDTH (ns) 1000 100 Rext = 80 kΩ 1000 10 Rext = 40 kΩ Rext = 20 kΩ 1 Rext = 10 kΩ Rext = 5 kΩ 10 100 Cext, EXTERNAL TIMING CAPACITANCE (pF) Figure 8 FAST AND LS TTL DATA 5-114

SN54/74LS122 • SN54/74LS123 0.65 Cext = 200 pF 0.6 K 0.55 – 55°C 0.5 0°C 25°C 70°C 125°C 4.5 4.75 5 5.25 5.5 VCC VOLTS Figure 9 Rext VCC Cext Rext REMOTE PIN 7 OR 15 PIN 6 OR 14 Figure 10. LS123 Remote Trimming Circuit FAST AND LS TTL DATA 5-115

SN54/74LS122 • SN54/74LS123 PIN 9 OPEN VCC PIN 13 Rext Rext PIN 11 Cext REMOTE Figure 11. LS122 Remote Trimming Circuit Without Rext PIN 9 VCC PIN 13 Rext PIN 11 REMOTE Figure 12. LS122 Remote Trimming Circuit with Rint FAST AND LS TTL DATA 5-116

QUAD 3-STATE BUFFERS SN54/74LS125A SN54/74LS126A VCC E D O E D O 14 13 12 11 10 9 8 QUAD 3-STATE BUFFERS LOW POWER SCHOTTKY 1234567 J SUFFIX E D O E D O GND CERAMIC CASE 632-08 LS125A 14 VCC E D O E D O 1 14 13 12 11 10 9 8 1234567 14 N SUFFIX E D O E D O GND 1 PLASTIC CASE 646-06 LS126A 14 1 D SUFFIX SOIC CASE 751A-02 LS125A TRUTH TABLES LS126A INPUTS INPUTS ORDERING INFORMATION ED OUTPUT ED OUTPUT SN54LSXXXJ Ceramic SN74LSXXXN Plastic LL L HL L SN74LSXXXD SOIC LH H HH H HX (Z) LX (Z) L = LOW Voltage Level H = HIGH Voltage Level X = Don’t Care (Z) = High Impedance (off) GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 4.5 5.0 5.5 V 74 4.75 5.0 5.25 TA Operating Ambient Temperature Range 54 – 55 25 125 °C 74 0 25 70 IOH Output Current — High 54 – 1.0 mA 74 – 2.6 IOL Output Current — Low 54 12 mA 74 24 FAST AND LS TTL DATA 5-117

SN54/74LS125A • SN54/74LS126A DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter Min Typ Max Unit Test Conditions VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for All Inputs VIL Input LOW Voltage 54 0.7 Guaranteed Input LOW Voltage for 74 0.8 V All Inputs VIK Input Clamp Diode Voltage – 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA VOH Output HIGH Voltage 54 2.4 V VCC = MIN, IOH = MAX, VIN = VIH 74 V or VIL per Truth Table 2.4 VOL Output LOW Voltage 54, 74 0.25 0.4 V IOL = 12 mA VCC = VCC MIN, 74 0.35 0.5 VIN = VIL or VIH V IOL = 24 mA per Truth Table IOZH Output Off Current HIGH 20 µA VCC = MAX, VOUT = 2.4 V IOZL Output Off Current LOW – 20 µA VCC = MAX, VOUT = 0.4 V 20 µA VCC = MAX, VIN = 2.7 V IIH Input HIGH Current 0.1 mA VCC = MAX, VIN = 7.0 V mA VCC = MAX, VIN = 0.4 V IIL Input LOW Current – 0.4 mA VCC = MAX –225 IOS Short Circuit Current (Note 1) – 40 VIN = 0 V, VE = 4.5 V 20 mA VCC = MAX LS125A 22 ICC Power Supply Current VIN = 0 V, VE = 0 V LS126A Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C) Symbol Parameter Min Limits Max Unit Test Conditions tPLH Typ 15 tPLH Propagation Delay, LS125A 9.0 15 ns Figure 2 VCC = 5.0 V tPHL Data to Output LS126A 9.0 18 CL = 45 pF tPHL LS125A 7.0 18 ns Figures 4, 5 RL = 667 Ω Output Enable Time LS126A 8.0 20 ns Figures 3, 5 tPZH to HIGH Level LS125A 12 25 ns Figures 4, 5 VCC = 5.0 V LS126A 16 25 ns FIgures 3, 5 CL = 5.0 pF tPZL Output Enable Time LS125A 15 35 RL = 667 Ω to LOW Level LS126A 21 20 LS125A 25 tPHZ Output Disable Time LS126A 20 from HIGH Level LS125A 25 LS126A tPLZ Output Disable Time from LOW Level FAST AND LS TTL DATA 5-118

SN54/74LS125A • SN54/74LS126A VIN 1.3 V 1.3 V VIN 1.3 V 1.3 V VOUT tPLH tPHL VOUT tPHL tPLH 1.3 V 1.3 V 1.3 V 1.3 V Figure 1 Figure 2 VE 1.3 V 1.3 V VE 1.3 V 1.3 V VE tPZL VE tPZH VOUT 1.3 V tPLZ 1.3 V tPHZ VOUT > VOH ≈ 1.3 V ≈ 1.3 V VOL 0.5 V 0.5 V Figure 3 Figure 4 TO OUTPUT VCC UNDER TEST RL SW1 5 kΩ CL SW2 Figure 5 SWITCH POSITIONS SYMBOL SW1 SW2 tPZH Open Closed tPZL Closed Open tPLZ Closed Closed tPHZ Closed Closed FAST AND LS TTL DATA 5-119

SN54/74LS132 QUAD 2-INPUT QUAD 2-INPUT SCHMITT TRIGGER NAND GATE SCHMITT TRIGGER NAND GATE The SN54 / 74LS132 contains four 2-Input NAND Gates which accept stan- LOW POWER SCHOTTKY dard TTL input signals and provide standard TTL output levels. They are ca- pable of transforming slowly changing input signals into sharply defined, jitter- J SUFFIX free output signals. Additionally, they have greater noise margin than CERAMIC conventional NAND Gates. CASE 632-08 Each circuit contains a 2-input Schmitt trigger followed by a Darlington level 14 shifter and a phase splitter driving a TTL totem pole output. The Schmitt trigger 1 uses positive feedback to effectively speed-up slow input transitions, and provide different input threshold voltages for positive and negative-going tran- 14 N SUFFIX sitions. This hysteresis between the positive-going and negative-going input 1 PLASTIC thresholds (typically 800 mV) is determined internally by resistor ratios and is CASE 646-06 essentially insensitive to temperature and supply voltage variations. As long as one input remains at a more positive voltage than VT+ (MAX), the gate will 14 D SUFFIX respond to the transitions of the other input as shown in Figure 1. 1 SOIC LOGIC AND CONNECTION DIAGRAM CASE 751A-02 DIP (TOP VIEW) VCC 14 13 12 11 10 9 8 1234567 GND ORDERING INFORMATION SN54LSXXXJ Ceramic SN74LSXXXN Plastic SN74LSXXXD SOIC VO, OUTPUT VOLTAGE (VOLTS) 5 VCC = 5 V TA = 25°C 4 3 2 1 0 0.95 1.2 1.8 2 0 0.4 VIN, INPUT VOLTAGE (VOLTS) Figure 1. VIN versus VOUT Transfer Function FAST AND LS TTL DATA 5-120

SN54 / 74LS132 GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 4.5 5.0 5.5 V 74 4.75 5.0 5.25 TA Operating Ambient Temperature Range 54 – 55 25 125 °C 74 0 25 70 IOH Output Current — High 54, 74 – 0.4 mA IOL Output Current — Low 54 4.0 mA 74 8.0 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter Min Typ Max Unit Test Conditions VT+ Positive-Going Threshold Voltage 1.5 2.0 V VCC = 5.0 V V VCC = 5.0 V VT– Negative-Going Threshold Voltage 0.6 1.1 V VCC = 5.0 V V VCC = MIN, IIN = – 18 mA VT + – VT– Hysteresis 0.4 0.8 V VCC = MIN, IOH = – 400 µA, VIN = VIL VIK Input Clamp Diode Voltage – 0.65 – 1.5 VOH Output HIGH Voltage 54 2.5 3.4 74 2.7 3.4 VOL Output LOW Voltage 54, 74 0.25 0.4 V VCC = MIN, IOL = 4.0 mA, VIN = 2.0 V IT+ 74 0.35 0.5 V VCC = MIN, IOL = 8.0 mA, VIN = 2.0 V Input Current at Positive-Going – 0.14 mA VCC = 5.0 V, VIN = VT+ Threshold IT– Input Current at Negative-Going – 0.18 mA VCC = 5.0 V, VIN = VT– Threshold IIH Input HIGH Current 20 µA VCC = MAX, VIN = 2.7 V 0.1 mA VCC = MAX, VIN = 7.0 V mA VCC = MAX, VIN = 0.4 V IIL Input LOW Current – 0.4 mA VCC = MAX, VOUT = 0 V IOS Output Short Circuit Current (Note 1) – 20 –100 mA VCC = MAX, VIN = 0 V mA VCC = MAX, VIN = 4.5 V Power Supply Current 5.9 11 ICC Total, Output HIGH 8.2 14 Total, Output LOW Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C) Limits Symbol Parameter Min Typ Max Unit Test Conditions tPLH Turn-Off Delay, Input to Output 22 ns VCC = 5.0 V tPHL Turn-On Delay, Input to Output 22 ns CL = 15 pF 3V 1.6 V 0.8 V tPHL tPLH VIN 0V VOUT 1.3 V 1.3 V Figure 2. AC Waveforms FAST AND LS TTL DATA 5-121

SN54 / 74LS132 VT , THRESHOLD VOLTAGE (VOLTS) 2 TA = 25°C ∆ VT, HYSTERESIS (VOLTS) 1.6 VT+ 1.2 VT– 0.8 ∆ VT 0.4 0 5.25 5.5 4.5 4.75 5 VCC, POWER SUPPLY VOLTAGE (VOLTS) Figure 3. Threshold Voltage and Hysteresis versus Power Supply Voltage 1.9 VT , THRESHOLD VOLTAGE (VOLTS) 1.7 VT+ ∆ VT, HYSTERESIS (VOLTS) 1.5 1.3 1.1 0.9 VT– 0.7 ∆ VT 75° 125° – 55° 0° 25° TA, AMBIENT TEMPERATURE (°C) Figure 4. Threshold Voltage and Hysteresis versus Temperature FAST AND LS TTL DATA 5-122

SN54/74LS133 13-INPUT NAND GATE VCC 13-INPUT NAND GATE 16 15 14 13 12 11 10 9 LOW POWER SCHOTTKY 1 2 3 4 56 78 J SUFFIX GND CERAMIC CASE 620-09 16 1 16 N SUFFIX 1 PLASTIC CASE 648-08 16 D SUFFIX 1 SOIC CASE 751B-03 ORDERING INFORMATION SN54LSXXXJ Ceramic SN74LSXXXN Plastic SN74LSXXXD SOIC GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 4.5 5.0 5.5 V 74 4.75 5.0 5.25 TA Operating Ambient Temperature Range 54 – 55 25 125 °C 74 0 25 70 IOH Output Current — High 54, 74 – 0.4 mA IOL Output Current — Low 54 4.0 mA 74 8.0 FAST AND LS TTL DATA 5-123

SN54 / 74LS133 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Symbol Parameter Limits Unit Test Conditions Min Typ Max VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for All Inputs 54 0.7 Guaranteed Input LOW Voltage for VIL Input LOW Voltage 0.8 V All Inputs 74 VIK Input Clamp Diode Voltage 54 – 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA VOH Output HIGH Voltage 74 2.5 3.5 2.7 3.5 V VCC = MIN, IOH = MAX, VIN = VIH V or VIL per Truth Table VOL Output LOW Voltage 54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN, 74 0.35 0.5 V IOL = 8.0 mA VIN = VIL or VIH IIH per Truth Table IIL IOS Input HIGH Current 20 µA VCC = MAX, VIN = 2.7 V 0.1 mA VCC = MAX, VIN = 7.0 V Input LOW Current – 0.4 mA VCC = MAX, VIN = 0.4 V Short Circuit Current (Note 1) – 20 –100 mA VCC = MAX Power Supply Current 0.5 mA VCC = MAX ICC Total, Output HIGH 1.1 Total, Output LOW Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C) Symbol Parameter Limits Unit Test Conditions tPLH Turn-Off Delay, Input to Output Min Typ Max ns tPHL Turn-On Delay, Input to Output ns VCC = 5.0 V 10 15 CL = 15 pF 40 59 FAST AND LS TTL DATA 5-124

SN74LS136 QUAD 2-INPUT EXCLUSIVE OR GATE QUAD 2-INPUT EXCLUSIVE OR GATE LOW POWER SCHOTTKY VCC 98 14 13 12 11 10 * * ** J SUFFIX CERAMIC 1234567 CASE 632-08 GND 14 * OPEN COLLECTOR OUTPUTS 1 14 N SUFFIX 1 PLASTIC CASE 646-06 TRUTH TABLE IN OUT AB Z LL L 14 D SUFFIX LH H 1 SOIC HL H HH L CASE 751A-02 ORDERING INFORMATION SN54LSXXXJ Ceramic SN74LSXXXN Plastic SN74LSXXXD SOIC GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 4.75 5.0 5.25 V TA Operating Ambient Temperature Range VOH Output Voltage — High 0 25 70 °C IOL Output Current — Low 5.5 V 8.0 mA FAST AND LS TTL DATA 5-125

SN74LS136 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter Min Typ Max Unit Test Conditions VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for All Inputs VIL Input LOW Voltage 0.8 V Guaranteed Input LOW Voltage for All Inputs VIK Input Clamp Diode Voltage – 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA IOH Output HIGH Current 100 µA VCC = MIN, VOH = MAX VOL Output LOW Voltage 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN, 0.35 0.5 V IOL = 8.0 mA VIN = VIL or VIH per Truth Table IIH Input HIGH Current 40 µA VCC = MAX, VIN = 2.7 V 0.2 mA VCC = MAX, VIN = 7.0 V IIL Input LOW Current – 0.8 mA VCC = MAX, VIN = 0.4 V ICC Power Supply Current 10 mA VCC = MAX AC CHARACTERISTICS (TA = 25°C) Symbol Parameter Limits Unit Test Conditions ns tPLH Propagation Delay, Min Typ Max ns VCC = 5.0 V tPHL Other Input LOW CL = 15 pF, RL = 2.0 kΩ 18 30 tPLH Propagation Delay, 18 30 tPHL Other Input HIGH 18 30 18 30 FAST AND LS TTL DATA 5-126

SN54/74LS137 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES DATA OUTPUTS 3-LINE TO 8-LINE DECODERS/ DEMULTIPLEXERS VCC Y0 Y1 Y2 Y3 Y4 Y5 Y6 16 15 14 13 12 11 10 9 WITH ADDRESS LATCHES Y0 Y1 Y2 Y3 Y4 Y5 LOW POWER SCHOTTKY A Y6 16 J SUFFIX B C GL G2 G1 Y7 1 CERAMIC CASE 620-09 123 4 56 78 16 A BC 1 N SUFFIX GL G2 G1 Y7 GND PLASTIC SELECT ENABLE OUTPUT CASE 648-08 16 D SUFFIX 1 SOIC CASE 751B-03 ORDERING INFORMATION SN54LSXXXJ Ceramic SN74LSXXXN Plastic SN74LSXXXD SOIC GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 4.5 5.0 5.5 V 74 4.75 5.0 5.25 TA Operating Ambient Temperature Range 54 – 55 25 125 °C 74 0 25 70 IOH Output Current — High 54, 74 – 0.4 mA IOL Output Current — Low 54 4.0 mA 74 8.0 FAST AND LS TTL DATA 5-127

SN54 / 74LS137 FUNCTION TABLE INPUTS OUTPUTS ENABLE SELECT GL G1 G2 C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 X X HXXXH H H H H H H H X L XXXXH H H H H H H H L H LLLL L HHHHHH H L H L LLHH L H H H H H H L H L LHL H H L H H H H H L H L LHH H H H L H H H H L H LHLL H H H H L H H H L H LHLHH H H H H L H H L H L HHL H H H H H H L H L H L HHH H H H H H H H L H H L XXX Output corresponding to stored address, L; all others, H H = high level, L = low level, X = irrelevant A (1) (15) Y0 (14) Y1 SELECT (2) (13) INPUTS B Y2 (12) DATA Y3 OUTPUTS (3) (11) C Y4 (10) Y5 (4) (9) GL Y6 ENABLE (5) (7) INPUTS G2 Y7 (6) G1 FAST AND LS TTL DATA 5-128