TTL_Databook

SN54/74LS168 • SN54/74LS169 SN54/ 74LS168 STATE DIAGRAMS SN54 / 74LS169 4 UP / DOWN DECADE COUNTER 0 123 01234 15 5 15 5 14 6 Count Up 14 6 Count Down 13 7 13 7 12 11 10 9 8 12 11 10 9 8 SN54 / 74LS168 SN54 / 74LS169 UP: TC = Q0 ⋅ Q3 ⋅ (U / D) UP: TC = Q0 ⋅ Q1 ⋅ Q2 ⋅ Q3 ⋅ (U / D) DOWN: TC = Q0 ⋅ Q1 ⋅ Q2 ⋅ Q3 ⋅ (U / D) DOWN: TC = Q0 ⋅ Q1 ⋅ Q2 ⋅ Q3 ⋅ (U / D) P0 LOGIC DIAGRAMS P3 PE SN54 / 74LS168 CEP P1 P2 CET U/D TC CP Q1 Q2 Q3 CP D FAST AND LS TTL DATA Q0 5-179

P0 SN54/74LS168 • SN54/74LS169 P3 PE LOGIC DIAGRAMS (continued) CEP SN54 / 74LS169 CET U/D P1 P2 TC CP Q1 Q2 Q3 CP D Q0 GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 4.5 5.0 5.5 V 74 4.75 5.0 5.25 TA Operating Ambient Temperature Range 54 – 55 25 125 °C 74 0 25 70 IOH Output Current — High 54, 74 – 0.4 mA IOL Output Current — Low 54 4.0 mA 74 8.0 FAST AND LS TTL DATA 5-180

SN54/74LS168 • SN54/74LS169 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter Min Typ Max Unit Test Conditions VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for All Inputs 54 0.7 Guaranteed Input LOW Voltage for VIL Input LOW Voltage 0.8 V All Inputs 74 VIK Input Clamp Diode Voltage – 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA VOH Output HIGH Voltage 54 2.5 3.5 V VCC = MIN, IOH = MAX, VIN = VIH 74 2.7 3.5 V or VIL per Truth Table VOL Output LOW Voltage 54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN, 74 0.35 0.5 V IOL = 8.0 mA VIN = VIL or VIH per Truth Table Input HIGH Current 20 µA VCC = MAX, VIN = 2.7 V Other Inputs 40 IIH CET Input 0.1 mA VCC = MAX, VIN = 7.0 V Other Input 0.2 CET Input Input LOW Current – 0.4 mA VCC = MAX, VIN = 0.4 V – 0.8 IIL Other Input CET Input IOS Short Circuit Current (Note 1) – 20 – 100 mA VCC = MAX ICC Power Supply Current 34 mA VCC = MAX Note 1: Not more than one output should be shorted at one time, nor for more than 1 second. FUNCTIONAL DESCRIPTION The Terminal Count (TC) output is normally HIGH and goes LOW, provided that CET is LOW, when a counter reaches zero The SN54/74LS168 and SN54/74LS169 use edge- in the COUNT DOWN mode or reaches 15 (9 for the triggered D-type flip-flops that have no constraints on SN54/74LS168) in the COUNT UP mode. The TC output state changing the control or data input signals in either state of the is not a function of the Count Enable Parallel (CEP) input level. Clock. The only requirement is that the various inputs attain The TC output of the SN54/74LS168 decade counter can also the desired state at least a set-up time before the rising edge of be LOW in the illegal states 11, 13 and 15, which can occur the clock and remain valid for the recommended hold time when power is turned on or via parallel loading. If illegal state thereafter. occurs, the SN54/74LS168 will return to the legitimate sequence within two counts. Since the TC signal is derived by The parallel load operation takes precedence over the other decoding the flip-flop states, there exists the possibility of operations, as indicated in the Mode Select Table. When PE is decoding spikes on TC. For this reason the use of TC as a LOW, the data on the P0 – P3 inputs enters the flip-flops on the clock signal is not recommended. next rising edge of the Clock. In order for counting to occur, both CEP and CET must be LOW and PE must be HIGH. The U/D input then determines the direction of counting. MODE SELECT TABLE PE CEP CET U/D Action on Rising Clock Edge L X X X Load (Pn → Qn) H L L H Count Up (increment) H L L L Count Down (decrement) H H X X No Change (Hold) H X H X No Change (Hold) H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial FAST AND LS TTL DATA 5-181

SN54/74LS168 • SN54/74LS169 AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V) Limits Symbol Parameter Min Typ Max Unit Test Conditions MHz VCC = 5.0 V fMAX Maximum Clock Frequency 25 32 CL = 15 pF ns tPLH Propagation Delay, 23 35 ns Test Conditions tPHL Clock to TC 23 35 ns VCC = 5.0 V ns tPLH Propagation Delay, 13 20 tPHL Clock to any Q 15 23 Unit ns tPLH Propagation Delay, 15 20 ns tPHL CET to TC 15 20 ns ns tPLH Propagation Delay, 17 25 ns tPHL U / D to TC 19 29 AC SETUP REQUIREMENTS (TA = 25°C) Symbol Parameter Limits tW Min Typ Max ts Clock Pulse Width 25 20 ts Setup Time, Data or Enable 25 ts Setup Time 30 th PE 0 Setup Time U/D Hold Time Any Input FAST AND LS TTL DATA 5-182

SN54/74LS168 • SN54/74LS169 AC WAVEFORMS CP 1.3 V 1/fmax 1.3 V CET 1.3 V 1.3 V Q OR TC tW 1.3 V TC tPLH tPHL 1.3 V 1.3 V 1.3 V tPHL tPLH 1.3 V Figure 1. Clock to Output Delays, Figure 2. Count Enable Trickle Input Count Frequency, and Clock Pulse Width To Terminal Count Output Delays CP 1.3 V 1.3 V ts(H) th(H) = 0 ts(L) th(L) = 0 CP 1.3 V 1.3 V 1.3 V P0 • P1 • P2 • P3 1.3 V 1.3 V 1.3 V 1.3 V tPLH tPHL TC 1.3 V 1.3 V Q0 • Q1 • Q2 • Q3 Figure 3. Clock to Terminal Delays Figure 4. Setup Time (ts) and Hold (th) for Parallel Data Inputs CP 1.3 V ts(H) 1.3 V ts(L) 1.3 V th(L) = 0 th(H) = 0 SR OR PE 1.3 V 1.3 V 1.3 V CP 1.3 V 1.3 V 1.3 V U/D 1.3 V 1.3 V ts(H) th(H) = 0 ts(L) 1.3 V th(L) = 0 th(L) = 0 tPLH tPHL CEP 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V TC 1.3 V ts(H) th(H) = 0 ts(L) Figure 6. Up-Down Input to CET 1.3 V 1.3 V Terminal Count Output Delays 1.3 V The shaded areas indicate when the input is permitted to change for predictable output performance. Figure 5. Setup Time and Hold Time for Count Enable and Parallel Enable Inputs, and Up-Down Control Inputs FAST AND LS TTL DATA 5-183

SN54/74LS170 4 x 4 REGISTER FILE 4 x 4 REGISTER FILE OPEN-COLLECTOR OPEN-COLLECTOR The TTL / MSI SN54 / 74LS170 is a high-speed, low-power 4 x 4 Register LOW POWER SCHOTTKY File organized as four words by four bits. Separate read and write inputs, both address and enable, allow simultaneous read and write operation. J SUFFIX CERAMIC Open-collector outputs make it possible to connect up to 128 outputs in a CASE 620-09 wired-AND configuration to increase the word capacity up to 512 words. Any number of these devices can be operated in parallel to generate an n-bit 16 length. 1 The SN54 / 74LS670 provides a similar function to this device but it features 3-state outputs. • Simultaneous Read / Write Operation • Expandable to 512 Words of n-Bits • Typical Access Time of 20 ns • Low Leakage Open-Collector Outputs for Expansion • Typical Power Dissipation of 125 mW CONNECTION DIAGRAM DIP (TOP VIEW) 16 N SUFFIX 1 PLASTIC VCC D1 WA WB EW ER Q1 Q2 CASE 648-08 16 15 14 13 12 11 10 9 NOTE: 16 D SUFFIX The Flatpak version 1 SOIC has the same pinouts (Connection Diagram) as CASE 751B-03 the Dual In-Line Package. 1 2 3 4 56 78 ORDERING INFORMATION D2 D3 D4 RB RA Q4 Q3 GND SN54LSXXXJ Ceramic SN74LSXXXN Plastic SN74LSXXXD SOIC PIN NAMES LOADING (Note a) HIGH LOW LOGIC SYMBOL 12 15 1 2 3 D1 – D4 Data Inputs 0.5 U.L. 0.25 U.L. WA, WB Write Address Inputs 0.5 U.L. 0.25 U.L. 14 WA EW D1 D2 D3 D4 EW Write Enable (Active LOW) Input 1.0 U.L. 13 WB RA, RB Read Address Inputs 0.5 U.L. 0.5 U.L. ER Read Enable (Active LOW) Input 1.0 U.L. 0.25 U.L. 5 RA Q1 – Q4 Outputs (Note b) Open-Collector 4 RB ER Q1 Q2 Q3 Q4 0.5 U.L. 5 (2.5) U.L. NOTES: 11 10 9 7 6 a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) b. Temperature Ranges. The Output HIGH drive must be supplied by an external resistor to VCC. VCC = PIN 16 GND = PIN 8 FAST AND LS TTL DATA 5-184

SN54 / 74LS170 12 LOGIC DIAGRAM D2 D1 EW D4 D3 1 15 13 32 WB WA 14 GD GD GD WORD Q Q Q 0 GD Q GD GD GD WORD Q Q Q G D1 Q GD GD GD WORD Q Q Q G D2 Q GD GD GD WORD Q Q Q G D3 4 7 9 Q RB Q3 Q2 10 11 6 Q1 ER Q4 5 RA VCC = PIN 16 GND = PIN 8 = PIN NUMBERS FAST AND LS TTL DATA 5-185

SN54 / 74LS170 WRITE FUNCTION TABLE (SEE NOTES A, B, AND C) READ FUNCTION TABLE (SEE NOTES A AND D) WRITE INPUTS WORD READ INPUTS OUTPUTS WB WA EW 0 1 2 3 RB RA ER Q1 Q2 Q3 Q4 L L L Q = D Q0 Q0 Q0 L L L W0B1 W0B2 W0B3 W0B4 L H L Q0 Q = D Q0 Q0 L H L W1B1 W1B2 W1B3 W1B4 H L L Q0 Q0 Q = D Q0 H L L W2B1 W2B2 W2B3 W2B4 H H L Q0 Q0 Q0 Q = D H H L W3B1 W3B2 W3B3 W3B4 X X H Q0 Q0 Q0 Q0 XXH H H H H NOTES: A. H = HIGH Level. L = LOW Level, X = Irrelevant. NOTES: B. (Q = D) = The four selected internal flip-flop outputs will assume the states applied to the four external data inputs. NOTES: C. Q0 = the level of Q before the indicated input conditions were established. NOTES: D. W0B1 = The first bit of word 0, etc. GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 4.5 5.0 5.5 V 74 4.75 5.0 5.25 TA Operating Ambient Temperature Range 54 – 55 25 125 °C 74 0 25 70 VOH Output Voltage — High 54, 74 5.5 V IOL Output Current — Low 54 4.0 mA 74 8.0 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter Min Typ Max Unit Test Conditions VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for All Inputs 54 0.7 Guaranteed Input LOW Voltage for VIL Input LOW Voltage 74 0.8 V All Inputs VIK Input Clamp Diode Voltage – 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA IOH 100 Output HIGH Current 54, 74 0.25 0.4 µA VCC = MIN, VOH = MAX VOL 0.35 0.5 Output LOW Voltage 54, 74 V IOL = 4.0 mA VCC = VCC MIN, 74 V IOL = 8.0 mA VIN = VIL or VIH per Truth Table Input HIGH Current 20 µA VCC = MAX, VIN = 2.4 V Any D, R, W 40 IIH ER, EW 0.1 mA VCC = MAX, VIN = 7.0 V Any D, R, W 0.2 ER, EW – 0.4 mA VCC = MAX, VIN = 0.4 V Input LOW Current – 0.8 mA VCC = MAX IIL Any D, R, W 40 ER, EW ICC Power Supply Current FAST AND LS TTL DATA 5-186

SN54 / 74LS170 AC CHARACTERISTICS (TA = 25°C) Symbol Parameter Limits Unit Test Conditions ns Figure 1 tPLH Propagation Delay, Negative- Min Typ Max ns tPHL Going ER to Q Outputs ns Figure 2 VCC = 5.0 V 20 30 ns Figure 1 tPLH Propagation Delay, RA or RB 20 30 CL = 15 pF tPHL to Q Outputs RL = 2.0 kΩ 25 40 tPLH Propagation Delay, Negative- 24 40 Figure 1 tPHL Going EW to Q Outputs 30 45 tPLH Propagation Delay, Data Inputs 26 40 tPHL to Q Outputs 30 45 22 35 AC SETUP REQUIREMENTS (TA = 25°C) Symbol Parameter Limits Unit Test Conditions Min Typ Max ns tW Pulse Width, ER, EW 25 ns VCC = 5.0 V ts Setup Time, Data to EW 10 ns RL = 2.0 kΩ ts Setup Time, WA, WB to EW 15 ns th Hold Time, Data to EW 15 ns th Hold Time, WA, WB to EW 5.0 ns tLATCH Latch Time 25 VOLTAGE WAVEFORMS WRITE-SELECT Vref Vref 3V DATA INPUT Vref 3V INPUT WA or WB tsu(W) th(W) 0V D1, D2, D3 or D4 DATA INPUT 3V tPLH 0V D1, D2, D3 or D4 Vref Vref 0V WRITE-ENABLE Vref Vref 3V tw tsu(D)th(D) 3V INPUT EW tPHL WRITE-ENABLE Vref Vref 0V Vref 0V INPUT EW 3V OUTPUT VOH 0V Q1, Q2, Q3 or Q4 Vref READ-SELECT 3V tPLH VOL INPUT RA or RB tlatch 0V Vref 3V READ-ENABLE VOH INPUT ER Vref Vref VOL DATA INPUT 0V D1, D2, D3 or D4 3V OUTPUT tW Vref Q1, Q2, Q3 or Q4 Vref Vref WRITE-ENABLE 0V INPUT EW tPHL 3V tPHL tPLH Vref Vref Vref OUTPUT 0V tPHL tPLH Q1, Q2, Q3 or Q4 Figure 1 Figure 2 FAST AND LS TTL DATA 5-187

SN54/74LS173A 4-BIT D-TYPE REGISTER 4-BIT D-TYPE REGISTER WITH 3-STATE OUTPUTS WITH 3-STATE OUTPUTS The SN54 / 74LS173A is a high-speed 4-Bit Register featuring 3-state LOW POWER SCHOTTKY outputs for use in bus-organized systems. The clock is fully edge-triggered allowing either a load from the D inputs or a hold (retain register contents) J SUFFIX depending on the state of the Input Enable Lines (IE1, IE2). A HIGH on either CERAMIC Output Enable line (OE1, OE2) brings the output to a high impedance state CASE 620-09 without affecting the actual register contents. A HIGH on the Master Reset (MR) input resets the Register regardless of the state of the Clock (CP), the Output Enable (OE1, OE2) or the Input Enable (IE1, IE2) lines. • Fully Edge-Triggered • 3-State Outputs • Gated Input and Output Enables • Input Clamp Diodes Limit High-Speed Termination Effects 16 1 CONNECTION DIAGRAM DIP (TOP VIEW) 16 N SUFFIX 1 PLASTIC VCC MR D0 D1 D2 D3 IE2 IE1 CASE 648-08 16 15 14 13 12 11 10 9 NOTE: D SUFFIX The Flatpak version SOIC has the same pinouts (Connection Diagram) as CASE 751B-03 the Dual In-Line Package. 1 2 3 4 56 78 16 OE1 OE2 Q0 Q1 Q2 Q3 CP GND 1 ORDERING INFORMATION PIN NAMES LOADING (Note a) SN54LSXXXJ Ceramic SN74LSXXXN Plastic SN74LSXXXD SOIC HIGH LOW D0 – D3 Data Inputs 0.5 U.L. 0.25 U.L. LOGIC SYMBOL IE1 – IE2 Input Enable (Active LOW) 0.5 U.L. 0.25 U.L. 9 10 14 13 12 11 OE1 – OE2 Output Enable (Active LOW) Inputs 0.5 U.L. 0.25 U.L. CP Clock Pulse (Active HIGH Going Edge) 0.5 U.L. 0.25 U.L. 12 Input MR Master Reset Input (Active HIGH) 0.5 U.L. 0.25 U.L. Q0 – Q3 Outputs (Note b) 65 (25) U.L. 15 (7.5) U.L. 7 IE D0 D1 D2 D3 CP Q0 Q1 Q2Q3 NOTES: 11 a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. 22 OE b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) MR b. Temperature Ranges. 15 3 4 5 6 VCC = PIN 16 GND = PIN 8 FAST AND LS TTL DATA 5-188

SN54 / 74LS173A LOGIC DIAGRAM D0 D1 D2 D3 IE1 9 14 13 12 11 IE2 10 CP CP D D DD QQ 7 4 56 3 MR 15 Q1 Q2 Q3 Q0 OE1 1 OE2 2 VCC = PIN 16 GND = PIN 8 = PIN NUMBERS TRUTH TABLE H = HIGH Voltage Level L = LOW Voltage Level MR CP IE1 IE2 Dn Qn X = Immaterial Hx xxxL L L x x x Qn L H x x Qn L x H x Qn L LLLL L L L HH When either OE1, or OE2 are HIGH, the output is in the off state (High Impedance); however this does not affect the contents or sequential operation of the register. GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 4.5 5.0 5.5 V 74 4.75 5.0 5.25 TA Operating Ambient Temperature Range 54 – 55 25 125 °C 74 0 25 70 IOH Output Current — High 54 – 1.0 mA 74 – 2.6 IOL Output Current — Low 54 12 mA 74 24 FAST AND LS TTL DATA 5-189

SN54 / 74LS173A DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter Min Typ Max Unit Test Conditions VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for All Inputs 54 0.7 Guaranteed Input LOW Voltage for VIL Input LOW Voltage 0.8 V All Inputs 74 VIK Input Clamp Diode Voltage 54 – 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA VOH Output HIGH Voltage 74 2.4 3.4 2.4 3.1 V VCC = MIN, IOH = MAX, VIN = VIH V or VIL per Truth Table VOL Output LOW Voltage 54, 74 0.25 0.4 V IOL = 12 mA VCC = VCC MIN, 74 0.35 0.5 V IOL = 24 mA VIN = VIL or VIH per Truth Table IOZH Output Off Current HIGH 20 µA VCC = MAX, VO = 2.7 V IOZL Output Off Current LOW – 20 µA VCC = MAX, VO = 0.4 V IIH Input HIGH Current 20 µA VCC = MAX, VIN = 2.7 V 0.1 mA VCC = MAX, VIN = 7.0 V IIL Input LOW Current – 0.4 mA VCC = MAX, VIN = 0.4 V IOS Short Circuit Current (Note 1) – 30 – 130 mA VCC = MAX ICC Power Supply Current 30 mA VCC = MAX Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C) Symbol Parameter Limits Unit Test Conditions Maximum Input Clock Frequency Min Typ Max MHz fMAX Propagation Delay, 30 50 VCC = 5.0 V Clock to Output ns CL = 45 pF, tPLH Propagation Delay, MR to Output 17 25 ns RL = 667 Ω tPHL 22 30 ns Output Enable Time CL = 5.0 pF, tPHL 26 35 ns RL = 667 Ω Output Disable Time tPZH 15 23 tPZL 18 27 tPLZ 11 17 tPHZ 11 17 AC SETUP REQUIREMENTS (TA = 25°C) Symbol Parameter Limits Unit Test Conditions Clock or MR Pulse Width Min Typ Max ns VCC = 5.0 V tW Data Enable Setup Time 20 ns ts Data Setup Time 35 ns ts Hold Time, Any Input 17 ns th Recovery Time ns trec 0 10 FAST AND LS TTL DATA 5-190

SN54 / 74LS173A AC WAVEFORMS CP 1.3 V 1 / fmax 1.3 V MR tW trec ts(H) tW 1.3 V D or E th(L) CP Q 1.3 V th(H) ts(L) 1.3 V Q tPHL 1.3 V tPLH 1.3 V tPHL 1.3 V Figure 1 Figure 2 VE 1.3 V 1.3 V VE 1.3 V 1.3 V VOUT tPLZ VOUT tPZH tPZL 1.3 V tPHZ ≥ VOH 1.3 V ≈ 1.3 V 0.5 V VOL 0.5 V Figure 3 Figure 4 AC LOAD CIRCUIT VCC RL SWITCH POSITIONS SW1 SYMBOL SW1 SW2 TO OUTPUT tPZH Open Closed UNDER TEST tPZL Closed Open tPLZ Closed Closed tPHZ Closed Closed 5 kΩ SW2 CL* * Includes Jig and Probe Capacitance. Figure 5 FAST AND LS TTL DATA 5-191

SN54/74LS174 HEX D FLIP-FLOP HEX D FLIP-FLOP LOW POWER SCHOTTKY The LSTTL / MSI SN54 / 74LS174 is a high speed Hex D Flip-Flop. The device is used primarily as a 6-bit edge-triggered storage register. The information on the D inputs is transferred to storage during the LOW to HIGH clock transition. The device has a Master Reset to simultaneously clear all flip-flops. The LS174 is fabricated with the Schottky barrier diode process for high speed and is completely compatible with all Motorola TTL families. • Edge-Triggered D-Type Inputs • Buffered-Positive Edge-Triggered Clock • Asynchronous Common Reset • Input Clamp Diodes Limit High Speed Termination Effects CONNECTION DIAGRAM DIP (TOP VIEW) J SUFFIX CERAMIC VCC Q5 D5 D4 Q4 D3 Q3 CP CASE 620-09 16 15 14 13 12 11 10 9 16 NOTE: 1 The Flatpak version has the same pinouts 16 N SUFFIX (Connection Diagram) as 1 PLASTIC the Dual In-Line Package. CASE 648-08 1 2 3 4 56 78 MR Q0 D0 D1 Q1 D2 Q2 GND PIN NAMES LOADING (Note a) D SUFFIX SOIC HIGH LOW 16 1 CASE 751B-03 D0 – D5 Data Inputs 0.5 U.L. 0.25 U.L. ORDERING INFORMATION CP Clock (Active HIGH Going Edge) Input 0.5 U.L. 0.25 U.L. Master Reset (Active LOW) Input 0.5 U.L. 0.25 U.L. SN54LSXXXJ Ceramic MR Outputs (Note b) 10 U.L. 5 (2.5) U.L. SN74LSXXXN Plastic SN74LSXXXD SOIC Q0 – Q5 NOTES: a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) b. Temperature Ranges. LOGIC DIAGRAM LOGIC SYMBOL MR CP D5 D4 D3 D2 D1 D0 3 4 6 11 13 14 1 9 14 13 11 6 4 3 D0 D1 D2 D3 D4 D5 9 CP DQ DQ DQ DQ DQ DQ 1 MR CPCD CPCD CPCD CPCD CPCD CPCD Q0 Q1 Q2 Q3 Q4 Q5 15 12 10 7 5 2 Q5 Q1 Q0 2 5 7 10 12 15 VCC = PIN 16 Q4 Q3 Q2 GND = PIN 8 VCC = PIN 16 GND = PIN 8 = PIN NUMBERS FAST AND LS TTL DATA 5-192

SN54 / 74LS174 FUNCTIONAL DESCRIPTION A LOW input to the Master Reset (MR) will force all outputs LOW independent of Clock or Data inputs. The LS174 is The LS174 consists of six edge-triggered D flip-flops with useful for applications where the true output only is required individual D inputs and Q outputs. The Clock (CP) and Master and the Clock and Master Reset are common to all storage Reset (MR) are common to all flip-flops. elements. Each D input’s state is transferred to the corresponding flip- flop’s output following the LOW to HIGH Clock (CP) transition. TRUTH TABLE Inputs (t = n, MR = H) Outputs (t = n+1) Note 1 DQ H H L L Note 1: t = n + 1 indicates conditions after next clock. GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 4.5 5.0 5.5 V 74 4.75 5.0 5.25 TA Operating Ambient Temperature Range 54 – 55 25 125 °C 74 0 25 70 IOH Output Current — High 54, 74 – 0.4 mA IOL Output Current — Low 54 4.0 mA 74 8.0 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter Min Typ Max Unit Test Conditions VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for All Inputs 54 0.7 Guaranteed Input LOW Voltage for VIL Input LOW Voltage 0.8 V All Inputs 74 VIK Input Clamp Diode Voltage – 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA VOH Output HIGH Voltage 54 2.5 3.5 V VCC = MIN, IOH = MAX, VIN = VIH 74 2.7 3.5 V or VIL per Truth Table VOL Output LOW Voltage 54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN, 74 0.35 0.5 V IOL = 8.0 mA VIN = VIL or VIH per Truth Table IIH Input HIGH Current 20 µA VCC = MAX, VIN = 2.7 V 0.1 mA VCC = MAX, VIN = 7.0 V IIL Input LOW Current – 0.4 mA VCC = MAX, VIN = 0.4 V IOS Short Circuit Current (Note 1) – 20 – 100 mA VCC = MAX ICC Power Supply Current 26 mA VCC = MAX Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. FAST AND LS TTL DATA 5-193

SN54 / 74LS174 AC CHARACTERISTICS (TA = 25°C) Symbol Parameter Limits Unit Test Conditions Maximum Input Clock Frequency Min Typ Max MHz VCC = 5.0 V fMAX Propagation Delay, MR to Output 30 40 CL = 15 pF tPHL ns tPLH Propagation Delay, Clock to Output 23 35 Test Conditions tPHL ns VCC = 5.0 V 20 30 21 30 AC SETUP REQUIREMENTS (TA = 25°C) Symbol Parameter Limits Unit Clock or MR Pulse Width Min Typ Max ns tW Data Setup Time 20 ns ts Data Hold Time 20 ns th Recovery Time 5.0 ns trec 25 AC WAVEFORMS 1/fmax tw CP 1.3 V 1.3 V tW MR 1.3 V 1.3 V ts(H) th(H)ts(L) th(L) trec D* 1.3 V 1.3 V 1.3 V 1.3 V Q CP tPLH tPHL Q tPHL 1.3 V 1.3 V 1.3 V 1.3 V *The shaded areas indicate when the input is permitted to Figure 2. Master Reset to Output Delay, Master Reset *change for predictable output performance. Pulse Width, and Master Reset Recovery Time Figure 1. Clock to Output Delays, Clock Pulse Width, Frequency, Setup and Hold Times Data to Clock DEFINITIONS OF TERMS nition. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from LOW to SETUP TIME (ts) — is defined as the minimum time required HIGH and still be recognized. for the correct logic level to be present at the logic input prior to the clock transition from LOW to HIGH in order to be recog- RECOVERY TIME (trec) — is defined as the minimum time nized and transferred to the outputs. required between the end of the reset pulse and the clock transition from LOW to HIGH in order to recognize and transfer HOLD TIME (th) — is defined as the minimum time following HIGH Data to the Q outputs. the clock transition from LOW to HIGH that the logic level must be maintained at the input in order to ensure continued recog- FAST AND LS TTL DATA 5-194

QUAD D FLIP-FLOP SN54/74LS175 The LSTTL / MSI SN54 / 74LS175 is a high speed Quad D Flip-Flop. The QUAD D FLIP-FLOP device is useful for general flip-flop requirements where clock and clear inputs LOW POWER SCHOTTKY are common. The information on the D inputs is stored during the LOW to HIGH clock transition. Both true and complemented outputs of each flip-flop J SUFFIX are provided. A Master Reset input resets all flip-flops, independent of the CERAMIC Clock or D inputs, when LOW. CASE 620-09 The LS175 is fabricated with the Schottky barrier diode process for high 16 speed and is completely compatible with all Motorola TTL families. 1 • Edge-Triggered D-Type Inputs • Buffered-Positive Edge-Triggered Clock • Clock to Output Delays of 30 ns • Asynchronous Common Reset • True and Complement Output • Input Clamp Diodes Limit High Speed Termination Effects CONNECTION DIAGRAM DIP (TOP VIEW) VCC Q3 Q3 D3 D2 Q2 Q2 CP 16 15 14 13 12 11 10 9 NOTE: 16 N SUFFIX The Flatpak version 1 PLASTIC has the same pinouts CASE 648-08 (Connection Diagram) as the Dual In-Line Package. 1 2 3 4 56 78 MR Q0 Q0 D0 D1 Q1 Q1 GND PIN NAMES LOADING (Note a) 16 D SUFFIX 1 SOIC CASE 751B-03 HIGH LOW D0 – D3 Data Inputs 0.5 U.L. 0.25 U.L. ORDERING INFORMATION CP Clock (Active HIGH Going Edge) Input 0.5 U.L. 0.25 U.L. Master Reset (Active LOW) Input 0.5 U.L. 0.25 U.L. SN54LSXXXJ Ceramic MR True Outputs (Note b) 10 U.L. 5 (2.5) U.L. SN74LSXXXN Plastic Complemented Outputs (Note b) 10 U.L. 5 (2.5) U.L. SN74LSXXXD SOIC Q0 – Q3 Q0 – Q3 NOTES: LOGIC SYMBOL a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. 4 5 12 b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) b. Temperature Ranges. LOGIC DIAGRAM 13 MR CP D3 D2 D1 D0 1 9 13 12 5 4 DQ DQ DQ DQ D0 D1 D2 D3 CP Q CP Q CP Q CP Q 9 CP CD CD CD CD 1 MR Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 VCC = PIN 16 14 15 11 10 67 32 3 2 6 7 11 10 14 15 GND = PIN 8 Q3 Q3 Q2 Q2 Q1Q1 Q0 Q0 VCC = PIN 16 GND = PIN 8 = PIN NUMBERS FAST AND LS TTL DATA 5-195

SN54 / 74LS175 FUNCTIONAL DESCRIPTION LOW input on the Master Reset (MR) will force all Q outputs LOW and Q outputs HIGH independent of Clock or Data The LS175 consists of four edge-triggered D flip-flops with inputs. individual D inputs and Q and Q outputs. The Clock and Master Reset are common. The four flip-flops will store the The LS175 is useful for general logic applications where a state of their individual D inputs on the LOW to HIGH Clock common Master Reset and Clock are acceptable. (CP) transition, causing individual Q and Q outputs to follow. A TRUTH TABLE Inputs (t = n, MR = H) Outputs (t = n+1) Note 1 D QQ LL H HH L Note 1: t = n + 1 indicates conditions after next clock. GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 4.5 5.0 5.5 V 74 4.75 5.0 5.25 TA Operating Ambient Temperature Range 54 – 55 25 125 °C 74 0 25 70 IOH Output Current — High 54, 74 – 0.4 mA IOL Output Current — Low 54 4.0 mA 74 8.0 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter Min Typ Max Unit Test Conditions VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for All Inputs 54 0.7 Guaranteed Input LOW Voltage for VIL Input LOW Voltage 0.8 V All Inputs 74 VIK Input Clamp Diode Voltage 54 – 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA VOH Output HIGH Voltage 74 2.5 3.5 2.7 3.5 V VCC = MIN, IOH = MAX, VIN = VIH V or VIL per Truth Table VOL Output LOW Voltage 54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN, 74 0.35 0.5 V IOL = 8.0 mA VIN = VIL or VIH per Truth Table IIH Input HIGH Current 20 µA VCC = MAX, VIN = 2.7 V 0.1 mA VCC = MAX, VIN = 7.0 V IIL Input LOW Current – 0.4 mA VCC = MAX, VIN = 0.4 V IOS Short Circuit Current (Note 1) – 20 – 100 mA VCC = MAX ICC Power Supply Current 18 mA VCC = MAX Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. FAST AND LS TTL DATA 5-196

SN54 / 74LS175 AC CHARACTERISTICS (TA = 25°C) Symbol Parameter Limits Unit Test Conditions Maximum Input Clock Frequency MHz VCC = 5.0 V fMAX Propagation Delay, MR to Output Min Typ Max CL = 15 pF ns tPLH Propagation Delay, Clock to Output 30 40 Test Conditions tPHL ns VCC = 5.0 V 20 30 tPLH 20 30 tPHL 13 25 16 25 AC SETUP REQUIREMENTS (TA = 25°C) Symbol Parameter Limits Unit Clock or MR Pulse Width Min Typ Max ns tW Data Setup Time 20 ns ts Data Hold Time 20 ns th Recovery Time 5.0 ns trec 25 AC WAVEFORMS 1/fmax tw CP 1.3 V 1.3 V tW MR 1.3 V 1.3 V ts(H) th(H)ts(L) th(L) trec D* 1.3 V 1.3 V 1.3 V 1.3 V Q tPLH tPHL CP Q 1.3 V Q tPHL 1.3 V tPLH 1.3 V 1.3 V 1.3 V tPLH tPHL Q 1.3 V 1.3 V 1.3 V Figure 2. Master Reset to Output Delay, Master Reset *The shaded areas indicate when the input is permitted to Pulse Width, and Master Reset Recovery Time *change for predictable output performance. Figure 1. Clock to Output Delays, Clock Pulse Width, Frequency, Setup and Hold Times Data to Clock DEFINITIONS OF TERMS nition. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from LOW to SETUP TIME (ts) — is defined as the minimum time required HIGH and still be recognized. for the correct logic level to be present at the logic input prior to the clock transition from LOW to HIGH in order to be recog- RECOVERY TIME (trec) — is defined as the minimum time nized and transferred to the outputs. required between the end of the reset pulse and the clock transition from LOW to HIGH in order to recognize and transfer HOLD TIME (th) — is defined as the minimum time following HIGH Data to the Q outputs. the clock transition from LOW to HIGH that the logic level must be maintained at the input in order to ensure continued recog- FAST AND LS TTL DATA 5-197

SN54/74LS181 4-BIT ARITHMETIC 4-BIT ARITHMETIC LOGIC UNIT LOGIC UNIT The SN54 / 74LS181 is a 4-bit Arithmetic Logic Unit (ALU) which can LOW POWER SCHOTTKY perform all the possible 16 logic, operations on two variables and a variety of arithmetic operations. 24 J SUFFIX • Provides 16 Arithmetic Operations Add, Subtract, Compare, Double, 1 CERAMIC CASE 623-05 Plus Twelve Other Arithmetic Operations • Provides all 16 Logic Operations of Two Variables Exclusive — OR, Compare, AND, NAND, OR, NOR, Plus Ten other Logic Operations • Full Lookahead for High Speed Arithmetic Operation on Long Words • Input Clamp Diodes CONNECTION DIAGRAM DIP (TOP VIEW) VCC A1 B1 A2 B2 A3 B3 G Cn+4 P A=B F3 24 23 22 21 20 19 18 17 16 15 14 13 N SUFFIX PLASTIC CASE 649-03 24 1 1 2 3 4 5 6 7 8 9 10 11 12 ORDERING INFORMATION B0 A0 S3 S2 S1 S0 Cn M F0 F1 F2 GND SN54LSXXXJ Ceramic NOTE: SN74LSXXXN Plastic The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. PIN NAMES LOADING (Note a) LOGIC SYMBOL 2 1 23 22 21 20 19 18 HIGH LOW A0 B0 A1 B1 A2 B2 A3 B3 A0 – A3, B0 – B3 Operand (Active LOW) Inputs 1.5 U.L. 0.75 U.L. 7 Cn Cn+4 16 S0 – S3 Function — Select Inputs 2.0 U.L. 1.0 U.L. M Mode Control Input 0.5 U.L. 8M A = B 14 Cn Carry Input 2.5 U.L. 0.25 U.L. F0 – F3 Function (Active LOW) Outputs 10 U.L. 1.25 U.L. 6 S0 G 17 A=B Comparator Output Open Collector 5 (2.5) U.L. G Carry Generator (Active LOW) 10 U.L. 5 (2.5) U.L. 5 S1 P 15 Output 4 S2 P Carry Propagate (Active LOW) 10 U.L. 10 U.L. Output 3 S3 F0 F1 F2 F3 Cn+4 Carry Output 10 U.L. 5 U.L. 9 10 11 13 5 (2.5) U.L. VCC = PIN 24 GND = PIN 12 NOTES: a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) b. Temperature Ranges. FAST AND LS TTL DATA 5-198

SN54 / 74LS181 LOGIC DIAGRAM 1 23 22 21 20 19 18 782 B0 A1 B1 A2 B2 A3 B3 Cn M A0 S0 6 5 4 S1 S2 S3 3 VCC = PIN 24 GND = PIN 12 = PIN NUMBERS F0 F1 A = B F2 F3 P Cn+4 G 9 10 14 11 13 15 16 17 FUNCTIONAL DESCRIPTION over extremely long word lengths. The A = B output from the LS181 goes HIGH when all four F The SN54 / 74LS181 is a 4-bit high speed parallel Arithmetic Logic Unit (ALU). Controlled by the four Function Select Inputs outputs are HIGH and can be used to indicate logic (S0 . . . S3) and the Mode Control Input (M), it can perform all equivalence over four bits when the unit is in the subtract the 16 possible logic operations or 16 different arithmetic mode. The A = B output is open collector and can be operations on active HIGH or active LOW operands. The wired-AND with other A = B outputs to give a comparison for Function Table lists these operations. more then four bits. The A = B signal can also be used with the Cn+4 signal to indicate A>B and A<B. When the Mode Control Input (M) is HIGH, all internal carries are inhibited and the device performs logic operations The Function Table lists the arithmetic operations that are on the individual bits as listed. When the Mode Control Input is performed without a carry in. An incoming carry adds a one to LOW, the carries are enabled and the device performs each operation. Thus, select code LHHL generates A minus B arithmetic operations on the two 4-bit words. The device minus 1 (2s complement notation) without a carry in and incorporates full internal carry lookahead and provides for generates A minus B when a carry is applied. Because either ripple carry between devices using the Cn+4 output, or subtraction is actually performed by complementary addition for carry lookahead between packages using the signals P (1s complement), a carry out means borrow; thus a carry is (Carry Propagate) and G (Carry Generate), P and G are not generated when there is no underflow and no carry is affected by carry in. When speed requirements are not generated when there is underflow. stringent, the LS181 can be used in a simple ripple carry mode by connecting the Carry Output (Cn+4) signal to the Carry Input As indicated, the LS181 can be used with either active LOW (Cn) of the next unit. For high speed operation the LS181 is inputs producing active LOW outputs or with active HIGH used in conjunction with the 9342 or 93S42 carry lookahead inputs producing active HIGH outputs. For either case the circuit. One carry lookahead package is required for each table lists the operations that are performed to the operands group of the four LS181 devices. Carry lookahead can be labeled inside the logic symbol. provided at various levels and offers high speed capability FAST AND LS TTL DATA 5-199

SN54 / 74LS181 FUNCTION TABLE MODE SELECT ACTIVE LOW INPUTS ACTIVE HIGH INPUTS INPUTS & OUTPUTS & OUTPUTS S3 S2 S1 S0 LOGIC ARITHMETIC** LOGIC ARITHMETIC** (M = H) (M = L) (Cn = L) (M = H) (M = L) (Cn = H) L L L LA A minus 1 AA L L L H AB AB minus 1 A+B A+B L L H L A+B AB minus 1 AB A + B L L H H Logical 1 minus 1 Logical 0 minus 1 L H L L A+B A plus (A + B) AB A plus AB L H L HB AB plus (A + B) B (A + B) plus AB L H H L A⊕B A minus B minus 1 A⊕B A minus B minus 1 L H H H A+B A+B AB AB minus 1 H L L L AB A plus (A + B) A+B A plus AB H L L H A⊕B A plus B A⊕B A plus B H L H LB AB plus (A + B) B (A + B) plus AB H L H H A+B A+B AB AB minus 1 H H L L Logical 0 A plus A* Logical 1 A plus A* H H L H AB AB plus A A+B (A + B) plus A H H H L AB AB plus A A+B (A + B) Plus A H H H HA A A A minus 1 L = LOW Voltage Level H = HIGH Voltage Level **Each bit is shifted to the next more significant position **Arithmetic operations expressed in 2s complement notation LOGIC SYMBOLS ACTIVE LOW OPERANDS ACTIVE HIGH OPERANDS 2 1 23 22 21 20 19 18 2 1 23 22 21 20 19 18 7 Cn A0 B0 A1 B1 A2 B2 A3 B3 16 A0 B0 A1 B1 A2 B2 A3 B3 Cn+4 7 Cn 16 Cn+4 8M LS181 A=B 14 8M LS181 A=B 14 6 S0 4 BIT ARITHMETIC G 17 6 S0 4 BIT ARITHMETIC G 17 5 S1 LOGIC UNIT 5 S1 4 S2 P 15 4 S2 LOGIC UNIT P 15 3 S3 F0 F1 F2 F3 3 S3 F0 F1 F2 F3 9 10 11 13 9 10 11 13 GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 4.5 5.0 5.5 V 74 4.75 5.0 5.25 TA Operating Ambient Temperature Range 54 – 55 25 125 °C 74 0 25 70 IOH Output Current — High 54, 74 – 0.4 mA IOL Output Current — Low 54 4.0 mA 74 8.0 VOH Output Voltage — High (A = B only) 54, 74 5.5 V FAST AND LS TTL DATA 5-200

SN54 / 74LS181 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter Min Typ Max Unit Test Conditions VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for All Inputs 54 0.7 Guaranteed Input LOW Voltage for VIL Input LOW Voltage 0.8 V All Inputs 74 VIK Input Clamp Diode Voltage – 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA VOH Output HIGH Voltage 54 2.5 3.5 V VCC = MIN, IOH = MAX, VIN = VIH 74 2.7 3.5 V or VIL per Truth Table VOL Output LOW Voltage 54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN, Except G and P V IOL = 8.0 mA VIN = VIL or VIH 74 0.35 0.5 V IOL = 16 mA per Truth Table Output G 54, 74 0.7 V IOL = 8.0 mA Output P 54 0.6 74 0.5 IOH Output HIGH Current 54, 74 100 µA VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table Input HIGH Current 20 Mode Input Any A or B Input 60 µA VCC = MAX, VIN = 2.7 V Any S Input 80 IIH Cn Input 100 Mode Input Any A or B Input 0.1 Any S Input Cn Input 0.3 mA VCC = MAX, VIN = 7.0 V 0.4 0.5 Input LOW Current – 0.4 Mode Input – 1.2 mA VCC = MAX, VIN = 0.4 V – 1.6 IIL Any A or B Input Any S Input – 2.0 Cn Input IOS Short Circuit Current (Note 2) – 20 – 100 mA VCC = MAX Power Supply Current 54 32 See Note 1A 74 34 mA VCC = MAX ICC 54 35 See Note 1B 37 74 Note 1. With outputs open, ICC is measured for the following conditions: A. S0 through S3, M, and A inputs are at 4.5 V, all other inputs are grounded. B. S0 through S3 and M are at 4.5 V, all other inputs are grounded. Note 2: Not more than one output should be shorted at a time, nor for more than 1 second. FAST AND LS TTL DATA 5-201

SN54 / 74LS181 AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V, Pin 12 = GND, CL = 15 pF) Limits Symbol Parameter Min Typ Max Unit Test Conditions tPLH Propagation Delay, 18 27 ns M = 0 V, (Sum or Diff Mode) tPHL (Cn to Cn+4) 13 20 See Fig. 4 and Tables I and II tPLH (Cn to F Outputs) 17 26 ns M = 0 V, (Sum Mode) tPHL 13 20 See Fig. 4 and Table I tPLH (A or B Inputs to G Output) 19 29 ns M = S1 = S2 = 0 V, S0 = S3 = 4.5 V tPHL 15 23 (Sum Mode) See Fig. 4 and Table I tPLH (A or B Inputs to G Output) 21 32 ns M = S0 = S3 = 0 V, S1 = S2 = 4.5 V tPHL 21 32 (Diff Mode) See Fig. 5 and Table II tPLH (A or B Inputs to P Output) 20 30 ns M = S1 = S2 = 0 V, S0 = S3 = 4.5 V tPHL 20 30 (Sum Mode) See Fig. 4 and Table I tPLH (A or B Inputs to P Output) 20 30 ns M = S0 = S3 = 0 V, S1 = S2 = 4.5 V tPHL 22 33 (Diff Mode) See Fig. 5 and Table II tPLH (AX or BX Inputs to FX Output) 21 32 ns M = S1 = S2 = 0 V, S0 = S3 = 4.5 V tPHL 13 20 (Sum Mode) See Fig. 4 and Table I tPLH (AX or BX Inputs to FX Output) 21 32 ns M = S0 = S3 = 0 V, S1 = S2 = 4.5 V tPHL 21 32 (Diff Mode) See Fig. 5 and Table II tPLH (AX or BX Inputs to FXH Outputs) 38 ns M = S1 = S2 = 0 V, S0 = S3 = 4.5 V tPHL 26 (Sum Mode) See Fig. 4 and Table I tPLH (AX or BX Inputs to FXH Outputs) 38 ns M = S0 = S3 = 0 V, S1 = S2 = 4.5 V tPHL 38 (Diff Mode) See Fig. 5 and Table II tPLH (A or B Inputs to F Outputs) 22 33 ns M = 4.5 V (Logic Mode) tPHL 26 38 See Fig. 4 and Table III tPLH (A or B Inputs to Cn+4 Output) 25 38 ns M = 0 V, S0 = S3 = 4.5 V, S1 = S2 = 0 V tPHL 25 38 (Sum Mode) See Fig. 6 and Table I tPLH (A or B Inputs to Cn+4 Output) 27 41 ns M = 0 V, S0 = S3 = 0 V, S1 = S2 = 4.5 V tPHL 27 41 (Diff Mode) tPLH (A or B Inputs to A = B Output) 33 50 M = S0 = S3 = 0 V, S1 = S2 = 4.5 V tPHL 41 62 ns RL = 2.0 kΩ (Diff Mode) See Fig. 5 and Table II AC WAVEFORMS INPUT 1.3 V 1.3 V OUTPUT tPLH tPHL 1.3 V 1.3 V Figure 4 A INPUT 1.3 V 1.3 V B INPUT 1.3 V 1.3 V INPUT 1.3 V tPLH 1.3 V tPHL OUTPUT 1.3 V tPHL tPLH 1.3 V 1.3 V 1.3 V OUTPUT Figure 5 Figure 6 FAST AND LS TTL DATA 5-202

SN54 / 74LS181 SUM MODE TEST TABLE I FUNCTION INPUTS: S0 = S3 = 4.5 V, S1 = S2 = M = 0 V Input Other Input Other Data Inputs Output Under Same Bit Under Test Test Parameter Apply Apply Apply Apply Al 4.5 V GND 4.5 V GND Fl tPLH Bl tPHL Al Bl None Remaining Cn Fl Bl A and B tPLH A Fl+1 tPHL Al None Remaining Cn B A and B Fl+1 tPLH tPHL A Bl None Cn Remaining P A and B tPLH B P tPHL Al None Cn Remaining A A and B G tPLH tPHL B B None None Remaining G A and B, Cn tPLH Cn A None None Cn+4 tPHL Remaining None B Remaining A and B, Cn Cn+4 tPLH B Any F tPHL None A Remaining or Cn+4 Remaining A, Cn tPLH None B B tPHL Remaining None A Remaining A, Cn tPLH B tPHL None None Remaining Remaining A, Cn tPLH B tPHL Remaining All A, Cn tPLH A tPHL All B FAST AND LS TTL DATA 5-203

SN54 / 74LS181 DIFF MODE TEST TABLE II FUNCTION INPUTS: S1 = S2 = 4.5 V, S0 = S3 = M = 0 V Input Other Input Other Data Inputs Output Under Same Bit Under Test Test Parameter Apply Apply Apply Apply A 4.5 V GND 4.5 V GND Fl tPLH B Fl tPHL Al None B Remaining Remaining Fl+1 Bl A B, Cn Fl+1 tPLH A A None P tPHL B Remaining Remaining A None Bl A B, Cn P tPLH B Al None tPHL A Remaining Remaining G B None B B, Cn A tPLH A G tPHL B A None Remaining Remaining Cn B, Cn A A=B tPLH B None tPHL None Remaining A=B None A A and B, Cn tPLH None cn+4 tPHL None B Remaining Cn+4 None A and B, Cn Cn+4 tPLH A None tPHL None Remaining B None A and Bl, Cn tPLH Remaining tPHL None A A Remaining A and B, Cn tPLH None None Remaining tPHL A Remaining B, Cn tPLH None tPHL Remaining None B, Cn tPLH tPHL All Remaining A and B A and B, Cn tPLH tPHL Remaining A and B, Cn tPLH tPHL None LOGIC MODE TEST TABLE III Input Other Input Other Data Inputs Output Under Same Bit Under Test Test Parameter Apply Apply Apply Apply Function Inputs A 4.5 V GND 4.5 V GND Any F tPLH S1 = S2 = M = 4.5 V tPHL B None B None Remaining Any F S0 = S3 = 0 V None A and B, Cn tPLH None A S1 = S2 = M = 4.5 V tPHL Remaining S0 = S3 = 0 V A and B, Cn FAST AND LS TTL DATA 5-204

PRESETTABLE BCD/DECADE SN54/74LS190 UP/DOWN COUNTERS SN54/74LS191 PRESETTABLE 4-BIT BINARY PRESETTABLE BCD / DECADE UP/DOWN COUNTERS UP/ DOWN COUNTERS The SN54 / 74LS190 is a synchronous UP/ DOWN BCD Decade (8421) PRESETTABLE 4-BIT BINARY Counter and the SN54/ 74LS191 is a synchronous UP / DOWN Modulo-16 UP/ DOWN COUNTERS Binary Counter. State changes of the counters are synchronous with the LOW-to-HIGH transition of the Clock Pulse input. LOW POWER SCHOTTKY An asynchronous Parallel Load (PL) input overrides counting and loads the J SUFFIX data present on the Pn inputs into the flip-flops, which makes it possible to use CERAMIC the circuits as programmable counters. A Count Enable (CE) input serves as CASE 620-09 the carry / borrow input in multi-stage counters. An Up / Down Count Control (U/D) input determines whether a circuit counts up or down. A Terminal Count 16 (TC) output and a Ripple Clock (RC) output provide overflow/underflow 1 indication and make possible a variety of methods for generating carry / borrow signals in multistage counter applications. 16 N SUFFIX 1 PLASTIC • Low Power . . . 90 mW Typical Dissipation CASE 648-08 • High Speed . . . 25 MHz Typical Count Frequency • Synchronous Counting D SUFFIX • Asynchronous Parallel Load SOIC • Individual Preset Inputs • Count Enable and Up / Down Control Inputs CASE 751B-03 • Cascadable • Input Clamp Diodes Limit High Speed Termination Effects CONNECTION DIAGRAM DIP (TOP VIEW) 16 1 VCC P0 CP RC TC PL P2 P3 16 15 14 13 12 11 10 9 ORDERING INFORMATION NOTE: SN54LSXXXJ Ceramic The Flatpak version SN74LSXXXN Plastic has the same pinouts SN74LSXXXD SOIC (Connection Diagram) as the Dual In-Line Package. 1 2 3 4 56 78 LOGIC SYMBOL P1 Q1 Q0 CE U/D Q2 Q3 GND 11 15 1 10 9 PIN NAMES LOADING (Note a) HIGH LOW 5 PL P0 P1 P2 P3 13 U/D RC CE Count Enable (Active LOW) Input 1.5 U.L. 0.7 U.L. 4 CE CP Clock Pulse (Active HIGH going edge) Input 0.5 U.L. 0.25 U.L. 14 CP TC 12 U / D Up/Down Count Control Input 0.5 U.L. 0.25 U.L. Q0 Q1 Q2 Q3 PL Parallel Load Control (Active LOW) Input 0.5 U.L. 0.25 U.L. Pn Parallel Data Inputs 0.5 U.L. 0.25 U.L. 32 6 7 Qn Flip-Flop Outputs (Note b) 10 U.L. 5 (2.5) U.L. RC Ripple Clock Output (Note b) 10 U.L. 5 (2.5) U.L. VCC = PIN 16 GND = PIN 8 TC Terminal Count Output (Note b) 10 U.L. 5 (2.5) U.L. NOTES: a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) b. Temperature Ranges. FAST AND LS TTL DATA 5-205

SN54/74LS190 • SN54/74LS191 STATE DIAGRAMS 0123 4 LS190 0123 4 15 5 UP: TC = Q0 ⋅ Q3 ⋅ (U/D) 15 5 14 6 DOWN: TC = Q0 ⋅ Q1 ⋅ Q2 ⋅ Q3 ⋅ (U/D) 14 6 13 7 13 7 12 11 10 9 8 LS191 12 11 10 9 8 UP: TC = Q0 ⋅ Q1 ⋅ Q2 ⋅ Q3 ⋅ (U/D) LS190 DOWN: TC = Q0 ⋅ Q1 ⋅ Q2 ⋅ Q3 ⋅ (U/D) COUNT UP COUNT DOWN LS191 LOGIC DIAGRAMS CP U/D P0 CE P1 P2 P3 PL 14 5 15 4 1 10 9 11 J CLOCK K J CLOCK K J CLOCK K J CLOCK K PRESET CLEAR PRESET CLEAR PRESET CLEAR PRESET CLEAR QQ QQ QQ QQ 13 12 3 26 7 RC TC Q0 Q1 Q2 Q3 VCC = PIN 16 DECADE COUNTER GND = PIN 8 LS190 = PIN NUMBERS FAST AND LS TTL DATA 5-206

SN54/74LS190 • SN54/74LS191 LOGIC DIAGRAMS (continued) CP U/D P0 CE P1 P2 P3 PL 14 5 15 4 1 10 9 11 13 12 J CLOCK K J CLOCK K J CLOCK K J CLOCK K PRESET CLEAR PRESET CLEAR PRESET CLEAR PRESET CLEAR RC TC QQ QQ QQ QQ VCC = PIN 16 GND = PIN 8 3 2 6 7 = PIN NUMBERS Q0 Q1 Q2 Q3 BINARY COUNTER LS191 FAST AND LS TTL DATA 5-207

SN54/74LS190 • SN54/74LS191 FUNCTIONAL DESCRIPTION Clock (RC) output. The RC output is normally HIGH. When CE is LOW and TC is HIGH, the RC output will go LOW when the The LS190 is a synchronous Up / Down BCD Decade clock next goes LOW and will stay LOW until the clock goes Counter and the LS191 is a synchronous Up / Down 4-Bit HIGH again. This feature simplifies the design of multi-stage Binary Counter. The operating modes of the LS190 decade counters, as indicated in Figures a and b. In Figure a, each RC counter and the LS191 binary counter are identical, with the output is used as the clock input for the next higher stage. This only difference being the count sequences as noted in the configuration is particularly advantageous when the clock state diagrams. Each circuit contains four master / slave source has a limited drive capability, since it drives only the flip-flops, with internal gating and steering logic to provide first stage. To prevent counting in all stages it is only necessary individual preset, count-up and count-down operations. to inhibit the first stage, since a HIGH signal on CE inhibits the RC output pulse, as indicated in the RC Truth Table. A Each circuit has an asynchronous parallel load capability disadvantage of this configuration, in some applications, is the permitting the counter to be preset to any desired number. timing skew between state changes in the first and last stages. When the Parallel Load (PL) input is LOW, information present This represents the cumulative delay of the clock as it ripples on the Parallel Data inputs (P0 – P3) is loaded into the counter through the preceding stages. and appears on the Q outputs. This operation overrides the counting functions, as indicated in the Mode Select Table. A method of causing state changes to occur simultaneously in all stages is shown in Figure b. All clock inputs are driven in A HIGH signal on the CE input inhibits counting. When CE is parallel and the RC outputs propagate the carry / borrow LOW, internal state change are initiated synchronously by the signals in ripple fashion. In this configuration the LOW state LOW-to-HIGH transition of the clock input. The direction of duration of the clock must be long enough to allow the counting is determined by the U/D input signal, as indicated in negative-going edge of the carry / borrow signal to ripple the Mode Select Table. When counting is to be enabled, the through to the last stop before the clock goes HIGH. There is CE signal can be made LOW when the clock is in either state. no such restriction on the HIGH state duration of the clock, However, when counting is to be inhibited, the LOW-to-HIGH since the RC output of any package goes HIGH shortly after its CE transition must occur only while the clock is HIGH. CP input goes HIGH. Similarly, the U / D signal should only be changed when either CE or the clock is HIGH. The configuration shown in Figure c avoids ripple delays and their associated restrictions. The CE input signal for a Two types of outputs are provided as overflow/underflow given stage is formed by combining the TC signals from all the indicators. The Terminal Count (TC) output is normally LOW preceding stages. Note that in order to inhibit counting an and goes HIGH when a circuit reaches zero in the count-down enable signal must be included in each carry gate. The simple mode or reaches maximum (9 for the LS190, 15 for the LS191) inhibit scheme of Figures a and b doesn’t apply, because the in the count-up mode. The TC output will then remain HIGH TC output of a given stage is not affected by its own CE. until a state change occurs, whether by counting or presetting or until U / D is changed. The TC output should not be used as a clock signal because it is subject to decoding spikes. The TC signal is also used internally to enable the Ripple MODE SELECT TABLE RC TRUTH TABLE INPUTS MODE INPUTS RC PL CE U / D CP CE TC* CP OUTPUT H LL Count Up LH H XX H LH Count Down X LX H H L X X X Preset (Asyn.) H H X X No Change (Hold) * TC is generated internally L = LOW Voltage Level H = HIGH Voltage Level X = Don’t Care = LOW-to-HIGH Clock Transition = LOW Pulse FAST AND LS TTL DATA 5-208

SN54/74LS190 • SN54/74LS191 GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 4.5 5.0 5.5 V 74 4.75 5.0 5.25 TA Operating Ambient Temperature Range 54 – 55 25 125 °C 74 0 25 70 IOH Output Current — High 54, 74 – 0.4 mA IOL Output Current — Low 54 4.0 mA 74 8.0 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter Min Typ Max Unit Test Conditions VIH Input HIGH Voltage 2.0 Guaranteed Input HIGH Voltage for V All Inputs 54 0.7 Guaranteed Input LOW Voltage for VIL Input LOW Voltage 74 0.8 V All Inputs VIK Input Clamp Diode Voltage – 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA VOH Output HIGH Voltage 54 2.5 3.5 V VCC = MIN, IOH = MAX, VIN = VIH 74 2.7 3.5 V or VIL per Truth Table VOL Output LOW Voltage 54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN, 74 0.35 0.5 V IOL = 8.0 mA VIN = VIL or VIH per Truth Table Input HIGH Current 20 µA VCC = MAX, VIN = 2.7 V Other Inputs 60 IIH CE 0.1 mA VCC = MAX, VIN = 7.0 V Other Inputs 0.3 CE Input LOW Current – 0.4 mA VCC = MAX, VIN = 0.4 V – 1.2 IIL Other Inputs CE IOS Short Circuit Current (Note 1) – 20 – 100 mA VCC = MAX ICC Power Supply Current 35 mA VCC = MAX Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. FAST AND LS TTL DATA 5-209

SN54/74LS190 • SN54/74LS191 AC CHARACTERISTICS (TA = 25°C) Symbol Parameter Limits Unit Test Conditions Maximum Clock Frequency MHz fMAX Propagation Delay, Min Typ Max VCC = 5.0 V PL to Output Q ns CL = 15 pF tPLH Data to Output Q 20 25 ns tPHL ns Test Conditions Clock to RC 22 33 ns VCC = 5.0 V tPLH 33 50 ns tPHL Clock to Output Q ns 20 32 ns tPLH Clock to TC 27 40 ns tPHL U / D to RC 13 20 tPLH 16 24 tPHL U / D to TC 16 24 tPLH CE to RC 24 36 tPHL 28 42 tPLH 37 52 tPHL 30 45 tPLH 30 45 tPHL 21 33 tPLH 22 33 tPHL 21 33 22 33 AC SETUP REQUIREMENTS (TA = 25°C) Symbol Parameter Limits Unit CP Pulse Width Min Typ Max ns tW PL Pulse Width 25 ns tW Data Setup Time 35 ns ts Data Hold Time 20 ns th Recovery Time 5.0 ns trec 40 DEFINITIONS OF TERMS tion. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from LOW- SETUP TIME (ts) is defined as the minimum time required for to-HIGH and still be recognized. the correct logic level to be present at the logic input prior to the clock transition from LOW-to-HIGH in order to be recognized RECOVERY TIME (trec) is defined as the minimum time and transferred to the outputs. required between the end of the reset pulse and the clock transition from LOW-to-HIGH in order to recognize and HOLD TIME (th) is defined as the minimum time following the transfer HIGH data to the Q outputs. clock transition from LOW-to-HIGH that the logic level must be maintained at the input in order to ensure continued recogni- FAST AND LS TTL DATA 5-210

SN54/74LS190 • SN54/74LS191 DIRECTION U/D RC U/D RC U/D RC CONTROL CE CE CE CP CP CP ENABLE CLOCK Figure a. n-Stage Counter Using Ripple Clock DIRECTION U/D RC U/D RC U/D RC CONTROL CE CE CE CP CP CP ENABLE CLOCK Figure b. Synchronous n-Stage Counter Using Ripple Carry / Borrow DIRECTION CONTROL ENABLE U/D U/D U/D CE CE CP TC CE CP TC CP TC CLOCK Figure c. Synchronous n-Stage Counter with Parallel Gated Carry / Borrow FAST AND LS TTL DATA 5-211

SN54/74LS190 • SN54/74LS191 AC WAVEFORMS CP 1.3 V 1/f MAX 1.3 V CP OR CE 1.3 V 1.3 V Q OR TC tW 1.3 V RC tPHL 1.3 V tPLH tPHL tPLH 1.3 V 1.3 V Figure 2 Figure 1 Pn 1.3 V 1.3 V Pn tW tPHL 1.3 V tPLH PL 1.3 V 1.3 V Qn tPLH Figure 4 Qn tPHL NOTE: PL = LOW Figure 3 Pn 1.3 V 1.3 V PL 1.3 V ts(H) th(H) th(L) tW trec PL ts(L) 1.3 V CP 1.3 V 1.3 V Q Qn Q = P Q=P Figure 5 * The shaded areas indicate when the input is permitted * to change for predictable output performance Figure 6 U/D 1.3 V tPHL CP 1.3 V th(L) th(H) tPLH 1.3 V 1.3 V ts(L) 1.3 V ts(H) TC 1.3 V tPLH CE CE MAY (H-L) CE MAY 1.3 V tPHL Figure 7 1.3 V CHANGE only CHANGE RC Figure 8 FAST AND LS TTL DATA 5-212

PRESETTABLE BCD/DECADE SN54/74LS192 UP/DOWN COUNTER SN54/74LS193 PRESETTABLE 4-BIT BINARY PRESETTABLE BCD / DECADE UP/DOWN COUNTER UP/ DOWN COUNTER The SN54/74LS192 is an UP/DOWN BCD Decade (8421) Counter and the PRESETTABLE 4-BIT BINARY SN54/74LS193 is an UP/DOWN MODULO-16 Binary Counter. Separate UP/ DOWN COUNTER Count Up and Count Down Clocks are used and in either counting mode the circuits operate synchronously. The outputs change state synchronous with LOW POWER SCHOTTKY the LOW-to-HIGH transitions on the clock inputs. J SUFFIX Separate Terminal Count Up and Terminal Count Down outputs are CERAMIC provided which are used as the clocks for a subsequent stages without extra CASE 620-09 logic, thus simplifying multistage counter designs. Individual preset inputs allow the circuits to be used as programmable counters. Both the Parallel 16 Load (PL) and the Master Reset (MR) inputs asynchronously override the 1 clocks. 16 N SUFFIX • Low Power . . . 95 mW Typical Dissipation 1 PLASTIC • High Speed . . . 40 MHz Typical Count Frequency CASE 648-08 • Synchronous Counting • Asynchronous Master Reset and Parallel Load • Individual Preset Inputs • Cascading Circuitry Internally Provided • Input Clamp Diodes Limit High Speed Termination Effects CONNECTION DIAGRAM DIP (TOP VIEW) 16 D SUFFIX VCC P0 MR TCD TCU PL P2 P3 1 SOIC 16 15 14 13 12 11 10 9 CASE 751B-03 ORDERING INFORMATION NOTE: SN54LSXXXJ Ceramic The Flatpak version SN74LSXXXN Plastic has the same pinouts SN74LSXXXD SOIC (Connection Diagram) as the Dual In-Line Package. 1 2 3 4 56 78 LOGIC SYMBOL P1 Q1 Q0 CPD CPU Q2 Q3 GND 11 15 1 10 9 PIN NAMES LOADING (Note a) HIGH LOW PL P0 P1 P2 P3 CPU Count Up Clock Pulse Input 0.5 U.L. 0.25 U.L. 5 CPU TCU 12 CPD Count Down Clock Pulse Input 0.5 U.L. 0.25 U.L. MR Asynchronous Master Reset (Clear) Input 0.5 U.L. 0.25 U.L. 4 CPD Q3TCD 13 MR Q0 Q1 PL Asynchronous Parallel Load (Active LOW) Input 0.5 U.L. 0.25 U.L. Q2 Pn Parallel Data Inputs 0.5 U.L. 0.25 U.L. 14 3 2 6 7 Qn Flip-Flop Outputs (Note b) 10 U.L. 5 (2.5) U.L. TCD Terminal Count Down (Borrow) Output (Note b) 10 U.L. 5 (2.5) U.L. VCC = PIN 16 TCU Terminal Count Up (Carry) Output (Note b) 10 U.L. 5 (2.5) U.L. GND = PIN 8 NOTES: a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) b. Temperature Ranges. FAST AND LS TTL DATA 5-213

SN54/74LS192 • SN54/74LS193 STATE DIAGRAMS 0123 4 LS192 LOGIC EQUATIONS 0123 4 15 5 FOR TERMINAL COUNT 15 5 14 6 TCU = Q0 ⋅ Q3 ⋅ CPU 14 6 13 7 TCD = Q0 ⋅ Q1 ⋅ Q2 ⋅ Q3 ⋅ CPD 13 7 12 11 10 9 8 12 11 10 9 8 LS193 LOGIC EQUATIONS LS192 FOR TERMINAL COUNT LS193 TCU = Q0 ⋅ Q1⋅ Q2⋅ Q3 ⋅ CPU TCD = Q0 ⋅ Q1 ⋅ Q2 ⋅ Q3 ⋅ CPD COUNT UP COUNT DOWN LOGIC DIAGRAMS P0 P1 P2 P3 PL 11 15 1 10 9 (LOAD) 12 TCU CPU 5 (CARRY (UP COUNT) OUTPUT) SD Q SD Q SD Q SD Q T T T T CD Q CD Q CD Q CD Q CPD 4 13 TCD (DOWN (BORROW OUTPUT) COUNT) 14 MR 7 (CLEAR) 3 2 6 Q3 Q0 Q1 Q2 VCC = PIN 16 LS192 GND = PIN 8 = PIN NUMBERS FAST AND LS TTL DATA 5-214

SN54/74LS192 • SN54/74LS193 LOGIC DIAGRAMS (continued) P0 P1 P2 P3 PL 11 15 1 10 9 (LOAD) 12 TCU CPU 5 (CARRY (UP COUNT) OUTPUT) SD Q SD Q SD Q SD Q T T T T CD Q CD Q CD Q CD Q CPD 4 13 TCD (DOWN (BORROW OUTPUT) COUNT) 14 MR 7 (CLEAR) 3 2 6 Q3 Q0 Q1 Q2 LS193 VCC = PIN 16 GND = PIN 8 = PIN NUMBERS FAST AND LS TTL DATA 5-215

SN54/74LS192 • SN54/74LS193 FUNCTIONAL DESCRIPTION The Terminal Count Up (TCU) and Terminal Count Down (TCD) outputs are normally HIGH. When a circuit has reached The LS192 and LS193 are Asynchronously Presettable the maximum count state (9 for the LS192, 15 for the LS193), Decade and 4-Bit Binary Synchronous UP / DOWN (Revers- able) Counters. The operating modes of the LS192 decade the next HIGH-to-LOW transition of the Count Up Clock will counter and the LS193 binary counter are identical, with the only difference being the count sequences as noted in the cause TCU to go LOW. TCU will stay LOW until CPU goes State Diagrams. Each circuit contains four master/slave HIGH again, thus effectively repeating the Count Up Clock, flip-flops, with internal gating and steering logic to provide master reset, individual preset, count up and count down but delayed by two gate delays. Similarly, the TCD output will operations. go LOW when the circuit is in the zero state and the Count Each flip-flop contains JK feedback from slave to master Down Clock goes LOW. Since the TC outputs repeat the clock such that a LOW-to-HIGH transition on its T input causes the slave, and thus the Q output to change state. Synchronous waveforms, they can be used as the clock input signals to the switching, as opposed to ripple counting, is achieved by driving the steering gates of all stages from a common Count next higher order circuit in a multistage counter. Up line and a common Count Down line, thereby causing all state changes to be initiated simultaneously. A LOW-to-HIGH Each circuit has an asynchronous parallel load capability transition on the Count Up input will advance the count by one; a similar transition on the Count Down input will decrease the permitting the counter to be preset. When the Parallel Load count by one. While counting with one clock input, the other should be held HIGH. Otherwise, the circuit will either count by (PL) and the Master Reset (MR) inputs are LOW, information twos or not at all, depending on the state of the first flip-flop, which cannot toggle as long as either Clock input is LOW. present on the Parallel Data inputs (P0, P3) is loaded into the counter and appears on the outputs regardless of the conditions of the clock inputs. A HIGH signal on the Master Reset input will disable the preset gates, override both Clock inputs, and latch each Q output in the LOW state. If one of the Clock inputs is LOW during and after a reset or load operation, the next LOW-to-HIGH transition of that Clock will be interpreted as a legitimate signal and will be counted. MODE SELECT TABLE MR PL CPU CPD MODE X HX X X Reset (Asyn.) LL H X Preset (Asyn.) LH H No Change LH H H Count Up LH Count Down L = LOW Voltage Level H = HIGH Voltage Level X = Don’t Care = LOW-to-HIGH Clock Transition FAST AND LS TTL DATA 5-216

SN54/74LS192 • SN54/74LS193 GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 4.5 5.0 5.5 V 74 4.75 5.0 5.25 TA Operating Ambient Temperature Range 54 – 55 25 125 °C 74 0 25 70 IOH Output Current — High 54, 74 – 0.4 mA IOL Output Current — Low 54 4.0 mA 74 8.0 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter Min Typ Max Unit Test Conditions VIH Input HIGH Voltage 2.0 Guaranteed Input HIGH Voltage for V All Inputs VIL Input LOW Voltage 54 0.7 Guaranteed Input LOW Voltage for 74 0.8 V All Inputs VIK Input Clamp Diode Voltage 54 – 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA VOH Output HIGH Voltage 74 2.5 3.5 2.7 3.5 V VCC = MIN, IOH = MAX, VIN = VIH V or VIL per Truth Table VOL Output LOW Voltage 54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN, 74 0.35 0.5 V IOL = 8.0 mA VIN = VIL or VIH per Truth Table IIH Input HIGH Current 20 µA VCC = MAX, VIN = 2.7 V 0.1 mA VCC = MAX, VIN = 7.0 V mA VCC = MAX, VIN = 0.4 V IIL Input LOW Current – 0.4 mA VCC = MAX mA VCC = MAX IOS Short Circuit Current (Note 1) – 20 – 100 ICC Power Supply Current 34 Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C) Symbol Parameter Limits Unit Test Conditions Maximum Clock Frequency Min Typ Max MHz fMAX CPU Input to 25 32 VCC = 5.0 V TCU Output ns CL = 15 pF tPLH CPD Input to 17 26 tPHL TCD Output 18 24 ns tPLH Clock to Q 16 24 ns tPHL 15 24 PL to Q ns tPLH 27 38 ns tPHL MR Input to Any Output 30 47 tPLH 24 40 tPHL 25 40 tPHL 23 35 FAST AND LS TTL DATA 5-217

SN54/74LS192 • SN54/74LS193 AC SETUP REQUIREMENTS (TA = 25°C) Symbol Parameter Limits Unit Test Conditions Any Pulse Width Min Typ Max ns VCC = 5.0 V tW Data Setup Time 20 ns ts Data Hold Time 20 ns th Recovery Time 5.0 ns trec 40 DEFINITIONS OF TERMS tion. A negative HOLD TIME indicates that the correct logic level may be released prior to the PL transition from SETUP TIME (ts) is defined as the minimum time required for LOW-to-HIGH and still be recognized. the correct logic level to be present at the logic input prior to the PL transition from LOW-to-HIGH in order to be recognized and RECOVERY TIME (trec) is defined as the minimum time transferred to the outputs. required between the end of the reset pulse and the clock transition from LOW-to-HIGH in order to recognize and HOLD TIME (th) is defined as the minimum time following the transfer HIGH data to the Q outputs. PL transition from LOW-to-HIGH that the logic level must be maintained at the input in order to ensure continued recogni- FAST AND LS TTL DATA 5-218

SN54/74LS192 • SN54/74LS193 AC WAVEFORMS CPU or CPD 1.3 V tW 1.3 V Q tPLH 1.3 V tPHL 1.3 V Figure 1 CPU or CPD 1.3 V Pn 1.3 V tPLH TCU or TCD tPHL tPHL tPLH 1.3 V Qn 1.3 V Figure 2 NOTE: PL = LOW Figure 3 Pn 1.3 V PL tW 1.3 V trec CPU or CPD tPHL 1.3 V tw tPHL PL 1.3 V Q 1.3 V tPLH Qn 1.3 V Figure 4 Figure 5 Pn 1.3 V 1.3 V ts(H) th(H) th(L) 1.3 V PL ts(L) trec MR tW 1.3 V CPU or CPD tPHL 1.3 V Qn Q = P Q=P Q 1.3 V * The shaded areas indicate when the input is permitted * to change for predictable output performance Figure 6 Figure 7 FAST AND LS TTL DATA 5-219

SN54/74LS194A 4-BIT BIDIRECTIONAL 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER UNIVERSAL SHIFT REGISTER The SN54 / 74LS194A is a High Speed 4-Bit Bidirectional Universal Shift LOW POWER SCHOTTKY Register. As a high speed multifunctional sequential building block, it is useful in a wide variety of applications. It may be used in serial-serial, shift left, shift J SUFFIX right, serial-parallel, parallel-serial, and parallel-parallel data register trans- CERAMIC fers. The LS194A is similar in operation to the LS195A Universal Shift CASE 620-09 Register, with added features of shift left without external connections and hold (do nothing) modes of operation. It utilizes the Schottky diode clamped 16 process to achieve high speeds and is fully compatible with all Motorola TTL 1 families. • Typical Shift Frequency of 36 MHz 16 N SUFFIX • Asynchronous Master Reset 1 PLASTIC • Hold (Do Nothing) Mode CASE 648-08 • Fully Synchronous Serial or Parallel Data Transfers • Input Clamp Diodes Limit High Speed Termination Effects CONNECTION DIAGRAM DIP (TOP VIEW) VCC Q0 Q1 Q2 Q3 CP S1 S0 16 15 14 13 12 11 10 9 16 D SUFFIX 1 SOIC CASE 751B-03 1 2 3 4 56 78 ORDERING INFORMATION MR DSR P0 P1 P2 P3 DSL GND SN54LSXXXJ Ceramic SN74LSXXXN Plastic SN74LSXXXD SOIC PIN NAMES LOADING (Note a) HIGH LOW S0, S1 Mode Control Inputs 0.5 U.L. 0.25 U.L. P0 – P3 Parallel Data Inputs 0.5 U.L. 0.25 U.L. DSR Serial (Shift Right) Data Input 0.5 U.L. 0.25 U.L. DSL Serial (Shift Left) Data Input 0.5 U.L. 0.25 U.L. CP Clock (Active HIGH Going Edge) Input 0.5 U.L. 0.25 U.L. Master Reset (Active LOW) Input 0.5 U.L. 0.25 U.L. MR Parallel Outputs (Note b) 10 U.L. 5 (2.5) U.L. Q0 – Q3 NOTES: a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) b. Temperature Ranges. FAST AND LS TTL DATA 5-220

LOGIC DIAGRAM P0 SN54 / 74LS194A P3 10 3 P1 P2 6 S1 45 7 9 DSL S0 2 DSR VCC = PIN 16 S Q0 S Q1 S Q2 S Q3 GND = PIN 8 CP CP CP CP R R R R = PIN NUMBERS CLEAR CLEAR CLEAR CLEAR 11 15 14 13 12 CP Q0 Q1 Q2 Q3 1 MR FUNCTIONAL DESCRIPTION The Logic Diagram and Truth Table indicate the functional Q3 outputs respectively following the next LOW to HIGH characteristics of the LS194A 4-Bit Bidirectional Shift Regis- transition of the clock. ter. The LS194A is similar in operation to the Motorola LS195A Universal Shift Register when used in serial or parallel data The asynchronous Master Reset (MR), when LOW, over- register transfers. Some of the common features of the two devices are described below: rides all other input conditions and forces the Q outputs LOW. All data and mode control inputs are edge-triggered, Special logic features of the LS194A design which increase responding only to the LOW to HIGH transition of the Clock (CP). The only timing restriction, therefore, is that the mode the range of application are described below: control and selected data inputs must be stable one set-up time prior to the positive transition of the clock pulse. Two mode control inputs (S0, S1) determine the synchro- nous operation of the device. As shown in the Mode Selection The register is fully synchronous, with all operations taking place in less than 15 ns (typical) making the device especially Table, data can be entered and shifted from left to right (shift useful for implementing very high speed CPUs, or the memory right, Q0 → Q1, etc.) or right to left (shift left, Q3 → Q2, etc.), or buffer registers. parallel data can be entered loading all four bits of the register The four parallel data inputs (P0, P1, P2, P3) are D-type simultaneously. When both S0 and S1,are LOW, the existing inputs. When both S0 and S1 are HIGH, the data appearing on data is retained in a “do nothing” mode without restricting the P0, P1, P2, and P3 inputs is transferred to the Q0, Q1, Q2, and HIGH to LOW clock transition. D-type serial data inputs (DSR, DSL) are provided on both the first and last stages to allow multistage shift right or shift left data transfers without interfering with parallel load operation. MODE SELECT — TRUTH TABLE OPERATING MODE MR S1 INPUTS OUTPUTS Q3 Reset LX S0 DSR DSL Pn Q0 Q1 Q2 L XX X X LL L Hold HI I X X X q0 q1 q2 q3 Shift Left Hh I X I X q1 q2 q3 L H Hh I X h X q1 q2 q3 Shift Right HIh I X X L q0 q1 q2 HIh h X X H q0 q1 q2 Parallel Load Hh h X X Pn P0 P1 P2 P3 L = LOW Voltage Level H = HIGH Voltage Level X = Don’t Care I = LOW voltage level one set-up time prior to the LOW to HIGH clock transition h = HIGH voltage level one set-up time prior to the LOW to HIGH clock transition pn (qn) = Lower case letters indicate the state of the referenced input (or output) one set-up time prior to the LOW to HIGH clock transition. FAST AND LS TTL DATA 5-221

SN54 / 74LS194A GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 4.5 5.0 5.5 V 74 4.75 5.0 5.25 TA Operating Ambient Temperature Range 54 – 55 25 125 °C 74 0 25 70 IOH Output Current — High 54, 74 – 0.4 mA IOL Output Current — Low 54 4.0 mA 74 8.0 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter Min Typ Max Unit Test Conditions VIH Input HIGH Voltage 2.0 Guaranteed Input HIGH Voltage for V All Inputs VIL Input LOW Voltage 54 0.7 Guaranteed Input LOW Voltage for 74 0.8 V All Inputs VIK Input Clamp Diode Voltage – 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA VOH Output HIGH Voltage 54 2.5 3.5 V VCC = MIN, IOH = MAX, VIN = VIH 74 2.7 3.5 V or VIL per Truth Table VOL Output LOW Voltage 54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN, 74 0.35 0.5 V IOL = 8.0 mA VIN = VIL or VIH per Truth Table IIH Input HIGH Current 20 µA VCC = MAX, VIN = 2.7 V 0.1 mA VCC = MAX, VIN = 7.0 V mA VCC = MAX, VIN = 0.4 V IIL Input LOW Current – 0.4 mA VCC = MAX mA VCC = MAX IOS Short Circuit Current (Note 1) – 20 – 100 ICC Power Supply Current 23 Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C) Symbol Parameter Limits Unit Test Conditions fMAX Min Typ Max MHz tPLH Maximum Clock Frequency 25 36 VCC = 5.0 V tPHL ns CL = 15 pF Propagation Delay, 14 22 tPHL Clock to Output 17 26 ns Propagation Delay, 19 30 MR to Output FAST AND LS TTL DATA 5-222

SN54 / 74LS194A AC SETUP REQUIREMENTS (TA = 25°C) Symbol Parameter Limits Unit Test Conditions Clock or MR Pulse Width Min Typ Max ns VCC = 5.0 V tW Mode Control Setup Time 20 ns ts Data Setup Time 30 ns ts Hold time, Any Input 20 ns th Recovery Time ns trec 0 25 DEFINITIONS OF TERMS recognition. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from SETUP TIME(ts) —is defined as the minimum time required LOW to HIGH and still be recognized. for the correct logic level to be present at the logic input prior to the clock transition from LOW to HIGH in order to be RECOVERY TIME (trec) — is defined as the minimum time recognized and transferred to the outputs. required between the end of the reset pulse and the clock transition from LOW to HIGH in order to recognize and transfer HOLD TIME (th) — is defined as the minimum time following HIGH Data to the Q outputs. the clock transition from LOW to HIGH that the logic level must be maintained at the input in order to ensure continued AC WAVEFORMS The shaded areas indicate when the input is permitted to change for predictable output performance. 1/fmax 1.3 V S0 (––– IS SHIFT LEFT) 1.3 V S1 CLOCK tPLH DSR DSL 1.3 V tW 1.3 V ts(H) tPHL OUTPUT 1.3 V th(H) = 0 OTHER CONDITIONS: S1 = L, MR = H, S0 = H P0 P1 P2 P3 ts(L) ts(L) 1.3 V th(L) = 0 Figure 1. Clock to Output Delays Clock Pulse th(L) = 0 Width and fmax CLOCK ts(H) OUTPUT* th(H) = 0 1.3 V MR 1.3 V trec OTHER CONDITIONS: MR = H tW 1.3 V OTHER CONDITIONS: *DSR SET-UP TIME AFFECTS Q0 ONLY CLOCK OTHER CONDITIONS: DSL SET-UP TIME AFFECTS Q3 ONLY OUTPUT tPHL 1.3 V Figure 3. Setup (ts) and Hold (th) Time for Serial Data (DSR, DSL) and Parallel Data (P0, P1, P2, P3) (STABLE TIME) OTHER CONDITIONS: S0, S1 = H S0 S1 ts th = 0 1.3 V OTHER CONDITIONS: PO = P1 = P2 = P3 = H CLOCK th = 0 1.3 V ts Figure 2. Master Reset Pulse Width, Master Reset 1.3 V to Output Delay and Master Reset to Clock Recovery Time OTHER CONDITIONS: MR = H Figure 4. Setup (ts) and Hold (th) Time for S Input FAST AND LS TTL DATA 5-223

SN54/74LS195A UNIVERSAL 4-BIT UNIVERSAL 4-BIT SHIFT REGISTER SHIFT REGISTER The SN54 / 74LS195A is a high speed 4-Bit Shift Register offering typical LOW POWER SCHOTTKY shift frequencies of 39 MHz. It is useful for a wide variety of register and counting applications. It utilizes the Schottky diode clamped process to achieve high speeds and is fully compatible with all Motorola TTL products. • Typical Shift Right Frequency of 39 MHz • Asynchronous Master Reset • J, K Inputs to First Stage • Fully Synchronous Serial or Parallel Data Transfers • Input Clamp Diodes Limit High Speed Termination Effects CONNECTION DIAGRAM DIP (TOP VIEW) J SUFFIX VCC Q0 Q1 Q2 Q3 Q3 CP PE CERAMIC 16 15 14 13 12 11 10 9 CASE 620-09 NOTE: 16 The Flatpak version 1 has the same pinouts (Connection Diagram) as 16 N SUFFIX the Dual In-Line Package. 1 PLASTIC CASE 648-08 12 3 4 56 78 MR J K P0 P1 P2 P3 GND 16 D SUFFIX 1 SOIC CASE 751B-03 PIN NAMES LOADING (Note a) HIGH LOW PE Parallel Enable (Active LOW) Input 0.5 U.L. 0.25 U.L. ORDERING INFORMATION Parallel Data Inputs 0.5 U.L. 0.25 U.L. P0 – P3 First Stage J (Active HIGH) Input 0.5 U.L. 0.25 U.L. SN54LSXXXJ Ceramic J First Stage K (Active LOW) Input 0.5 U.L. 0.25 U.L. SN74LSXXXN Plastic Clock (Active HIGH Going Edge) Input 0.5 U.L. 0.25 U.L. SN74LSXXXD SOIC K Master Reset (Active LOW) Input 0.5 U.L. 0.25 U.L. Parallel Outputs (Note b) 10 U.L. 5 (2.5) U.L. LOGIC SYMBOL CP Complementary Last Stage Output (Note b) 10 U.L. 5 (2.5) U.L. 9456 7 MR Q0 – Q3 Q3 NOTES: 2 J PE P0 P1 P2 P3 a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) b. Temperature Ranges. 10 CP Q3 11 3 K MR Q0 Q1 Q2 Q3 1 15 14 13 12 VCC = PIN 16 GND = PIN 8 FAST AND LS TTL DATA 5-224

SN54 / 74LS195A LOGIC DIAGRAM PE J K P0 P1 P2 P3 MR CP 923 4 5 6 7 1 10 R CD Q0 R CD R CD R CD Q3 CP CP CP CP S Q0 S Q2 S Q3 S Q0 14 13 12 11 VCC = PIN 16 15 Q1 Q2 Q3 Q3 GND = PIN 8 Q0 = PIN NUMBERS FUNCTIONAL DESCRIPTION pins together. When the PE input is LOW, the LS195A appears The Logic Diagram and Truth Table indicate the functional as four common clocked D flip-flops. The data on the parallel characteristics of the LS195A 4-Bit Shift Register. The device is useful in a wide variety of shifting, counting and storage inputs P0, P1, P2, P3 is transferred to the respective Q0, Q1, applications. It performs serial, parallel, serial to parallel, or Q2, Q3 outputs following the LOW to HIGH clock transition. parallel to serial data transfers at very high speeds. Shift left operations (Q3 → Q2) can be achieved by tying the Qn Outputs to the Pn–1 inputs and holding the PE input LOW. The LS195A has two primary modes of operation, shift right (Q0 → Q1) and parallel load which are controlled by the state of All serial and parallel data transfers are synchronous, the Parallel Enable (PE) input. When the PE input is HIGH, serial data enters the first flip-flop Q0 via the J and K inputs and occurring after each LOW to HIGH clock transition. Since the is shifted one bit in the direction Q0 → Q1 → Q2 → Q3 following each LOW to HIGH clock transition. The JK inputs provide the LS195A utilizes edge-triggering, there is no restriction on the flexibility of the JK type input for special applications, and the simple D type input for general applications by tying the two activity of the J, K, Pn and PE inputs for logic operation — except for the set-up and release time requirements. A LOW on the asynchronous Master Reset (MR) input sets all Q outputs LOW, independent of any other input condition. MODE SELECT — TRUTH TABLE OPERATING MODES INPUTS OUTPUTS Asynchronous Reset MR PE J K Pn Q0 Q1 Q2 Q3 Q3 L X XXX L L L L H Shift, Set First Stage H h h h X H q0 q1 q2 q2 Shift, Reset First H h I I X L q0 q1 q2 q2 Shift, Toggle First Stage H h h I X q0 q0 q1 q2 q2 Shift, Retain First Stage H h I h X q0 q0 q1 q2 q2 Parallel Load H I X X pn p0 p1 p2 p3 p3 L = LOW voltage levels H = HIGH voltage levels X = Don’t Care I = LOW voltage level one set-up time prior to the LOW to HIGH clock transition. h = HIGH voltage level one set-up time prior to the LOW to HIGH clock transition. pn (qn) = Lower case letters indicate the state of the referenced input (or output) one set-up time prior to the LOW to HIGH clock transition. FAST AND LS TTL DATA 5-225

SN54 / 74LS195A GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 4.5 5.0 5.5 V 74 4.75 5.0 5.25 TA Operating Ambient Temperature Range 54 – 55 25 125 °C 74 0 25 70 IOH Output Current — High 54, 74 – 0.4 mA IOL Output Current — Low mA 54 4.0 74 8.0 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter Min Typ Max Unit Test Conditions VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for All Inputs VIL Input LOW Voltage 54 0.7 Guaranteed Input LOW Voltage for 74 0.8 V All Inputs VIK Input Clamp Diode Voltage – 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA VOH Output HIGH Voltage 54 2.5 3.5 V VCC = MIN, IOH = MAX, VIN = VIH 74 2.7 3.5 V or VIL per Truth Table VOL Output LOW Voltage 54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN, 74 0.35 0.5 V IOL = 8.0 mA VIN = VIL or VIH per Truth Table IIH Input HIGH Current 20 µA VCC = MAX, VIN = 2.7 V 0.1 mA VCC = MAX, VIN = 7.0 V IIL Input LOW Current – 0.4 mA VCC = MAX, VIN = 0.4 V IOS Short Circuit Current (Note 1) – 20 – 100 mA VCC = MAX ICC Power Supply Current 21 mA VCC = MAX Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C) Limits Symbol Parameter Min Typ Max Unit Test Conditions fMAX Maximum Clock Frequency 30 39 MHz tPLH tPHL Propagation Delay, 14 22 ns VCC = 5.0 V Clock to Output 17 26 CL = 15 pF tPHL Propagation Delay, 19 30 ns MR to Output AC SETUP REQUIREMENTS (TA = 25°C) Symbol Parameter Limits Unit Test Conditions CP Clock Pulse Width Min Typ Max ns VCC = 5.0 V tW MR Pulse Width 16 ns tW PE Setup Time 12 ns ts Data Setup Time 25 ns ts Recovery Time 15 ns trec PE Release Time 25 ns trel Data Hold Time ns th 10 0 FAST AND LS TTL DATA 5-226

SN54 / 74LS195A DEFINITIONS OF TERMS recognition. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from SETUP TIME(ts) —is defined as the minimum time required LOW to HIGH and still be recognized. for the correct logic level to be present at the logic input prior to the clock transition from LOW to HIGH in order to be RECOVERY TIME (trec) — is defined as the minimum time recognized and transferred to the outputs. required between the end of the reset pulse and the clock transition from LOW to HIGH in order to recognize and transfer HOLD TIME (th) — is defined as the minimum time following HIGH Data to the Q outputs. the clock transition from LOW to HIGH that the logic level must be maintained at the input in order to ensure continued AC WAVEFORMS The shaded areas indicate when the input is permitted to change for predictable output performance. tW PE 1.3 V 1.3 V CLOCK tPLH J&K 1.3 V 1.3 V ts(H) tPHL ts(L) OUTPUT th(L) = 0 th(H) = 0 1.3 V P0 P1 P2 P3 1.3 V CONDITIONS: J = PE = MR = H ts(L) ts(H) K=L th(H) = 0 th(L) = 0 Figure 1. Clock to Output Delays and Clock Pulse Width CLOCK 1.3 V OUTPUT* MR tW CONDITIONS: MR = H 1.3 V 1.3 V *J AND K SET–UP TIME AFFECTS Q0 ONLY Figure 3. Setup (ts) and Hold (th) Time for Serial Data (J & K) and Parallel Data (P0, P1, P2, P3) CLOCK trec OUTPUT 1.3 V LOAD PARALLEL DATA LOAD SERIAL DATA SHIFT RIGHT tPHL 1.3 V PE 1.3 V 1.3 V CLOCK ts(L) trel ts(H) trel CONDITIONS: PE = L PO = P1 = P2 = P3 = H 1.3 V 1.3 V Figure 2. Master Reset Pulse Width, Master Reset OUTPUT Qn = Pn Qn* = Qn–1 to Output Delay and Master Reset to Clock Recovery Time CONDITIONS: MR = H *Q0 STATE WILL BE DETERMINED BY J AND K INPUTS . Figure 4. Setup (ts) and Hold (th) Time for PE Input FAST AND LS TTL DATA 5-227

4-STAGE PRESETTABLE SN54/74LS196 RIPPLE COUNTERS SN54/74LS197 The SN54/74LS196 decade counter is partitioned into divide-by-two and di- 4-STAGE PRESETTABLE vide-by-five sections which can be combined to count either in BCD (8, 4, 2, 1) RIPPLE COUNTERS sequence or in a bi-quinary mode producing a 50% duty cycle output. The SN54/74LS197 contains divide-by-two and divide-by-eight sections which LOW POWER SCHOTTKY can be combined to form a modulo-16 binary counter. Low Power Schottky technology is used to achieve typical count rates of 70 MHz and power dis- J SUFFIX sipation of only 80 mW. CERAMIC CASE 632-08 Both circuit types have a Master Reset (MR) input which overrides all other inputs and asynchronously forces all outputs LOW. A Parallel Load input (PL) 14 overrides clocked operations and asynchronously loads the data on the Par- 1 allel Data inputs (Pn) into the flip-flops. This preset feature makes the circuits usable as programmable counters. The circuits can also be used as 4-bit 14 N SUFFIX latches, loading data from the Parallel Data inputs when PL is LOW and stor- 1 PLASTIC ing the data when PL is HIGH. CASE 646-06 • Low Power Consumption — Typically 80 mW 14 D SUFFIX • High Counting Rates — Typically 70 MHz 1 SOIC • Choice of Counting Modes — BCD, Bi-Quinary, Binary • Asynchronous Presettable CASE 751A-02 • Asynchronous Master Reset • Easy Multistage Cascading • Input Clamp Diodes Limit High Speed Termination Effects CONNECTION DIAGRAM DIP (TOP VIEW) VCC MR Q3 P3 P1 Q1 CP0 14 13 12 11 10 9 8 NOTE: ORDERING INFORMATION The Flatpak version has the same pinouts SN54LSXXXJ Ceramic (Connection Diagram) as SN74LSXXXN Plastic the Dual In-Line Package. SN74LSXXXD SOIC 1234567 PL Q2 P2 P0 Q0 CP1 GND PIN NAMES LOADING (Note a) LOGIC SYMBOL 1 4 10 3 11 HIGH LOW 8 CP0 PL P0 P1 P2 P3 CP0 Clock (Active LOW Going Edge) 1.0 U.L. 1.5 U.L. 6 CP1 MR Q0 Q1 Q2 Q3 Input to Divide-by-Two Section 13 5 9 2 12 VCC = PIN 14 CP1 (LS196) Clock (Active LOW Going Edge) 2.0 U.L. 1.75 U.L. GND = PIN 7 Input to Divide-by-Five Section CP1 (LS197) Clock (Active LOW Going Edge) 1.0 U.L. 0.8 U.L. Input to Divide-by-Eight Section MR Master Reset (Active LOW) Input 1.0 U.L. 0.5 U.L. PL Parallel Load (Active LOW) Input 0.5 U.L. 0.25 U.L. P0–P3 Data Inputs 0.5 U.L. 0.25 U.L. Q0–Q3 Outputs (Notes b, c) 10 U.L. 5 (2.5) U.L. NOTES: a. 1 TTL Unit Load (U.L.) = 40µA HIGH/1.6 mA LOW. b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) b. Temperature Ranges. c. In addition to loading shown, Q0 can also drive CP1. FAST AND LS TTL DATA 5-228