Laptop Repair Part 1 OCR

PWM way.it is the system power supply. 2.Intel itJ:t~M;r-;la1J¥ Intel chipset standard timing Figure 8-2 is Intel chipset standard sequence diagram. PLTRsn Running <&011l CPUI'WRGO Scanned by CamScanner PWROK CLKGEN VRMPWRGD VCORE Vee VDIMM PWRBT . . . VSREF_SUS 32761l<Hz SRTCRSTI RTCRSTI VCCRTC Figure 8-2 -84-

rding to the sequence diagram shown in figure 8-2 is explained as follows. .1-1Jf:tR System State) 03: JU1U1J ~Jlj~~ l';fj • •the po er of the whole system are closed. 5: ~tJl.:tR~. :po r offstate. 4: i*~:tR~. :donnant state. 3: DiQ~. :sleeping state. 0: *m:tR~. SO:power on state. ~n the interpretation of the signal CCRTC: MmRTCEt!i~HfJ-mEt. 3V. ~i¥i.jfrl*JtfllUjCMOS~~J:t CRAM) ffJ:Et!.. CCRTC:the power supply of the South bridge RTC circuit,3Y.supply power to CMOS chip ..~.••~ insid the South bridge. \"*mRTCRST#: RTC Et!i~HfJJ:fft.m~. 3V. ICH9 l,;},J§itl1Jn7.§5-/j' RTC R1ft1§ ~, ~*~ SRTCRST#. RST#:the reset signal of the South bridge RTC circuiUY.ICH9 added another RTC reset the name is SRTCRST#. \"* m-2.768kHz : m jU 7 VCCRTC ~ RTCRST# J§. ~ rlTJ fJ& {,~ Et!.. n'T, ~m ~ 1m unning). dMijJijJJilJIt!..l3itE O.I-O.5V. 768kHz: after the South bridge receiving VCCRTC and RTCRST#,supply power to the oscillator:the crystal oscillator running.The voltage of two pins of the crystal oscillator is :sRBF_SUS: 5V ~mlt!..ffi. ~~_ U :5V standby voltage. N&<~SUS3_3: 3.3V ~m$..l3i. ~Tj.S3._3: 3.3V standby voltage. leSl:1SI_OS: Mt1fpg~IHb:~13 afJtEt!1Y-J I.OSV. 7HJTJt-t~Jt-t:fffl~~~1'Et!ffi.. OS: the South bridge internally produced the power supply 1.05V for itself,not to _*IfWhen we analyze the timing. B.3V ft'mlt!..l3ilE'J', Et!.l3i 3.3V. ~T;~$IIt!.i&. the SQUth bridge that 3.3V standby voltage is nonnal voltage 3.3V is -85- Scanned by CamScanner

PWRBTN#: POWER BUTTON.3.3V-O-3.3Y pulse signal. • SLP_S5#: 3.3Y, F-iHJi:ill.[L\\~~1Lt'C~O~4~*U1§~o SLP_S5#: 3.3Y.the control signal when the South bridge exit the power off state. • SLP_S4#: 3.3Y, i¥i#fill:±lf*lJ~:\\7C~O~~*U1§~o (-fJ~ S5#%n s4#9:W-ffl--\"j , )=1=1:* ~*IJjft~l*J1'¥f~rg, !f!J--t£~o) SLP_S4#: 3.3V,the control signal when the South bridge exit the donnant state.(usually just use S5# or S4#,used to control the production ofthe memory power supply,and another is idle.) • SLP_S3#: 3.3Y, i¥Jm=i1HI:\\lJjlJ~t'C~B~~*IH§~0 (-!RJ=iHt~~*'Jm=1fr-~, }~.~ W It, ~!ll~~It, CPU fAlt~.) SLP_S3#: 3.3V,the control signal when the South bridge exit the sleeping state.(usually used to control the bridge power supply,the bus power supply,the independent graphics power supply.CPU power supply etc.) • VDlMM: l*J1'¥fAlt. VDlMM: the memory power supply. • YCORENCC: mm=f~lt, .~~~El!, ~!ll~~It, CPU {,:ltlt~o VCORENCC: refers to the bridge power supply,the bus power supply,the independent power supply.CPU power supply etc. • YRMPWRGD: ji~mm.Jlt1l1 CPU ~ltiE'M', 3.3Y. VRMPWRGD:infonn the South bridge that CPU power supply is nonnal,3.3V. • CLK GEN.: II1tajJ~J:t1fMiIf'F, ~l±I~Jmll1tajJ. CLK GEN: the clock chip starts to work,send various clock. • PWROK: ii~lrmm.JltIl1~ItWiE11ty (SLP_S3#tE*5C~)' 3.3Y. PWROK: infonn the South bridge that power supply is normal (SLP_S3# complete task),3.3V. • CPUPWRGD: mmttl±l~ CPU a<J PO, l.OSV. CPUPWROD:the South bridge send PO to CPU,l.OSV. • PLTRST#: ~i1'~{:!z:, Wim~l±\\a<J.--tJ[fm, 39V PLTRST#: the platfonn reset the South bridge North bridge.EC,MINI slot etc. • PCIRST#: PCI jt{ft, mm~l±Ia<J.= PCIRST#: PCI reset,the South bridge send used. • CPURST#: ~~mt&~1j PLTRST#fii, CPURST#:after the North bridge recei; • [)(){> 8.1.2 ~@~itf1 the soft ~r*1;.L Intel ~m (1lJJ GM4 ) -lli1m.~o Next to the Intel bridge (sue -86- Scanned by CamScanner

In the process of the computer hard start,CPURST reset signal is sent and keep a low level of a ceJ'tiilii ~e,when the power supply circuit has been stable,then removed the RESRT low level and k~:a high level,CPU start to work,the hard start finished,and start to the soft start. ~j) CPU ~i&it~[:lEl!j!a<J DBSY#f§%~~~ FSB Fltrftjlij.~,~~~1.i~,tto 3 DBSY#./':1 :fW&~p;j~7J' FSB .~~.tt, ~1ffHtfW~, CPU :t~~-WIf'F; 3 DBSY#./':1it1EE!.~Bt ~$SB .(i~;r:.i't, CPU ~;mu ADS#±I!l.±.Il:i&Jmf§%~Ei)f~tt1Hft~:hti!~Wio ADS ~10~:mm 8-3 fJT7J'. CPU will check FSB front bus line is busy or not through the DBSY# signal of the interface ciiWitWhen DBSY# is low level,it means that FSB bus is busY,only released it,CPU will be the ~~ep worlc;when DBSY# is high level,it means that FSB is not busy.CPU will through ADS# strobe signal line to tell the North bridge ready to send the data. S waveform as shown in figure 8-3. (2) ~~tm=~~J~1-ffi%m, ~lll:* 13 ~5MHf Bi1£46-~f. ~tm4l':& tJj -1'-ff£ EE!.f D~ ;y#~ CPU, i9-W CPU B?l46-jf, iiJ~*l&~~o ~Bt CPU :t4l'iffirl A3l ~AO :&i! OHU1i§%, ~~BIOS 1*Ja<J-~M~m~. AO~A31 flJ~tml¥J FSB jj1JftjIij.~.~~t~D, SB (fCJ1Jji~~, El!.sp:~~*,~:l:.JI:~~mfUtl~tm=. ~tmq~ftl CPU B~~±.Il:m~J§Jmrl ~~~~mm=. fter the North bridge receiving this signal,if its in good condition and has been ready,the '8ge-will send a low level ofH_TRDY# to CPU,told the CPU is ready,and can receive the CPU will through A31-AO send FFFFOH address signal,which is ajump instruction in the rAo-;...A31 to FSB front bus interface of the North bridge,through FSB frequency ~level conversion and address decoding send to the North bridge.After the North bridge , g eRU addressing instruction,through DMI bus send to the South bridge. ~.Mf DMI .~~E8 16 ~~m1iX, ..aM..a~tifg, m%~1:i!.m DMI_RXP(O:3), 0:3), DMI_TXP(O:3), DMI_TXN(O:3), 1101118-4 fJTiF. bridge and the South bridge DMI bus consists of 16 Iines,point to point gNlllines including is lMCRXN(O:3) DMIjUCN(O:3),DMI_TXN(O:3),as shown in figure 8-4. Scanned by CamScanner

00 8-3 ADS#a!i7f3 Figure 8-3 AOS# wavefonn Figure 8-4 OMI bus signal diagram (moo *Ii(3) iWffi:q~~IJ~~ffi:\\¥J~:W::lll~~JfMi~·jtBIOS, tBtJ!!l~ PCI .~~J:£~~ BIOS 8-5). ~ PCI .~~J:~fl BIOS, PCI .~.~1\"§-%11m.**~~ BIOS fr1ti.±iH1J. :!In W<: BIOS tttE EC r, iWffi:iI):1: PCI m~w~~~.7f~~~ LPC .~.~J:\\¥J EC 3m1\"§, 3 EC q5l~IJ B.:l:Il:m~~.fJ}~£ X-BUS .~~!iJt1!t SPI .~!U~ BIOS. BIOS .fJ}mtJmiS.@]fll:1m~~ CPU, CPU i.E 1T BIOS t:j:J\\¥J POST ~~m~, Jff!€i~~~1'J;. After the South bridge receiving the addressing instruction of the North bridge,then start to search BIOS,first search whether there is BIOS on the PCI bus(see figure 8-5).When there is no BIOS on PCI bus,according to the PCI bus signal set to determine where BIOS is.IfBIOS is under EC,after the South bridge through PCI decoding module,then to communicate with EC on the LPC bus,when EC receiving the addressing instruction,then through X-BUS or SPI bus to BIOS.BIOS returns the data to the CPU,CPU running POST seIf-check program in the BIOS,and start self-check action. -88- Scanned by CamScanner

.. BIO J!:ai;bi~BCJ~ffi~: C :: Uki$ f§-,%). Ill( Et!Sfi$9:J. ~Et!Sf&:ffm9:J c key signal to detennine whether 810 action:C =(chip elect). lected \\,hen low 19~~~,1S not selected hen high Ie el. CPU iEMiitiJ BIOS i3 ~~n:.Fo. lfilfJ ff PO T fg48~j1J~L ~- CPU reading BIOS self-test correctly. then tart to e:-.e ute the pro ess of POST <D.~ CPU ~JtiE'i\"JiiWJ BIOS ~@]8~ POST El . ~Jf:.Fo~1ftl1<1]~1-t;t;Jt~1l (lli~~m :i£htftit PCI-E ~il (!!It1L~-t )c -~I\"'I.CPU addressing is normal, received POST self-test program returned by BIOS. then start iitiJ!U#!d1 1be chipset(the South bridge and the orth bridge).and also initialized PCI-E ~Meodc!lDt graphics). @ *~tftitJii, ;!i:t 5MBUS .~~:I1IiJttP3f¥. *trYJ~1-t. ~*WlOO 8-6 fiJfij,;c ~.&~'tbe South bridge initializing grab the memory through S 1BUS bus to be initialized. the ~~~'isshown in figure 8-6. \"-~J'~ ffEl~Jii, BIOS :f3.i3*Mf¥AP3f¥o the memory self-test finishing BIOS stores the self-test program into the memo!). )A~ffJ:i,IIIm BIOS M~-.l1l:~l'-i.9:~. Wlm~~~tl~. ~-t. jE-t~o Called the BIOS program from the memory to test each device one by one. such as the 'COntroller. network cards, souild cards etc. ~_.a~ .~ll-FBCJ BIOS, *i.llm't{fJ~I£~-tl¥rfJJ{zijf.to 1be graphics cards, find BIOS of the graphics cards.. and call them to complete the ofthe graphics cards. ~~ EDID ~!litJIUHg.@. (};\\!.m 8-7). ~¥iJM.Fo, 1tIt rn-'%Iffcl M~ Et! cs cards starts to read the screen information through EDID bus(shO\\\\n in figure 8-7). • ~ then sends a signal to open the screen power supply and backlight. 111-7 BOmO Scanned by CarnScanner

It ri'lir 8-7 FDID wavcl'Orlll () !II\"/J,JrHL I O(i() 111111(11, )1 Jl'1~(d,;'ti~IIJJ( 1/'IIJ{f )HIII~ r'411J''LJlI~JII Di.'pla, tht: hoot piclllr', ami slllrt to I 'sl til' cxtclldl:d III 'Illnry ami give Ihe l;oITl:spondin ' addr s . (H t~i~!IJ .JIl:t'J\\(fLi~;;).. HMM!/,''\\' )VJI~, /1\\11, )1·11. (1)i'JI~~1 . Te. t some standard 'quipmcllt, including hard disk, CD drives, serial ports, parallel pOl1S, floppy drive etc. ® ~/J;~h i~ ~t~-l.i~!~ '/l!,J, i, ;f. Nt I),j ,~lll'l~ Xn 1!IJ M[IIJ) IJ f~(il~;I~) r~(it;(J.~)!IJ.flil'll~ \\\"1# ric 'II (I~) ['PM UIJ Jl]l~ ~. ~l: 1:J~ I/\"~ i~ 1h-5}J\"lG '11J'l;Ji jIll JII:, DMA )ll1m.f11 I/O !liM I I ~: IJitl);( 0 After te ting the standard equipment, the plug and play code supported by the system will start to te t and configure the plug and play equipment in the system, und distributes the interrupt address, DMA channel and I/O port and other resources 1'01' these equipment. 10 r!JTrifl\\!!1'H'.@:w!fl~Jii. ~1;i'l1l'lHill·/'IIJ~iJW.J11:. l!!.liVtJ1:!9r{j (I0fJ!l! f'HIl \\'f.IW [ \"I {1!l!1'1;f tic. lS:IIJ:!t·'I=JJl(. 1- ESCD X1!I: (~tJt BIOS m~~lj~~~11:~tJt?(W~fJll!f'l:fflGf·i_1I'j.I.;!,(I() -.fIll r r~. ~il~lJ&W:fftE CMOS ~I~), CPU 01el.l:IJ~(I~ ESCD fllJ:(j(((~) ESCD illrrbt~. 1x:fYlXJ}IJ 111, i';1J.!.fffr ESCD 4'A~!I&~. Afier all hardware testing and being assigned the interrupts address,that is.all the hardware set up a hardware system then it will generate a ESCD file (it is the method that the system BIO exchange hardware configuration information for the operation system.the data is in CMOS),CPU will compare the generated ESCD with the last ESCD,if finds the difference.it will update the data in ESCD. @ ESCD J!flTJ5, CPU i:B$Ue POST \"~4'ItJT)JIUHi~:J:MTjGl:r-. f1Fr.f~illrrj},tJt(I~I'1 7~*'EJ}. j},#t BIOS t'fJJ6f4Jft{il9;\"UlmF~1i:iEtJ<J~f4JJIIDl~*J6f4J~ff-*tJt, 7tf:[Ja i'iIJi&*\" I ~~~tlKJqJ)tf!f, ~J5~A~ff, BIOS ~E!.~$tl:+X~~J6f4J)(1!f, r:lJJ6iJr>cfit-iJl W':!'JRWffi rfc. ~Il Windows XP, Windows 7 •• After updating ESCD CPU will complete the interrupt service routine,and then carry out the bootstrap program of the system ystem BIOS start the operating system according to the boot sequence ~i hoot files in the starting device first.then write in the memory BIOS give uter to the boot files.the operation system guided by the bootfiles,suc on. -90- Scanned by CamScanner

!'trR!Ul1!l (Advan d onfi uration & Power Inlcrt1H:e) '(; I :;:-~ j'lfG 'n. I. IQ;'~1 II t'f. nF. aizto' ft ilm~El!.$i Jlli~!\\!ti~)(;IIJi~k!lj''l~I&(I~ . I BID ,'tlij \\P I t \\d\\anc d M1!'~'IQm'lent) ACPlit !UfI(Xf~l:J.Il~nj P 1 ( dvaneed Conti uration & Power Interface) i. til -tandard f th ad\\:lI1 d on and the pow r interfac .Before A PI pr p sed.lhc univ rsal p \\\\ r managem '01 iib4iriliS PM with a BIO I v I developed by Micr n. PI i to repla th pr \\ i uP\\. Eb lnt 1 Microsoft, To hiba rrrJUliJi~IJii:t'10. J1:.J:J J (£n~f'f:*tJifD1i2!f'fZ.I8]A­ rlI~O. J;At!Xi!J;AJiU t£ 1t!?!J;[1TlJU L:.11J r~ IliJ (I~ Il'iiJirrl~tl i.E ary:ftJi -1~ Do ..~~\"I isjointly developed by Intel.Micro ofi.~ shiba.is to have a comm n pow r managem nt een the operating system and the hardware,and t impro e the di unit) interfa' !¥Q»Red by th different manufacturers on the power management before. \"'OLI,-...tndo s 98/8E, Windows ME & Windows :WOO, Windows rp 7f~3tr.-J CPI M. ~ .~.Lm~.*.~§*~~~~~o m Wtndows 98/SE,Windows ME and Window 2000.Windows XP taning to uppon rom the laptops to the desktops and servers are included in thi p citi arion. I iiJJ;AiJ:~tJfi!A1~El!.~m'M~ , 1Ii~~..,.. \", tm~mfl1i*IIa:~. § B~fJt~~ ,1 E@. tfi. I can make the system to enter a 10 power consumption of \"sic p state\".su h as tandb: the purpose is to control the power consumption of the computer. IRi~tJ(J~~iiJ~'.JG (GlohaJ), D (Device), S tSleeping), C (CP ) . ofACPI can be divided into G(Global).D(Device).S(Sleeping).C(CP ). 8.2.2 ACPII¥J G ( Global) ~~ Scanned by CamScanner

this time.As long as any wake-up activation events message into the system.it will soon be restored to a working state.Under this state.the machine can not be disassembled and assembled. @G2/S5: Soft Off (!i9\\:!JHJ1) :l7Ci$. llt:I7Ci$r ~tfLR 1~c\\If:i'~~'~YB~ ~tJffi. 1i*T1f1iiJ1tJfJ ~~.~.m~fi~~~ff.~~~~r~~~*~~~*~.~I~~~.~~~r. ~ (j~tfl;~m. G2/S5:Soft Off state.System only keeps very little power under this state,no users and the operating system programs are executed.The state takes a long time to return to a working state.Under this state.the machine can not be disassembled and assembled. @G3: Mechanical Off :I7C~. llt:I7C~r~~*mB~ EE!.tJffit>.J;tcI~. 11:~1fiiiJ EE!.¥mJIDli* m. •m9H.~n*EE!..~@ft~*;tc*.~.llt:I7C~rEE!..~mft•~• G3 :Mechanical Off state. Under this state.the power of the whole system is closed,there is no current through the system,the system can only reopen the power supply switch to active. Under this state,the power consumption is zero. ~» 8.2.3 ACPI (l(J D (Device) :tR~ 1») D(Device) state Device ~m-@ii1i-. i9JHmiP!l*tlfiWJ~, li}!ff!, :7't~I8:~, x.PJ*~~Dr4 #. Device refers to some devices,such as modems,hard drives,CD-ROM,etc,also can be divided into the following 4 kinds. (DDO: FuIly-On. iE1ItIf'I:::m~. DO:FuIly-On.The normal working state. ®DI: PJ~~~Y~m~. ~~~~m~~ii1i-m~~D2~~r~$~$.~~~rn ~~*~m*~. ~@ii1i-~~~ADl~~. DI:1t can save less power consumption,the device function with keeping activities is much more than which in D2 state.This sate is determined by the device itself,and some devices cannot enter into the 0 I state. is determined by the -92- Scanned by CamScanner

.2 .. C (J(J (lcCllillg ) ~J(.a· .\"~;\"\"'\" means Sleeping and refers the system enter inlo the .. I<.;eping siale ill (i I,alsu (;(111 he ~_q~~1{l'to 0 SI S2,S3,S4,S5. 1 0: ~~ it. ~ifJJF'lIlj((~ U12:j)'i:, mil i}tf,V,-Jr. J)JnflJ.~~,1iiH HOW\" Q~ faet,this is our normal working state,all devices arc ('lilly open,the power con. lInlpticJII is \"I more than SOW. lr r£JIt:jjti5r B~:I4J CPU r)H~II'HJI'.x: I~J, {1I;HJc ( PI), 'Hche ,I~,l'i?ll) (I(J I),) ~, itk~S1Htj:iJ3t),t.iE1lf; 11'0 ~II,J'(I~J)J~~ ·mUF 30W ~~, I:\" Jty:. 1) JII~ 'pu • ~Jff.Iit:f+ if.JjJ{JJIlff~ ((1 0 , U internal clock has been shut down under this state,bUI the contents 0(' the system ibe chipset) are not lost,the other parts arc still working normally.At lhis time,lhe power 'on is generally below 30W.ln fact,some of CPU cooling sofiware is developed in II is rinciple. 2: ~i!j.{T SI. iAp;j CPU ~r-f .l1:iE1f.*~. CPU III Cache (JWn;~ IjJllV··, \";~,?.!G ~m, fEl.~~atJli4iJ3tI.Ui~0 'l8r to SI at this time,CPU is in the state of stop,the content of CPU and uche has been bus clock is also shut down,but the rest of the device is still running. : itilt ~ifJ\"~atJ STR (Suspend to RAM), [l#i 7 r)~ :(:J.(I(J ~i ~\\l~I' JU 'P mtro ~~J$Jit~, ~ ~atJ ~ ~ E8iil1!ittr.f~~1Jt~~Q.~Hp f!iH1'J {E. j.6:IH (J~ J)J~G 's ~ TR(Suspend to RAM) we familiar with,in addition to the information of the content of CPU,Cache,chipset is lost,the content of the memory is provided by the er. service data is exist.The power consumption is less than lOW at this time. D (Suspend to Disk), lUJt~Et!.Il~~, fEI. ~tJt1 .rn,~{l-AfiJIWL it.f1:~tJt Jji!., ~1¥~J.m~i1I**i~H¥!UiV!m:1¥.I hiberfil.sys X{!f:rll, ii!1!JM: ::ro<Suspend to Disk) the system main power supply is shut down but the red in the hard disk.By the operating system implementation after :6fitllie~J1~&rnorysaved to hiberfil.sys file in the hard disk the hard disk is Scanned by CamScanner

V;r,Ml't~Jg~ff-'1;jibt:'~Ii~i5t1&(~~II1, ~:J.f1ffJ(~~'J&:IJ.'i'fT;j~. I(ijJUl!!.i)!'1ilJ~'Hd: J XriJ:l) .~..• I tJtI't1f€rt! t&1~0 -13 ft1fH1i:T-\"r-gilm11(m, -*rfti;(}tf&:I~~II~. til 1·.M.IJ~{f 'I Jj.I'lI\\( 'kV,'; Jill}. J.I) n.STR z.tru((.]I1\"F~~0 JJ-jfffl~i~1gj£tJrf&·~Jl. 1~l!t}lJ! I !u,'?j;ljillAtll~~ JF S\" R ~} LJ~i 'I}((I') lI;j'riij::fii~JLfyffij Go ffij S4 ~;:t. E!P STD (.j:b~i'ljfJ!I!~U. 1&JJ~:){ (~\"{{(1: M! I,',{ 'I I (I() III J /1/)1 1M:1¥J~/~it&bt.~f¥!&t3H~$, lEJl1tffl~*iliifJttL*i STR )JIS i',·tk /0 The most commonly used is the S3 state.that is Su pend to RAM state.referred to S'I R.J\\. thl: name impfies,STR is that to save the data of the working state before the system entering S\" R into the memory.Under the state of STR.the power still continues to supply the power for the most necessary devices,such as memory.to ensure that the data is not lost,while other devices arc in \" closed state,the power consumption of the system is very 10w.Once we press the power hutton.the system will be awakened.immediately read the data from the memory and return to before workin I state of STR.The read-write speed of the memory is very fast.so users feel that it takes just a few seconds to enter and leave STR state.And S4 state,that is,STD,the data is stored in the hard disk.Because the read/write speed of the hard disk is much slower than the memory,so it dose not so fast like STR in using. [)(){> 8.2.5 ACPI t¥J C ( CPU) ~~ C state of ACPI ACPI I'fJ C ~~~m CPU ta~~, XiJJ7t~~r 5 #0 The C state ofACPI refers to the state ofCPU and can be divided into the following 5 kinds. CD CO: CPU j£'/ltIfF:tR~o CO:the normal working state of CPU. c!oi£:ii'~~~, 'ff f~a<J~MlJ1fil]o {£~:U' @ CI: CPU 13i;1}lfWIfF ~ ~~~~m~~4I!'tiJJ~~~~~~~ r;5 B~{iJ!!1tf~gl!'tfBJ!.IZ'~Ji!..\"J ~*' r:1ft ~ 1'fJ~1tf~1W1!'t fBJ 0 C 1:CPU suspends worle automati unaffected under this state,and there is a minimum time to iVU .s state must be small enough.so the operating software caDI time in this state when determine whether use this ® C2: ~fl;,{ C I. J1tfl\\.t*~~ ~f'l.~~~jf:j)l~ffa<J-!l:11ho C2:Similar to CI the So CPU continues to monitortbe in figure 8-8. -94- Scanned by CamScanner

(':==..-)I'CPfUi~IIF '-'...L.L-...o Latched (l'J,Wf) II I Unlatched !I (~~~ml+) =~F'J/llr J11I425-_0\\-r-_---j-+<~I:>=-=-t'2--J7.3,.-.-.!._.1-2.7JI1_4__ _ SlPO.J(# (Q*ftI:) I 00 8-8 CO-C2-CO 01\"J.J. Figure 8-8 the sequence of CO-C2-CO @ C3: C3 1*D~~~, Ilp~~5'Hmll1~, i¥JtftRtI:J STP cpu#~ll1t.sp;t;JtIj,~HfJ CPU mJ~\"', 18J1t-j**:&ili DPSLP#~ CPU, Jm~ CPU JitA C3 ~J!f1;*D~~;:tQ CO-C3-CO B1Ff 8-9 ffi7J'o G3:C3 sleeping state,that iS,close the external c1ock,the South bridge send STP_CPU# to clock close CPU clock,the South bridge send DPSLP# to CPU at the same time,to infonn CPU into C3 sl~ing state.The sequence ofCa-C3-CO is shown in figure 8-9. CPUUF I UnlJllchec!: Latched (t111f: ) Unlatched I ( II,WI1f:) Signals (~IiIl1f ) ~ ~ I STPCLK' I Bu. Muter I [;1 I Idl.(~f.*I) ActIve( ffiidJ);I< (~) I 1211 1270 DPSLN t+\\ J cPUIJottII I c;;: ~ \"\"'\" 1.7 Runnlng( \"\"~) (lfl!:) Running ( ,Il,l1l<Aill1l< ) -=' r=;~ III 8-9 Co-C3-e0 II'tJ1: Figure 8-9 the sequence ofCO-C3-CO ftkf C3 f*~~if;, 1£~m:&lli STP_CPU#~~ CPU 1l1~J5, i¥J#fRtH )FRSTP#ffI~~ CPU ~1t1t~'lf3;!!~Jt, m!;A~~ CPU m,t.\\ltffi. CO-C4- Scanned by CamScanner

(JIIJ IIF I~ I.Sd1ed ( I~Hi ) ~ IIIMI I \"\"II 'J ( IIIVHf 1+_ \\ I )kIo (.,;~ r~·1 l AdlYo ( i!,4J )':t' I I~ I21ll ~ r;: Ira.fr;s:j .....IbwircI ( ,\\I,l.\\(.I!lltil )(f';!l) .... 1UrW1l( ,\\I.lAi@<) I (JIIJ IHi'I' t ';I( SIllA>Bd ~ \"I I - ~r.a:-~ lZ!Il (JIIJYa: \\J 00 8-10 CO-C4-CO I!'tFf Figure 8-10 the sequence ofCO-C4-CO m[){)I> 8.2.6 ACPI iJCJ II!.II ,\"~'J oft the power and the control signal of ACPI Scanned by CamScanner

S,E,P_83#. 8LP_S4#. SLP_S5#:the signal of the low level control enter S3,S4,S5 state.For I~Riill'tlple the system is in the state of SO when running normally.three signals should be invalid.is d .SlJSB# SUSC# and others are similar to SLP_S\"'# signal.The state of the sleep signal in each $Ieepmg state is shown in figure 8-11. ~1111} so Sl S3 S4 S5 SIoP_S3' 1 1 0 0 0 SLP_S4. 1 1 1 0 0 SLP_S5. 1 1 1 1 0 Figure 8-11 the state of the sleep signal in each sleeping state. :a:@ PWRBTN#: Power Button, fl!~~m. 1<:fJLlit , 1ft1~ PWRBTN#1]§-'%, ACPl ~~1~ 8LP_SS#. SLP_84#, SLP_S3#¥tJ 3.3V. ~ll:~ PWRBTN#~~4s 1~Et.'Sf, ~~1!£*~jf.S.¥. S5~~. TN#:Power Button.At shutdown,pull low PWRBTN# signal,ACPI will set high ~~S!'im. SLP_84#, SLP_S3# to 3.3V in turn.lf PWRBTN# continues being the low level for will be forced into the 85 state. Scanned by CamScanner

The clock circuit The working condition of the clock chip. ~[l 00 8-12 fiff7F, Et1~~Jt 8~I f1=9.k{tj:~[lr 0 As shown in figure 8-l2,the working condition of the clock chip is following: *0CD fjiJt!.: 83+3VS ~ LI6 L32 f=:±.+CLK_VDD, +CLK_VDDI t~fft 3.3V, d3 + 1.0SVS ~ LIS f=1:.+CLK_VDDSRC m:1;J:l: 1.0SV 0 The power supply:+3VS produces +CLK_VDD, +CLK_VDDI through LI6 and L32 and provides 3.3V.+ 1.0SV produces +CLK_VDDSRC through LIS and provides J.OSY. ® 7fJf-l{i§.!% CK]WRGD/PD#: ~F4!:if 3.3V 7f~ a The open signal CK]WRGD/PD#:the high level 3.3V opened. ® 14.3 18MHz t!i1Ur:.:J1& Y2 a 14.318MHz benchmark crystal Y2. @) CPU_STOP#, PCI_STOP#: CPU ~ PCI B1~1~Jtllit<~·, iElitIf1=B1~nit\"r:g:ifa CPU_STOP#, PCI_STOP#:CPU and PCI clock stop instructions,it needs to be the high level when working nonnally. @ 5MBCLK, 5MBDATA ~~1fJ!(.~~: fflffHu'U BIOS m~ 0 5MBCLK, 5MBDATA system management bus:used to transfer BIOS instructions. ® FSLA, FSLB, FSLC !Wi.~~: IHi/f'1iiJ1¥J CPU f=:±'/F[iiJB''11iUftffij.~~B1tTo FSLA, FSLB, FSLC frequency selection:according to the different CPU to produce the different front bus clock. The clock signal distribution ofGM45 chi -98- Scanned by CamScanner

s t display clock thutlhc clock chip send 10 the North bridgc,96Mllz and It-tfl1·~,Jt1it~I*HJi:lkJ(l~ ATA tJ~mlj~II'H)I't IOOMHz. ATA controller clock that the clock chip end to the outh bridge, 100M Hz. It-tfl1~Ft1it~m#j:(I~ PCI-E ~~~cn~'~llt IOOMHz. 6 pin is the PCI-E module clock that the clock chip send to the South bridge, IOOMHz. 56. 1t-t~;cjFt1it~~tm(j{JIOOMHzf~/c..'Ii'H~l. pm is lOOMHz core clock that the clock chip send to the North bridge. I~~ 45 .~It-t~;e;Jt1it~ MfNI PCI-E flJt(j~ IOOMHz 1l1ll~ t ffl T7C~~-F~. ;45 pin is lOOMHz clock that the clock chip send to MIMI PCI-E slot,used for wireless ~etc. ir§j\" 47 JJp~It-t~~Jt1it~tlH~~-F(jj 100MHz IW~ll0 ~ .l47 pin is lOOMHz clock that the clock chip send to the onboard card. ~ 15 .:Jllt-tflll;e;Jt1ittft EC ~Jta~ 33MHz 11'J·~ll. mis 33MHz clock that the clock chip send to the EC chip. 7 .:1!It-t~~Jt1it~WJml'¥J 33MHz lI1iT t ffl T mffi: rJ;j f.fIHY0 ~1iL Et!.~ 0 hi is 33MHz clock that the clock chip send to the South bridge, used in the reset circuit in bridge. o• •It-t~;e;Jt:tt~SD ~-FB;e;JtllJWJml*J USB ~*IJ-1*B~ 48MHz Mtrt'. is 48MHz clock that the clock chip send to the SO card reader chip and USB controller bridge. ~lt-tflll~ Jt:tttftAim I'¥J 14.318MHz ~t1E1!'J~ 0 . 14.328MHz reference clock that the clock chip send to the South bridge. 8 43, 46 21 JJpJ!~S&lt-titl'it*ffi%, f~rt.!JZfl~o ;46~1 pin is the request signal of each clock,the low level is effective. Scanned by CamScanner

Clock Genera/or .,........_ ...........=-__-<:> D_ot.~l... ,....\" SQI( D_Ol..~ \",'. \"\"\"-\"\"\" 41-\"-_-\"\"'-\"\"'U!!4'-_-<:::JQJ\\.CP\\I~KIJI 0'UCU1'fV\" c:ut.CPU_1lCl.J\\I • \".\",.'JJ\"LF ....--\"\"'.....\"\"'''---<:::Ja.-...aDL8CI.Jt r 0'\\lC1.J.\"!'V • ~~-=~_7 _ 8flClD_U\"MXJ'fT__J,rR aJt.DMY__ I &ACCll.lIMJOT'C__....,... fA-,......\"\"'!.!!!\"---<:::JCUL...\".- • nutt...~.J,J\"RIE,I---~\"\"\"\"'''-'''L.:.YGk=·'''''C''51~~~~.1IIOS ZMtr,.1MRlC1J.I'MID a.x..DfII(F_1KI • ~lATJI\"'I---\"\"';:J:&ll\"\",,\"\",,:a.~..:.Y.::llk\":'·\"'·Ot'~\"J~ ~TA(;J.I\"fl ~~SA'Ut1 \"\"'\"_ cm loL..--<:::Jcu....lIIDLaot'U. • ....- --<:::JClJl...IOL........ I-'--r------..........a....---\"i .. ,.....-. ~;~~~~~~~~~~:~~~ .....- \"\"''-'''L---<:::JaJlLPCE...._ 11 CU-.DrlD ....- \"\"'U!!l....--<:::JCUL~_ D .. IJClJI...OL1\" 1...- - ' ~I....'---.:=Jcuc..~LMI • ....._ \"\"'UoIllL---<:::Ja.Jl.\"ClI:,....... ~......_ .........,_.....-<:::J_ _ • Figure 8-12 the clock sign!ij,.d.,il\"\"·.......,...\" The clock signal distribution ofHMSS clii~ HM55 ;C;iH.lift-jttl'1~%I'(.J?t;(p:tm1l 8- f!} El3 PCH ~:It te ~i&ft-jttl'i'f3Jt{1Bli~ .. -ItO. ffr7ffl1f 25MHz ~~. The clock signal distribution of clock chip is just sent to PCH cloc~then the display set,and the display set suppg crystal. -100- Scanned by CamScanner

The clock signal distribution of above HM65 chipset 65 ~J:.~Jtmllt~{~~(j{]7.t;(Ptmoo 8-14 JiJT7F:. %'=.8~m~px:n~·t.rp~Jt, 1Z'~~ ....~.\":\"lr- Afi. The clock signal distribution of above HM65 chipset is shown in figure 8-14,the characteristic • must be 25MHz crystal when the bridge integrates the clock chip. PCIE GraphICS-'- -101- Scanned by CamScanner

The clock signal dislribution of AMD double chipset AMD ~ffi:;e::J-t~RD1~..pf§-I%B10\"1fj ~f100 8-15 f'fTjF, f1~/flP;0)ibttIJ ~Jmn'HJII, illllllAw 1 iii 1i:&tI:l33MHz D1Mt, 33MHz A~·trI1El311Hj'f:&tI:lo The clock signal distribution of AMD double chipset is shown in figure 8-15,the clock chip sends each clock,but is just not responsible for sending 33MHz clock.33MHz clock is sent by the South bridge. --. .- ........aa-. ....... - -8'1' fOlE - mul118 Scanned by CamScanner

--..-\"'\" AMDFCH Hudlan D2/0l -- _--........... ,---\"\"--\"\" '\" \".,\".\"..\"\" roil• _CAlI> (TU ..\"\" .... ROM _PCIE ,\"T_GFX..CUC ..... '-GPP_CLK1 - Figure 8-16 the clock signal distribution ofnVIDIA chipset signal distribution ofnVIDIA chipset mvtlJilM'fIl?};{fi:(m 8-17 JiJfiF, ~R.:~:m.J£lt-.tfll. SIgnal distribution of nVIOlA chipset is shown in figure 8-17,the characteristic is that the clock. Scanned by CamScanner

.-\"\"\"'''.,.\".-......\",.....\"..-.. - ..__ wo ( \"'_.\"'\",..., ...- , OltAtO \"\"-U:LIlI AMD638 Kt~I' ........ a.< ( _a.< ~.r.-.-..;.~; ~-g:-: L:J<, ...-\"\" ~I IlIMM1 ..--\"\" _J>\" ..- O'V a._ ....-....~....' ..\",.,..,. IPO' IPO. tJ'U_Q.lf..tr\",,~~f' '«.J<='\" IPO' --\"\"\"'...M_J._.t.-l.G.J.-U.. N'''-'''''''''''''''' .--=-- .~ ::t=- ...... 0 0\"'lI0II!\"\"'(:\"U\"(\" ~ -=- ........ -....-.. ,••HI;I!:)4M1U , _- -.>' nVIDIA IPeO . . ~ [C n- -O=-- .... ( ==--._-.........P~..O..a..............t.... ~ P...O.. [ ~....... - Lr.nnJ [£] l:j I - 1 1b~ 1 \"t- ..--. I ..... \" ~-.- Figure 8-17 the clock signal distribution ofnVIDlA chipset [)t){> 8.3.2 PWRGD '\"tlf;ltl!. PWRGD and the reset circuit Intel i¥im:l*Jfflla~ VRMPWRGD M:fJ~DTo The explanation of VRMPWRGD in the South bridge is following: VRMPWRGD: J1tffi%@~~11 tf< 'G' EI!lli Bf!)E 0 JItffi -i}:tET~UJf ~ \"!zn~ 8-18 JiJTlFo VRMPWRGD:this signal supply chip,used to indicate PWROK signal in the South b 8-18. VRMPWRGD -104- Scanned by CamScanner

Figure 8-18 the screenshot of the text about VRMPWRGD pin definition OK: 1Ei~lf~lI1, PWROK Jm9;O ICH Jifr~ttWi!B~~t\"~Jl~JE 99ms, PC1CLK -~ Ims. PWROK ~;I:]f~~4'-II1, ICH f\"~il\\;tt4'-B~ PLTRST#. 8:: PWROK 1Z,~.m7G y 31\"RTCCLK lI1~fflIM. PWROK ijl}J!fJfE5Zrntt~~~D~ 8-19 Jifr~. DOK:when the signal is effective,PWROK infonn that all power oflCH has been generated Ie for 99ms,PCICLK has been stable for Ims.When PWROK becomes lower level.lCH PLTRST# with low level.Note:PWROK must be inactive for three RTCCLK clock cycles screenshot ofthe text about PWROK pin definition is shown in figure 8-19. CNlPWRGD: CPU E@.~~f, ~l'f§-%@ii~iO~~~B~PWRGOOD)]!P, ~~ CPU O~ *0~3:fttJ<J. i!:J!-l'Wu:±l{§~, ~ PWROK VRMPWRGD if§l=j*JJX. CPUPWRGD lljC:flIJm8-20 WT7J'. UPWRGD:CPU power good,this signal should be connected to PWRGOOD pin of the ~dicates that CPU power supply is effective.This is an output signal.fonned by the phase IDK and VRMPWRGD.The text ofCPUPWRGD pin definition is shown in figure 8-20. \",ROK Power OK: When asserted, PWROK Is an indication to the ICH9 that all power ralls have been stable for 99 ms and that PCICLK has been I stable for 1 ms. PWROK can be driven asynchronously. When PWROK Is negated, the ICH9 asserts PLTRSTlf. NOT!!. 1. PWROK must deassert for a minimum of three RTC clock periOds In order for the ICH9 to fully reset the power and properiy generate the PLTRST# output. 2. PWROK must not glitch, even If RSMRSTf Is low. Figure 8-19 the screenshot ofthe text about PWROK pin definition CPUP.WRGD CPU Po_r Good: This signal should be connected to the processor's PWRGOOD Input to Indicate when the processor power Is 0 valid. This Is an output signal that represents a logical AND of the ICH9's PWROK and VRMPWRGD signals. m8-20 CPUPWRGD i3IMJ~.:x.Jl)C.OO as -10]- Scanned by CamScanner

PLTRST# Platform Reset: The Intel' ICH9 asserts PLTRST# to reset deVICes on the platform (e.g., 510. FWH, LAN. (G)MCH. TPM, etc.). The ICH9 asserts PLTRSTII during power-up and when SIW 'nltlates a hard reset sequence through the Reset Control register (110 Register CF9h). The ICH9 dnves PLTRSTII Inactive a minimum of I ms after both PWROK 0 and VRMPWRGD are dnven high. The ICH9 dnves PLTRSTI: active a minimum of 1 ms when Initiated through the Reset Control register (lID Register CF9h). NOTE: PLTRST# Is in the VccSus3_3 well. Figure 8-21 the screenshot of the text about PLTRST# pin definition PCIRST#: i!~~=-t~flLffi%, 't~d3 PLTRST#~Il1~fPmH1to PCIRST#91JJti1~)( mt)(~OO 8-22 PJT7Fo PCIRST#:this is the second reset signal,which is produced by the PLTRST# delayed buffer.TI1c text of PCIRST# pin definition is show in figure 8-22. PCI R...t: Th'. IS the Secondery PCI Bus reset signal. It I. a Io9lcal OR of tile primary Interface PLTRST# signal and tile stale of the Secondary Bus Reset M of Ihe Bridge Control register (030.FO:3Eh. bit 6). Figure 8-22 the screenshot of the text about PCIRST# pin definition i«JI5, ~t#j:1¥J RSTIN#JJp (i31 JJp~5(W.OO 8-23) ~~~$IJrw#f1JtIH I¥J PLTRST#J§ 0 No'j 1 ms ~IH CPURST#~ CPU, ~ffltil!JSi;lJo HCPURST#i]I)J!IJ}E5(~OO8-24 JYT7J\"o At lastafter the RSTIN# pin (the pin definition is shown in figure 8-23) of the North bridge receiving PLTRST# sent by the South bridge.Delayed Ims send CPURST# to CPU.to complete the hard start.HCPURST# pin definitionJs shown in figure 8-24. RSTIN# I When asserted, this signal asynchronously resets HVIN k:. this IIgnal Is connected to the PCIR5Tjp ICH7. All PC! Express Graphics Attach 1M complIant to PO Express\" 1. Figure 8-23 HCPURST' -106- Scanned by CamScanner

!!1t!..H1~:(m1ll8-25 JiJT~o e sequence ofthe reset circuit is shown in figure 8-25. Figure 8-25 the sequence ofthe reset circuit Scanned by CamScanner

--::::::=:::=::== ;f4tnPl:W: ~Mnll(4P1uJ.lset!.WS3i-dilt-h1tM4t-o$dIuJllart.i}o-nf)l';ft1fp~!l>t~-i'!'~:9{€tJr..ti;'.!lt-t$~'],, j;ij i,fft--B!l>.t-m:9t.i2(£J.-$M.rJ~.JIJ-,'t:.i::,fIJ m.fkBtJ£~€r.;4t J i!1t j.J Jj] if-ti:-$IJ ~f.lr.}*f.~t.~~~t!..tkfft*t!.t!.S3-.*m~#~A.~~.~.4~a, PWMt!.S3-•••~,.~~.k.~~, ~~~t!.S3-.1~€r.;~~· Chapter 9 The explanation ofPWM circuit PWM is that pulse width modulation,it is a very effective technique of using the digital output of the microprocessor to to control the artificial circuit,is widely used in many fields from measurement,communication to power control and transformation.This way is used in most of the power supply circuit in the laptop.Compared with the linear regulated power supply,the PWM circuit has the advantages of high efficiency,high output power,but also has the disadvantages of complex circuit. 9.1 ~~*~~±~~~PWM~.-. :..r.MOS+~II+Et!.~~px;. The PWM circuit in the laptop mo ~ ofPWM chip and MOS and the coil and the capacitance. [)(){> 9.1.1 PWM t'JCJIft:IlU,..:1t PWM jffiMirnjiJff~McX'M1JUJ !l'l 00 9-) 73f~J, ff~fflIM~Jt!.Ii. 5V X50%=2.5V • PWM regulates the output 0 for the proportion of the entire period ofthe highest voltageam is 5V·50010=2.5V. -108- Scanned by CamScanner

18k J'L II Trlg'd MPOI: 0.000, AUTOSET + 'rI I UuI I I \"-\"Ii'an \"\"'- Ji!ilM S.08V ;p.~1! 2.S0V JW?~~ '.OOOm, ~$ 1.000kHl iJJt~; cHii.oov MSOO)!1 CHl / 2.60V 9-Nov-1312:S6 l.0000Ol:Hl 00 9-1 PWM 1B<* Figure 9-1 PWM waveform ~1'mJ M the entire cycle the valid cycle ff~mJM *l-diffl peak-peak value mJM cycle .ijZ:ltgfl the average value !J;iii$ frequency lflm i3i;IJ-tiI cancel the automatic set-up ttU~.JI • principle ofPWM power supply IJJI.:W:i1l 9-2 fffffi, PWM ~Jt~*,L.t~'1flY-JiWiil7f::}t*ir.JTiEgff, 3 d::1ft€i LC iiUM!~1tIt!.#~m~~It!.: ~Jtil~ FB %i:~iUJt:Egm7 \"\"f1f, ft;jfflt LC 1f~It!.i&IY-J:6XIt!.@)~, ti~~m~tftlt!.. \\Il1:j:l TI1-.J7f ~ R~~*,J TIIY-J 6~~~iiJl».~*,J.1±l UIY-Jitlifl£. PQwer supply circuit is shown in figure 9-2 PWM chip controls the high r, anCilower tube to adjust the voltage,when the upper tube is opened,the be to charge LC energy storage circuit and supply power to the rear; c~eifull then closes the top tube,and opens the down tube,forms c're '~aild continues to supply power to the rear.TI in the figure is oog as control the duty cycle of TJ then it can control the Scanned by CamScanner

PWM Zit FB LORV LGATE Figure 9-2 the principle figure ofPWM power supply circuit The working process ofPWM power supply m:PWM t~ l{i.Af*Ii'Fi1~X JJJ~*lI!I1'WJ- The specific working process ofPWM power supply can be subdivided into four stages: CD Tl z-ffiJ, ~IKBtrBJ, J:.~r~:l$Jti, lltBtJ:.r'lf!}gzlJJ1~-'%i5J/'gil£~4'-, jlij~i5Jf&.LL Before hthe dead time the top tube and down tube are cut off,at this time,the top and down tube drive signals are low level,and two tubes are cut off. ®nBt~~,J:.~~~~%~~~~,r~~~m%/'g~~~,lltBtJ:.~~~, r~ ~lL YIN ~ffi~£J:. ~ D-S fi, i1 L1 Ji§itJILMffJ.t1, .~tJlLjRJi1!!, ~ ~mtmt~ ~~Bt, 1£ ~ fi.IC;J:.f=~1i: iE:1:i ffJ.1¥J ~mz ~ffi. The period oftimen ,the top tube drive sigtial is high UGATE L level.the down tube drive signal is low leve~atthiS:time the omtop tube is conducted,and the down tube, s voltage through the D-S pole of the top t1:l1:Je flows through the load,and flows to the inductance,produces the positive on the lett inductance. Figure 9-3 the waveform of the top and @ Tt-T2 BtrBJ~, lltl!'t:¥c~U: ~ffi.IC;jlijftilij~f=~-1'&jRJtf.J~Bi, 9-3 JiJTli;, UGATE 1t/'g{l£Ji§i, }ip;Ji BtrBJ • The period of time Tt\"\"\"'T2 inductance disappeared suddenly; inductance will produce a reve -110- Scanned by CamScanner

·ve on the left.The enlarged drawing of the top and down tube signal waveform is shown in , 9-3 after UGATE becoming to be 10w,LGATE will be driven to be high after delaying \\ ftiis period of time is also the dead time. * nH~., ~\"~.~~~U~~. ~W~~~~~~.~~~W.~, T~~ i&.J:..mzffHJ~;fi.iEti:~B<J~J§Z~ff!2ii LI 8j;fift;m~tl:DH.t ~1f.ii~~ S-D f&. 1J}i',m1oJ (J(JJAtIi, llP LI B<Jli:~ • ~ period of time T2,at this time,the top tube drive is low level and the down tube drive is high I.~ the top tube is cut off,the down tube is conducted,the induced voltage with the positive on right and the negative on the left inducted on the inductance through the right end of LIto the flp.ws through the S-D pole of the down tube,then flows to the negative tenninal of the that is the left end of LI. *S PWM f@.~~¥J.J:tmOO 9-4 PJT~, -f.Rffl~I*J11'{~~, m{f!;~, ,(;H~{f!;~, ~-F e real object of the single phase PWM circuit is shown in figure 9-4,is usually used for m ory power supply,the bridge power supply,the bus power supply, the graphics card e supply and others. Figure 9-4 the real object of the single phase PWM circuit f@.~~~:tmIil9-S JilflJ', -~ffl~ CPU ~IC.'~~. o ~ect of the multiphase PWM circuit is shown in figure 9-S,is usually used for the supply. Scanned by CamScanner

Figure 9-5 the real object ofthe multi phase PWM circuit The meaning of common English abbreviation in PWM circuit SKIP, SKIPSEL: If'F.J:tiiJEo SKIP, SKIPSEL:the work mode setting. TON, RT, FS: 1J;jji~iiJE (IDt-1-Jt!.~.I3.~:li!!eJt~~~JtEi&JE~*)o TON, RT, FS:the frequency setting(set the frequency by the resistance connecting the ground or the power supply). BOOT, BST, BOOST: 13*:ftliJJI4I, ...t1fG.~f;JJ.t.J*~o BOOT, BST, BooST:boot-strap pin,the wJlt source of the G pole ofthe top tube. UGATE, DH, HDRV, DRVH: ...t1f!Jl~ UGATE, DH, HDRV, DRVH:the tOlrtil LGATE, DL, LDRV, DRVL: ~1f~- LGATE, DL, LDRV, DRVL:the down FB: &.ijtir.Jli\"JJt4J 0 FB:the feedback adjusting pin. CaMP: &.1l1H~, fJjlE&~Et!..1W COMP:feedback compensation,correct OUT, VOUT, VO: ttl:HEt!.Bi~ OUT, VOUT, VO:output vol PHASE, SW, LX: ~iftJJI4I, ~~ liJf~ Et!.mt~~~ 0 PHASE, SW, LX:the phase • tube/the inductance,forms the IOQP CSP/CSN: rt!.~~IU' .. CSP/CSN:the currentd -1l2- Scanned by CamScanner

lfRIP, CS: i1mt~1F~mi5bE. fJklll~I1!.¥jfEiiJEo ~ CS:the over current protection threshold value setting.the limited current setting. -strap circuit 1IiJ:l, -ftJ:.Q~ N 14JiH. ;l't~Attffi~~§Ti;*teo E13TttWi!~Jt*~X1...t~ Ill, JL~mfl(t-J~Jt$*ffl7 E1l:l5*ffittR!*m~IJIR~~5.1Jo §~*J±JJtII36*-f:&: ST, BOOST. U E1**ffi1J~1¥J PWM E{i.R!t!DOO 9-6 PJT7Fo power,the top tube is usually N channel,the output voltage is from the common :1he power chip is limited to the driving ability ofthe top tube.and almost all of the chips are ~ circuit to improve the driving ability.The name of boot-strap pin are usually T.PWM circuit using the method ofboot-strap is shown in figure 9-6. ~-M, )I-mi1kiJI:*¥ § **ffiJ~J~.: gwe 9-6 an example,explains the principle of boot-strap: +!*iii_1'f PQS ~E{i., Jltlt-t G ~~¥9:flE{i.. J5JT12A S fJk!fu\"trtl:\\ avo li5Jot. 19V B~ 03, ~HllIr.:~ SV (t-J~ttJtlli VL, ~~J:t~$=fJkrg~~ BOOT1 ~E{i., ~,maffiJ~ y, 1JlljJ PC33 (t-J I JJ!p, ~JtJtJt. Jt~~fififl5V l¥JE!!ffio supplies power to the high-end tube PQ5,at this time,the G pole is no power,so the S OVAt the same time,B+ of 19V is input to PU3,the internal produces the linear voltage ugh the internal diode supplies power to BOOTl,if skips the pressure drop,its still m ofPC33,to charge it,the capacitor stored SV voltage. 00l'1 !* UGATEI t>!HJ:~Z9JjJ. £I±l~ili 5V (t-J~Jt:SP:, J!iU PQ5 B~ G fJk, !!tat s6 11~ SV, t&~ OV, PQS (t-J14JilrpJl2Ajc~~Jm, 19V ¥m.i1 PQ5, PL4 ~ sII'I±l (t-J JtJ.3iii~ .L1T• SV supplies the power to UGATEI,sends the high level about SV,is sent to the G time,the G pole of the moment PQS is SV,the S pole is OV,the channel of PQ5 completelY,19V flows through PQS and PU to charge PC35,the voltage output by . creased. Scanned by CamScanner

B. Pl._ \".7UH PCWcoe::rr-tR1MN 5.5\" ......-~VL Typ: 175mA Figure 9-6 PWM circuit using the boot-strap method 3 PQ5 ~tI:Il¥JJt!lli~~7t~Il1, flii;Jg 2V, l!1- 2V IfiJIl1;bQ¥UJt!$ PC33 I¥J 2 Jli\\l, E13-r~ ?&:AtliftE, 'BI1IJ;tfffit7 5V tJ(JJt!, JltfJ1-iJb-1- 2V, JiJTv)', Jt!$ft~tE.Wi:~ BOOn ~~ 7g 7V, 7V m~~ UGATEI ~Jt!, PQ5 rro '5j m~;Jg 7V, ~ PQ5 -f*r.f Vo>Vs, *'§J~i:t 4.5V, PQ5 1*M:~~7t~~m, s ltatBi !ftit, :pJ~~QJU PC33. ~QlIt~1f, :{£ PIA (J'~ftftiMPJv)'~~¥U.iI!li 19V, 1I1~ OV tJ(J~. 33 tJ(JJt!.:M:i~¥i1f:'&:~j!j!, Boon Btl ~lli t!?8Jt4?7j(ili;~t PIA ftjfiiij 5V, liP 19i: - UGATE1 1¥J~%t!?JM';~:lif~ OV, A:ifIi 24Y.. When the voltage output by PQS .is increased,if this voltage is 2V,and 2V is ad VIIIl_ of the capacitance PC33 at the same time feature of the capacitance,it just stOreS 5V.at this time,adds 2V,so,the left 0 (that is BOOTl)will become to be to supply power to UGATEl,the (jJ also become to be 7Y.keeps PQ than 4.5V,PQ5 keeps conducted of the S pole will also follow to highest 19V and the lowest 0'1. not be discharged the vol~ Q -114- Scanned by CamScanner

~onn ofUGATEl is also that the lowest is OY,and the highest is 24Y. e regulation circuit iI..-, iI~ FB .&tJtlJ!lJiinHf.JjJ}31-!fR~~~£I.:5HL -'=i~$i¥J¥ifE~ffbt$x, N tU~*:tt~ in figure 9-7,through two sampling resistance connected by FB feedback pin o ,compared with the internal reference voltage,so as to realize the output voltage putational formula is Vour=FB X (I+RtlR2) , Rl f1l R2ff1~, D!~ Vour=1.6Y. lis equal to R2,then Vour= 1.6Y • .......~r-+-...---t:---- .5V ALWAYSON Scanned by CamScanner

protection).3.3V of standby voltage over-voltage protection waveform is shown in figure 9-9. 'Ii JL • At eoo.,lele MPos: 0.000, M£ASUlE ... : --nil . . . . . . .. . . . : . • fi5J1S ; ; : ::; 1~ ... ; : :: : ~ : : ~~ 1 --nil '~-\"IS 'l.?6V ~ JalM _1- . .. : : : : .: .. :. CH1 ..: :: 7C CH1' v M JJS 1~ 22-001-1210:18 <llJ1Z Figure 9-9 .3.3V of standby voltage over-voltage protection waveform [)(){> 9.1.6 ttlii-ttillttlJ& the current detection circuit PWM [email protected]~MIl't*Id.I:I1~¥ilto ~i1mtll't, ~Jtpg$mffl OCP (i1¥m.{~Hf') ;t!tllJlJ. RTI201A1B1C ttld ~¥iIt((']1JJ:t~j1ijf'P: BOOT I-----.J\\A--. UGATE 1----.\"\"\"~~__1 ... PHASE I-_-!-_L--+-:'':':'''....rrn. LGATE 1---.!!:~~~i4. PGNDII-----~ FBI-------=:.....--=--- ~ 9-10 -116- Scanned by CamScanner

urrent,its not very precise.During calculating,we should use the maximum value of the 'n the data manual of the field effect transistor,and considers that the resistance value d effect transistor conducting will be increased with the rising of the temperature,so its certain allowance.The benefit of this way is reliable,and its the nondestructive over- ·on. 1±I1@,EHtffi, ~m l:ti 1tV1ti1V1tat, ~Jt~Jr.5 ffl i*J WB~~'tr tI:J llX ItmJt0 !ltmAr , .iibffl~ft~lfi~ OV f~lt3f, r~ G f}HgZ9Jf§%iUgZ9J~ 5Y i'8'i1t-'f, !ltB1J:~~ ~ ~iI, \"1±I~~It~LfiM¥1¥-JIt1niimi1r~illi!X1!f!!}j)(It, !fu-'tr:±lltffi:k~ 0 output voltage is over or the output current flows through,the chip will use the internal ~rgit1.Ii mode.In this mode,the top tube G pole driver signal is turned off to be OY low Ie driver signal of the down tube is driven to 5Y high level,at this time,the top tube is cut tube continues to be conducted,the charge stored on the output filter capacitance is quickly the ground through the down tube,the output voltage is closed. : PWM 1t1&1fi, p:~t1F*~Jt m:IJlllto ..t\"if G m~~~-@f~ YIN lIit1JIl3Wm ~\" , ~nder:in the PWM circuit,is strictly prohibited to remove the chip then power e ot: the top tube is suspended,which will cause that YIN is added to the rear stage the components. • 1fi~*$1lr PWM It~ IC ~~If1=:A::f/6J1¥-JW3flPmJtr, PWM t~Al*. ~~~.~), ~§~.~7.m:f/6J~~~~~r,.tI:J:f/6J~It~(.tI:J ~~Ifi~S~mT~~.Jtm~, ~S~~~~at,~JtI~T~~~~m :m), JltIl'1'u.l±I [email protected]./J', 3V #[email protected], :A:#ftltB1 ~ mfIf1=:A: SKIP f~Aen R 3V ft:tJt [email protected]¥-Jm tI1 [email protected]~\\ ~!l1JJl , j;§~JltB1-@ ~!Jf 1tJ.I:l$J El3 3V fJim Itffi ~.tI:IE@.:i)ft~\\@i!l*, ~Jt~ SKI~ <1itfflICH ~tI1~ SLP_S3#~f1i~) jj WM.~,.tI:[email protected]:f~,@.tI1E@.~*~o 051 ofPWM power IC can work in the different two modes,PWM mode and .on mode) the purpose is to adapt to different sleep state and outputs the different ~ cqnStartt).There is SKIP# in the chip,is used to realize the mode switch,when c' works in the pulse separation mode(SKlP mode),at this time,the output as 3V standby voltage,it just needs to work in the SKIP mode when in the P9wering on,the output current of 3V standby voltage must be system voltage at this time is from the 3V standby voltage Ui'J'etlt\\IDust be increased,SKIP#(usually controlled by SLP_S3# sent works in PWM mode the output voltage is constant,but the Scanned by CamScanner

I. PWM.~ PWM mode PWM m~rlt!ffi*:D1~fj~j]53L ~utl:llt!mt::k. PWM m~rl¥J~m:tmoo 9-11 PffiF. ~ $~ 299.4kHz. In PWM mode,the voltage load capacity is strong.the output current is large.The waveform in PWM mode is shown in figure 9-ll,the frequency is 299.4kHz. 2. sKIPi#l;t (McitPfBJllMmit) SKIP# mode (pulse separation mode) J¥!.{ftlJ1fiijpg. PWM ~m~y, V!lJ4iI\"IjtJj It!mt~/J'. SKIP#m~rl¥J~m:tmoo 9-12 ffiiF. ~$-rx. 34.63kHzo Within the unit time,the less the PWM waveform,the smaller the output current.The waveform in SKIP# mode is shown in figure 9-12,the frequency is just 34.63kHz. \"- lIllWiEI f4Jii.5h1~\";\"\"\"'''''''''''''''''.-...:f~~'''''~iftot1,a.v- 2ISIQHz Figure 9-11 the waveform in PWM mode Figure 9-12 the waveform in SKIP mode -118- Scanned by CamScanner

. A~M~~mit~ PWM fjtit~~: ~*Jrlffi'lZffif~iH?J1J~~o (is in common use with MAX 1999) is the standby power chip with high efficiency o\\¢put produced by MAXIM company to use for the laptop.The main features:not detection resistance; 1.5% output voltage accuracy;supplies the linear output with maximum current with IOOmA;can output two path of PWM power supply:3.3V ~....'..'l!i voltage range of 4.5-24V;the choice of the pulse mode and PWM mode;over- -voltage protection. the pin name ofMAX8734A(the top view) 'on ofthe pin definition and common used pin ~ 51J1J!6~:lm1ll9-13 ffTlJ'o e ofMAX8734A is shown in figure 9-13. slB_lJjJtiJE)(~~ 9-]. 'tion oftbe pin function ofMAX8734A is shown in table 9-1 . • 9-1 MAX8734A SI.IjJ~;E)( the definition ofthe pin function ofMAX8734A iiible inputON3 connects to REF,3.3VSMPS will start after 5V SMPS being le'inpuhONS connects to REF,5V SMPS will start after 3.3V SMPS being stable. The main switch ofthe chip,the opening ofthe linear voltage. Scanned by CamScanner

12 low noise mode controI.When SKIP# connects the ground,works in the idle mode,when SKIP# connects VCC,works in the PWM mode,when SKIP# connects REF or is vacant,works in the ultrasonic mode. 13 frequency selective input.When TON connects VCC,chooses 200/300kHz worlcing mode,when it connects the ground,chooses 400/500kHz working mode(respectively corresponding the switching frequency of5V,3.3V SMPS) 14 the bootstrap capacitor connection terminal of 5V SMPS 15 the inductance connected 5V SMPS.lts the internal low-end power supply rail ofDH5.LX5 is the current detection input of 5V SMPS 16 the high-end G pole driver of 5V SMPS 17 the analog supply voltage input of PWM core.It needs a I capacitor bypass 18 SV linear regulation output.It can provide 100 current.If the voltage of OUT5 end is higher than the LD05 switch threshold,then LD05 regulator is turned-off,and LD05 connects to OUTS through a small resistance. 19 the low-end tube G pole driver of 5V SMPS 20 the main power input 21 5V SMPS output voltage detection input.When the voltage of this pin is higher than 4.56V.it will replace the internal LDOS output. 22 3.3V SMPS output voltage detection input.When the voltage of this pin is higher than 2.91 V.it will replace the internal LD03 outpul 23 ground connection 24 the low-end G pole driver of3.3V SMPS 25 3.3V linear regulator outpuUt can prov.'(ie higher than the LD03 switch threshold,then IOOJ3 OUTJ through a small resistance, 26 the high-end G pole driver of3.3V S·ME~\" 27 28 the bootstrap capacitor connecti ~~ fft ~ N,C. 2 PGOOD -120- Scanned by CamScanner

ON3 3.3V SMPS f~tJMiJ1jA. ~~ ON3 ~ REF il'Oi1, 3.3V SMPS ~f-E 5V SMPS ~~J§Ja ZJJ SV SMPS f~BMlltlA. ~~ ON5 ~ REF il'Oitf, 5V SMPS ~1£ 3.3V SMPS a~J§Ja ZJJ 3.3V SMPS ~~¥!rUp.j:P 3.3V SMPS &tjftWiA. ~ FB3 lim GND ~j~IJj])E~tll±J 3.3V, ~ FB3 ~~~ OUT3 *tJ GND z.rEi]I¥Jr:g~.§.7tlli~, Fi~~~~fJil2~5.5V B~ iiIiJIIWHti SV SMPS &tJHlitiA. ~~ FB5lij~ GND ~;j$~JE:'futll±J 5V, ~~ FB5 ~~~ OUT5 ~ GND z.rEi]B~r:g~.§.7tlli~, fj~1yp~fJil2~5.5V (j<JPJifril _ttl j1ffi~Xffif~H?f~\"~JJ!P. PRO#m vee 1Jt, ~.L!:f;\\jHF. PRO#m:l:iP. IM\", 1fJ6 f~UFJ1J\"~ f~~fI5.;i:\\~$JJ. SKIP#~±t!!.at, If1=1£~I*Jf~A, SKIP#m vee IM\"If1=t£ PWM m;i:\\, SKIP#~ REF §x~£Bt, If1=?±~Ff~A ~.~~.A. TON ~ vee at, ~;j$ 200/300kHz IfF*~A, j~ i&1l'j~1f 400/S00kHz If\"Fm~ (7t~IJ)(1Jiil 5V, 3.3V SMPS B~7f* ~.) ~~ SV SMPS 1¥J1t~. ~ DH5 I¥JI~rmH~~It~!fJL. LX5 t! 5V SMPS 1¥J ltVft:ttld4tA w *ilM:a5• •ttl. 1iJ~~ lOOmA It¥t. :tm~ OUT5 ~Et!lli,~ 005 **J1Illl, JJI1.. LOOS tiffia~litfi, 1l LD05 JiIi)i-l' .-JJOUTS fJf~.1'G .~f;IJ Scanned by CamScanner

24 OL3 3.3V S~JM},PtS.H~Ol~lfi~~~~H':II:rI.G mjj~Jit;lHIJ]~ WJ* OUD ~Et!lli~ 3.3V IOOmA r4!mt. 25 LOO3 f L003 7f~f1llfL JJI) Z L003 frJ.ffi$~WT, jt-J3. LD03 illi1 \"1 'J' rgliIl.i!t~ftl OUT3 26 OH3 3.3V SMPS ((.]j@j~1f G ~&~i;lJ 27 LX3 i!t~ 3.3V SMPS a!Jr4!~. ~ 3.3V SMPS ((']r4!mt~~U~A 28 BST3 3.3V SMPS a!J 13 ~r4!~i!~g;jij The electrical features of SHDN# threshold value in the MAX8734A data manual are described as shown in figure 9-14. mmR Inpul Trip Level Rising edge 1.2 1.6 Failing edqe 096 1.00 The screenshot of the description of the electrical features of SHDN# threshold value of MAX8734A [~] explanation SHDN#tuJV,,~{ir4!.;y;: l:7Hft:ll:f~{i 1.2V, -1li73 1.6V, ~i'1i73 2.0V. HDN# input threshold value level:the lowest value of the rising edge is 1.2V,usually is 1.6V.the maximum is 2.0V. SHD #~A~{ilt!.;y;: \"fJf¥mllfQ;{i O.96V, -~73 I.OOV, .~73 I.04V. SHON# input threshold value le\\lel:the lowest value of the falling edge is O.96V.usually is I.OOV.the maximum is I.04V. MAX8734A 1'flti:tt&-¥JJtep~ @ In the MAX8734A data manuil described as shown in figure 9-1 01'3. ONS Inpul Voltage 0.8 2.3 v Figure 9-15 the screenshot 0 [1m] • Explanation ON3. ONS .AE! ON3 and ONS inp ON3, ONs.A -122- Scanned by CamScanner

mput oltage:when it i 1.7 - 2.3 V,delays start. 4* It: T 2AV 111, I'UtJFJtlo input voltag :when its higher than 2.4V,opens directly. ~lcli tllfl:f:l~fflJWi1ffif*:tPI~{r:IrtJiTI~W't1j1:1i~!lDI~ 9-16 J5fr7.f;o Witl:Jrt!. 'llI:I'I:[;-~-flitJfli\";IJi:J:llif~H?: ~/Hll 8%, -mHil 11%, l7?l::k1t 14%0 {VtlYD, i& JJ 3.3+3.3*1 I %=3.663 V ifJtf~iH?o 8734A data manual,the electrical features of over-voltage protection threshold shown in figure 9-16.When the output voltage is higher than the set voltage to a it will start the over-voltage protection:the minimum value is 8%,usually is • urn value is 14%.For example.sets to be 3.3V,achieves 3.3+3.3* II %=3.663V,then to FB3 or FB5 with respect to nominal regulation point +8 +11 +14 the screenshot of the description of the electrical features of the over-voltage protection in the MAX8734A data manual A (j(jU~M9='~~I±iXffi~1?~flltr-JEt!/=t*fttrai~~DOO 9-17 fifr7.f;o ~D;~Hiltr li~lt!ffil¥J 7()O/O (-ftfll), utJSz;lJxllif*1?o 8734A data manual the electrical features of the output under-voltage protection described as shown in figure 9-17.1f the output voltage can only reach 70%(the f:the set voltage then it will start the under-voltage protection. FB3 or FB5 w11h respect to nominal output voltage 65 70 75 screenshot ofthe description of the electrical features of the under-voltage ~:ecti'on threshold value in the MAX8734A data manual PJ.:& oun ~ LOO3 tr-JtJJ~It!i&:tmm 9-18 ffi7fi: OUTS/3 Mi:ct ~i$lt!ffitifl ilia of OUT,LOOS and OUTI,LOO3 is shown in figure 9-18:when OUTS/3 ill r;place the internal linear voltage output Scanned by CamScanner

FB3/FB5 connects to the ground,You can choose a fixed output 3.3V and 5V.If FB3/FB5 connects to the resistance divider between OUT3/0UT5 and the ground,then it can adjust the output in the range of 2-5.5Y.The specific calculation formula is VoLJFVFBoCRl+R2)IR2.is shown in figure 9-19. MAXIM M~8732A MAX8733A DL MAX8734A GND 00 9-18 MAX8734A I'f.J OUTx!3 LDOx t.m~oo 00 9-19 MAX8734A 1'f.J!iu~l:!:lffi.iJlfiJOO Figure 9-18 the switching graph of OUTx and LDOx of MAX8734A Figure 9-19 the output voltage regulation diagram of MAX8734A ~~~moo:tmoo 9-20 JiJT7J'o The typical application diagram is shown in figure 9-20. 3. -f6:If'Fat~ 1r $'G~ V+!iu\"U A, V+t£JJJ::J:I!m.7}ffi.A.~~;'HmJli~* J:I!.If~ SHDN#fF ~7fJI5 • MAX8734A J14~;a:~ L005, PiJ'IlIS!6t1Jtmlll9-21 JiJT7J'o First,V+ inputs,V+ through the: resistance divider input or the high level sent by the external acts the open for SHDN#,MAX873~A will produce LOO5,the internal structure is shown in figure 9-21. -124- Scanned by CamScanner

.... lUllV '\\r-..;;,.\"...j 11LI1-----=i 'IaI---I OllTll----=--==-----...J .'---l tal '1c I~I----+-- '\"\" III 9-20 MAX8734A A~}§Zm 1*1 the typical application diagram ofMAX8734A Scanned by CamScanner

r---------1!:.v.--------, PGOOO ~AXI~ MAX8l32A MAX8133A MAX8l34A TOIl 4)(UlIAXII·.:.:T.I4 :----It-;:=~==;-n 5V SMPSPWM j(!\"lB Vee 009-21 MAX8734A P3$~OO 00 9-22 Figure 9-22 Figure 9-23 -126- Scanned by CamScanner

REF being stable,outputs the linear voltage LD03 of 3.3Y.The timing sequence ofV+,LOOS LOO3 is shown in figure 9-24. r'T~-_-r-_~'~W<:!!!!9rJ2~A.l3.AJ~'~\">:22~v+ lOV .. \" 10V/div :: :' :I\" :,. :_.~.O ,f\".-:.- -t;-...-!\"\"-;......-4 LD/05 '-'--1 :DV:~v '+. . . . .or\"\"'-¥-t\"l-+i4-i-m..,.f,....i,. ~1I....J ..;...~~ 2V/div o..._..:.... : J7~\"\":\":' ~~:~...-.-.--I ~~jdiV o tI '·:,_:.. . .: • I :. 400llS!div rr[II 9-24 MAX8734A ~tt il!llillt the timing sequence of the linear voltage ofMAX8734A DDects Vee,ON3 connects REF,is shown in figure 9-25,so,the chip produces PWM o SV first,after being stable,then produces PWM power supply of 3.3 Y. 5 .~, :tzolll 9-26 ffii.f;, i!~~7E~tl:l 3.3V ~ 5V. 3JiJf1:f4TItrl:l:\\m~JE m• •Iti PGOOD, vee t£j:j: IOOkn x.fJL. 5 are connected the ground,is shown in figure 9-26,chooses the fIXed output 3.3V uts being stable,the chip open drain outputs PGOOD finally, is pulled up by the ~: FB3 100kQ -- PGOOD 1119-26 FBD Scanned by CamScanner

Control timing relationship MAX8734A ~*IJlltff*~~}(m!;&.9i!.;&9-2. The original of MAX8734A control timing relationship in English is shown in table 9-2. Table 9-2 MAX8734A control timing relationship(the original in English) SHDN VON3 VaNS LD05 LD03 5VSMPS 3V SMPS (V) (V) (V) Off Off Off Off Low X X \"> 2.4\" => High On On (after REF powers up) Off Off \"> 2.4\" => High Low Low \"> 2.4\" => High High High On On (after REF powers up) On On \"> 2.4\" => High High Low \"> 2.4\" => High Low High On On (after REF powers up) Off On \"> 2.4\" => High High REF REF High On On (after REF powers up) On Off On On (after REF powers up) On (after 3V SMPS is up) On On On (after REF powers up) On On (after 5V SMPS is up) [111m] Explanation '!lOW: SHDN#t:11~1t:sy., JjJ3~, 1'~ ON3 ~ ON5 ItBi~1~, i:!G'tj: 5V, i:!G,tj: 3V, 5V 7f ;kFQ.1L5'!, 3V 7f*It~~~*~, &~!ifilili. If SHDN# is low level,then,no matter what ON3 and ON5 iS,the linear 5V,linear 3V,5V switching power supply and 3V switching power ~ply will be closed,there is no output. '!ln~ SHDN#::kr 2.4V, W ON3 ON5 .~~a;It!.~, ~115V, ~tt 3V ~:fJjz7f~ (~ tl: 3V ~tt REF ~J;EJ§~l;JJ), 5V, 3V 7f If SHDN# is higher than 2.4V,and ON3 an 0 el,the linear 5V and linear 3V will be opened(the linear 3V will start after REF be\" switching power supply are closed. ON5 fi] '!lO* SHDN#::kr 2.4V, ON3 ;k E\\:!.iliflflI~1T7f, ~ Itffiffi ili • If SHDN# is higher than 2.4V:ON3 arid B supply and 3V switching power supply will \"!LO* SHDN#::kr 2.4V, ON3 ~ rt!.¥Jh!~ff~, 5V 7f*It.i£~mo If SHDN# is higher than 2.4~ and 3V switching power supply are; \"!LO* SHDN#::k-F 2.4V, m rt!~mtflt7f ~, 3V **ItKU -128- Scanned by CamScanner

#•I is hi her than 2.4V'ON3'IS Iow level.ON)~.I hi.gh level,thc linear SV.the li.near 3V *7-nNg#pow r supply are opened'3V SW.ltCI)'Illg power supply i closed. 2.4V, ON3 ~~Et!.!jL, ONS l!H~ REF m~t 0JH1sv, t:JH13V, 3V 7f ~, SV 7f~rt!.It~tE 3V ~~J§Wm~J. 1•# is h. igher than 2.4VON3'IS hI'gh level.ON)- connects REF pin.the linear SY.the linear tchlDg power supply are opened,)~V sWl.tCI1'll1g power supply will start after 3V bel.l1g SBDN#:kf\"- 2.4V, ON3 i!1l REF J]t;p, oNs1~jl6!jEg~t ~JH1sv ~JH13V, sv 7f ~, 3V 7f~rt!.ft~tE SV ~~J§fI}JSi0. # is higher then 2.4VON3 connects REF pin.ONS is high level,the linear SV,the linear 'tching power supply are opened.3V switching power supply will tart after SV being TPS51125~;tfi analysis ofTPSS112S 5~~~.ffl&~~~~~~-~ffl~~~*~.~m~IT~~m~~~~n allo ~If1:JtBs:~ 5.S-28V, ml±llt!ff~ 2-S.5V Q)'ijlJJ, 1J<ff 5V fa 3.3V rm ~~5~ili, ~~~~~I%~2v~~lt!ff~I±l,~~urr,~IT,u~~ JjJMo 'Emilt 270kHz (fl VCLK ml±lQ)'ffl~~Z;tJ~r1:tfl§~fj-ITI:I3lij, 1:£/1' !Ef.1:3lt*trotf~r ~ffltffl ~J§1.1 1t!?Jj~~ 7f1c~~IJH& ~~19J It!IT. TPS5 I125 5f. ~1fi~:JHi1~Ha~~1tfmffi%. Out-of-AudioTMmAtH~t*fF/1'{g~:E.w. 7 111 M.T~~~$tl PWM • • (8Jl economical and efficiency dual channel synchronous buck controller produced use for the standby voltage of the laptop.The voltage is 5.5-28V.the output adjustable with SV and 3.3V two path of IOOmA linear voltage output and 2V o ilt with internal error I%,integrates the over-voltage,under-voltage and over- the function of over-heat protection.It provides VCLK output of 270kHz to boOtstrap circuit,in the case ofno reduction in the working efficiency ofthe the gate drive voltage for the rear power conversion switch.TPS51125 ien response and provides a combination of enable signaI.Out-of- operation realizes low noise and its efficiency is higher than the traditional Scanned by CamScanner

Figure 9-27 the name ofthe pin ofTPS51125(the top view) TPS51125 i]IJl!IJJE5C~!.~ 9-3. The pin definition ofTPS51125 is shown in table 9-3. • 9-3 TPS51125 sIJl$~)( Table 9-3 the pin definition ofTPS51125 Channel I open and current limit set pin.The direct grounding closes the output,sets the threshold value of the over-current through the resistance grounding 2 the feedback of channel 1 3 2V reference voltage output 4 the frequency setting 5 the feedback of channel 2 6 channel 2 open and current limi • ding closed the output,sets the threshold value of the over-current through the 7 8 9 10 II 12 13 the main starting sl -130- Scanned by CamScanner

open the linear when through the resistance grounding,c1ose VCLK and ready to open grounding,close the whole chip. Ode and pulse mode select pin power supply input,is the origin of the linear voltage power supply voltage output of 5V ency output of 270kHz,is used for the boot-strap circuit of 15V tube drive of channel 1 pin of channel 1.Function:<Dthe top tube conducts the 100p;(2)the current detection . g pin of channell,the boot-strap terminal ojtage detection of channel 1.Function:<Dvoltage detection;(2)is used to replace the e~......~....,.. ~_~ ----, # )E )l.. iii! 1 7ffi3~IIIHAt1i)E~ • .m~~±I!!.*I~HiJ\"Ul±I, illi:ctEE!.~.EI.*±l!!. \\ijEitmtfIJil •ilil27ffi3~~~1ijE~ .m~~~~~~I±I,~uEE!.~~±I!!. ii~u.JJil ;1m2 tIfIl±lft!.llittl~. i'Fffl: <Dft!.llitt$J!~; ®FllT~~~ttEE!. Ii. ·~2~~~.~ffl:<DL~~iI~~;®~mt:~ft ,ft.llacJ::J)\"\"~f;b fFJ:lJ: ®.~I!'t1T7f~1t, m-l-1T7f VCLK ~ ~~~~) Rn7f~~,~~V~K~m~1T7f 1. ~mtil;1f Scanned by CamScanner

l'~ H,:rlJll'l'. ~ ENO l'I~I;'9Jfat~'i.i£~nl~ 9-28 pJT}i;: ~ ENO n~L{Uld\\T­ rfJl: I·NO lUll k O.8V II·JJH·lrJG'~E. ~I;n VCLK; ENO 1t!1li:kr 2AV I K. hI \\11 rr 11_: d It \\ Illanual.the threshold value of ENO described as shown in figure 9- .' \"h II \\h ,)lta' l rENO is Ics' thun OAY,th chip will be closed;when the voltage of END is III, h'l \\han 0. \\, p n th Iinc'lr und do 'cs VCLK:when the voltage of ENO is higher than l ,'I 'II, til lin ar and LK. Il-_~_:l;d ::[J l Ibng ~;.=. ~ ;. . :~:JI-\"=;.;.;;U;:.;;1dOWll;.;..: li'II\\'-_ 1'tI TP 11 fth d ription of electrical features of ENO threshold value in the til TP 51125 data manual NTRIP#tt<JlJJmtli~oo 9-29 PJT7F: ENTRlPl {O ENTRlP2 l'i~un: -_ til Scanned by CamScanner

II Inlh' L'hip is ~11lI\\' 11 ill Ii 'lire 9- O. I FU\"'. IJIII'III 11 iV, 'J, (J { EN iJ~, VIN )t;~~¥,r~ II,; n~JII·.'t' :l:·I'I(J)X.~'I1'III~Au;i,j, ·lvml]/Clt. VREG5-t1l t.th n produ' . VI ELi''',L shown in Ii 'urc 9-31 ,aftcr EN being n 1.lh II I EF Is inpllt I th' invcrtctl input terminal of the • ntrol. Ih· pI' ltillction ol'VREG5 lind VREG3. IUlIIII.JBH~ ~ n~ll!. !1~·t/I·JUd£UIII·1 () 2 mIJ··: V 'LK 1':1 270kHz ~jz [ I ~I~ O.06V (~Q 'II! !I'I) \" ornu I th I 'Iri 01 l'clItllrCS V LK de. cribed as shown in figure 9- 7 kH I 4.9. V in Ih • high Icvcl.i. O.06V in the low levcl(the typical . - ' - - - - - - - l - { \" J VRCG3 h m tic diagram ofthe production ofVREF and VREG* in the TP 51125 data manual 4.84 4.92 v 0.08 0.12 175 270 325 kHz ription ofthe lectrical features ofVCLK in the TPS51125 d manual ~. &a. VCLK ~i~E!.Jf, VOl t&i:2: 2 :b~ sv (~.-. .m.> ~~ IOV. IOV 2 !t )'fifl!.. ~hhS sv ~i:2: 04. Scanned by CamScanner