Laptop Repair Part 1 OCR

DosXX Dunkel 1.0 l~fJLFl1K~7J\\\"~fi • ofInventec DosXX DWlkel 1.0 standby circuit Bt+VBATR {tt¥:~~tfLrg&~t-Jt TPS51120 (/j YrN JY.IJ, rD-f- EN3, ?apgm~t£~lli YREG3 ;fD YREG5. TPS51120 ~·(JtrtU+Y3AL. (Be. SMC KBCI070) 1t=79Jt1~fJ1:(j~FQ., !.lIJI~ 13-6 f1fff;. common point voltage +VBATR is supplied to the YIN pin of the standby 6ecat1Se EN3,EN5 is hung in the air,is set to be opened automatically the VREG3 and VREGS.TPSSI120 outputs +V3AL,+VSAL.+Y3AL is (1070) as its standby power supply.is shown in figure J3-6. ~.. ~ _, J_.<'II RTC 'tY1AL -~ 0_\"' <OPEl 1 Scanned by CamScanner

U1B_DATA 1.... XTAL1 70 XTAL2 71 CLOCIO 5IlI -TP721_ X1 32KHZ_OUT_GPl022 75 32.7A~ •nRESET_OUT 10 TEST_PIN 41.11 T7 II II VCC1_PWRGD 113 ~-~ _nBA_T_11..££IIll tt5 r--..!.~64 nFDD_LED 114 .!..-\" ..oIIS_1.£Il ttl I PWEGD 711 •NC Il5 He 17 NC 127 NC 121 He II! I~I! = SIISC_KBC1070_VTQFP_128P Figure 13-7 the standby clock of EC EC (t-J 77 JJ!lJJg~fiL(§%o BB1=*1mit!: +V3AL g':i1 RI23 5¥O CSO ~nt~ ~ UIO Jg/f!JrPJ~, ~M 4 Jj!p~')jI:JJ~EEl.fB1 VCCI_POR#_3. t1000 13-8 in ofEC is the reset signal.The origin is:+V3AL through R123 and n high level of UIO,UIO is synthetic.it will output the high Ie elof ill own in figure 13-8. Scanned by CamScanner

'( (' In\" 1111' \\\\llell Illth Vl . V A llllltlh) Scanned by CamScanner

.B~ ~ ~--_=-=-=------t----;j:!~l C~ ~ ~ ~L. ~~' ~ ,\"7> fl -0 lsi '><+n - -! ~lII'II'i::5 I . I.i <t: it -=n. Ii ,2 -,.Idlal ><'1 + 5, 0- ~ I :::! ~ Scanned by CamScanner

~1 igure 13-9 the production ofV3A. V5A ;)trJ-J t~lU rrfi:ft. f Wf1T GPIO f~ I,;, rll GPIOO? ~n1UJ RSMRST# e ··~~~T#Ej TPS51 120 ~ 30}j!p (y~ I~ 13-9) !hJiJ 111 (fJ f;; g ~1'I!=:j (;{H~:(£ - ~]~;T#JJt1J , jillr.il r*HJflit[J·H!HJL1l!.).f.IE1(,' of standby being satisfied. its internal procedure configures all of GPIO by GPI007.is shown in figure 13-10.R MRST# phase with(connected ut by 30 pin of TPS51120(as shown in figure 13-9).then to send to ~:$Qlttb bridge.to inform the South bridge that the standby voltage is normal at ~lD~~L~~~, ~~~~~~o ~!!91lIWJlete the subsequent trigger and power- Scanned by CamScanner

n1 . 3. 1 ocp Fl:!.i~ fFf *li\"~ nal) i f P ircuit l~J.:9Ub~ D XX Dunkel 1.0 l HP_ :1 Ob) -'*.J I ~ fIT ocp E€.g~ ~ 13-11 +VBDC N:E€.$lE.Jlt~r:J, t£ii- I o,ol·~ag~~ift~; ~Et:!.~1lt\". I -0*-\\ BDCR, C5E€. (ft' jJij1-tt!1liPJlJ.~J7X;f§raJ. (~~ ;t;:*!EJ(~;tP.1V-, ~ ~. ~IIY, It ~ . 7j'!.Cr-#: As In enlec Do ' Dunkel 1.0 an :\\ample to explain OCP ir uit in thi rion.ln the fi\", 13-11,+VBDC is the battery di charging p rt,thr ugh lh ulTenr ns I' i tor \\\\ith 0.01·~ make a new name - BDCR.b cau the re i tance value i vel') mall.rwo of\\olta;:;e an be nas the same,(calculated as 3 core series bart 1')'.3*3. \"\"\" II ',take an integer,i com enient t cal ulat . rn 13-12 r:p. ·0· ~-1 L r' :8. ~~Z:0- ~7.-. +V8DC ~,-19raJiiHiL ~. -~&ffi~': ~,~ T'->T'-Bt. ~JtI:J VCC ~~, .3 r'-<r:.l!'t'. o-r , G D ~~. ii~. -l ij!;JJag G ~:IF~~, I~ m¥IJ.,.-VBDCR EEl II , ili~si~3 r:..<rllt ..:. tI:J 1\\i7*~ llV. ~ 8 ~ B:J \\'cc ~ eg B ~­ MAX_LX5 agEt:!..!3iE]-v·S §~Tf-.!3i~*. tEl@~~ tt!~ C530 LF1:.- I {8 16V B:J~Ili. ' G'\\D 3= IIV f.litI:J7 :V, PJ~~~1.&·:J~~~;_· ~ 3 .=' B9+~~+VBDC B:J 11 \\ • In the figure 13-1-.U·O- is L\\13 ·S.i the • vc;rting input terminal- is the inverted input terminal.\\\\11 n o uts GND logic. ote,G D with 4 pin is not !!found d.-. Y-i <Y- the output should be Il\\'SCC po\\\\ r 5 lifting pressure.and produ e the GND tenninal II V to -Y.it an tenninal of 3 pin L II \\' 0- Scanned by CamScanner

U505 .,1o...'.'-..1J-,1\"'~G-.3t~\"',JI-,J\",AS.~.47_.,S4.. '.+VBATR : 'OUT , BAJ~S~30Vj.2A· +~sS· 11N· vee t\"---+---J. 2 \"\"-t------1l'IN. Q38 5-.1-.7-.....·, 1-.1J-,n ClND ~M3K7002F ' 09025 RLZ18 3 1\"' 1 DP_PRES 2£1 .. \"''',7·''''''''· Q38 ~SM3K7002F o 7· MAX LX5 !,.Ia~~ .r.e~~ ' - 17 . .L.14: tHENKO_LL~f48_2p· J&~E13+V5S ~ Q38 t~1~B~, J3.~2 Q39 ~ ADP]RES ~fjJIJ, ill .~m~~, ~~n*ffi~, g~ill~I~o circuit is provided by +V5S through Q38,and is controlled by y~der the case of no power or the adapter inserted.it can not orking. tp#im~Jt U28 ~\"trl±l+V5A Itffi~;ffi1}iMP. 7J~tnru ~ATP ~EI!.ffi. EI!¥t!!.mA~~1iltffi~T IIV 0 the phase pin of+V5A voltage output by the standby ~utP-titS.The voltage of pulse crest value produced by ~ the crest voltage is equal to 11 V in the battery M''''''''U\"'l'~'~' +V5A Scanned by CamScanner

1iClII . I .-11 thl: ori:ill of' IA.· LX5 JotJ 1 :O~. I, J.(Jnuli'l~ _.5 '1i1iJ 11\\ 1'10 .[' I. IfiI){ I.::!..J. V IJ~J 431 L (~I R fl1 C L' t ~ IJ IIJ, p .;;J ll!.lIZ IIMH!: ~;I~ Ill! 1.24V) 0 I~ qI A yiM Ii:i.I n~~t±fu. B R. \"ljl'llljTJ.O:U I \\;iull!.lk·~ A+1.24V=12.24V (lb.iEJJ)(D~ vee }IFn~~ J'oII-J: !lt~ R·T- 1;~1'J~ 1-._-1 tfii\" I 1l!.IIIUU A tri[J. 1TJJi&I:!Pi-f7HII: 100kn )j-1F. il ~H,Jj;u -05 I'J~ 2 JJ14179 II.095V. J:11*i-I-~J~[1.24V/(100~+ I o 7.6 k...,) 11 10 1 -I_.the hip 504 is n t -1 1 output by the ordinary 2.5V,is 431 L of 1.24V nn t d t gether.it a t as an voltage-regulator diode,the voltage of R terminal th n t nninal t 1.24V).The A terminal is also not grounded in the ~VBDCRof II .0 we can know that the R tel111inal is A+1.24V=12.24V(VeC pin liti through R516 to supply the electric power),12.24 of REF terminal h to A tenninal.if there ha e the differential pressure,then there have 7.68kn series partial pressure.calculated that 2 pin of USOS is .24V/(100~ + 619n+7.68k~)*(6l9n+7.68~)+ II V]o JII(J(J 11.095V, V+< V., 1 J]!p~1!iI:B GND, wtfik 11V, ~ DCRllV, -f&~~~ii.!L )§~:f:$J11=o in is less than Il.095V of 3 pin, V+< V-, I pin outputs Je ofQ509,the B pole is +VBOCR 11 V,the triode is . .-illm~.m.~*, M®~~2~~lli&~ vcc, ff)t~ l6Vo 16V fu Q509 ~~M 017 -B:iID, ¥IJ)§[ffiB~~t!IXim the R terminal of 43 IL is also when the voltage of 2 pin is r than 2 pin,and outputs R,then the triode is electric current Scanned by CamScanner

OCP Scanned by CamScanner

JIj JEW-N. Q22 ~jI]HI\\)KIY~Ill.J.f,t:fiU 1.88V nt. -Urt1* Q21 \\j-M, FL1~ SRSET 'hil. .tJ:ft:~, J~' -~~jJJl1J: U2 (I~ OCP :j;J.tATIl!,J#L )2Jt;JJ OCP_OC#o In the figure 13-15,whcn the voltage of LIMIT_SIGNAL becomes higher(not original adapter) r the voltage of VBIAS reduces a ccrtain extent,when the voltage from Q22 conducted is higher 1.88V,one path makes Q21 conducted,pulls the SRSET voltage low,stops charging,and another -_._ __reaches to OCP execution circuit of U2.starts OCP_OC#. •....... _-~. 31 17 • 2 1 C51S 1 CS18 RS84 0_5% 22 • n circuit of OCP_OC# in the adapter mode tt!ffi. r*iilE~ 7V J.r.;;(:J 0 VBIAS ~~iNG~ltffi [email protected] 5.79V, ~[]OO 13-16 JiJT7J'o o J!ge of the adapter,the manufacturer set it to be m the adapter after through the resistance Scanned by CamScanner

+VADP 1 R106 2 =\"1'l1oClN_U1313DR2G_SOP_8 a Scanned by CamScanner

o.1UF_ olfJ 1~25V1 I § (l) -..= ~ D515 I CHEHIIKD_B 0.- OR' .. I~I 13-17 ~ U..T..P. 1•2• BATURVI n S olfJ § ~

oul'.>ll-----+ dB ~ON_~_SOfl FJ l!- , ~~ 2 tS 1041(_'% II ~ ~ ~ •-~m ~ OCP +VBDC _25V 10UF_25V lli<&15.!1C516 R564 IR1KU_1e% Wn..- ..!L -1 C 0_5% 2 210l 21 2\" C30 ~ 10UF_25V BAT54_3P I V' MJ__ J~n I :''c ~\\YJ0 OCI' rl!.I,'ii /ff,1

~I ofBig OR GATE circuit f\" *Jt~!.~n& 0\" I!IIM113l-1(81t1-11-:+tVr13-SA:Jxt~:·/tft'~n:~i%I,D.uI:Un!oJTi5H4J~(]lJJ:~j.\\l:S0-SERIES . *t!I l\"ii*tf~i 7ttIT n\" design of \"Big OR GATE' circuit (called by the author) in many Inventec section as S-SERIES(HP_6531 s) an example to explain the \"Big OR GATE\" 3-18 +V3S is not pull-up called usually. -ZllREF 1 R1Z7 2 >Y3S 1011K..n. • IlI3 • ofthe Big OR GATE\" circuit VSS iI~ R130 ~ RBI j!t§H.£-~, .J3}jij1Ji [email protected]\"I:fHW?tlliJt~, lJJ~m II+h=h Sg0 Law) Scanned by CamScanner

t +V3S can not be less than 2.727V.1he result is shown in figure 13-20. VI J.J V 1I4nlIitlJ VI 2.727 --, V2 5 V V2 5 I HI 68.1 II V~l --R=J=:JI=! -~ '3'1= V R2 102 II RJ 49.9 II - -~ V IYJ 2.189 \\·2;r; HI 6&.1 II - R2 102 II R3 49.9 Q V3 2 V U -------_. computational process of the node voltage putational process ofthe threshold value voltage of -V3S VSS ::f\"~{~T 4.141V, tmOO 13-21 pJr~o culate that +V5S can not be less than 4.141 V.is shown in figure 13- 3S ~ VSS l¥Jf'l!lliftB~, *00 13-22 rp VCCP]G ~Ia rfl~73£ {~ (;It1mfg -'% I5l 1:1 )• oltage value of V3S and V5S.in the figure 13-__.if and Rl29 series.the value of resistance becom s 1 RlI7 2 10K 5% Scanned by CamScanner

'lll\\lIl'It,11t1 \\ ullll' 11',u l,11I1I111 Ill' 11I~\"'1'1 111.111 ) I{I I Ill!' 11 111 \"'III,' 11 '1.(111 lit, 11'111\" IiiI' \\ dill' III I\"\" 1.1111 l' • ),/11 Itlo11011 •• ,VI I I V V III VJ II If' II III 11111110 II III 10JIIII0 V \"' n1111 VI 11,11/\" ullnllhl' IItllle \\ (llllll'e 11'11 'II VCt' \"( i is lUll level Scanned by CamScanner

14 ~ Intel P[H H~~ ( 13/15/17) B~fi -+(Platfonn Controller Hub) fJr ~ J:i:'4i'J 'f ..:; 0 Intel PCH ~ -1'- Intel /... 6) 6ry -*~ft-~ • --fJ{. PCH Dry f-\"oo J:J Intel 5 ff. JIJ, -110 Intel HM55 if, ~t~e.--f-\\ 13/15/17 CPU; ¥-=.., JIll;,:] Intel 6, 7 ff. JIJ, ~t~e...=., -=--f-\\ 13/15/17 CPU, i.!.r13'J-f-\\JLf-.ff, CPU iill..m 0 JiU~ *--Pi. e..tf:.t. A'fJ, J:J Intel 8 ff. JIJ 0 PCH $ J4 -A~ ~ :;ijUCH 6!; ~.g.~;:JJ fit. 5lA~ ~ MCH .yJ£~I~;:}]fjL 4e. PCH ~jg~IAff-t1:.M, oftJ:Jm{ff-t1:.M, :1I~:lC.PJTi)1Jo ,*-\"*..=t*1l'~g e...If.1lJ,fo 6, 7 ff. J'J at jf. ..=t~~1' 14 ofIntel PCH sequence(I3/15/17) , the platfonn controller hub.lntel PCH is the single bridge chipset in the Intel uct of the first generation PCH is Intel 5 series,such as Intel HM55 and so generation 13/15/17 CPU;the second generation and the third generation is Intel 6 the second generation and the third generation 13/15/17 CPU,these two of same,CPU is in common used.The newest fourth generation has been chip has all functions of the original ICH,also has the function of 'ginal MCH.It dose not matter to call PCH the North bridge or the . Iy introduce the main feature of Intel 5 series,6 series and 7 tel ME fIl Intel AMT and Intel AMT 5'_, ~ij!dtf-AtE~tm~PCH 1*1 8g~9!iL ~~-l';t,Jtr:p, f.!M1t§J~.:lL Intel dware inset the North bridge or t in the same chip,but they wn in figure 14-1. Scanned by CamScanner

00 14-) Intel ME,fJ] ME ~('f~~1;}lfI the architecture figure oflntel ME and ME firmware 7-~f$~ \"iAMT\" D~<gJ~IHJ(*o Intel AMT (Intel Active \"J!~*) ~mt.t~-;rIJW:JJX;{£;t;Jt~.Il':jJ(1~*Ai(*~Jc. ~~fj~ilJlaXi'j:~jCD{JI!'IEJ0 technology called \"iAMT\" in ICH7.lntei AMT(lntel bedded system integrated in the chipset in effect.it does ir!>it is the biggest difference between iAMT and the *as ~Jt J:/=l , ;Jtr}]fiE EI3 ME ~m 0 i~pjM5~>it iJJ , :¥cmAH\\@1~, ep1~tE-1 :9EtJL, lcfJLgX; , l!A BIOS j1HTj;,H/:ili~~{£itr 0 ~tes in the BIOS chip.the function is e status of the hardware. it can start in the system with crash,power 8lso can enter into BIOS to Scanned by CamScanner

&M~I-~~mITW~A~~~B: mp~m~~~£~~B~m7~apCk~~i~ ~~a#~~~~m~W~.~®~A, ~~~mpw~, ~~.~~fi~~*. Intel AMT technology can appear as a subsystem been independent of existing operating system,because of the environment independent of the operating system.when the operating sYStem is broke down,the administrator can remote monitoring and manage client-side.By this technology,the computer been controlled also can remote manage and detect system when the operating system is damaged or the system is broke down.or when the system goes \\\"/Tong,it can send the warning message ,to detect the software and hardware,remote update BIOS and virus code and the operating system,even when the system is power off, it can also manage work by the website then it has worked out the problem troubled IT manager:users closed the safety and management software on the PC deliberately or by accident,which leads to unacceptable anagement.These features can significantly reduce the administrative cost for the company user. ~*' AMT ag*mff S5 {*OlVI7C~61, ME m~, B1~p~Jt, Intel PHY LAN, SPI MEMORY (CHANNELO DlMMO) ~tm~1feg. system supported AMT is in the S5 sleeping state,ME module,the clock chip.lnlel lOS MEMORY (CHANNELO DIMMO) need to be powered on. lCH8M lftlf:l, ACPI 1f1{*D~JZ~]j:~*Uf*-%~:iJDl-1- SLP_M#. SLP_Mil 4-2 JiJT7F. ICH8M.in the ACPl.donnant logical control signal is added a oshot ofSLP_M# is shown in figure 14-2. ......._b111ty SI. .p Stllte Control: 5LP_M# Is for power plane contral. If no Management Engine firmware Is present, 5LP_M# will the same timings as 5LP_53#. the power of Inter AMT subsystem. When the ME 'Siconsistent with SLP_S3# (while generating S4_STATE#. the pin Scanned by CamScanner

Type Description :uSleep Control: 5LP_54# Is for power plane control. This signal 01skts) power to all non-critical systems when In the 54 (Suspend to or 55 (Soft Off) state. NOTE: This pin must be used to control the DRAM power In order to o use the ICHB's DRAM power-cycling feature. Refer to Chapter 5.13.10.2 for details NOTE: In a system with Intel AMT support, this signal should be used to control the DRAM power. In Ml state (where the host platform Is In 53-55 states and the manageability sub-system Is running) the signal is forced high along with 5LP_M# In order to properly maintain power to the DIMM used for manageability sUb-system. 14-3 the pin definition screenshot of SLP_S4# ~~tJc~T 84, 85 f*n~~~, fflTt£fM;l{PJTj:Qf~~89~ffiB97f*o ~ft\", fflTj:Q~~~~ffiOO7f*o~Ml~~(~~~~~T iilt\"), 8LP_84#~ 8LP_M#~!iH~~tLit, fflT}f-~rr AMT tk:65r : when the system is in the state of 84.85 sleeping.is used to control iIl~ by itself. ~ the AMT function-is used to control the switch of the ~when the main platfonn is in the state of 83 -85 and the is forced to be pulled up by 8LP_M#,is used to open the ofAMT. m18111:fm 14-4 JiJT7F 0 ofICH8,ICH9 is shown in figure 14-4. T S4 ~:tt 85 )jj\\:65 0 ~ ~&d:T S3 ~~z. HU 0 means that the main be used to Scanned by CamScanner

~ 14 ~ Intel PCH Dg~ ( 13/15/17) fltrr MEPWROK Management Engine Power OK: When asserted, this signal Indicates that power to the ME subsystem Is stable. [] 1-l-5 MEPWROK CJIIl!lJJEx.ri.\\!OO Figure 14-5 the pin definition screcnshot of MEPWROK ME~.M: ~~ffi~~~M .~ME.~~~B~.~. xplanation] ME Power Good:when this signal is effective,it means that ME module POwer has been stable. T Ji1fj~~liijlJ..t. ft[ljjWlH~~IM1§~B1ff*~tLDI!I 14-6 JiJT~. ffi!E~z..j§. SLP_55#:it J6J1! SLP_S4#fO S4_STATE#.il~, f&j§~ SLP_S3#.m'.r'SJ, SLP_M#~D SLP_53#1!t AMT function is closed.the sequential relationship of each sleeping control signal 14-6.After triggering.SLP_S5# is set up to be high first.then SLP_S4# and to be high,SLP_S3# is set up to be high at last.the timing sequence of e. SLP_MMJHum.;<Ji, SLP_54= , :pJ.\"~ S4_STATE#f-\\ffi Scanned by CamScanner

I 1I I _ I I ~~I I I 1/1 I 11297 1 1 -----r:---------t--\"i~ : : : :~I)1 I I I I 1 1l9~~(&\\} I I I hen AMT function is opened.the timing sequence of each sleeping control signal , ~IIiD~~iMf§-'%~~Il:m* 14-( 0 ·on is opened,the logic of each sleeping control signal is shown in the table is opened,the logic table of each sleeping control signal S3 S4 S5 ooo o oo ~p;j, SLP_S4#fflTt£f~U r\"'J 1J Itlli(i~ (!?cOO, 1 PHY LAN, SPI BIOS ~ltlli01{*m 0 IT state of S5 sleeping.SLP_S4# is used to used to control the clock chip,part of C- voltage.We can open or shield AMT S4_STATE#.When the to be supplied -303- Scanned by CamScanner

m1~ ~ Intel P[H IM~ ( 13/15/17) B~fi 1 ~ j~fJlll1., :' ~;~;Yljfl\\ 6 ~~u.c::J4·mjfj1;t1}JI] T SLP_LAN#. i51!J};IJ5ExJfJOO 14-8 fifr7.r-o Th • scrie. chip et till retain. LP_M#.the 6 series chipset renamed it to be SLP_A#,but it t 'ontrol the power upply of ME module.The 5 series and 6 series chipset also add #.thc pin definition is shown in figure 14-8. LP_LAN# / LAN Sub-System Sleep control: When SLP_LAN# is deassert:d it GPI029 indicates that the PHY device must be powered. When SLP_LAN\". IS asserted, power can be shut off to the PHY device: SLP_LAN # will always be deasserted in 50 and anytime SLP_A# IS deasserted. a AuSSinLgP_SLLAPN_L#A/GN;P;!IOfunScetlieocnta5li0tyft-tSo trreavpecrat ntobGe PuIs0e2d9foursasgyes.teWmhseNnOsToft~ strap Is 0 (default), pin function will be SLP_LAN#. When soft-strap IS set to 1, the pin returns to its regular GPIO mode. The pin behavior is summarized in Section 5.13.10.5. Figure 1'+-8 th.: pin definition sere nshot of SLP_LAN# tionl LAN subsystem sleeping control,when SLP_LAN# is ineffective,the power of ;:.~~'C8lrd must to be retained:when SLP_LAN# is effective,the power supply of the network LP_LAN# is in the state of SO and SLP_M#/SLP_A# is ineffective it keeps to detection signal and SUS_PWR_DN_ACK signal.is shown in Scanned by CamScanner

pJ origin is altemating current or the system battery.The high level refers supply. . JAMEf11i*~t6 EC DtJ(*\\~. 1~1:Q..:qz.~{;;f>'t-fim~:I1j~Fl:!.~Jjjf. 'the signal sent from ME module to EC.the high level means that it does sis of Intel HM55 series chipset tinling sequence 1lJll¥l14-1O JiJT7j;, 1!Ii:j:I1*~fO~~~D~. tel 5 series chipset is shown in figure 14-IO,rhe explanation of the Scanned by CamScanner

m14 ~ Intel PCH 1Mf' (13/15/17) fltfi aou.a Destination SIgnal w..\",. -------------------- ( ~) (f;1 '.H,H;j ( f:ll·j;} I!oI<\\l VCCRTC PCH 8oar:l ~RTCRSTti =_ PCH --80'\" PCH S3Q2T7C6RSSkTh'2 ---{L _0 V5REf.SUS PCH VCCSUS3_3 - - - - ' POl PCH RSMRST. -'1 80'\" BOll'll SUSClK PCH (= PCH PCH -PVIRBT'l' PCH ----u- ' . - 1 - - - - - - - - - - - - - - - PCH Boar.! Boa'll _d!loIu<: I_ _ _ _ _ _.L-_ _...J\" C(lUU O\"M I.Q I't \",,1111 bBliJe SLP_~ 0' ala. ~SLP.S3a' bwl f'lOWa' - _ _ _ _..L./~_ ____'7 Vee ME ------_/ \\ICC - - - - - - - - - - - / ----------~! ~.~m..,~l.Q ...- t l r PV.~ bA N) IOte< \\..AN_RST8 ~y~lloerterlJ'¥lOIl' .... Mr!'IeI\",...AP\" 'tOIl: 0 I r-aybl:.:atI:llllt~b'parcm\".sI'lClW\"'9I~l. LA\" Scanned by CamScanner

: m*:it1(I(J 32.768kllz ,\\1',11&, ~Jj:~ft~~·J)R1)~111, iIlWrHJl;1)1:iJ;~i:f~(1~Jj: :32.768kHz cry tal next to the bridge.the bridge supplies the power to the crystal supplies the frequency to the bridge. 3_3: '±~~MJf(l~q'j:~n1~~I@\" 3.3V 0 :3_: 3:'th±e~m~foHthMeIr~bo3ar.3dVsuip'Jpjl1ti!e,s-'ltZh(Je~ power tUo1tfhLe{bJ§r%idg, e.;3I;.i3:}Vi!J.,ff::jillj;n~ft, l1:tM~~j-VL43)..f ACPI :the motherboard sent the ACPl reset signal with 3.3V high level to the bridge,it the bridge that the standby voltage has been n0n11al at this time. : tff:&:tI:1fB 32.768kHz B1~rD !m* EC i*JB'~ld}f~O~, -rj~ SUSCLK *'*~~ bridge sends 32.768kHz clock. If EC is built-in crystal.SUSCLK is usually sent to k. .tror~7gM!l!:&:1J§ %, 3.3V-OV-3.3 V, jmf;r.I~~'fjJr 12)j~ tI:1 ft!lf~[HIC~ 0 • e receives the falling edge trigger signal,3.3V-OV-3.3V,to infon11 the I \\State. m#~, .RiWi SLP_S5#JJX: 3.3V, */J\\~tI:1:J.i:~n;jjC~0 receiving PWRBTN#,set up SLP_S5# high to be 3.3V,it means that it 3.3V, ~/J\\iJ!tI:11*O~;jjC~ 0 S4# high to be 3.3V,it means that it exits the sleep state. 9.3V, ~7J'jJ!tI:1*m~~, illA SO 7ft:J1;jjC~o 83# high to be 3.3V,it means that it exits the standby state and Scanned by CamScanner

~ 111 ~ Intel P[H 1M~ ( 13/15/17) fltfi SLP_LAN#:L subsystem sleep control,controls the power supply of the network card.lfthe motherboard not use Intel integrated network card.this signal is not to be used. If the motherboard uses Intel integrated network card.and supports network awaken,then this signal is high in the standby;when it not supports the network awaken.this signal follows SLP_M# or SLP_S3#. VCCME: ME t~~Bj{ftE\\:J. (ep~J.9i.\\ AMT rJJ~~B%JtEt!.), ~~T SLP_M#. SLP_M#~~ 1M\" (:£t&X ME IflIftf), VCCME ][}1C*ffl SO ~~B~{t~r:@, ~ttlD,~,~~~\"I:!.jfD VCC3_3. VCCME:the power supply(power supply to achieve AMT function) of ME module.is controlled by SLP_M#.When SLP_M# is hung up(there haven't ME module on the motherboard).VCCME uses the power supply of SO state directly.such as the bus power supply and VCC33. VDIMM: tlfi~fHj.tE£!, ~~T SLP_S4#. VDIMM:refers to the memory power supply,is controlled by SLP_S4#. VCC: tlim~Jt~,~,~{ftEg~SO ;j)C~B~r:gEL ~f!lT SLP_S3#. :€C:refers to the voltage in the SO state of the bridge power supply and the bus power trolled by SLP_S3#. ±~~ CPU 1¥J~,c.,{ftJt, ~;lf:~f!lT SLP_S3#, 1fJjfB1. therboard sends the core power supply to CPU,is also controlled by 99JtiJj'ifJl~Jt~~miJ~ 3.3V ~Jt.If, ~IEUT VRMPWRGD. 'gh level to the bridge by CPU power management chip.is equal to Egolf, ~~ SO ;j)C~Jtlli:tfl).IE~ (#HIJ,~.~{~It). ¥ high level to the bridge, it means that the voltage of SO ~ply). rnME I~H1j:Bt, MEPWROK ME f~JR~Et\\N -~. there have ME firmware,MEPWROK is haven't ME firmware,MEPWROK erboard sent the reset wer good signal is forced to Scanned by CamScanner

bridge sent PO to CPU,it means that the memory module power supply of outputs,it should be extemal pulled up. ettML€i!itL 3.3V, ~i1~19c (-n9:~*~5tED itJ19 CPU !lift. ~:m reset 3.3V sent by the bridge.as CpU reset by conversing(is usually chipset timing sequence above Intel HM65 series Scanned by CamScanner

1M\" (;g 1~ ~ Intel pm 13/15/17) fltfi • . ...pc\" ..... PC• Ole SA1CIt!U ~'} 7& k • _...• PC\" \" cOM',J _.~CH PC\" OI'WROK SLP~ 5JS. ..... 1:lI.rd \\~IS:l_3 ASMR:;t. \"C _ PCri PCH 80\"\\1 ,. . lUI PO< SUSClK -- -- - - -.. r'.·.·RB1U. - -- - -.. SLP_S5' - -.. SJ'_SOO SY)i.\\f --...... SJ'_'\" 9.P_LNU PO< ws.' \\/D\"\" vee PYIIDC _ -, - - - - - - \"\"\",.-,_.,-..,..\"4_ I .- ......... RTC Et!~Et!, i?lf¥1¥ CMOS ~!!&, otherboard,supplies the power to RTC of Scanned by CamScanner

US3 3 Ji \"JUl, otherboard provides the deep sleep wcll power sllpply to the pports the deep slecp,lhis voltage connccts with VCC US3 3. ~1¥'.I3\"3V \"':JI~ 'I~, C{/j·· V CDSW3 3 (I{JIl!.1IJtH, 3.3Vo /Gjd#1;f-JJ1 T#ii ·JW. rboard sent 3.3V high level to the bridge.refers to the VCCD5W3_3 not supports the deep leep,this signal connects with RSMR5T#. 1I&~~m/J':'1,·i\\.1, IiJJ1J-f-Jr-Jri S5 ~R.UI~4:!.[Ii, bt:tzO VCCSUS3_3o SUs#g\"~o state indicator signal.it can be used to open the voltage of 55 state,such ot supports the deep slcep,SLP_SUS# is hung up. ~m(f.j~1=fJl{jl.lg, 3.3V. erboard sent the standby power supply to the bridge,3.3y' fro 3.3V r rt!5{l-(I~ ACPI UffL1~ S-, klJ!HJ!jw9:n.ffl: , Jltr\"H~A:Jl,rtU± t ACPI reset signal of 3.3V high level of the bridge,to inform ynow. fJjj.;JI, ffi1'-J'EfHl.±:f&*rn. olock,but it not necessarily be adopted by the motherboard. ~, 3.3V-OV-3.3V , jffi~n.fJr-pJ iJ,llil±\\ rnIW~;[j(~. ing edge trigger signal,3.3V-OV-3.3V,informed the LP_S5#JiX. 3.3V, ~7Fi!!t±'I~~JL;[j(~. #,set up SLP_S5# to be 3.3V,it means that it exits eans that it exits the sleep state. ~~, i£.l\\ SO 7f.tJ1Af\\~. eans that it exits the standby state.and Scanned by CamScanner

!m*3:.ffUC 1E~ft. if1Z:t#A n. LP .Lh'1,fJIJ Ifthere haven't 1E finnwarc.i not support 1\\1T. LP # hung not u. es. LP_LA \": LA -=t3f-tJtf*nltti::f!JIJ. t<t~jIJf(~{:fJ~ll!.o lllltr-. l ~Ri\\! (Jf*)1J Inl I rl(JfllJ~I(~ Jltnl'%/F*ffl. W1.~ltt~f~Jfl Intel 801tJJJGi«J-.F· 1-1,H\"Jf~119~nJII(10ir~. JILf,~~JfHnll'Jltt . /F1:~~~~~lJ1. Jltl*-I5-N~Pill SLP_A#:!3j( LP_S3# 0 SLP_LAN#:LA subsystem sleep control.control the n Iwor\" card power . uppl) .If the rboard not uses Intel integrated network card.this signal i' not adopted.Ifthe motherboard liS integrated network card.and upports the neh\\ork awaken. this • ignal i high when it is in ;when it not supports the network awaken.thi signal follows LP_A# or SLP_ 3#. 1t**fflVCCASW: ±:~1M;9ltEt=!.~B%!teg..<:1.1£-'f SLP_A#. SLP_A#;{,,~\"LIIJ U:.tJ{ 7C M 1,',1 VCCASW so ;jft;eB~{J:tIt. VCCASW:the power supply of the active sleep circuit.i controlled by LP_A#. When LP_A# up(there haven't ME finnware on the motherboard).VCCASW adopls the power suppl) or directly. IMM: m~ff1ftlt! ~:j1T SLP_S4#. :refers to the memory power supply.is controlled by SLP_S4#. flCJ3:.~It~ SO :If(;eB~ltlL ~~-'f SLP_53#. voltage of SO state or the main power supply or olhers or the bridge.i *jf-8V ~Et!3f. SO :~~F[1.&'Mlnti~H T ,jff*Il,~.g~1jlrh. 3.3V high level to the bridge. it means that the voltage of SO power supply. AMT JJJfmat, APWROK d3 AMT Jtrr1£;~JJ, *I~ AMT function.APWROK is controlled by AMT consistent with PWROK. u, ~ffm*f:Jj;~(lE~H]\". CPU that memory module power supply is Scanned by CamScanner

U_SVlD is a group of signal sent to CPU power supply chip by cPUjt consists bus consisted of DATA and CLK and ALERT# signal with the function of ntrol CPU core voltage and The integrated graphics power supply. D 1:f~j§, CPU:&t±J SVIDo GO being effective.CPU sent SVlD. lJ: CPU 1't-J~1L.\\f#Eto *7FU:the core voltage of CPU. CPU t*1L.,{jlr:t!(1t~H7 0 IE CPU I't-Jf#Et;t:Jt1H.g-ffi:D~ 3.3V ~Etf. U power supply chip sent 3.3V high level to the bridge.it means that CPU core l:I:HJ'.JSP:€l~1iL 3.3V. ~:ct~¥jdFJg CPU 1flf:fLo dge sent the platfonn reset 3.3V,as CPU reset by conversing. ?\"tlI¥JIJ'JFf, ~ Intel 6 *J~B~DtFf~*-f~o :it]FF.j3}~:~~J1iJj£o of Intel 7 series and 8 series is almost consistent with Intel 6 series. We Scanned by CamScanner

1s~~fiDj K42--1R (HMSX) H~~fl~fi .5Ji K42JR ,'Vr... Jfl Intel S !f; 7']Z j; iJl6~~1L~o $.1:4+71 ~Jf$iti5c.~~*A Ta~1HJL;fDJ:. RTC ~ 3~ ffil 59 &. $.~II .! :;r- ~, $.1:I!J.&-ii :;r-i}f 0 15 is ofASUS K42JR(HM5x) timing sequence US K42JR uses Intel S series chipseLWe will analyze the standby and the power-on timing ce under the adapter mode,because RTC circuit is almost the same,so we don t explain in this 15.1 The standby state !:I:i AID_DOCK_IN, ~o 00 IS-) JiJfjf-; 0 _DOCK_IN,is shown in figure IS-I. ,-------------, : eumnt settlng::6A , Depend on \\he current : of . COO03 C60!)4 I UFJ25V O.lUF~V GND Scanned by CamScanner

CHO vce CHG t-ATH lliJ'V PCOO02 o lUF125 .0.002 ,f'VVX '----<:.......JCHG vee GATE the production ofCIIG_VCC Et!.~Jt MB39AI32 O~ ACOK JJ!p, ~nOO 15-3 fffiFo ACOK TH_19 t~u PR8904 frJ PR8906 7tffi1.{j-iU 6V lr:;(:jB~A;E1x~-1e;; :ACOK pin of the charging chip MB39A 132,is shown in ~el then it will make CHG- PATH- 19 through PR8904 evelof6Y. Scanned by CamScanner

~ 15 ~ ~fijj Kl12JA (HM5x) D'.l~fl.fr pR8903 PR8IlO6 ~ 22 lIS ,;, <a: ~ 0 '\"<> CHG_VCC Q. lUFI2 'f bCNl~mU~50)'(-'m>~SoclZc(3n~ VlN • CTl1 GND! VREF AT CS AOJ3 BAn to output the low . to say,AC!N Scanned by CamScanner

CIN and ACOK is described a shown in figure 1'l-6.lhat is to say,if ACOK will output the low level. 1II11ot!5 VlU' 1.237 1250 1.263 V V\". 1.227 1.240 1.253 V 1_II\"1'meJ1iIl.l¥! V\" mV 10 200 nA ACOK glJIIlflili I'INC! 5 ACOK gllll- 25 V 0 I'\" MJl!if. I..... 5 ACOK glJII- 1 rnA 0.9 1.1 V ACQKollJIIlllll1 VACOI(L 'l\"1\\l'l'1\\l1li 00 15-5 MB39A 132 l'J~l~mf)llt9-J;<·j AC jli!!iC.6~+&iY!tltJ~ rt!'=(tJt1tillifr,£ r~ features ofAC adapter detection in the data manual of 4) \"5tl'l' 1.24 V( A'l!). Jl'~ AC llIEDoIIffitl1l!MnYJ Jllle \".24) \"\"UJiI'J-HlJlI&. ~\".Ml. Scanned by CamScanner

ff-fid! Kl12JA (HM5x) U~I~fl ij th t th'l' 1\\\\ 'r uppl) ol\"thl: chip is IN. C1lQ \\'CC I ~M.;' V1\\(f CHGO~DCEllS PRUl . . J '(l(lI(Qm At (lA SVS C G vee .IINNCCI..--+--+--~ vee 1.--' I ! , ACIN -lr=i;;;~\"~C~OB'iCCII ~INN.~' ''0D~~ ~AC~L~: COMP'p ('I ~ • to AOJl •. , 'l-ao\"; ~ ePuRx8C9'lerm I 'U7_1- r<:ell 2 CHGPMB3~A'32 V o.ur v' I OUTC' '0 III 0..- ~ GND 8 PCHGCI .. l'bl -----'$' -=-l:c uff HG c to CIIII GNO Co. !.l ~~ Figure 15-7 the screen hot of AClN circuit CHG_VCC r~i1 PR8911 {II PR8915 it ffiJ§ B~*, ~J1it~, ACOK ~ ~~U tl:l1111t!.f 0 e CHG_VCC to through the PR8911 and PR8915 partial e ofCHG_VCC is not less than 17.4V.ACOK will output TE irlliJ£1L. PQ8902 ~im, rn:~*et!~mB~ Eli AC_BAT_SYS. ~IJ 00 15-8 J5ffJF c 1EJil't [email protected] 0 VCC_GATE partial pressure to be t CHG_PATH_19V.through PR8903 to wn in figure IS-8.At the same cut off,the battery is isolated. =----_----<: AC_\"T.S'S Scanned by CamScanner

hown in P ·3VSU9 ~ EN to i 1'IClOI'2UllF~ 00 15-9 RT8205 f~~tl VfN 'fn EN Figure 15·9 RT8205 gel VI and E i:iil~J!~7g+3VA. tuJOO 15-10 fifr?F, +3VA.i shown in figure 15- .......- - - - - - o . : N A ImOO 15-11 Scanned by CamScanner

1,1 if-Hi KL'1 JR (11M x) n~Jllfl fi I'*! 15 L 13V IJ.!. ¥,J:J-I VA Fe Figure 15-12 +3VJ\\n:numcdt be+3VA I· VA_EC {ij.f7.ii JP300\" II!: :gJ9_3V ,~III~ 15-13 JiJTIi' 0 VA_EC through JP3003 to r named t b \"'VA C.i h wn in ligur 15-13. ~VPLL ~ Cl30OO06F~ ~VACC GNO 00 15-13 +3V _EC :9!¥,T:J+3VA C +3VA_EC renamed to be +3VACC 1) a9 74 Ill~JtJ!1~t~HJt rt1ffi.. \"!,to 1*1 15-14 JiJT;F 0 voltage to 74 pin ofEQU300 I).is shown in figure 15-14. GPAO GPA1 PWM2IOPA2 PWtoI3IGPA3 ~1IJ 00 15-15 fiJTiF 0 I oscillation send back the Scanned by CamScanner

-E=C=--\"\"'--1 GPFO G PF1 PS2CLK1/GPF2 PS2DAT1/GPF3 Note: ---\"><'-1 PS2CLK2IWUI20/GPF4 Cl_12.SPF --\"\"\"'-I PS2DAT2IWUI21/GPF5 pi_dose 10 EC sen: F.:C XOUT _-l...Ll.L SMCLKO/GPB3 cOJ _....LL.JL- SMDATO/GPB4 '\" _--'-'-\"L.. SMCLK1/GPC1 _...J...LI,'--I SMDAT1/GPC2 _J-U-I WUI221GPF6 _...J...LI,'--I WUI23/GPF7 1T8500E-L the standby clock of EC ~~EC U!ifl'Lf§-5, ~D~ 15-16 J'i)l/j,o lJ;t1§-'%~ \"~fjIf{Jta1. ~tL1~ EC O{J}l{l'L3kfjl;t,lfJT i:l3 ° circuit to supply the reset signal to EC,is shown in ,when it is lack of the voltage or the temperature ~e. Scanned by CamScanner

dby voltage,controls PQ81 05B conducted,pulls 2 pin of PQ8 J05A 100v.then PQ8105A keeps to cut off,ENBL signal is not grounded and into the hung state.is shown in figure 15-17(@ means the component is not installed). VSUS ON BA154CW PR8118 @ PD8I04 1KOIwn o ENBL PR8121l Pll8IOSA IllOKOIwn UIl6KIN PR8121 lllOhm 00 15-17 ENBL f\"1::rt\\~ft igure 15-17 the production circuit ofENBL ~.l1:o *mlt!.¥Jl\"g~~Jt RT8205 sj ENTRIPI, ENTRIP21l!!J , ~WiJm PWM Bj:ctlm.I~{i, I5Jntf1=JgJl'J3~ PWM S~frJa1g PWM 1fft3 ffi %.IE JIt J§, ~\"tr I±l Jl'J3 fi!~ PWM: +3VSUS, 1be cut off.The standby power manages EN TRIP I pin and 8102 and R8103 grounded to set respectively the over as the open signal of two path of PWM at the same signal of RT8205 being nonnal then outputs MO :standby voltage pin of the bridge. Scanned by CamScanner

P-s NN...JLL __ -t----'-=='f-\"4-()=--~ VQ2 ffi... ffic!!roll!~lJJ~ll!!c!ro GN02 ~1p!dtj M~C-ri-;=iii-if;~-~\"=..-.'..\"..-\"...-Lyl~ VREQ3 vo, !lOOn PGOOO UGATE2 BOOT' PHASE2 UGATE. LGATE2 PHASE' (r-SOOkBZI PU8tOlA m !.GATE. ATB2(PSCGQW mV) ilI.i.lil. i0-i~~Cw~ll uIu.l lbe production circuil of the open signal of RT8205 Sll1S_LG_20 OI~E1T 5VSUS E§.~8~~~ G 1'&, jg OV-5V ~ 12VSUS Jt!.ffi. ~ 00 15-19 r}T5F 0 d -.:*SVSUS...\"LG_20( comes from the down tube G pole of U!Ue wave) through twice bootstrap to produce +12VSUS P U3Zl Scanned by CamScanner

rement,only have the instantaneous waveform.not the continuous waveform. 1£~~JE BIOS )5, ~+:@:~YW~re~, Af<1~~11f¥I 15-21 J5fT/F: ~[!jc~ Eg)Jij-T 14.37V ~ PR893 I ;rn PR8932 ?-}ffFi~~t1~ PQ8907 %:iiJl, ti1~ AC_1N_OC#, :i!rt5\" EC f1=T:J~ .Ul5o WJ* EC fjbJU~Ij~Ij~re7,§.1illA (AC_IN_OC#:7~1~) , ~~~~ftl~ VSUS_ON n~ <moo 15-22) ; ~IJ~~ EC *:@:~Y1PF~Ij:@re~, ~~~:f.f~tL1~ VSUS_ON, ~~l S +5VSUS, ~*$, BIOS m;I~&ff7Itffo 00 15-23 pfT7J'Jg VSUS_ON *~E1i0.iit 50ms kE~iJUJIJ~Ij:@i'!C.@, VSUS_ON ~tL1~B~~ff~OOo EC reading BIOS,it will detect the adapter the specific is shown in figure 15-21 :after the of adapter being higher than 14.37V,through PR893 I and PR8932 partial pressure to make f7 conducted,pull AC_IN_OC# low,to send to EC as the adapter detection signal.If EC can the adapter inserted(AC_IN_OC# is low),it will keep the high level ofVSUS_ON(shown in <5-22);if EC doesn't detect the adapter,it will pull VSUS_ON low,and close +3VSUS and tben,BIOS will be out of voltage.ln the figure 15-23,after VS US_ON being set up Jy: it does not identify the adapter in 750ms,VSUS_ON is pulled low. • 10.C2IIQ2 1UFII6V Scanned by CamScanner

PR8931 33OKOHM 1% POI!907 • PMllSJ904 2 PR8932 PC8923 16.llKOhm Q.1UFI25V cOOI2 Figure 15-21 the prOduction circuit oflhe adapter detection signal ..Tck .J'L • ACQ COmpiele M Pos: 740.Dms SAVE_REt ,J iM'F 1. . >: [ 011 I.OOV M250m, J!~ ~'M§~~A:\\ :Zjt-~ Miff T[J(0004.JPO CHl .r 1.44V 11115-23 .M~i9nlj~~~~lIt V US_ON V.!U~OO detecting the adapter not detect the adapter WRGD ffi \"% , ~n I!I 15-24 f!IT7F 0 1 after the standby voltage being stablc,is Scanned by CamScanner

Figure 15-24 the circuit screcnsho( thaI RT8205 outputs PG SUS]WRGD B3 PR8601 J:fi79i¥ri[~.If, lFdiiEiIJ7 EC, iiHQ EC Jltn;H'!ffll'tJI.iE 1m1ll 15-25 fiJTlF 0 SUS]WRGD is pulled up to be high level by PR8602.and sent to EC at lastto inform Ec that dby voltage is nonnal,is shown in figure 15-25. PR8601 l00KOhm GPIO VelA AlBITI BPI. GP12 SUS_PWRGD GPl3 _PI4 AIlCI5IW\\JI2aIOPI5 1I-'ii==i~ECPG1P176 t==::b AADDCC7I1IWWUUlm31'1GGPPI1&7 the circuit screenshot that EC received SUS]WRGD T#~ PCH, im%1A**IlEE!.lliB~ff.Jt~o PCH 1~m*1tj:iE 1t!..3f ME_SusPwrDnAck ffi ~, 1st It ECo EC :& ill j!~ PCH lItBtx¥jft@~~jffiA, ~D 00 15-26 ffT1F. MRST# to PCH,infonns that its standby voltage has aI,ME module in PCH internal outputs the high level ds ME_ACPRESENT]CH signal to PCH,infonns in figure 15-26. PCH Scanned by CamScanner

~15.2 Trigger ~7fmfe!ll;&f§~ PWR_SW#¥ EC 125 }jl.jJ, ~nOO 15-27 f:ff7J'o keyprodueing the boot trigger signal PWR_SW# to 125 pin of EC.is ~------<::-lPWR_SW'(53) ~-----C=LD_SW' ('S,53) EC received PWR_ W# pWRBTN#. PCH :fjt1±J SLP_S5#, SLP_S4# iLP_S4#, SLP_S3#7tJJIJ~i;:7g PM_SUSC#, of PCH,PCH sends SLP_S5#.SLP_S4# and SLP_S4# and SLP_S3# renamed to be sure 15-28. =------,c::::> ......... /3DI ::;::,----<::> \"'_SYNCI m Scanned by CamScanner

M15 ~ !ffiW K42JA (HM5x) D~~fl fi RI1I1WU\\M;POO ~_--\"-PW-\",R\"-,,l .=.rr,-,-._-,-,:Or,o:21115 = R~~,g~~ ~6~~~o#~ (45) TACfO'GPll6 FAND_TACH (33) TACH1/GP07 L8DH.ATIWU124'GPEO 1-..JlL.----'~\"\"\"-J'-' JPWRJ;N' (53) WUl2&GPE1 UD_SW' (45,53) a WUI26'GPE2 iL PWWRUSI2W7/IGGPPEE34 ~-----< 'k~~~ l.8Cl.lATIWUI7/GPE7 ~ --<<=]PIoCSUSBt (22) GPGln07 1-1W:.. EC Figure 15-29 EC received the power-on instruction SUSC_EC#~~IJ PQ8504 B~ NPN .=.t!Hf.IiTJBL 6 Jji;p:flU:ft1~J§, PNP - ~~i'ill-ij: =fi'f E ¥m.rPJ C, f=:t.+12V, ~IJOO 15-30 p!riFo +12V ~~ii PR8507 ~IIJ 8512 j£-i:~Jm, +5VSUS $t~:±l+5Vo SUSC_EC# controls NPN triode of PQ8504 conducted,after 6 pin being conducted,+12VSUS flows to C from the triode E,to produce +12Y.is ugh PR8507 send to the G pole of PQ85l2,PQ8512 conducted +5V. :-..,- +~-------__<lI5V PR85D7 +. PC850lI (1. 29A/O, 33A) 4.1\\JFJe.3V '\"'::t:;;-----.......r - - - - - - - - - O + 12V (0.0 12A) RT8202A (PU91 01) O~ 1¥J~r-g~/1. [1 Jtff~~Ll\\ Scanned by CamScanner

1of SUSC_EC# is also sent to PD91 0 I.makes it to be cut off.is shov.n in figure ()2A(PU9101 ) is hung up.according to the manual of RT8202A.the hung is ply of RT8202A being satisfied and EN/DEM being hung up.RT8202A er +1.5V being nonnal.the chip open drain outputs + 1.5V_PWRGD.and 3VS produced later. PD9101 INc' 2 P 1.5V TON '0 z ~--o '5VSlJSO 1PDl'9,,1=02vI f-2--?COlli! ¥ +\"-'~='--''''---\"'-i Q.1UFflSV '5VSlJSO COIlO3 +12VS, +12VS )UH~1j1JD~1j PQ8510, .sVS, !mOO 15-32 ?fr~o ~S +12VS is added respectively to the VS +3VS,+1.5VS.is shown in figure Scanned by CamScanner

SUSBtLPWR POWER Tf'C28T TI'C2lIT oPT1507 PTB50II 0 :J~~~gt;:~'5VSf'Cll5OC To.D33l.tFnSVPfl8SlJ2 *M.CCI.,·lQ% ,.- (1. 29A/O. 33A) ''5 I~:=:,cw ~~ Tl'C28T oPmID --:~~~t.-----rL---,L---o.,2VS (0. 012A) [email protected], {E;t;)=H~¥~+1.5V [email protected]:J&+1.5V \\1115-33 JiJT~o trot voltage,after the chip receiving +1.5V :J...SV partial pressure. the chip outputs Scanned by CamScanner

Jt +15V .75VS/O.5A PI I ~125VPCi'&C PAlI181 101l0l\"\" GND vs EC#lii.Ip;Ji!~ UP7706 (PU8402A) . II] T-l'\"i;b~tr.~+ I.BY , ?~ 11115-34 ijflf- • # to UP7706(PU8402A) at the same time.i u ed to 1.8VS PWRGD,is shown in figure J 5-34. (1A/ l000rFI5OV I'l\\1o&81 in figure 15- Scanned by CamScanner