Laptop Repair Part 1 OCR

33.Firsl,VCLK is low level,VOI charges CI through DO.5V.When VCLK comes,4.92V add 5V(ignore the diode voltage drop) is IOV.The voltage of IOV flows through Dl and C3 voltage rectifier filter,then charges C2 through D2.Add again is 15V,outputs 15V(the measured voltage is between 12....... 14V) through D4 and C3 rectifier fi Iter. VCLK' r r TV01 (SV) 15V/10mA <J--...-.£*----+~~__._____E'*_ ........._e~~__t. C3 C3 luF m 1000F 1000F .& PGND PGND PGND Figure 9-33 the boot-strap circuit of 15V 2. *'@iil~~$tJ*~ the open signal control relationship TPS51125 ((.J7f Ja f~ -'%~*,J;k~~)cJj~m~ 9-4. The original table in English of the open signal control relationship of TPS51125 is shown in figure 9-4. Table 9-4 the signal control relations • ENO ENTRIP1 ENTRIP2 VREf GND Don't Care Don't Care 0If RtoGND Rto GND orr orr On R to GND orr On RIo GND On On On On Open orr On Open On On Open On Open orr On orr orr On On On orr On On (fi~l Explanation ~ ENO J9*!1!!I11, :f'lf ii}iifi 1, imil2, VCLK ~;klil. When ENO is ground is.VREF,VREGS,VREG3 c ~ ENO imj1Et!.~.lill:tm, -134- Scanned by CamScanner

1~ ilil2 VCLKit~I~. ois ground connection through the resistance.and ENTRIPI and ENTRIPI are low •• 05 VRE03 are opened,channel l,channeI2,VCLK are closed. ~m~:i1k, ENTRIPI :Ri@i, ENTRIP2 791~1J-.t, jj]:i!r 2 jfO VCLK :WZ;;Clfl, jf; o is ground connection through the resistance,ENTRIP I is high,ENTRIP2 is ana VCLK are closed,others are opened. ~1Sil~:i1k, ENTRIPI :R1~, ENTRIP2 7:Ji@iot, Jmm 1 jfO VCLK fIJi:!JClfI, jf; o is ground connection through the resistance,ENTRJPI is low.ENTRIP2 is and VCLK are closed,others are opened. • ~JtISJl~:i1k. ENTRIPI jfll ENTRIP2 ~~79i'liJM, VCLK ~lfI, jf;1lt!.:i:$1J7f. o is ground connection through the resistance,ENTRIP I and ENTRlP2 are • closed,others are opened. ~, EN1RIPI ~ ENTRIP2 ~:>':J1ltflt, W3-t-immlO VCLK Wi:;;Clfl, ft:1ffi1J7f. ois vacant,ENTRIPI and ENTRlP2 are low,two channels and VCLK are closed others ~, ENTRIPI ~tli. ENTRlP2:>':J1ltflt, .R1fimm2~~lfI, ft:1t!!.~~1J7f. (;) is 'Vacant,ENTRIP1 is high,ENTRIP2 is low,only channel 2 is c1osed,others are , EN1RIPI ~flt. ENTRIP2 :>':Jiiiflt, iQiil I jfll VCLK ~:!JCltI, jf;1ffi~1J3f. ~C8n1:,ENTR.IPl is low,ENTRIP2 is high,channel I and VCLK are c1osed,others are ~m'RIPl .. ENTRIP2 ~:hJ~fIt, :i:HlI1T7f• • wcant,ENTRIPl and ENTRIP2 are high,all ofthem are opened. A1.RT8206B ~W~T~(~.#~~~flm0~)~~~~m~~~~, ~~~ ,~ SV 70mA ~tltJ:±l. iiJti~I§I~t*f:I:j 3.3V 13 5V !!,IG 2V iU A,fLlI: 6-25V. Stanaby power supply chip produced by RichTek,the internal of the ator module,which provides the output of 5V 70mA.It can olmge of 3.3V and 5V or 2V to 5.5V.The range of the main Scanned by CamScanner

RT8206A1RT8206B i31JJt4J~f$J9itmOO:tllJoo 9-34 JiJTlJ'o The top view of the pin name ofRT8206A/RT8206B is shown in figure 9-34. !!~I~ffi~~ ~3§N1~~QNffi~~iWN REF BOOT2 REF BOOT2 TON TON VCC c:J LOATE2 VCC c:J LOATE2 ENLDO ENLOO POND POND NC NC VlN OND VIN • OND LDO LDO NC SECFB NC , NC PVCC , PVCC LGATE1 LOATE1 BOOTl BOOTl ~m~-f-!-l-f-f-i~-~ gi>a.§.-m...:..:..E. -Q-zj-!!w- WQAII-32L 5x5 m>L1.;;l§w (a) RT8206A ll. WQAII·32L 5x5 (b) RT8206B 1119-34 RT8206AIB i31 JJt4J ~ f$ (J9ifm I~D Figure 9-34 the pin name ofRT8206A1B(the top view) RT8206A1RT8206B i31 Jjip:tJJff~~)(£~ 9-50 The definition of the pin function ofRT8206A1RT8206B is shown in table 9-5. • 9-5 RT8106A1RT8206B 5IJJP~)( Table 9-5 the pin definition ofRT8206A1RT8206B 2.0V reference voltage output tenninal connects VCC(200kHzJ250kHz),connects 2 the switching frequency setting REF(300kHzJ375kHz),connects GND(400 3 the switching power supply input,conn low 4 LOO module open level.LOOIREF is closed 5 the vacant pin 6 7 SV 70mA LDO voltage output, is c1osed,and through internal switch 0 SMPS 8 the vacant pin 9 10 -136- Scanned by CamScanner

eedback inputWhen FBI connects to vee or the ground wire,SMPSI is the fixed Ode'when FBI connects to the resistance partial pressure between VOUTI and the output voltage to be 2\"'S.SV ell good signal output,when SMPS I output voltage is less than the standard es to be the low level signal input.If ENI is high level,SMPS I is opened,if its low level,SMPS I is REF,8MP8l is opened after SMPS2 working driver signal output tenninal is vacant pin of low-end M08FET driver signal 82 power good signal • g end.connect the ground:custom mode.Connect REF:ultrasonic Scanned by CamScanner

I REF 2.0V ~f1t El!ffi~1trlli~ 2 TON 7f~~~i9:.'ii~, ~ VCC ( 200kHz/2S0kHz ) • ~ REF (J00kHzJ37SkHz), ~ GND (400kHz/SOOkHz) 3 VCC *~~~~EI!~A. ~~H~~~-~I~~EI!~ 4 ENLD LOO f~:lR7f Ja {§ %~ A, ~ EI! f , LOOIREF 7f Ja , flt ~:if. 0 LOO/REF ~ If! S NC ~Jlt4J 6 VIN ~ Jt ±:{jt EI! A~!fn'tA 7 LOO SV 70mA LOO El!lli!fn'tlli, ~~U1t~Et!. SV r=~J§, LOO m~1(If!, :J:f:if1li1I*JW I.S~B~7f;jCtJ]WdUEi35'~W SMPS rz:~B~ sv {;!tEt!. Jlt4J ~ 1ft ~ 8 NC 9 BYP 10 VOUT I SMPSI &1#!.Ao lt~ FBI ~U VCC ~!i!!~B1, SMPSI :7:11I!1J;E~'trl±l II FBI sv Et!.ffim~; lt~ FB I ~U VOUTl ~!i!!Z.rEi)~ Et!.~1l7tffi, iJJ I;:J. i~m.~-: lli Et!.ffi~ 2--S.SV n12 [LIM I SMPS I tiD tJj Et!.~ ISlliI 13 PGOO SMPSI Et!.~1LTm~.tfj, ~ SMPSI .tJjEt!.ffi1~T~;r-l1E7.S%II1. Jltf§ 01 -'%~~:7:11~ Et!.-'F SMPSI 'fj!~-m.li}.x.o ,l :J9i\\!fji:@.-'F SMPSI 7f~, {~ft!.f. 14 ENI SMPSI ~mo 1m.~ SMPS2 IfFJS7fJE SMPSI IS UGAT ~Yitij MOSFET !jg~ EI 16 PHAS EI 17 BOOT 1 18 LGAT EI 19 PVCC 20 SECF (RT8206A) B 21 GNO 22 PGNO LGAT 23 E2 24 BOOT -138- Scanned by CamScanner

.SMPS2 UHI.1I,.tJ:..,u...uJ thre hold vailic of ENx and ENLI () dl:scrihcd us shown in 0.6 V 1.8 2.3 V 2.6 1.2 1.6 2.0 0.94 1 100 ~~tIJIJ1j£11~I I o th d scription ofth lectrical featurcs of ENx and I~NLD shold valu ofRT8206 2.3V MIiJ If;j' idJ 2.SV !;AJ.:II-j, JFJ(: SM PS\" ~lb~em 18 2.3 lay starts'when its higher than 1.6V. :kii 2,OV • 1) j 1.2Y.the typical Scanned by CamScanner

2, ~*,JII1J* control timing sequence RT8206A1RT8206B B~t£*IJIltFf~:tmU&.9t!.* 9-60 The original in English of control timing sequence of RT8206A1RT8206B is shown in table 9-6. ~ 9-6 RT8206A1RT8206B 1'rn~*IJII1J¥: (~)cJJ~) Table 9-6 the control timing sequence ofRT8206A1RT8206B(the original in English) ENLOO M ' VON< M I V.w,lV) LDO $V SMPS1 I 3V SIIPS2 Low Olf Olf Ix X Olf '>';N' High On Olf Olf I Low (aft9r REF DOwers up) Low On '>';N' High Low REF Olf Off (aft9r REF DOwers up) '>';N' High Low High Olf On On \">';N' High IREF Low I Olf Olf (aft9r REF powers up) '>';N' High IREF REF I Olf I Olf On \">';N' High , REF High Ilalter ~~S2 on) I On Low (aft9r REF powers up) , ~O<On REF On '>';N' High I High (lIIlIlr REF DOwers up) -- On \">';N' High I High On (alter SMPS1 on) IIlllBr REF powers up) '>';N' High I HIgh High iOn On On (alter REF powers up) On (eller REF powers up) On feller REF powers up) [Mml Explanation 3 ENLDO 791IUt, ~p, EN) ~ EN2 tro~~, LDO~ 3V, 5V 7f:JC~~~$:JC1~0 When ENLDO is low,no matter what the state of EN) and EN2 is,LDO and 3V,5V switching power supply are closed. 3 ENLDO 79*r 2V (I{J~lt-SJZ, EN1 iOOm~llt, LDO 1£ REF ~J:E:)§~tf:l. 5V, 3V 7f:JC~~ff:JCl~o When ENLOO is high lever more than 2l being stable,5V,3V switching power supply 3 ENLDO 79*r 2V tro~lt-SJZ, E tf:l, 5V, 3V 7f*~~ff:JCf:flo When ENLOO is higher level more after REF being stable,5V,3V switching 3 ENLDO 79*r 2V a9~lt~, 5V 7f:JC~~~f:fl, 3V 7f~lt.tF When ENLDO is high level m being stable,5V switching power ~ ENLOO 79*r 2V lWiffi i±J. 5V, 3V 7f~lt~ik~fflo When ENLDO is high le.v.el -140- Scanned by CamScanner

REF being stable SV,3V sWitching power supply are closed. ~ ENLDO ;J~J*T 2V ~iWilt-'¥, ENI ~ REF}JiijJ, EN2 ·tM~ REF Jjj;p, LDO 1£ REF ~5E 1£ SV 3V 1f~It$t~~tf.I. en ENLDO is high level more than 2V,EN I connects REF pin,EN2 also connects REF 00 is output after REF being stable,SV,3V switching power supply are closed. § ENLDO ~*T 2V a<J;iiIt-'¥, EN] mREF n!IJ, EN2 ~iWiB~', LOO 1:£ REF f.~JEJ5~ 3V :m:tl7fJS, 5V:(£ 3V ~JEJ5{I}~\"iJI±i 0 When ENLDO is high level more than 2V,EN] connects REF pin,EN2 is high,LDO is output REF being stable,3V is opened directlY,5V is output after 3V being stable. ~ ENLDO ~*T 2V a<J~It-'¥, ENI 73i<lJ, EN2 73f~8t, LOO 1£ REF ~JEJ5!ffltrI±i, ~Ja, 3V f£~tf.I. When ENLDO is high level more than 2V,EN I is high,EN2 is low,LOO is output after REF stable,5V is opened,3V is closed. § ENLDO ~*T 2V a<Jiiilt-'¥, EN] ~?iJj, EN2 ~ REF JJ!lJBt, LOO 1£ REF ~JEJ5~\"tr sv :fttl7fJS, 3V:(£ 5V ~JEJ5~~I±i 0 ~ ENLDO is high level more than 2V,ENI is high,EN2 cormects REF pin,LOO is output being stable,5V is opened directly,3V is output after 5V being stable. ~ ENLDO ~*T 2V a<Jif6It\"F, ENI 73rf!lJ, EN2 i1?73i<lJBt, LOO 1£ REF ~.JEJ541Jtr fiV.\" 3:V ~~:m:tl7fJS. \"Wlil~ ENLDO is high level more than 2V,EN I is high,EN2 is also high LOO is output after jog stable,5V,3V are opened directly. Analysis of the memory power supply chip * introduction ofthe pin definition and common pin -14:1- Scanned by CamScanner

ISL88550A (28 LDTQFN) TOP VIEW !E~:l gQ •a. c 1zi 0 ~ Z ~ i2 Z~ t' >0 ~ a. 0 OVP/UVP ~~ ~2=D~ BOOT REF ILIM -, ...~1-9\" PHASE ~-~, POK1 ~.~, [~: UGATE 5.-,,• ....--~1-7· YIN !~ .16 OUT Figure 9-36 the name of the pin ofISL88550A(the top view) ISL88550A ;;;1 JJt;pJ1Jfj~}:EJO\\!.~ 9-70 The definition of the pin function ofISL88550A is shown in table 9-7. • 9-7 ISL88550A S1IIilJ:.lE)t~ Table 9-7 the table ofthe pin definition ofISL88550A I frequency selection:TON connects AVDD(200kHz),when its in vacant,connects REF(4S0kHz),connects the ground(600kHz) 3 2V reference voltage output 4 the limiting current setting 5 PWM power good 6 LDO power good 7 8 soft start 9 -142- Scanned by CamScanner

~~ voltage output,connects to VTTS to keep it to be half of VREFIN mvoltage ofVlT voltage regulator,in the application ofthe memory power supply.will ect it to PWM output tenninal back of PWM.When it connects AVDD,fix output J.8V,when it connects the i.lt 2.5V.If its adjusted by the resistance partial pressure,it can output the voltage 3.5V • ,power supply input,the range of 2\"\"\"'25V pin ofPWM.the function of the top tube drive loop and the current detection ~ply ofthe chip,the origin ofthe driving force ofthe down tube it connects AVDD,low noise forced PWM mode,when n I:input A the rising edge clear fault latch,connects the high level open chip Scanned by CamScanner

R F 2V Jt~~ 1l!,lf~JiJ III ---- 4 IUM fJk ~~ Il!, ~!JE & ,~ 5 POKI PWM ll:!.ilJ;fH JlW ~ ~ 51-. if!. ¥1f- 6 POK2 LOO t1!.i}gH 7 STBY# !! STBY#~f~lI1, VTT ~lltrc~, ¥. ;I§ii ~ll~ 8 SS ~.Fci\\lJ 9 VTTS VTT rt!.ffif&~~4B~.A 10 VTTR f;t. ~iliHtt 'tffi , {fi.!¥i VTT - ff 11 PGN02 ~:il!! 12 VTT ~~ [email protected]~ I±l, i!~~u VTTS f~z. {~M'73 VREFIN Et-J-* 13 VTTI VTT.ffi~Et-J • [email protected], a~~~~~ffl~, .3~re~i!~~ PWM _I±l jjjij 14 REF IN ~~!II~i1t ~ffi4UlJ.A, ffl Tir.J~ VTT f-O VTTR, B ffJ 4B~ ttl a~ ~ffi~ REFIN I¥J-~ 15 FB PWM I¥J&~. 1t AVOO Bt~);E4B~1±l I.8V, ~±t!!.Bt~);E4B~tl:l 2.5V. iI~ItISlHtff~iJtI~i!, PTIV-~~:±l 0.7-3.5V z.rEi]Et-J~lli 16 OUT PWM B<J.l±Iltffi*~!dtt A- 17 VIN :±-mIt''A, 2--25V m:~ 18 UGATE PWM B<JJ:'lf~i;fJ 19 PHASE PWM B<J*DO. J:'f~i;lJIEl~IV-&ltmt~~H'Fffl 20 BOOT ~.3Tffi_ 21 LGATE PWM B<Jr\"l:.i! 22 VOO ;e;J:tB<J~,g, 23 PGNDI filtlk 24 GND fil*& 25 SKlP# I~D JJt~.st 26 AVDO LOO 27 SHONA # 28 TPO -144- Scanned by CamScanner

.9-8 ISL88550 r..J7f~1~.!i5-~iliIJ*~ (~3tJjj[*) the open signal control relationship of ISL88550(the original in English) IttDNAI STBy, BUCK vn VTTR GNO OUTPUT X OFF AVOO OFF OFF GNO (Tracking Y. AVOO (Discharge 10 AVOO REFIN) OV) ON OFF ON (High Impedance) ON ON ON - ~._- ~ iNA# COnnects the ground,no matter what the state of STBY# is,PWM,VTTR are also closed(discharge to OV). NA#~ AVDD, STBTY#~fl!!Il1, PWM til VTTR t1~1Jff, VTT ~*I~ (j;,J SBDNA# connects AVDD,STBY# connects the ground,PWM and VTTR are Will be closed(the high resistance state). #~ STBY#fII~ AVDD 111, PWM, VIT, VTTR :i:$1Jff 0 iNA# and STBY connectsAVDD,PWM,VTT,VTTR are opened. troA~mzffl:tulI!l9-37 ffilfi. 51 lication ofISL88550A is shown in figure 9-37. Scanned by CamScanner

ISL88550A -U---IAVOD OYPIUYP 5Y BIAS SUPPLY CI: OPEN S5 YDD TON YIN C8: bl0~F VODQ SKIP' BOOT 1.8V/12A GND UGATE ~Ql STBY' Ll: SHDNAI FALCO ER13l19 POK2 1~~H.3~ ~ POKl PHASE C11 C12 cn vrn Q2 IZZO~F IzzoP' I l~F LGATE 12mO _1~ _ R3 R2 PONDl \"'=' - - 1_ 1_ OUT Rl: 182k Ql: IRF782113OVl9mO IUM 02: IRF7832J3OV/5mO R4 200k REF YTT: a.loni.IA YTT FB ......_-==\"\"--0 AVOD ~ -VTTS RUIN O.tvMDmA Cl YTTR bl0pl' C. ~ OPEN llP' - 00 9-37 ISL88SS0A A~~Jfl 00 Figure 9-37 the typical application ofISL88SS0A Jl: 1 * I f\"Flm.~: The specific working process: CD SV ¥r?i 22 W4J-mIt, 4.S--2SY tit 17 JJ1J~ 5V supplies power to 22V,4.S--2SV' s~ ® 3 Jl!IJf=j: 2V ~$ltffo 3 pin produces 2V reference voltage. ® j¥jfjj::&:±l ~ It3f1W SLP_S5#1 The South bridge sends the higH ~ @ PWM 7fJi3, _1:1:1 VD~ PWM is opened,outputs VD~ @ VOOQ ~§I~ OUT VOOQ is returned to 0 power to REFIN. ® ~4I:±l VlTR, Jt~ Itfa, r~i:J:j1ij 1- 10kO -146- Scanned by CamScanner

lJ!.\\~bij)1~tbro is the half of REFIN h . .t at IS 0.9V(as shown in figure 9-39.after • ugh two of IOkQ resistance serie divides into the voltage to b th O.9V through voltage follower).At the same time.lhe chip output REFIN/2 REFIN IOkO 1Oko VITI VIT 1-----1--0 PGND2 tofthe internal relationship ofREFIN and VTI,VTIR ofTSL88--0 Scanned by CamScanner

3 the ground connection 4 output discharging mode setting pin.Connect to VOOOQ trace discharge:connect to the ground,the non trace discharge;connect to VOO,not discharge 5 VTIREF voltage output pin.is sent to the memory reference voltage 6 the diode emulation mode open pin.Connect to VOO to open the diode emulation mode;connect to the ground,is always working in the forced CCM mode 7 the vacant pin 8 the reference input pin of VTI and VTIREF.The output voltage of VTT and VTTREF is the half of VOOQ.If FB connects VDO or GND,VDDQ can be acted as the output voltage feedback input pin 9 VDDQ(PWM) output voltage setting pin.Connects to GND,outputs I.5V;connects to VOO,outputs 1.8V;it can set the adjustable output voltage between 0.75 ~3.3V through the resistance partial pressure )0 SLP_S3# sent by the South bridge,is used to control the output ofVTI 11 SLP_S5# sent by the South bridge,is used to control the output ofPWM and VTIREF )2 connects to VIN through a resistance,sets the frequency 13 the open drain output pin ofthe power good,it means that PWM control output VDOQ voltage has normal 14 the power supply 15 the power supply 16 17 the vacant pin 18 the ground connection(the ground co 19 the down tube drive 20 21 the top tube drive 22 the boot-strap pin 23 24 the output ofVTI -]·18- Scanned by CamScanner

=:ti.-f1i• •~7f.€l./l!ll. hitl VDD 7fJa=~hZ:g1jjJffjt:rt Jt~itl :l1!!., tt&~I f'Ff£~!ii*,J CCM ~A tA-*\".VIT ~ VITREF rt:J~;1UifUA./l!II. VTT .fO VTTREF sf](fu\"Ut!:J 1t!.J.I~ VDOO 1m* FB 1i VDD EX GND, VDDQ iiJ!?J1'Fjg(fu\"Ut!:JIt!.J.I .&tlIlABIlJ VDOO (PWM) ~tl:lEt!.ffitt)i;./l!II. J!1iitl GND, (fu\"Ut!:J 1.5V; 3i1i !tJ VDD, .tl:l I.8V; ili1Jt1J.Il?tffiiJ!?Ji,iJE:~t!:JEgJ.I O.75-3.3V Z. rajiiIiJf!l Scanned by CamScanner

The typical application ofRT8207 is shown in figure 9-39. R4 V,N Il2Ot< 2.5V II> 26V RT8207 1 C8 Vvooo BOOT ~--./'./V--, 'O~Fx2 '.8V/l.5V 12 TON C6 VODPo--t_---..---..,p-----!.2l15 VDOP 1220~F 5V Rl ~-5-.1-<.-.!:!.j4' VDD :J;lC~2F R2 R3 5.6k lOOk PGOODo---......- - - - . ! > ! . j VTT Conlnll o-------Wl 53 VDDQNTTREF ConInlI 1 55 ' DIKh8Ige Mode MODE CCMlDEM OEM 3 FB 9 VDOP fa< CORII I!--------OGND fa< DDRIII = m9-39 RT8207 A~gffl 00 Figure 9-39 the typical application ofRT8207 RT8207 tr-J S3 1O S5 ~flitJ;r.~~~)t.J.l.J\\!.~ 9-90 The original in English of the control logical relationship between S3 and S5 of RT8207 is shown in table 9-9. Table 9-9 the control logical Ie • STATE 53 as SO HI HI S3 Lo HI S41S5 Lo Lo (Ql -150- Scanned by CamScanner

'ng process ofRT8207 is shown in figure 9-40. v.., 2.5V 10 26V R4 620k FB 1\"-9 -oVOOP fo< OORU GNO for DORIII ~~ I\\!.lI'tPWM~l±l1.8V ~:Il!!il'tPWM~tfjl.5V 1119-40 RT8207 BgI11=mE~~ Figure 9-40 the working process of RT8207 ~ It!. the power supply 7f.\"ttl-1 PO -1 open drain outputs PO Mm~* SLP_S3# the South bridge sends SLP_S3# Mm~* SLP_S5# the South bridge sends SLP_S5# :ti~d detection _ttl VOOQ output VODQ _ttl~Et!Bi~Rlt VTT (VODQ ~-*\") convert the voltage input by VLOOIN to VTT output( half ofVODQ) output VTTREF halfofVODQ PWM outputs 1.8V when it connects the Scanned by CamScanner

Analysis of the bridge/bus power supply chip m~~~A~~~Z~~~~., -.*ffl.PWM~#~PWM~~•• The bridge power supply and the bus power supply chip is relatively simple,is usually used a single PWM or dual PWM controller. I){)I> 9.4.1 Jtl PWM ~\"JH RT82091Hfi Analysis of the single PWM controller RT8209 '~ffl(f.J. PWM ~*Ijft RT8209 iJTfflTm~~, ,~,~~~, i*Jf¥.:t1;!t~~1&~~~~. IT l~:: RT ~'UZJt*1*-.f6:~:::f~ff.~~%, .Rfff=£.f-t%· 19Hz!], RT8209BGQW, ~Jt *1*P1f \"AO=\" ::j::~, 1m1ll 9-41 m~. J1t~ZJt(f.J~lltj~%iR§}'J~JfF~ RT ~Jt(f.J!-g-9&Jt 11f. g iiUlitJTmt{~I:tl(f.J.tfiAli*~ 09 1¥(f.J, Jt1tf~73 Richtek_Marking_Code_090424.PDF, I'iJ ~{fmmlAAJ (www.chinafix.com) '\"\"F~¥U. The common single PWM controller RT8209 can be used for the bridge power supply,bus power supply,the memory main power supply and other circuits.Note:RT series chip body usually do not have a real model only the product code.For example,RT8209BGQW,the chip body is only the word \"AO=\",is shown in figure 9-4l.About the actual ~ recognition of this series chip,you need to download the packaging file ofRT chip,at version ofthe new efferent is 2009,the name of this field is Richtek_MarkinLCode_ ,PJl>F,you can download in the website:www.chinafix.com. -152- Scanned by CamScanner

~ .h===::::;:;:{\\--'BOOT RT8209B (WQFN-14L 3.5x3.5) UGATE PHASE CS VDDP LGATE PGND '--lC==~ RT8209C (TSSOP-14) Figure 9-42 the pin definition of RT8209 series chip (the top view) .~IJIJ: ~7 PWM :m~5IlJ14J7'~, ~EBJl!lJ VDD, VDDP -!J9:J1fHglj 5V, CS ~t)H~ ~ TON :JgMJi*1i~, 7fJalJl4J EN/OEM B~JE:x.~;arn/=~1H211JAr~:rt~1IjIJ$r1trA Q=t-mJlfl ENIDEM B\"J~fliJNiit~OO 9-43). ~~flj VDD 7g-,I'lJZ~11JAf~:rt, jrf -mg~.~~~OCM(• •EBfi)m:rt.-.I~~, .~~~~~, *ffi~ ~. ;important pin:in addition to the PWM related pin,the power supply pin VDD. VDDP are connected to SV,CS is the current limit set,TON is the frequency setting,the definition of the ENlE>EM is the start using/the diode emulation mode control input(the threshold value or RT8209 data manual described as shown in figure 9-43).Connected to VDD,is the \"on mode,connected to the GND tum off chip,is CMM(the continuous current) mode ~~:antGenerally,its the vacant state during working,and is the ground state when its turned ENlDEM Low 0.8 Z9 V IENlDEM High 2 ENlDEM ftoat the screenshot ofthe description of the electrical features of EN/OEM pin threshold value in RT8209 data manual 7,~rKJ.mzffl:tznIll9-44 ffi7J', If\"Ffi~fijit:tzn\"f. of RT8209A1B/C is shown in figure 9-44,the description of the working Scanned by CamScanner

Starts PWM outputs VOUT. @ ]A VOUT )J!p~WlU r:fiffio Detect the voltage from VOUT pin. @ 7f~~1:tl PGOOD, IE VDDP LtL79~Jtl.fo Open drain output PGOOD,is pulled up to be the high level by VDDP. RTON 250k VOOP RT820BAIBIC R4 VOUT = 1.05V PGOOD 0 ': OpllonaJ TON BOOT RS 0 VOOP Rl R7' GS' Gll\"' G1 R2 10 UGATE 1220~F 1001< C2 R8 VOO PHASE I1~F LGATE = PGOOO PGNO 12k GGMIDEM cs FB R9 30k ENIDEM VOUTI-----------===----...J GNO \":\" 00 9-44 RT8209A/B/C B~mffl 00 Figure 9-44 the application ofRT8209A/B/C :«[)(){> 9.4,2 PWM ~.1jJ1 TPS51124 ~trr Analysis of the dual PWM controller TPS51124 m1t ffl T tit JtI. ~ I~ ~ ~ It! l¥J)OC EWM ~Jt!~ J:r TPSS1124 1f 3-28V l¥J~Alt!ffi~lJJ, • Jg O.76-S.5V 0 The input voltage range of th~ ffi:iil supply chip TPS51124 which is c~ bridge power supply and the bus power to 28V,and the output voltage range is fro TPSSI124l¥JijIJJtll~f$:tmm 9-45 The pin name ofTPS51124 is sh :m~ijIJJtllm~: 15, 16'-;>'g $~, ~ 1, 2, 17-24 )Jip~~= ~LHi, EN1/EN27tj}lJ7fJaPJlU The explanation of the lID frequency selection,from 5 pin pin and from 17 pin to 24 pj respectively the over-c -154- Scanned by CamScanner

• •.=f.MJ:j:IX'j VSIN, VSFILT (jry1~1:rE!.~U:I:liI:Ii~~~rJ[~1 9-46 fn7J\\: V5JN, WiIl4.s-s.SV. 51124 data manual,the power supply range ofV51N and V5FILT described as shown :tile power supply range ofVSIN and VSFILT is from 4.5V to S.SY. VSIN, VSFILT MIN MAX 4.5 5.5 the screenshot ofthe description of the power supply range ofV51N and V5FILT in the TPSSl124 data manual 4fdl.=f.MJ:j:IX'j EN ~l!IJil#fl~~[)OO 9-47 JJJT7ft:, EN Enl*JiliUdl£:tJ IV, -119:7:1 1.5V. 51124 data manual,the threshold value of EN described as shown in figure 9-47,the Id value ofEN is 1V,is usually I.3V,the maximum is 1.5V. the screenshot ofthe description of the electrical feature of EN pin threshold value in IWlTCHING FREQUENCY CH1 CH2 ClND 240 kHz 300 kHz FLOAT (Open) 300 kHz 3110 kHz V5F1LT 3110 kHz 420 kHz the screenshot ofthe description ofthe frequency setting ofTPS51124 .-JI PWM I11=1£ 240kHz, ~=J& PWM I11=1£ 3OOkl-iz. the ground connection the first path of PWM works in 240kHz,the second .=J&kHz. PWM IfF1£ 360kHz. PWM I11=1£ 300kHz, die first path of PWM works in 300kHz,the second path of PWM PWM I f1=.tE 360kHz ~~. PWM If'F1£ 420kHz. e rSt ~th of PWM. works in 36O~the-second paUl of Scanned by CamScanner

SKIPTfP!S;5b:1t1~24764!Im'dfV,t},-,¥-PJuWt1Ml1x-JfthFtB1'9IJ7i5l8lrmfJVrQ~/=V2I5~H°1CrAro1j£,~IiJO~O~*f9fJ-J4[9+P0J.T97%Fo, F0B~85I°tlCliIifIW1i!f~J&\"*i!IlE'miJH!tJl: + 1.3%. -40-85°ClI1wt~;fflJ3t± 1.6%. In the TPS51124 data manual,the electrical features of FB pin described as shown in figure 9. 49.1n the SKIP mode,the reference value of FB voltage regulation is 764mV,in the PWM mode,the reference value is 758mV.the error precision is about 0.9% in 25 °C ,the error precision is about 1.3% in 0~85°C,and the error precision is about 1.6% in -40-85°C. VF8 VOLTAGE and DISCHARGE RESISTANCE 764 mV VVFB VFB regulation voltage FB voltage, skip mode (fPWMI10) -0.9% 0.9% TA ~ 2Soe. bandgap lnillal accuracy -1.3% 1.3% -1.6% 1.6% VVFB VFB regulation voltage TA= ooe to 8Soel') tolerance TA • \"\"\"coe to 8Soe ll ) VFB regulation Shill In 758 mV VVfOBSKIP conlmuous conduction see0.75S-V target for resistor divider. PWM Oparatlon of Detailed Descripllon (1) Figure 9-49 the screenshot of the description of the electrical features ofFB pin reference value in the TPS51124 data manual TPS51124 A~@FIUIJ 00 9-S0 Jijf7f.; a The typical application ofTPSSl124 is shown in figure 9-50. InlWl VoIlIIge R4 R5 R1 28.7kO 3VIo2SV 73.2kO 75kQ C9 22uF SOND POND V02 10 uF '.5 V/10A V01 1.05V110A C4 2x330uF V51N 4.5Vlo5.5V Fi~9~S fsj ~I f'FiALfj!~\"F 0 The description of the wor • CD ~E\\:!~A 4.S--S.SV -156- Scanned by CamScanner

er supply outputs 4.5 --5.5V to 15p'm and 16 pi.ll. EN2 tlfrIA. 2 input r--.,ij,\\G~~=~ PWM. path ofPWM or the second path of PWM. @1 ~~ V02 tijl8!'f!lli. voltage from VOl or V02. lim PGOODI ~* PGOOD2. output PGOODI or PGOOD2. Analysis of CPU core power supply .Jt:~~!'f!1f$1\", :ro:J 478 at CPU li~ 3 #1~~, -1\"\\ 13/[5/17 ~~ 5 1'-1~~ msjCC ..::t~~'c.,~!'f!. *li':±~ijj:fA¥JL#'M' CPU ~JL.'tit~~c;JtI 11=J~J~o y requires a nwnber of power supply,for example,CPU of 478 needs three kinds of first generation 13115117 needs five kinds of power supply,but only VCC pin is the core this section,we mainly explains the working principle of several common CPU core of CPU VCORE power supply ~1\"1t¥!jj~4iI±lii~tE-~, ~1!'J:J3 CPU ~~, ~.WijJE CPU A~¥j[1ffl m~~:tm !I 9-51 JiJT7J'. output is that the output of multiple current sources are connected er to €PU,whieh meets the demands of CPU large current.The real object of ypply is shown in figure 9-51. ~~J.~ts.I{,FIt.ffi~/f'jRJ(J(j, m~ilJt:-#~*IJ1fA*§Z9J~g~ IlP.I±lIt.ffi~ VID rl*~. w.ol~ required by CPU at the different times is different,so it needs the tieatly, tbe requirements of the different CPU on the voltage that is,the G ~~m~)~-~~s~~tt*, ~k~jRJ~~U, ~~ Scanned by CamScanner

nrVlD 7t7~ PVlD (JHf VID) ;fn SVID ($ ff VlD) 0 VlD can be divided into PVID(parallel VlD) and SVID(serial VID). Figure 9-5] the real object of two phase CPU power supply AMD .!liM*\" Intel 5 -*~tl~Jt~!l (HM55 ~) ziW, m~~T PVIDo Jt~*JJjU~8Jt~tE CPU J:i5Hi7 4-8 l' VlD i~UIIJJJI4J, *ii!lJiffiii:(£~®iJUIUJj!pJ:B~?iflj1~1:1~!;~fl, ~p)t-m VID in}}U1§-5, ~ VlD iJU}tlJJtpJ:13~It!.-'FIJ't, 9!tl13=:itt$IJ8\"J I *~, ~ VID iJUltlJj!pJ:~1~~~D'J, JjltlJ~~*ltiIJ8\"J 0 *~o Ui!® I ~ 0 8\"J~.Il~, Wt~p)t7 -~!l:li~*B~m~rrf§1§-5' *83 CPU fl;4JlIJf-U CPU f;tt:lt!.~rm9J8\"JIt!.~'fJl~Jt, 1t!.~'fJl~JtfLHf.5JiJf~JIJB~ VID 1§%, iPiJ~!fu'tt±JJljjcf1=P f§%AtJ d.:i£l:t. i§.~ CPU ~1t!.$J&.:±IIW.m:mtttBi~ffi1i8\"J VID JiJf1-\\:~8\"Jfl-3&o AMD early and before Intel 5 series chipset(HM55,etc),are all belong to PVID.The basic principle is thatsets 4-8 VIO recognition pin on the CPU,and through the high and low level values preset in these recognition pin.to fonn a group ofVID recognition signal,when its high level on V1D recognition pin,then is the I state of the binary,and when its the low level on the V1D recognition pin,is the 0 state of the binary.According to the combination ofthese 1 and O,forms the group ofthe most basic machine language signaI.and is transmitted to the power Chip in the CPU power supply circuit by CPU,according to the VID signal,the power . adjusts the duty cycle of the output pulse signal,which forces the DC voltage output by CR circuit to be consistent with the value represented by pre-set VID. • ~.~ (Voltage Regulation ~t&m VRD (Voltage Intel 0jjj~jt~liiJlJ'tfB]~;a:IW~. CPl!1 (Intel Mobile Model, VRM) iiit~!U[, JA Prescott ~I BiiJlill!mmliI Regulation Down) *1ftr:t, :(£~ia*f,@; Voltage Positioning), ~~*~EI!l i l t \" ~:iFffIliiJ 0 Intel company developed the ~ each CPU produced at different regulation specification used Mobile Positioning,the VlD digits the various version ofthe pow IiIBti!#mJ:tIW VID, -158- Scanned by CamScanner

~~!t2pJ.~r~t-:jJ1!@-:I~.CC~~P:tUf-i~!V~ID~.f:~I ~0/F:1talJ±8blj!!~,.EJlJ.to~t,EfJt.1£m. *. ~IC~t8I~HVBI~DOOj~EVgIEDL7 mi]8IJJJti;~lJiJ:£8),t~!Ji~Ut O'thldis, mode can ' cheat' the CPU to come out by loading the dummy 10ad.After loading co~ects one or more VlD signal of VIDO ~ VlD7 to the ground,at this 7 pm of the power IC ge15 the new voltage combination according to this different \"pow\"er IC will control to send the correspond.mg vo'ltage.That is to say let CPU 6hip IDlstakenly assume that the true CPU is loading. AM2+ CPU 7f1lfj, CPU 1~;fg-~W3$7tEfJ.LI (AMD %\":z.tJ Dual-Plane), -1'-~ lit -1-~ CPU P3~1iX:((.]~tm:8j EfJ.LIo -~J3.j-HT VID ~*IH~:ljc7C~1:EfiJ-a;j *ffl *lX1\\§\"l+rtBt, IS!~FNm~-m:JHT VID ~*IJ CPU ep8'~~tm:~LI, 19j!~~~ • rJ! AMD *$I6ml±lffi-f-tltlliifiiJT.it~:ljc~.mm, fT VID (SVID) tffi;~* • $tr YID ~-~·~~~m!((']#J·-j,)(o JAli9!ftj:J:*~, JiJTi¥r~Et-J)1H11mHJ El3 (;l. 5 jt 6 -t~Pl SVC (*qTa;J~), SVD (*qT~1J.O fm1-, r.iJ(;l.i.£~rn.!ftJ H1r$tr VID :J!-~.~~Iffm~, JiJTlV-tffi~tj~1tj:8jwc.1r, 19fiJH;jm~U*~ f1:tt~J!5;o iWM*iW1t AMD '±:lJX:T:JJ*t~ AM2/AM2+/AM3, *ffl J PWM~fMBo m AM2+ CPU,CPU contains two parts of the voltage(AMD calls it to be Dual- core voltage of CPU,one is the voltage of the North bridge integrated in CPU.A el VID control modules can not asynchronous control these two voltages at the same \"des a group of parallel VID again to control the voltage of the North bridge in • be more complex.So AMD launched a new generation of voltage regulation \"on,using serial VID(SVID) mode to solve this problem.Serial VID is a type of bus hardware point of view,the required external interface is from the previous a total of 6 becoming into SVC(serial c1ock),SVD(serial data),it's very use the serial VID is the bus working mode,so it needs the cooperation of the means that the operability adjusted latter wi1l be stronger.Most of the previous USed PVIlSVI compatible of PWM controller in order to to compatible with ft.Ja(l(J Core i31iS/i7 CPU .fflt7~~~Ic.\\, 197£M±l!!~*Uj!W3~J3.1t WD _l::::J W.?HJIJ~$tJ CPU tr.J~lc.\\~ffi*,~~~lc.\\~ffi, j!p:ij~J3.ItLI N.. ita~J!~H.~7-@. . lay core in Core i3/iS/i7 matched with 5 series platform in order to er supply better,so provides two groups ofPVID interface to control a cree and the display core voltage,these two groups of voltages are tel Y.RDI J.t which is more complex. 2 ~~ -mitJ!l$qf VID .~. ~ AMD SVI.:tt : SYD (lilHr V1D ~.)\"\\ (SV:C $iT VJD lI[~) Scanned by CamScanner

Starting from 6 series platform,lntel imports VRD 12 specification.that is the serial VID mode.its exactly the same with AMD SVI mode.There are three line of SVID of Intel platform:SYD(serial YID data).(SVC serial VID clock),ALERT#(waming signal). [)(){> 9.5.2 MAX87701,Hfi Analysis of MAX8770 MAX8770 ~ MAXfM 0'§]j::f\"(j~RlT CPU ~lc,\\1j±~~~*tl;L:;Jt, rq:g- IMVP-6 ;ij!,m:, .±~~ };~t~ll\"F • MAX8770 is the control chip produced by MAXIM company,which is used for the CPU COre power supply,in accordance with the IMVP-6 specification,the main features are as follow. • xt.fjlij.ffi CPU ~~. Support two phase CPU power supply. • xt.¥ 7 UL VIO, ~~tl1~lli O-t.5000V iJJ~. Support 7 bit VID,the output voltage is adjusted from OV to 1.5000Y. • x t.fiifJ~.ffiULW!.Mll1*D~. Support for dynamic phase adjustment and sleep. • ~Jj.l(;!3giifJ;L:;J:f • Integrated driver IC. • Jl,-i-~~mt~ (PWRGD) .tl1f=nIt-J\"~~fl~ (CLKEN#) ~\"i]tl1. With power ready (PWRGD) output and clock enable(CLKEN#) output. • *J ~~%i:~~i:1~00? With the power monitoring and over-heat protection. • xt.f 4-26V ffllA~.lli1l1I1o Support 4-26V input voltage range. 3 JJTlJ'o • ~~ tl1 i:1Ekf*:tF • Output over-voltage protection. MAX8770 iJlJl!p!6~:tm1m 9-52 ffim, The pin name of MAX8770 is shown • :of MAX8770 is shown in figure 9-53. -160- Scanned by CamScanner

00 9-53 MAX8770 ~!/o/}OO the pin name ofMAX8770(the top view) the real object ofMAX8770 70 ~iJlJ)ip}E50~!.~ 9-11 0 m definition ofMAX8770 is shown in table 9-11 . • 9-11 MAX8770 iJIJP;E)( Table 9-11 the pin definition ofMAX8770 o the clock enable logic signaJ.When the output voltage detected from FB pin reaches ue this pin outputs the effective logic low level. 00d signal of the open drain output.When the output voltage detected from FB pin ified value,this pin open drain outputs the high level. logic signal and DPRSLPVR commonly set the power mode.lf PSI# is low,then Me ofN-l phase.When PSI# is high,then recovery the PWM mode ofN phase. lUt pin of the internal comparator.When the voltage ofTHRM terminal is less 'WUiOT# is pulled low.Its the high resistance at shutdown internal comparator.Connects one end of the thermistor(usually is NTC) end to THRM,and through a resistance to vce at the same time.By lhe required temperature,the voltage of THRM end is reduced to less oltage swing)control pin.TIME connects a resistance to the ':Ihe application of the voltage slew rate contains:the chip chip enter VID MODE from BOOTMODB.For toe soft start Scanned by CamScanner

and shutdown process the chip reduced automatically the slew rate to 1/8. 8.the switching frequency setting pin.The switching frequency is set by a resistance connecting to the power supply end and the TON end. 9.the capacitor connection of the voltage integrator. 1O.the current balance compensation 11.2.0V reference voltage output,through a maximum of 1 11 F capacitor bypass to the ground.REF can provide SOO\"A current to the external loads. 12.the feedback input.The external resistance capacitance element is used for detecting the output voltage. 13.the negative of the inductance input end of the feedback bypass.Connects to GND of the load end in general. 14.the positive input end of the second phase output current detection.This pin must be connected to the positive end of the output current sense resistor.Connects the PIN pin to VCC.the second phase is closed. IS.the negative input end of the second phase output current detection.This pin must be connected to the negative end of the output current sense resistor.Under the case of the DC inductance of the output inductance being used as the output current detection resistance,this pin is connected to the output filter capacitor :t detection.This pin must be connected to 16.the negative input end of the first phase otitp c e case of the DC inductance of the the negative end of the output current sense .resi ,this pin is connected to the output inductance being used as the output cumm output filter capacitor must be connected to the CC,the first phase is 18.simulated ground 19.the controller power supply pin.Co 11 F bypass capacitor to connect to the 8r.9 21.the output end of the top between LX2 and BST2.ltS -]62- Scanned by CamScanner

• ill end ofthe output inductance of the second phase.It sets up the opening voltage on top tube acts as the input end of the zero crossing comparator of the second phase at hase power ground.Its the ground end of DL2.1t acts as the input end of the zero or ofthe second phase at the same time. end of the down tube drive signal of the second phase.The voltage values is changed aDd GND.DL2 is high in the shutdown.When the output voltage is abnormal,it has tie high.!t also is low in the small load mode,until detecting the inductance current IZero crossing ply pin of the down tube drive of each phase.!t acts as the charging source of the ofeach phase at the same time.This pin connects to the voltage source of 4.5~5.5V of the down tube drive signal of the first phase.The voltage values is changed ifid GND.DLl is high in the shutdown. When the output voltage is abnormaI.it has high.!t also is low in the small load mode,until detecting the inductance current crossing und of the first phase.Its the ground end ofDLI.It acts as the input end of the zero [ ofthe first phase at the same time. end of the output inductance of the first phase.It sets up the opening voltage on ,acts as the input end of the zero crossing comparator of the first phase at the Scanned by CamScanner

39.the input end of the depth sleep control.This signal and PSl# signal set commonly the pOWer mode 40.the deep sleep awaken signal When this signal is low it means that CPU is in a deep sleep state JW ~ 5:E X. fir. f* ~~~R~.m~~.ilio§MffiJWM.~~.ili~ffi~~~~m 1 Ci:KEN ~, ~JJI4J4iJlI tlF(if ~iZ .1l;t Jt.>f 8tJHfi!4irllilil¥J~~~H§%o §JA FB JjI;fJ~~tl¥tl8g.ili ~ffi~¥tl~~;Em 2 PWRGD ~, ~JJlJ7fim.ili~~3f ~1l;t~ff~.m~.!§ DPRSLPVR ~~i9:ff~im!~Ao ;ff PSI#~1K. 3 PSI 9!~i£A N-I ~'fHir.EJ<J PWM mAo § PSI#~~~t~![ N .ffi1ft PWM t~A 4 POUT Ef!~~P-t~tB a5 ~ 1flI It ~ EJ<J iI ~ 7f lffl. $)11 tB Jj!p 0 § THRM jffij ~ ffi 1a T 1.5V VRHOT (JO%VCC) ~, VRHOT#1fL1ao *m~79~~£I. P31flIIt~_NW. ~-11Mi&Ef!~£I. (iM-m-~ NTC) ._jffij~:tt!!., ¥J-Jilrati 6 THRM THRM, ~~iiit-1-Ef!Jm.~JtlVCCo ~R§8g~1tf:. 1~.mtEfffl~B~ ¥M!;AJ:, THRM _t¥JEf!EIi~~ 1.5V !;AT Ef!ffiJI* (Ef!ffitl*~R: Ef!ffitlz;/J rJgj£$) ~li;;1 JW 0 TIME M±{!!A~- 7 TIME REf!Jm., fflT~.~~.$oEf!ff~*rJgEffl~: ~~~A~~tB~~ fBJ/fiI.A, ~JtJABOOTMODEi£A VIDMODE. X1T~jgz;b~:¥-:IjjTi1 N, ~~E1z;/J~~$\"M1/8 8 TON 7f~~$~I~om-~~m~.~.~~roN~*~.7f~~$ ~~ JW ~ 1ft ffF 9 CCV 10 CCI II REF 12 FB 13 GNDS 14 CSP2 15 CSN2 16 CSNI 17 CSPI -164- Scanned by CamScanner

m•I .:. IIWM 1t!fl8:t1.iWl hown Scanned by CamScanner

QfBSLELB ~ MlIl1ll l a V e r y low currenl (I-phase skip) 1 1 Low currenl (approximately 3A)(I-phase skJp) a a Inlermed'a'e power polenlie' (1-phase PWM) a 1 Max power palenlia' (2- or l-pha.e PWM as canligured al CSP2) Figure 9-54 the screenshot of the original of the combination of DPRSLRVR and RSI# setting in the information of MAX8770 chip ~ DPRSLPVR :J3liii, pSI#:J3f~B1, ;r;JtI ff~:rt:J3 ~¥!rE~P1tIJ', I ~B~~J]ik{rf 0 When DPRSLPVR is high.PSI# is low.the chip working mode is that the current is very small,the 1 phase jump pulse. ~ DPRSLPVR :J37lIi, pSI#:J3liiiB1, ;r;Jt I ff1£ 3A IJ' ~¥!rEf~:rt, 1 ;f1]~~Jlik{rf 0 When DPRSLPVR is high,PSI# is high,the chip works in the 3A small current mode,the I phase jump pulse. ~DPRSLPVR:J3f~, pSI#:J3f~B1, ;r;JtI1f1£ I ;f1]PWMm:rt. ~im:~,*o When DPRSLPVR is low,PSI# is low,the chip works in the PWM mode of I phase,the current is moderate. ~ DPRSLPVR :J31lk, PSI#13~II1, ;c';JtI1f1£r~UB PWM m:rt, ~:kEl!¥!rE~~tI:I0 When DPRSLPVR is low,PSJ# is high,the chip works in the PWM mode of the full phase,the maximum current output. ctllif*3P: IC ~~lI1ti• •tI:i~Bi:1!:a12iJlJOVP fff,i1Eo ~~~tI:I~lli~T~Jru VID xtJ.iiZ !fritrtl:l£t!.lli-aI 300mV 111 (~m, .%111 9-55), ~1£Jlijci1PriiJl!lm:rtr (DPRSLPVR :J3~) ~ T J.8V 81. IC J€3z;JJ OVP 1*!Po ~:tE~;f1]tbtr (DPRSLPVR :J31lk PSI#:J3~) f.&m~~U OVP 111. IC :fl:l'!p:m- DLl .. DL21iLjij\", DBl .. DB2~fI£. ~~1!~r'lf~z;JJfi1i-'% r!i~bt:J3 100%, r~ili~m~~tI:I~~,1!m.tI:i~m The over-voltage protection:IC will ut voltage meets the OVP standard or not in real.When the output voltage is hi of the output voltage current VID corresponding 300mV(the typical vaJue;' or is higher than 1.8V in the pulse interval mode,IC starts OVP proteclion. Ultiphase mode(DPRSLPVR is low and PSI# is high) IC pulls DLl uDs DH I and DH2 low.lt makes the down tube driving sigijlil 's emptying the output capacitor rapidly,the using output vol Figure 9-55 -166- Scanned by CamScanner

threshold value in MAX8770 data manual . ~.I±lJt~f~T VID M@~~:±lEt:!.J.Im 400mV n1 C:9tr-lli!ffi, ~OO 9-56), IC I\\t.N 1J't~#-li\"'Mc~'t1li~, lL~~~:±l Et:!.J.Ifl1~ OV 0 IC lItD14H~HllutL~ DLI , 1 DH2o:l4f SHDN#Jtffit1:ttLE,lt~~ VCC Et:!.&tLfl1~ O.5V ~ r ~1f=j~it~J~~.!Ji Co er- oltage protection:when the output voltage is less than the output voltage value Cal value,is shown in figure 9-56) that VlD corresponding to,IC starts SHUTDOWN and sets the fault latch until the output voltage as low as OV.At this time,IC will be . mDLI and DL2,and pull DHI and DH2 low.Pull the SHDN# voltage clamp or down to less than 0.5V to clear the fault latch,and re-activate Ie. Vwp Measured at FB with respect to unloaded -450 ·400 -350 mV output voltage 10 tuvP FB farcad 25mV balow trip threshold the screenshot ofthe description ofthe electrical features of the over-voltage CONDlTION8 MIN TYP MAX UNITS 4.5 5.5 V nshot ofthe description ofthe electrical features ofvee pin and VOD pin threshold value in the MAX8770 data manual '\" ffiJ MAX8770 1¥J ~. ffi %IiJJ {l1¥J El! '=i: ~ tt 11 ~ .l~J, SOON, ~itiJt.lf <JI:*m:), VIDO~VID6, PSI, DPRSTP i1iii O.67V 75JiWi 0;) V ;1gfl£~SP: <lI*m:). -'58 is the screenshot ofthe description ofthe electrical features ofthe key 8770,SOON and DPRSLPVR are the high level(the maximum 2.3V:VIDO'-'- VID6, PSI and DPRSTP are the high level(the ~er ~ 0.67Y.are the low level (the maximum value) when its less 1.2 17 2.3 V 13 V Scanned by CamScanner

Figure 9-58 the screenshot of the description of the electrical features of the key signal threshold value in the MAX8770 data manual IMVP-6 ~W:I¥J VID ~ffiM~~~ 9-120 VID voltage corresponding of IMVP-6 specification is shown in table 9-12. ~f1lJ: ~ D6-DO m19f~~-;:P:Dt, ~te~ffi19 I.5000V; ~ D619f~~-;:P:, D5-DO ~~ ~-;:P:Il-L ~\"tr:±llt!ffi190.7125V; ~ D6-DO ~19~~-;:P:Dt, ~\"trte ~ffi~ OVo For example:when D6-DO are the low level,the output voltage is 1.5000V;when D6 is the low level,D5-DO are the high level,the output voltage is 0.7125V;when D6-DO are the high level.the output voltage is OV. Table 9-12 the table 1 ofVID corresponding of IMVP-6 ~te 06 D5 D4 D3 02 Dl DO It!ffi D6 D5 D4 03 D2 DI DO (V) o 0 0 0 0 0 0 1.5o00 o o o o o o 0.700 o o0 0 0 0 0 1 1.~87 1 0 0 0 0 0 1 0.687 5 o 0 0 0 0 1 0 1.~75 1 0 0 0 0 o 0.675 o o 0 0 0 0 1 1 1.46 ooo 0.662 5 5 o 0 0 0 1 0 0 1.4o50 1 o o 0.650 o 0 0 0 1 0 1 1.43~ o 1o 0.637 5 o 0 001 1 0 1 o 0.625 o o0 0 0 1 1 1 0.612 5 o0 0 o C1 0.600 o o0 0 o0 0.587 00010 5 75 00010 o0 0 1 o0 0 1 -168- Scanned by CamScanner

M9!.\"1 PWM Ef!fmll'lifiW 5 5 1 0 1.325 00 0.525 0 00 1 11 1.312 00 0.512 5 5 0 0 0 1.300 0 0000 0.500 0 0 000 1.287 0 000 0.487 5 5 0 1 0 1.275 0 00 0.475 00 0 0 1 1.262 0 00 0.462 5 5 0 1 0 0 1.250 0 0 0 0 0.450 0 0 0 1 0 1 1.237 0 0 0 0.437 5 5 1 0 1.225 0 0 0 0.425 0 0 1 1 1 1.212 0 0 0.412 5 5 1 0 0 0 1.200 1 0 0 0 0 0.400 0 0 00 1.187 0 00 0.387 5 5 0 1 0 1.175 0 0 0 0.375 0 0 0 1 1.162 01 0 0.362 5 5 1 0 0 1.150 1 0 0 0 0.350 0 0 0 1 1.137 0 1 0 0.337 5 5 1 0 1.125 0 1 1 0 0.325 0 0 1 1 1.112 0 1 1 1 1 1 0.312 5 5 0 1.100 1 1 0 0 0 0 0 0.300 0 0 1.087 1 1 0 0 0 0 1 0.287 5 5 1.075 1 1 0 0 0 1 0 0.275 0 0 .062 0 1 0.262 5 o-aso 0 Scanned by CamScanner

~ ~iCjM!Ifj!l.'1\\l'i!$Jl 0 00 0 1.025 00 0 0.225 0 0 0 00 1.012 00 0.212 5 5 0 0 0 0 0 1.000 0 0 0 0 0.200 0 0 0 0 00 0.987 0 00 0.187 5 5 0 0 0 0 0.975 0 0 0 0.175 0 0 000 0.962 00 0.162 5 5 00 0 0 0.950 0 0 0 0.150 0 0 00 0 0.937 0 0 0.137 5 5 00 0 0.925 0 0 0.125 0 0 00 0.912 0 0.112 5 5 0 0 0 0 0 0.900 0 0 0 0 0.100 0 0 0 0 0 0 1 0.887 1 1 000 0.087 S 5 0 0 0 1 0 O.8i1 1 00 0 0.075 0 0 0011 10 0 0.062 0 0 100 5 0 0 0 0.050 0 0 0 10 1 10 0.037 5 ~~ 06 05 04 03 02 01 ~tI:l DO et!JI ( V) 0 10 11 0.025 0 01 0 0.012 5 00 :0 00 01 0 11 -170- Scanned by CamScanner

Mg~ pWMll!fmMM 1 0 0 0.750 0 0 0 0 0 0 0 0 1 0 1 0.737 1 0 5 1 1 0 0.725 0 1 1 1 0.712 5 sm Et!M&:fm1ll9-59 m~, lIlJ:j:Jtff-:±lJ JL1-~~I 1\"F~1tj:: on circuit of MAX8770 is shown in figure 9-59,several key working conditions figure: 5V~) fAL/!.ffiA ] . . . . . . - - - - - - - . -.........- - _ _ o l SUPPlY ~~II 1GIl 112 lJIQ Vee VII) INPUT V,. BV 10 2'\" C2 -I'IWIISO AlB 2IIIIln 22jIF~ m RION Ill2 III 8ST1 --{(!VI.-:) III RCS1 D1 IJII1 U lm1l 112 IX1 Al2 lIS 1Il1O 04 11.1 e11 IIli 2.2Jf III PlIIII1 lIID II!lI iiii!ft; CSP1 IJI'IISIJ'\\IR 'C&II1 iii ~.p II _C7 AIIlIl a:~ r:tN lIl3 AUXlAII III 1lAll87lD IIf IWlAJlIlI8lTmI CCI 1IIIE 1512 ..-_.~GIIl IJll2 u Ill2 ...112 Scanned by CamScanner

Figure 9-59 the typical application figure of MAX8770 CLKEN#~ PWRGD ~)~I±l CLKEN# and PWRGD output VID ~A VID input 7ffa (§\" -% the opening signal {,It Eg~A the power supply input CPU 1~ Eg~\"tr I±l CPU power supply output MAX8770 fa Z;I]~O ~ l:fl lltff ~O 00 9-60 JiJf7j: • The timing sequence of MAX8770 starting and closing is shown in figure 9-60. Vcc~ VIO (OD 06) '--=~.= . 1/8lliS~~~t~ ~;-ii -~<,:-i~------;'----i-j~ ::Vco~ ~~ SOFT-SHUTDOWN = (fl:1<fiJ, '1<fiJiU: 118111 SLEW RATE SET )l]T IIEI!IJtl!.ffilll: :'-./~: BYRn!\"E ii::1El'1l$1Y-J1/8) PlVM ~~R~~ tXX><XixxXXxj'FORCED PWM:!:: (§ltPli.o:!:: FORCED PWM (j;!1b1l~ j •••• (rJ.&-f,PWIlI1lM> jPHASEGO ------;----:--...:....:.~:1f---__!. .- - - - - : - - + - - - + - - - •0 o• CLKcN ~ -- :. ._ _~--i-i L - . - - - - ~ . ...:.. ..:\" -~-'--- ­ PWRGO __..:...o__'~i----; _ _- '&.- :...I--..;...:--:-_~~..,:,. t... OOpsTYP: - .. :- : : : 5nTYP I2al.wJcps1YP~ :: : tlllNl( : ~ 2lJpsTYP Figure 9-60 CD 1tf:Jt;C;Jt~¥U~It!., pg$~J:tJt OL Firstthe chip gets the power supply,the • ® ~J§5'r$~*~It!..sy:~7fJilm~ Then.the external sends the high level 0 ® VCORE :Jt~i1i9J~-~EI!.BiJlrl - ), ~!iHM PWM m~. VCORE soft starts to a certain v.o resistance setting the slew rate),forcecl @ ;C;Jt7f~M~ CPU i!*tB The chip starts to decode VID $i @ VCORE i1i9J¥tl VID li -172- Scanned by CamScanner

corresponding voltage set by VlD. ~.s, ~1l1601JS .l.f~ CLKEN#o being nonnal,delays 60lls to set CLKEN# low. ~ VID \\[email protected], ~R1 5ms B~ PWRGD (MAX8770 &~ ~ply achieving the voltage set by VlD,delays 5ms to set PWRGD PHASEGD signal). ~~. be low level. #, PWRGD i:$~737C~:I7C~, PWM t!l(j:s!iHM PWM ~~~, VID aIid PWRGD are turned into the invalid state,PWM restores the forced aecoding. CLKEN#-&~:l9f~ 1t.>jZ 7, ;tJt ItFfIt7 0 CLKEN# also changes to be low level,the chip is outage. IMVP-6 ;l;im;1¥J CPU -mJt;tJt t ;It.±:~% R~O-\"f 0 'Vier supply chip confonned the IMVP-6 specification.its main features , ~~=~-mJtt liJtIU~; . el voltage regulator,supports for three-phase power supplY,ls Scanned by CamScanner

o _ _ _ ,,_ _.. \" \" . .140113111)1113711311135. ':WI 1)3_ .32. '31' PGD_IN ~] GNDPAD ~~ VIDZ R8tAS ~] (BOTTOM) VR...nl ~] ~~ \\#lin €:NTC €] [€. VIDO SOFT [~ PWM1 r~ PWMZ [~ PWM3 ocsn €] - - - - _...I [2! FCCM VW €] [~ tsEN1 !;COMP r~ lIEH2 '!:FB _\" .. _ ~~ I8£N3 .. _ .... _, .. _ .... _ .... _ .... - .. rOo'\" .. _ .......... r .... '111112' '13- \".1 1151 '11' '17' '1111'\" 120 1 009-61 ISL6260 51}J1;JJ~~ (]9Hml~j) Figure 9-61 the pin name ofISL6260(the top view) ISL6260 51}J1;JJJ:E50\\!.~ 9-13. The pin definition ofISL6260 is shown in table 9-13 . • 9-13 ISL6260 ~IJP;E:)( Table 9-13 the pin definition of ISL6260 ] .low load current input indication,is effective in the low leveI.ISL6260 can be used to close the PWM2 2.the high level input means that VCCP ana vce,- precondition ofCLK_EN# and PGOOD sent by IS ! 3.through 147k.... bias resistance connect the grQ 4.over-heat indication output,is effective in the 10 I o.the feedback pin,which is -174- Scanned by CamScanner

differential amplifier iitQliIR~aid 0 the internal attenuation ampIifier ~y~qmput end of the internal attenuation amplifier li'.iJliP\\lUJ:1CI ofthe output voltage detection Dooduction mode enable pin(forced PWM mode) of the driver chip Scanned by CamScanner

.., ISL6260 tstili CLK EN#.fQ PGOOD (fliWfJHjH~ ..> RalAS imii 147k•..{;11 E\\! ~lHt±l!!. . ii:Q:: ~ $~ i1t E\\!mt 4 VR IT# ii1t.':m7J'~~ ill, 1~ E\\!3fff%c 5 NTC ~~:6U1ftUt~~~~ffAE\\!~.I3., 1\"1\"79 VR IT#E\\!w.!-tW:$t )lii-*9!E\\!~ii:Q::.*B~ E\\!lli~:f*i!$ (lli~$, 1~s B1fB]lI! 6 SOFT E\\!lli*.(fl~&, • •~.E\\!lli~.~*~• •m.B1~, .~ im7ltff VIs. V/ms.fQ V/~ =#) 7 OCSET ii¥RE1i~~AJjt;p 8 VW iiiiE\\!~.l3.j!~COMP ~:Q::7f~~$ 9 COMP ~~*H~, j!~I*J$~~$:*~B~tu~illjlfij 10 FB .l~:i1tJJt4J, j!~I*J$~~$:*~B~&ffitu\"trAylfij 11 VDIFF ~:$t$:*~~!ilitrillYlfij 12 VSEN E\\!lli~j!d, jEjifij 13 RTN E\\!lli~~d, ~9jtij • • •14 DROOP ~$.~jj$(*.\"tI:l~ 15 DFB ~ ~jj$(* .&ffi~A~ 16 VO • ili E\\!lli~JU*A~ 17 VSUM .~E\\!.~. IJ!Il ~~ 1ft 18 VIN 19 VSS 20 VDD 21 (SEN3 22 ISEN2 23 (SEN( 24 FCCM 25 PWM3 26 PWM2 27 PWMI 28~ VlDO~ 34 VID6 35 VR ON 36 DPRSLPV R 37 DPRSTP# 38 CLK_EN# 39 3V3 40 PGOOD -176- Scanned by CamScanner

frrI L6260 (J(J Jl.1' til ffi ;7 IlIJ 11:1 (I~ Il!/ {~,'f't1JNii£: 1;;1 )( OX I~I ~III~I 9-62 7ft I VR_ON, epRSLPVR, PGDJN J:3HIH:iJilili~uJ\\J~ 2.3V, n~7:i1!'~lflM)'J~ IV; VfDO-VJD6, psJ#, DPRSTP#-.C3HfHiJ-{ti IJ t-J 0.7V, F~~~1AI~liJlfUIl[j-J~ O.JV 0 'The original screenshot of the description of the electrical features of several key signals threShold value ofISL6260 is shown in figure 9-62.the minimum of the rising edge threshold value ofVR_ON DPRSLPVR and PGD_lN is 2.3V,the maximum of the falling edge threshold value is lv·the minimum of the rising edge threshold value of VIDO-VJD6,PSJ# and DPRSTP# is O.7V,the UIIIIC_maximum ofthe falling edge threshold value is O.3V. _La !\\/R.CH _ _ \"'PGO .. Vl.U3Vl 10 V =- . . .-.... Yll,.ON .............. PGO .. v~SVI >, v YlU1 0\\I1 I 0] v 0' V IIlI'RITPI_ =- . . --1 V....I1M the original screenshot ofthe description of the electrical features of VR_ON and other key signals threshold value of ISL6260 \"'EliIII~3 }1f7J', ISL6260 ~ VID i:~ 0 JJ;f, VCC_CORE ~*%ljtJjEE!.).I 1.5V; VlD 7'.1 ~(iLC0RE.-f:I:l O.3V, ~ VID i:~ 1 l!'t, VCC_CORE 1ij1j tJj OV 0 ~Mb'tiJ·p·:figure 9-63,when all VID of ISL6260 are OV,the maximum of the output voltage is l.SB;Wb.en MD is llOOOOO,the output voltage of VCC_CORE is 0.3 V,when all £0 O\\JlP. O~ 1.soo v 0.300 v 0.0 v SCreenshot ofthe decoding range of ISL6260VID II 9-064 I$L6260 ~ PGOOD ~ _ *~.blll Scanned by CamScanner

power supply of 3V3,then it will send CLK_EN#.So,no PGD_IN will not cause no CPU POWer supply it will only cause no output ofPGOOD,no 3V3 will not cause PGOOD does not output,it will only cause CLK_EN# does not output low level. The simplified application diagram and the key pin of ISL6260 are shown in figure 9-65. Figure 9-64 the intemallogic figure ofPGOOD and CLK_EN# ofISL6260 m VDO YIN 3V3 m-~ll1:fi~ VIN RBIAS ~:±l Lo ISL6208 ?JR C PHASE lli4i1lJ:f1 0 [ VIDs J>VIO<O:6> C:LK_ _ -ISEN2 ISL6208 Lo TCo OPRSTP# = VR..OH PHASE OPRSLPVR -PGOOO fi\\ 1111: 1\"11 'Ii\" MCHOK RlN fJH\\J;~~ CLK_ENABLE# VDIFF ( JfJr~ J==':VMVRP~OPNWRGO Fa - COIIP Remote Clc\\:1I0!T Sense .J YW alCPU CORE GHD DFB _ C, C, Figure 9-65 the simplified 8I?pli 11frUt~W!tl ~i1t1ilm~ -178- Scanned by CamScanner

Egfff'J:W!IJ the voltage detection .~Jt:±fJt rl!. the chip main power supply eLK EN#.~fJtEg CLK_EN# module power supply .-*tI1i~mtl:l the first phase of square wave output OO:i;b~JtfJt~ driver chip power supply Egim¥,q:~~tl the current detection PGOOD (J{J~f!f the condition of PGOOD the second phase of square wave output the current detection the third phase of square wave output the current detection the total current detection soft start Scanned by CamScanner

The chip decodes VID,drives VCORE to the voltage set by VID according to 1MVP-6 standard,the starting speed is lOmV/I!S. ® 7ms J§, ~Jt~tI:l PGOOD. 7ms later,the chip outputs PGOOD. Figure 9-66 the starting timing sequence figure ofISL6260 The set voltage Analysis of commonly used chip ISL9583I by HM65 motherboard ISL95831 ~-1'x~ 3;ffi CPU ~,c.,.gtlt~ I ;ffi.JiX;~-F.gtItB9rt*tlB, :±~mT Intel 8~ HM6x LHLt-f-Ei, ~.g. IMVP-7/VRI2 ~m:, TQFN ~~, 48 JJ!IJ. 1t:±J!%' }~ ~D -r- • ISL95831 is the controller supported three phase CPU core power supply and 1 phase integrated graphics power supply,is mainly used for HM6x and above platform of Intel,in compliance with the IMVP-7/VRI2 specification,is TQFN packaged,48 pin.The main features are as follow. • x~~~ill: ~-~ltlli~~~~reI~3;ffi,2ffi,.;ffi;~=~~lli~~Bx~ ~;ffi!ill\" ill • Support dual outputthe first path of the voltage regulator can be configured as 3 phase,2 phase and single phase;the second path of the voltage regulator supports a single phase output. • W3l~MtIliill;Jt$ SVID ~*tl. Two path of output shared SVID control. • ~~'=:1'~Z;JJ~Jt (~-~W31', ~=~-1'). Integrated three driver chips(the first path has two,the second path has one). • x~ ~1'P~~:I: 1t7jfUI~1i7*. Support a kinds of methods of current measurement. • xM'i:1:~, Mmtf*1r'. -180- Scanned by CamScanner

1119-67 ISL95831 iJl )J!lJ~f* (JYlt~l¥J) tgure 9'-67 the pin name of ISL95831 (the top vie\\\\) 9-14. ~~tC!lh9.S831 is shown in table 9-14. ~!SbiIDCeto set the switching frequenc) of thl: \\ ollage !J!cC~ent of the voltage regulator::! form· a certain that the oltag regulator 2 has nomlal.The ~Ansgetnont cbjp .aI VlD bu has nonnal.The Scanned by CamScanner

temperature of the voltage regulator I 12.connects this pin to COMP through a resistance to set the switching frequency of the voltage regulator I(8k 0 resistance is about 300kHz) 13.the output end of the error amplifier of the first path of the voltage regulation 14.the inverting input end of the error amplifier ofthe voltage regulator 1 IS.when the voltage regulator 1 is configured as a 3 phase,is used to detect the current of the third phase. When its configured as 2 phase,the internal connects the switch of FB2 and FB,is used to adjust the precision of the compensation voltage regulator I.When its configured as 1 phase.the switch is invalid 16.the second phase current detection of the voltage regulator 1 17.the first phase current detection of the voltage regulator 1 18.the input end of the voltage detection of the voltage regulator 1 19.the loop end of the voltage detection of the voltage regulator 1 20.21.the input pin of the droop current detection of the first path of regulator 22.SV power supply 23.the power supply 2S.the first phase boot-strap pin ofthe voltage regqt pin oftbe first phase 26.the first phase of the top tube drive signal ofth 27.the first phase of the top tube driver loop oftb tube,the D pole of the down tube and the outputind 28.the first phase of the down tube driver loop 0 the down tube 29.the first phase of the down tube drive signal 30.the third phase of the square wave 0 5V,disable the third phase 31.the power supply of the capacitors 32.the second phase of the down tube • -182- Scanned by CamScanner

11hi~ond phase of the down tube driver loop of the voltage regulator I,connects to the pole of tube Bttlie second phase of the top tube driver loop of the voltage regulator J.connects the S pole of the toP1Ube,the D pole ofthe down tube and the output inductance 35.tlte second phase ofthe top tube drive signal of the voltage regulator 1 36.tbe second phase of the boot-strap pin of the voltage regulator 1.Connects the PAHSE pin of the Second phase through a capacitor 31:tbe down tube drive signal of the voltage regulator 2 ~ tube driver loop of the voltage regulator 2,connects the S pole of the top tube.the D pole ~and the output inductance . e signal ofthe voltage regulator 2 pin ofthe voltage regulator 2.Connects the PHASEG pin through a capacitor Scanned by CamScanner