Laptop Repair Part 1 OCR

+<lVSUSO ~ 15 ~ ~Ml Ka2.JR (HM5x) lM~fl fi PR/lli03 l()(1(Otrn PR851l2 Figure 15-35 the production circuit ofSY TE l_P\\\\'RGD WRGO ~£j1 PR8301 i!r'& RT8202 (PU8301) , ~~tl~ ttl. TT_CP , 1115-36 PJT~o ~lIr:~iE'ffi J§, ;L:;;Jt~tI:J-YTT_CPU_PWRGD. GO through PR830 I send to RT8202(PU830 I).control outpUts is shown in figure 15-36.After the voltage production being nonnal.the WRGD. ~1t!~iI. PR865L PR8652 ?tffJ§, F~ H_ TTP\\\\ RGD J!~ CPU_PWRGD j1 eE!. ~ PL8650 £.g 7g ALL_SYSTEt-.l the resistance PR865 1 and PR865_ panial e.pu is shown in figure 15-37.- TT_CPU_PWRGD _SYSTEM_PWRGD to EC. Scanned by CamScanner

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Figure 15-36 the production circuit ofVTT_CPU.VTT_PCH +3VS 1.IK~I~1 ~VTTl'WRGD iE CPU PRllllS2 PRll8!:oO +Yn CPU PWIlCID c:>--24_9Q+hm2!!!lli'L.2~-v--L~~--C::>H ~ x ECPUl650 L - - _.........,,0--2----.----'1..-....::> AU._sYSTE\"]WRGD Figure t5-37 the differentiation circuit of+VTI_CPU]WRGD ~~tl+VTT_CPU *0 H_VTTPWRGD J§ ~tIJ GFX_VRON JJz GFX_VlD .3?: RT8152 ) , 7fJi5J*J.I.~-FB~~{J'ItJ.I+VGFX_COR£' ~OI!l15-38 PJT~o e!'U receiving +VTT_CPU and H_VTTPWRGD,sends GFX_VRON and GFX_VlD to 201A),opens the core voltage of the built-in graphics cards +VGFX_CORE,is shawn 8. Scanned by CamScanner

]WRGD being sent to EC,EC delays 99ms send CPU core voltage open signal is sent to VRON pin of RT8856(PU880 IA),is used to open CPU VCORE.After +YCORE production being normal.the chip outputs _EN#,is shown in figure 15-39. \"..... ... f*~ffl T 3:J& Ag'lzffi f~Hf' r:g~~ , JI: VRM PWRGD ff:@:-jj!~.Af~1t lA .1t. EC JXtlJAg 3.3V (Ig , f.J 2.6s J§ PQ860 IB A~ G F#. -tl?fJt~ijt. 2.6 J§, ~. lit It ~ ~t'- 4U:fL 1[1 ;Eg EC_RST#ii!lu O~Fg Scanned by CamScanner

FORCE_OFF# 10w.That is to say.after 2.6s.if ALL_SYSTEM_PWRGD and VRM_PWRGD have not turned into the high level,this circuit will pull FORCE_OFF# low,then pull EC_RST# 10W,to realize mandatory outages.(FORCE_OFF# and EC_RST# connect together through 0... resistance shown in the part ofEC reset circuit in 15.1 section.) . . -11KOHW I'UII9I (JO) --L....-------lJ,;.\"''--'--..----1:=>AU,..SYSIBU'WllOO \"\"'\" -..r- c:::::o_L ----'--!4J--\"-i--T--z \"T..... ~l~ PTIIIlO1 It-t, G f.&7Crm...t*~~ 3.3V, llt:l:h~;:m:rgB<:I G *&I~{i~ I:I:iJiiillt!)§ Is $JlJt4i'~E[:!\" )jJt:f&JJtE[:!,~%ijz:o MHlint ~8601, m~ PQ8601, m~~ PD8603 ~-=.f-W:~PiiIfJT It!~~~e.pPJ 0 If the switch,the G pole does not need to rise to tu is about 1.2V.So,ASUS motherboard will by this circuit.During repairing,we can circuit PC860 I,dismantling PQ8601 gradually to trace each power Scanned by CamScanner

........ 0602 ~~J$OOtli +VGA_VCORE oruit of tile core power supply the independent graphics cards !lltJ Q7601 ~Jm, it R7603 MUIh. Q7602 B~ G t1kf~~IJ 1:.+3VSG, ~[]OO 15-42 JiJT5F. iRE_EN controls Q7601 conducted.makes R7603 low level after +3 VS partial pressure.Q7602 is Scanned by CamScanner

~ljH~IC.'iJtl:lUE1i~0 PU8201 ltW(l~ YGA_YCORE]WRGD ~£ UP7706 (PU8403A) 7fJa+1VS, :!lnl~ 15-43 lfriF. After the core power supply of the independent graphics being nonna!.PU820 I send GA VCORE_PWRGD to UP7706(PU8403A) to open + I VS.is shown in figure 15-43 . • 1 10 .-.....' ~ 15-43 +IVS f=~F.€!.~ Figure 15-43 the production circuit or +IVS ~ ~ ~ PQ8560. ~ it!f!t:t~ ~ *IJ +O.75YSG , + l .5YSG, sent to PQ8560.by conversing to control Scanned by CamScanner

~~~~~\".5VSG~\"\" '--__~~.z...,,'V'3V2lllJKQwn-..L-~'~ ~~ (O.79A/O.056A) -, PRJ!S63 1I10K0l1\", +12VS send to Scanned by CamScanner

PARK_PECLK_REQMit PCI--(' iu*fttJj~ Fn1 100MHz }:;':,~~Mt.II'. ~nl*115-46 (if/Fc VGA-VCORE- PWRGD is sent to Q7504 at the same time.makes it conducted.and produc~ the 10 level of PARK)PECLK_REQ# to PCI J,requests to send 100M Hz bus clock of the graphics cards is shown in figure 15-46. N/II 1.1 VS]WRGD OOhm @ GND the production figure of the graphics cards clock request signal CLK_EN#~2i1 CQ2 &*F:lMr'&J E\\!-fBj 27) ffJBAt~c 6 chip outputs CLK_EN# through 15-47.This signal is sent to the Scanned by CamScanner

r the clock IC opening work,producing each clock to PCH,then produced each clock by Jock to the peripheral.The block diagram of pel-] built-in clock is shown in figure 15- .. PClc'\" loe M err-n J rCI loopbac.k chip outputs VRM PWRGD to Scanned by CamScanner

J.jgun: 15-50 PM PWROK renamed to be PM_PWROK]ClI PM_PWROK_PCII ~~ PCII n~ MEPWROK, SYS_PWROK PWROK J]/;Il, .t!oOO 15-51 mm PM_PWROK]CH is sent to MEPWROK.SYS]WROK and PWROK pin of PCH.is shown in figure 15-51. PIA PWROK PCH _ _:!:::ROK _ _-----'W--. toAEPWROK 00 15-51 PCII ~UO-=l' PG Figure 15-51 PCl-! received three PG auc!lJ PWROK j§, ~tl1 DRAMPWROK f*Ji%~ CPU; 1:£ PCH i*Ji\\il, PWROK lJ. 0K i!:.~.!:j, 1'= 1:: PROCPWRGD ~ CPU. PCH ;& tl1 PLTRST#, £ ~ 7:J 0318 R0319 irlliP.lt 1.\\ V ~ CPU. 00 15-52 TJ CPU D~ PG :fD~fiI~ OK,sends DRAMPWROK signal to CPU;in the PCH OK Jogie,to produce PROCPWRGD to CPU .PCH sends through R03I 8,R03 19 partial pressure to be 1.1 V to wn in figure 15-52. Scanned by CamScanner