Eletro-X_VEGAS TURIS SKL-KBL (15341-1 91N85)

5 43 D C Vegas Sc B SKL/KB 2016/06 REV : A Elet DY : None Installed UMA: UMA only installed A OPS: DISCRTE OPTIMUS inst 543

32 1 D chematic C B BL-U 6/27 A00 tro-X <Core Design> Wistron Corporation A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. talled Title 3 Cover Page Size Document Number Rev A4 Vegas SKL/KBL-U A00 Date: Monday, June 27, 2016 Sheet 1 of 105 21

5 43 Project code:4PD09P010001 Vegas SKL-U/KBL-U PCB P/N: 15341-SD Revision: A00 2GB = 256b x 16 x 4pcs D VRAM(DDR3L) *4 GDDR5 GPU PCIE x 4 Intel CPU 2GB(256Mbx16) AMD Skylake-U 2+3e 78,79 R16M-M1-20 Kabylake-U 2+3e VE DIS only 25W 15W (UMA&DIS) 28W (UMA) 73,74,75,76,77 14\"/15\" LCD eDP x2 SKL PCH-LP KBL PCH-LP 55 Touch Panel USB2.0 x1 10 USB 2.0/1.1 ports 6 USB 3.0 ports High Definition Audio Camera USB2.0 x1 3 SATA ports C Digital MIC 6 PCIE ports LPC I/F ACPI 5.0 LAN 10/100 TURIS only REALTEK RTL8106G RJ45 Conn. PCIE x1 32 LAN 10/100/1000 REALTEK RTL8111G 31 VEGAS only HDMI V1.4a DDI1 57 VGA Conn. DP/VGA Converter DDI2 Elet 56 REALTEK RTD2166 VEGAS only 56 Left side USB2.0 x1 USB3.0 x1 USB1(USB3.0) B 36 Left side USB2.0 x1 USB3.0 x1 USB2(USB3.0) 36 2CH SPEAKER Audio Codec HDA (2CH 2W/4ohm) ALC3246 USB2.0 x1 29 27 USB2.0 x1 Universal Jack MIC_IN/GND HP_R/L A USB3(USB2.0) SD Card Slot CardReader Realtek RTS5170 IO Board 4 3 5

2 1 44 45 Block Diagram CHARGER DDR4 1866/2133MHz Channel A ISL88739 EGAS only INPUTS OUTPUTS DDR4 1866/2133MHz Channel B AD+ DCBATOUT BT+ SYSTEM DC/DC TPS51225RUKR-GP INPUTS OUTPUTS 3D3V_PWR 3D3V_S5 D DCBATOUT 5V_PWR 5V_S5 DDR4 1866 CPU Core Power SODIMM A NCP81208MNTXG 46~50 12 33 DDR4 1866 NCP81382MNTXG x 2 SODIMM B 12 NCP81382MNTXG (23e) NCP81253MNTBG INPUTS OUTPUTS DCBATOUT VCC_CORE DCBATOUT +VCCGT DCBATOUT +VCCGT (23e) DCBATOUT+VCCSA DDR4 SUS USB2.0 x1 FRINGERPRINT RT8231AGQW-GP 51 PCIE x1 CRW-CP-GHC-F1 USB2.0 x1 APL5930KAI-TRG SATA (Gen3) x1 92 INPUTS OUTPUTS SATA (Gen1) x1 VEGAS only DCBATOUT 1D2V_S3 LPC BUS 3D3V_S5 0D6V_S0 2D5V_S3 C NGFF WLAN CPU VCCPRIM_CORE 1V 802.11a/b/g/n BT V4.0 combo 11 61 INPUTS OUTPUTS 1D0V_S5 +VCCPRIM_CORE tro-X HDD CPU DCDC-V1D00A 60 AOZ2262QI-10-GP-U 53 INPUTS OUTPUTS DCBATOUT 1D0V_S5 ODD LDO-V1D8V 60 APL5930KAI-TRG 54 EC VEGAS only INPUTS OUTPUTS SMSC MEC1404-NU-GP TPM 2.0 3D3V_S5 1D8V_S5 NPCT650JBAWX 5V/3V S0 91 TPS22966DPUR-GP 40 LPC debug port INPUTS OUTPUTS 68 5V_S5 5V_S0 B FAN Control 3D3V_S5 3D3V_S0 26 EOPIO/EDRAM (23e) 24 TPS22961DNYT 40 INPUTS OUTPUTS 1D0V_S5 +V_EDRAM_VR 1D0V_S5 +V_EOPIO_VR 3D3V VGA 86 AO3419L INPUTS OUTPUTS 3D3V_S0 3D3V_VGA_S0 SPI Flash ROM Int. KB VGA_CORE 16MB 65 ISL62771HRTZ-GP-U 85 25 INPUTS OUTPUTS 26 DCBATOUT VGA_CORE 1D5V_VGA_S0 86 PS2 Y8288RAC-GP 2 PrecisionTouch pad INPUTS OUTPUTS DCBATOUT 1D5V_VGA_S0 A I2C 65 <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Block Diagram Size Document Number Rev C Vegas SKL/KBL-U A00 Date: Tuesday, June 21, 2016 Sheet 2 of 105 1

5 Elet43 D (Blanking) C 43 B A 5

3 21 D ) C 3 tro-X B <Core Design> Wistron Corporation A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title (Reserved) Size Document Number SKL/KBL-U Rev A4 Vegas A00 Date: Thursday, June 16, 2016 Sheet 3 of 105 2 1

5 4 3 Main Func = CPU #544 #543016 Rev0.7: Ra = 500 ohm / Rb = 1k ohm +VCCST_CPU #544669 Rev0.52: Ra = 56 ohm (TO BE CHANGED TO 100 OHMS) / Rb = 62 ohm and 150 ohm 21 +VCCSTG 21+VCCSTG = 1.0 V R419 1KR2J-1-GP Elet R420 PCH_THERMTRIP 12 DYD [PECI] and [PROCHOT#] Rb R401 0R2J-2-GP Impedance control: 50 ohm 1KR2J-1-GP JTAG TP401 CPU1D P TPAD14-OP-GP D63 CATERR# SKYLAKE_ULT PR 1 H_CATERR# A54 C65 24 H_PECI 499R2F-2-GP 1 R403 2 H_PROCHOT#_R C63 PECI PCH_THERMTRIP A65 24,44,46 H_PROCHOT# 1SKTOCC# PROCHOT# C55 Ra 1XDP_BPM0 D55 THERMTRIP# 1XDP_BPM1 B54 TPAD14-OP-GP TP402 1XDP_BPM2 C56 SKTOCC# 1XDP_BPM3 TP405 CPU MISC TP406 TPAD14-OP-GP TP407 BPM#[0] TPAD14-OP-GP TP408 BPM#[1] TPAD14-OP-GP BPM#[2] TPAD14-OP-GP BPM#[3] TPAD14-OP-GP TP403 1 GPP_E3/CPU_GP0 A6 GPP_E3/CPU_GP0 PCH_ A7 GPP_E7/CPU_GP1 PCH 24,55 TOUCH_PANEL_INTR# TOUCHPAD_INTR# BA5 GPP_B3/CPU_GP2 1 GPP_B4/CPU_GP3 AY5 GPP_B4/CPU_GP3 PCH_ TPAD14-OP-GP TP404 PCH_ PROC_POPIRCOMP CPU_POPIRCOMP AT16 PCH_OPIRCOMP P OPCE_RCOMP 24,65 INT_TP# 1 R410 2 PCH_POPIRCOMP AU16 OPC_RCOMP 0R0402-PAD EDRAM_OPIO_RCOMP H66 EOPIO_RCOMP H65 SKYLAKE-U-GP C 071.SKYLA.000U 49D9R2F-GP 2 R412 1 CPU_POPIRCOMP R413 1 PCH_POPIRCOMP 2 49D9R2F-GP 49D9R2F-GP 2 R414 1 EDRAM_OPIO_RCOMP R415 1 EOPIO_RCOMP 2 49D9R2F-GP (#543016) PROCHOT# Routing Guidelines B A M1,2,3,4,5: <3 inches 5 M6: 1-11 inches MCPU: 0.3-1.5 inches Mt <0.3 mils Main route(M1+M2+M3+M4+M5+M6+MCPU 43

21 4669 CRB Rev0.52 +VCCSTG = 1.0 V +VCCSTG H_THERMTRIP# 40 D 4 OF 20 XDP_TMS 1 DY 2 XDP_TDI 51R2J-2-GP1 DY 2 R421 XDP_TDO_CPU 51R2J-2-GP DY R422 PCH_JTAG_TDI 1 PCH_JTAG_TDO 51R2J-2-GP 2 R423 PCH_JTAG_TMS PROC_TCK B61 XDP_TCLK XDP_TCK_JTAGX 1 DY 2 PROC_TDI D60 XDP_TDI 51R2J-2-GP R408 A61 XDP_TDO_CPU XDP_TRST# PROC_TDO C60 XDP_TMS XDP_TCLK 1 2 PROC_TMS B59 XDP_TRST# 100R2J-2-GP R409 ROC_TRST# PCH_JTAG_TCK B56 PCH_JTAG_TCK 1 2 _JTAG_TCK D59 PCH_JTAG_TDI 51R2J-2-GP R416 H_JTAG_TDI A56 PCH_JTAG_TDO _JTAG_TDO C59 PCH_JTAG_TMS 1 2 _JTAG_TMS C61 XDP_TRST# 1KR2J-1-GP R417 PCH_TRST# A59 XDP_TCK_JTAGX R402 1 DY 2 51R2J-2-GP JTAGX 2 51R2J-2-GP R406 1 2 51R2J-2-GP R407 1 DY XDP_TRST# C tro-X DY EC401 21 SC1KP50V2KX-1GP B U): 1-12 inches <Core Design> A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title CPU_(JTAG/CPU SIDE BAND) Size Document Number Rev A3 Vegas SKL/KBL-U A00 Date: Monday, June 27, 2016 Sheet 4 of 105 21

5 43 Main Func = CPU DDR4 ball type: Inter D CPU1B 2 OF 20 SKYLAKE_ULT 12 M_A_DQ0 M_A_DQ0 AL71 DDR0_DQ[0] DDR0_CKN[0] AU53 M_A_CLK#0 12 12 M 12 M_A_DQ1 M_A_DQ1 AL68 AT53 M_A_CLK0 12 12 M 12 M_A_DQ2 M_A_DQ2 AN68 DDR0_DQ[1] DDR0_CKP[0] AU55 M_A_CLK#1 12 12 M 12 M_A_DQ3 M_A_DQ3 AN69 AT55 M_A_CLK1 12 M 12 M_A_DQ4 M_A_DQ4 AL70 DDR0_DQ[2] DDR0_CKN[1] M_A_DQ[32:39]1122 M 12 M_A_DQ5 M_A_DQ5 AL69 BA56 M_A_CKE0 12 M M_A_DQ[0:7] 12 M_A_DQ6 M_A_DQ6 AN70 DDR0_DQ[3] DDR0_CKP[1] BB56 M_A_CKE1 12 12 M M_A_DQ[8:15] 12 M_A_DQ7 M_A_DQ7 AN71 AW56 12 M M_B_DQ[0:7] 12 M_A_DQ8 M_A_DQ8 AR70 DDR0_DQ[4] AY56 12 M M_B_DQ[8:15] 12 M_A_DQ9 M_A_DQ9 AR68 12 M M_A_DQ[16:23] 12 M_A_DQ10 M_A_DQ10 AU71 DDR0_DQ[5] DDR0_CKE[0] AU45 12 M M_A_DQ[24:31] 12 M_A_DQ11 M_A_DQ11 AU68 AU43 12 M M_B_DQ[16:23] 12 M_A_DQ12 M_A_DQ12 AR71 DDR0_DQ[6] DDR0_CKE[1] AT45 M M_B_DQ[24:31] 12 M_A_DQ13 M_A_DQ13 AR69 AT43 M_A_DQ[40:47]1122 M 12 M_A_DQ14 M_A_DQ14 AU70 DDR0_DQ[7] DDR0_CKE[2] M 12 M_A_DQ15 M_A_DQ15 AU69 BA51 12 M 13 M_B_DQ0 M_B_DQ0 AF65 DDR0_DQ[8] DDR0_CKE[3] BB54 12 M 13 M_B_DQ1 M_B_DQ1 AF64 BA52 12 M 13 M_B_DQ2 M_B_DQ2 AK65 DDR0_DQ[9] AY52 13 M 13 M_B_DQ3 M_B_DQ3 AK64 AW52 13 M 13 M_B_DQ4 M_B_DQ4 AF66 DDR0_DQ[10] DDR0_CS#[0] AY55 M_A_CS#0 12 13 M 13 M_B_DQ5 M_B_DQ5 AF67 AW54 13 M 13 M_B_DQ6 M_B_DQ6 AK67 DDR0_DQ[11] DDR0_CS#[1] BA54 M_A_CS#1 12 M 13 M_B_DQ7 M_B_DQ7 AK66 BA55 M_B_DQ[32:39]13 M 13 M_B_DQ8 M_B_DQ8 AF70 DDR0_DQ[12] DDR0_ODT[0] AY54 M_A_DIMA_ODT0 12 M 13 M_B_DQ9 M_B_DQ9 AF68 13 M 13 M_B_DQ10 M_B_DQ10 AH71 DDR0_DQ[13] DDR0_ODT[1] AU46 M_A_DIMA_ODT1 12 13 M 13 M_B_DQ11 M_B_DQ11 AH68 AU48 13 M 13 M_B_DQ12 M_B_DQ12 AF71 DDR0_DQ[14] AT46 M_A_A5 M_A_A5 12 13 M 13 M_B_DQ13 M_B_DQ13 AF69 AU50 M_A_A9 M_A_A9 12 13 M 13 M_B_DQ14 M_B_DQ14 AH70 DDR0_DQ[15] DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] AU52 M_A_A6 M_A_A6 12 13 M 13 M_B_DQ15 M_B_DQ15 AH69 AY51 M_A_A8 M_A_A8 12 13 M M_A_DQ16 BB65 DDR1_DQ[0]/DDR0_DQ[16D]DR0_DQ[16] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] AT48 M_A_A7 M_A_A7 12 12 M_A_DQ16 M_A_DQ17 AW65 AT50 M_B_DQ[40:47]13 M 12 M_A_DQ17 M_A_DQ18 AW63 DDR1_DQ[1]/DDR0_DQ[17D]DR0_DQ[17] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] BB50 M_A_A12 M_A_BG0 12 M 12 M_A_DQ18 M_A_DQ19 AY63 AY50 M_A_A11 M_A_A12 12 13 M 12 M_A_DQ19 M_A_DQ20 BA65 DDR1_DQ[2]/DDR0_DQ[18D] DR0_DQ[18] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] BA50 M_A_A11 12 13 M 12 M_A_DQ20 M_A_DQ21 AY65 BB52 M_A_A13 13 M 12 M_A_DQ21 M_A_DQ22 BA63 DDR1_DQ[3]/DDR0_DQ[19D] DR0_DQ[19] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] M_A_A15 M_A_ACT_N 12 M 12 M_A_DQ22 M_A_DQ23 BB63 AM70 M_A_A14 M_A_BG1 12 12 M 12 M_A_DQ23 M_A_DQ24 BA61 DDR1_DQ[4]/DDR0_DQ[20D] DR0_DQ[20] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] AM69 M_A_A16 12 M 12 M_A_DQ24 M_A_DQ25 AW61 AT69 M 12 M_A_DQ25 M_A_DQ26 BB59 DDR1_DQ[5]/DDR0_DQ[21D] DR0_DQ[21]DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] AT70 M_A_A2 M_A_DQ[48:55]1122 M 12 M_A_DQ26 M_A_DQ27 AW59 AH66 M 12 M_A_DQ27 M_A_DQ28 BB61 DDR1_DQ[6]/DDR0_DQ[22D] DR0_DQ[22]DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] AH65 M_A_A10 12 M 12 M_A_DQ28 M_A_DQ29 AY61 AG69 M_A_A1 12 M 12 M_A_DQ29 M_A_DQ30 BA59 DDR1_DQ[7]/DDR0_DQ[23D] DR0_DQ[23] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# AG70 M_A_A0 12 M 12 M_A_DQ30 M_A_DQ31 AY59 BA64 M_A_A3 12 M 12 M_A_DQ31 M_B_DQ16 AT66 DDR1_DQ[8]/DDR0_DQ[24] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] AY64 M_A_A4 12 M 13 M_B_DQ16 M_B_DQ17 AU66 AY60 12 M 13 M_B_DQ17 M_B_DQ18 AP65 DDR1_DQ[9]/DDR0_DQ[25] BA60 M_A_DQS_DN0 M_A_A13 12 M 13 M_B_DQ18 M_B_DQ19 AN65 AR66 M_A_DQS_DP0 M_A_A15 12 M_A_DQ[56:63]1122 M 13 M_B_DQ19 M_B_DQ20 AN66 DDR1_DQ[10]/DDR0_DQ[26] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] AR65 M_A_DQS_DN1 M_A_A14 12 M 13 M_B_DQ20 M_B_DQ21 AP66 AR61 M_A_DQS_DP1 M_A_A16 12 12 M 13 M_B_DQ21 M_B_DQ22 AT65 DDR1_DQ[11]/DDR0_DQ[27] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] AR60 M_B_DQS_DN0 12 M 13 M_B_DQ22 M_B_DQ23 AU65 M_B_DQS_DP0 M_A_BA0 12 12 M 13 M_B_DQ23 M_B_DQ24 AT61 DDR1_DQ[12]/DDR0_DQ[28] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] AW50 M_B_DQS_DN1 M_A_A2 12 12 M 13 M_B_DQ24 M_B_DQ25 AU61 AT52 M_B_DQS_DP1 13 M 13 M_B_DQ25 M_B_DQ26 AP60 DDR1_DQ[13]/DDR0_DQ[29] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] M_A_DQS_DN2 M_A_BA1 12 13 M 13 M_B_DQ26 M_B_DQ27 AN60 AY67 M_A_DQS_DP2 M_A_A10 12 13 M 13 M_B_DQ27 M_B_DQ28 AN61 DDR1_DQ[14]/DDR0_DQ[30] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] AY68 M_A_DQS_DN3 M_A_A1 12 M 13 M_B_DQ28 M_B_DQ29 AP61 BA67 M_A_DQS_DP3 M_B_DQ[48:55]13 M 13 M_B_DQ29 M_B_DQ30 AT60 DDR1_DQ[15]/DDR0_DQ[31] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] M_B_DQS_DN2 M_A_A0 12 M 13 M_B_DQ30 M_B_DQ31 AU60 AW67 M_B_DQS_DP2 M_A_A3 12 13 M 13 M_B_DQ31 DDR0_DQ[16]/DDR0_DQ[32] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] M_B_DQS_DN3 M_A_A4 12 13 M M_B_DQS_DP3 13 C DDR0_DQ[17]/DDR0_DQ[33] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] 13 SM_PGCNTL 13 DDR0_DQ[18]/DDR0_DQ[34] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] 13 DDR0_DQ[19]/DDR0_DQ[35] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] M_B_DQ[56:63]13 DDR0_DQ[20]/DDR0_DQ[36] DDR0_MA[3] 13 13 DDR0_DQ[21]/DDR0_DQ[37] DDR0_MA[4] 13 13 DDR0_DQ[22]/DDR0_DQ[38] 13 DDR0_DQ[23]/DDR0_DQ[39] DDR0_DQSN[0] M_A_DQS0 M_A_DQS1 DDR0_DQ[24]/DDR0_DQ[40] DDR0_DQSP[0] M_B_DQS0 DDR0_DQ[25]/DDR0_DQ[41] DDR0_DQSN[1] M_B_DQS1 M_A_DQS2 DDR0_DQ[26]/DDR0_DQ[42] DDR0_DQSP[1] M_A_DQS3 M_B_DQS2 DDR0_DQ[27]/DDR0_DQ[43] DDR1_DQSN[0]/DDR0_DQSN[2] M_B_DQS3 DDR0_DQ[28]/DDR0_DQ[44] DDR1_DQSP[0]/DDR0_DQSP[2] DDR0_DQ[29]/DDR0_DQ[45] DDR1_DQSN[1]/DDR0_DQSN[3] DDR0_DQ[30]/DDR0_DQ[46] DDR1_DQSP[1]/DDR0_DQSP[3] DDR0_DQ[31]/DDR0_DQ[47] DDR0_DQSN[2]/DDR0_DQSN[4] DDR1_DQ[16]/DDR0_DQ[48] DDR0_DQSP[2]/DDR0_DQSP[4] DDR1_DQ[17]/DDR0_DQ[49] DDR0_DQSN[3]/DDR0_DQSN[5] DDR1_DQ[18]/DDR0_DQ[50] DDR0_DQSP[3]/DDR0_DQSP[5] DDR1_DQ[19]/DDR0_DQ[51] DDR1_DQSN[2]/DDR0_DQSN[6] DDR1_DQ[20]/DDR0_DQ[52] DDR1_DQSP[2]/DDR0_DQSP[6] DDR1_DQ[21]/DDR0_DQ[53] DDR1_DQSN[3]/DDR0_DQSN[7] DDR1_DQ[22]/DDR0_DQ[54] DDR1_DQSP[3]/DDR0_DQSP[7] DDR1_DQ[23]/DDR0_DQ[55] M_A_ALERT_N 12 M_A_PARITY 12 DDR1_DQ[24]/DDR0_DQ[56] DDR0_ALERT# V_SM_VREF_CNTA DDR1_DQ[25]/DDR0_DQ[57] DDR0_PAR D 2 1 Elet V_SM_VREF_CNTB DDR1_DQ[26]/DDR0_DQ[58] 12 13 DDR1_DQ[27]/DDR0_DQ[59] DDR_VREF_CA DDR1_DQ[28]/DDR0_DQ[60] DDR0_VREF_DQ DDR1_DQ[29]/DDR0_DQ[61] DDR1_VREF_DQ DDR1_DQ[30]/DDR0_DQ[62] DDR1_DQ[31]/DDR0_DQ[63] DDR CH - A DDR_VTT_CNTL SKYLAKE-U-GP 071.SKYLA.000U DQ Bit Swapping is allowed within the same byte, and Byte Swapping is allowed within the same channel. 3D3V_S5 Clock (CLK and CLK#) and Strobe (DQS and DQS#) differential signal swapping within a pair is not allowed. Also differential B R507 clock pair to clock pair swapping within a channel is not allowed. 10KR2J-3-G PDG: DDR/ODT SM_PGCNTL G Q501 DMN5L06 84.0506 S A 543

2 1 rleaved Type CPU1C 3 OF 20 D C M_A_DQ32 M_A_DQ32 AY39 SKYLAKE_ULT AN45 B M_A_DQ33 M_A_DQ33 AW39 AN46 M_A_DQ34 M_A_DQ34 DDR0_DQ[32]/DDR1_DQ[0] DDR1_CKN[0] AP45 M_B_CLK#0 13 M_A_DQ35 M_A_DQ35 AY37 DDR0_DQ[33]/DDR1_DQ[1] DDR1_CKN[1] AP46 M_B_CLK#1 13 M_A_DQ36 M_A_DQ36 AW37 DDR0_DQ[34]/DDR1_DQ[2] DDR1_CKP[0] M_B_CLK0 13 M_A_DQ37 M_A_DQ37 DDR0_DQ[35]/DDR1_DQ[3] DDR1_CKP[1] AN56 M_B_CLK1 13 M_A_DQ38 M_A_DQ38 BB39 DDR0_DQ[36]/DDR1_DQ[4] AP55 M_A_DQ39 M_A_DQ39 BA39 DDR0_DQ[37]/DDR1_DQ[5] DDR1_CKE[0] AN55 M_B_CKE0 13 M_A_DQ40 M_A_DQ40 BA37 DDR0_DQ[38]/DDR1_DQ[6] DDR1_CKE[1] AP53 M_B_CKE1 13 M_A_DQ41 M_A_DQ41 BB37 DDR0_DQ[39]/DDR1_DQ[7] DDR1_CKE[2] M_A_DQ42 M_A_DQ42 AY35 DDR0_DQ[40]/DDR1_DQ[8] DDR1_CKE[3] BB42 M_A_DQ43 M_A_DQ43 AW35 DDR0_DQ[41]/DDR1_DQ[9] AY42 M_A_DQ44 M_A_DQ44 AY33 DDR0_DQ[42]/DDR1_DQ[10] DDR1_CS#[0] BA42 M_B_CS#0 13 M_A_DQ45 M_A_DQ45 AW33 DDR0_DQ[43]/DDR1_DQ[11] DDR1_CS#[1] AW42 M_A_DQ46 M_A_DQ46 BB35 DDR0_DQ[44]/DDR1_DQ[12] DDR1_ODT[0] M_B_CS#1 13 M_A_DQ47 M_A_DQ47 BA35 DDR0_DQ[45]/DDR1_DQ[13] DDR1_ODT[1] AY48 M_B_DQ32 M_B_DQ32 BA33 DDR0_DQ[46]/DDR1_DQ[14] AP50 M_B_DIMB_ODT0 13 M_B_DQ33 M_B_DQ33 BB33 DDR0_DQ[47]/DDR1_DQ[15] BA48 M_B_DQ34 M_B_DQ34 AU40 DDR1_DQ[32]/DDR1_DQ[16] BB48 M_B_DIMB_ODT1 13 M_B_DQ35 M_B_DQ35 AT40 DDR1_DQ[33]/DDR1_DQ[17] AP48 M_B_DQ36 M_B_DQ36 AT37 DDR1_DQ[34]/DDR1_DQ[18] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] AP52 M_B_A5 M_B_A5 13 M_B_DQ37 M_B_DQ37 AU37 DDR1_DQ[35]/DDR1_DQ[19] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] AN50 M_B_A9 M_B_A9 13 M_B_DQ38 M_B_DQ38 AR40 DDR1_DQ[36]/DDR1_DQ[20] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] AN48 M_B_A6 M_B_A6 13 M_B_DQ39 M_B_DQ39 AP40 DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] AN53 M_B_A8 M_B_A8 13 M_B_DQ40 M_B_DQ40 AP37 DDR1_DQ[38]/DDR1_DQ[22] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] AN52 M_B_A7 M_B_A7 13 M_B_DQ41 M_B_DQ41 AR37 DDR1_DQ[39]/DDR1_DQ[23] M_B_DQ42 M_B_DQ42 AT33 DDR1_DQ[40]/DDR1_DQ[24] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] BA43 M_B_A12 M_B_BG0 13 M_B_DQ43 M_B_DQ43 AU33 DDR1_DQ[41]/DDR1_DQ[25] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] AY43 M_B_A11 M_B_A12 13 M_B_DQ44 M_B_DQ44 AU30 DDR1_DQ[42]/DDR1_DQ[26] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] AY44 M_B_ACT_N M_B_A11 13 M_B_DQ45 M_B_DQ45 AT30 DDR1_DQ[43]/DDR1_DQ[27] AW44 M_B_DQ46 M_B_DQ46 AR33 DDR1_DQ[44]/DDR1_DQ[28] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# BB44 M_B_A13 M_B_ACT_N 13 M_B_DQ47 M_B_DQ47 AP33 DDR1_DQ[45]/DDR1_DQ[29] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] AY47 M_B_A15 M_B_BG1 13 M_A_DQ48 AR30 DDR1_DQ[46]/DDR1_DQ[30] BA44 M_B_A14 M_A_DQ48 M_A_DQ49 AP30 DDR1_DQ[47]/DDR1_DQ[31] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] AW46 M_B_A16 M_B_A13 13 M_A_DQ49 M_A_DQ50 AY31 DDR0_DQ[48]/DDR1_DQ[32] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] AY46 M_B_A15 13 M_A_DQ50 M_A_DQ51 AW31 DDR0_DQ[49]/DDR1_DQ[33] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] BA46 M_B_A2 M_B_A14 13 M_A_DQ51 M_A_DQ52 AY29 DDR0_DQ[50]/DDR1_DQ[34] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] BB46 M_B_A16 13 M_A_DQ52 M_A_DQ53 AW29 DDR0_DQ[51]/DDR1_DQ[35] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] BA47 M_B_A10 M_A_DQ53 M_A_DQ54 BB31 DDR0_DQ[52]/DDR1_DQ[36] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] M_B_A1 M_B_BA0 13 M_A_DQ54 M_A_DQ55 BA31 DDR0_DQ[53]/DDR1_DQ[37] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] BA38 M_B_A0 M_B_A2 13 M_A_DQ55 M_A_DQ56 BA29 DDR0_DQ[54]/DDR1_DQ[38] AY38 M_B_A3 M_A_DQ56 M_A_DQ57 BB29 DDR0_DQ[55]/DDR1_DQ[39] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] AY34 M_B_A4 M_B_BA1 13 M_A_DQ57 M_A_DQ58 AY27 DDR0_DQ[56]/DDR1_DQ[40] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] BA34 M_B_A10 13 M_A_DQ58 M_A_DQ59 AW27 DDR0_DQ[57]/DDR1_DQ[41] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] AT38 M_A_DQS_DN4 M_B_A1 13 M_A_DQ59 M_A_DQ60 AY25 DDR0_DQ[58]/DDR1_DQ[42] DDR1_MA[3] AR38 M_A_DQS_DP4 M_B_A0 13 M_A_DQ60 M_A_DQ61 AW25 DDR0_DQ[59]/DDR1_DQ[43] DDR1_MA[4] AT32 M_A_DQS_DN5 M_B_A3 13 M_A_DQ61 M_A_DQ62 BB27 DDR0_DQ[60]/DDR1_DQ[44] AR32 M_A_DQS_DP5 M_B_A4 13 M_A_DQ62 M_A_DQ63 BA27 DDR0_DQ[61]/DDR1_DQ[45] BA30 M_B_DQS_DN4 M_A_DQ63 M_B_DQ48 BA25 DDR0_DQ[62]/DDR1_DQ[46] DDR0_DQSN[4]/DDR1_DQSN[0] AY30 M_B_DQS_DP4 M_A_DQS4 1D2V_S3 M_B_DQ48 M_B_DQ49 BB25 DDR0_DQ[63]/DDR1_DQ[47] DDR0_DQSP[4]/DDR1_DQSP[0] AY26 M_B_DQS_DN5 M_A_DQS5 M_B_DQ49 M_B_DQ50 AU27 DDR1_DQ[48] DDR0_DQSN[5]/DDR1_DQSN[1] BA26 M_B_DQS_DP5 M_B_DQS4 R505 M_B_DQ50 M_B_DQ51 AT27 DDR1_DQ[49] DDR0_DQSP[5]/DDR1_DQSP[1] AR25 M_A_DQS_DN6 M_B_DQS5 470R2F-GP M_B_DQ51 M_B_DQ52 AT25 DDR1_DQ[50] DDR1_DQSN[4]/DDR1_DQSN[2] AR27 M_A_DQS_DP6 M_A_DQS6 M_B_DQ52 M_B_DQ53 AU25 DDR1_DQ[51] DDR1_DQSP[4]/DDR1_DQSP[2] AR22 M_A_DQS_DN7 M_A_DQS7 M_B_DQ53 M_B_DQ54 AP27 DDR1_DQ[52] DDR1_DQSN[5]/DDR1_DQSN[3] AR21 M_A_DQS_DP7 M_B_DQS6 M_B_DQ54 M_B_DQ55 AN27 DDR1_DQ[53] DDR1_DQSP[5]/DDR1_DQSP[3] M_B_DQS_DN6 M_B_DQS7 M_B_DQ55 M_B_DQ56 AN25 DDR1_DQ[54] DDR0_DQSN[6]/DDR1_DQSN[4] AN43 M_B_DQS_DP6 M_B_DQ56 M_B_DQ57 AP25 DDR1_DQ[55] DDR0_DQSP[6]/DDR1_DQSP[4] AP43 M_B_DQS_DN7 M_B_DQ57 M_B_DQ58 AT22 DDR1_DQ[56] DDR0_DQSN[7]/DDR1_DQSN[5] AT13 M_B_DQS_DP7 M_B_DQ58 M_B_DQ59 AU22 DDR1_DQ[57] DDR0_DQSP[7]/DDR1_DQSP[5] AR18 M_B_DQ59 M_B_DQ60 AU21 DDR1_DQ[58] AT18 SM_DRAMRST# M_B_DQ60 M_B_DQ61 AT21 DDR1_DQ[59] DDR1_DQSN[6] AU18 SM_RCOMP_0 M_B_DQ61 M_B_DQ62 AN22 DDR1_DQ[60] DDR1_DQSP[6] SM_RCOMP_1 M_B_DQ62 M_B_DQ63 AP22 DDR1_DQ[61] DDR1_DQSN[7] SM_RCOMP_2 M_B_DQ63 AP21 DDR1_DQ[62] DDR1_DQSP[7] AN21 DDR1_DQ[63] tro-X DDR1_ALERT# M_B_ALERT_N 13 1 R504 2 DDR4_DRAMRST# 12,13 DDR1_PAR M_B_PARITY 13 21 1 R501 0R0402-PAD 21DRAM_RESET#1 R5022 121R2F-GP DDR_RCOMP[0] 1 R503 2 80D6R2F-L-GP 12DDR_RCOMP[1]2 100R2F-L1-GP-U DDR_RCOMP[2] DDR CH - B #543016 SKYLAKE-U-GP ED502 071.SKYLA.000U DY AZ5725-01FDR7G-GP 3D3V_S0 Layout Note: 83.05725.0A0 Design Guideline: SM_RCOMP keep routing length less than 500 mils. R506 close to CPU 220KR2F-GP GP Q502_G Q502 SM_PGCNTL_R 51 G 6K-7-GP 67.031 D S 2N7002K-2-GP 84.2N702.J31 2ND = 84.2N702.031 3rd = 84.07002.I31 M_A_DQS_DN[7:0] 12 M_B_DQS_DN0 M_B_DQS_DN[7:0] 13 M_A_DQS_DP[7:0] 12 M_B_DQS_DN1 M_A_DQS_DN0 M_B_DQS_DN2 M_B_DQS_DP[7:0] 13 M_A_DQS_DN1 M_B_DQS_DN3 M_A_DQS_DN2 M_B_DQS_DN4 A M_A_DQS_DN3 M_B_DQS_DN5 M_A_DQS_DN4 M_B_DQS_DN6 <Core Design> M_A_DQS_DN5 M_B_DQS_DN7 M_A_DQS_DN6 Wistron Corporation M_A_DQS_DN7 M_B_DQS_DP0 M_B_DQS_DP1 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, M_A_DQS_DP0 M_B_DQS_DP2 M_A_DQS_DP1 M_B_DQS_DP3 Taipei Hsien 221, Taiwan, R.O.C. M_A_DQS_DP2 M_B_DQS_DP4 M_A_DQS_DP3 M_B_DQS_DP5 M_A_DQS_DP4 M_B_DQS_DP6 M_A_DQS_DP5 M_B_DQS_DP7 M_A_DQS_DP6 M_A_DQS_DP7 2 Title Document Number CPU_(DDR) Rev Monday, June 27, 2016 Size Vegas SKL/KBL-U A00 A2 Sheet 5 of 105 D ate: 1

5 4 3 Main Func = CPU CPU1S 19 OF 20 RESERVED SIGNALS-1 TPAD14-OP-GP TP618 1 CFG0 E68 CFG[0] SKYLAKE_ULT RSVD_TP#BB68 BB68 B67 CFG[1] RSVD_TP#BB69 BB69 TPAD14-OP-GP TP619 1 CFG1 D65 CFG[2] D67 CFG[3] RSVD_TP#AK13 AK13 TPAD14-OP-GP TP620 1 CFG2 E70 CFG[4] RSVD_TP#AK12 AK12 C68 CFG[5] TPAD14-OP-GP TP621 1 CFG3 D68 CFG[6] RSVD#BB2 BB2 C67 CFG[7] RSVD#BA3 BA3 TPAD14-OP-GP TP622 1 CFG4 F71 CFG[8] G69 CFG[9] TP5 AU5 TPAD14-OP-GP TP623 1 CFG5 F70 CFG[10] TP6 AT5 G68 CFG[11] TPAD14-OP-GP TP624 1 CFG6 H70 CFG[12] RSVD#D5 D5 G71 CFG[13] RSVD#D4 D4 TPAD14-OP-GP TP625 1 CFG7 H69 CFG[14] RSVD#B2 B2 G70 CFG[15] RSVD#C2 C2 D TPAD14-OP-GP TP626 1 CFG8 E63 RSVD#B3 B3 TPAD14-OP-GP TP627 1 CFG9 F63 RSVD#A3 A3 TPAD14-OP-GP TP628 1 CFG10 E66 RSVD#AW 1 AW 1 F66 TPAD14-OP-GP TP629 1 CFG11 RSVD#E1 E1 E60 RSVD#E2 E2 TPAD14-OP-GP TP630 1 CFG12 E8 RSVD#BA4 BA4 TPAD14-OP-GP TP631 1 CFG13 RSVD#BB4 BB4 AY2 TPAD14-OP-GP TP632 1 CFG14 AY1 RSVD#A4 A4 RSVD#C4 C4 TPAD14-OP-GP TP633 1 CFG15 D1 D3 TP4 BB5 TPAD14-OP-GP TP634 1 CFG16 CFG[16] TPAD14-OP-GP TP635 1 CFG17 K46 CFG[17] RSVD#A69 A69 K45 RSVD#B69 B69 TPAD14-OP-GP TP636 1 CFG18 CFG[18] TPAD14-OP-GP TP637 1 CFG19 AL25 CFG[19] RSVD#AY3 AY3 AL27 49D9R2F-GP 2 1 R601 CFG_RCOMP CFG_RCOMP RSVD#D71 D71 C71 RSVD#C70 C70 TPAD14-OP-GP TP638 1 ITP_PMODE B70 ITP_PMODE RSVD#C54 C54 F60 RSVD#AY2 RSVD#D54 D54 RSVD#AY1 A52 TP1 AY4 RSVD#D1 TP2 BB3 BA70 RSVD#D3 BA68 VSS AY71 RSVD#K46 ZVM# AR56 J71 RSVD#K45 J68 RSVD_TP_AW71RSVD_TP#AW 71 AW 71 C RSVD#AL25 RSVD_TP_AW70RSVD_TP#AW 70 AW 70 F65 RSVD#AL27 G65 MSM# AP56 RSVD#C71 PROC_SELECT# C64 F61 RSVD#B70 E61 RSVD#F60 RSVD#A52 TPAD14-OP-GP TP601 1 RSVD_TP_BA70 RSVD_TP#BA70 TPAD14-OP-GP TP602 1 RSVD_TP_BA68 RSVD_TP#BA68 TPAD14-OP-GP TP612 1 RSVD_F65 RSVD#J71 TPAD14-OP-GP TP613 1 RSVD_G65 RSVD#J68 VSS Elet VSS RSVD#F61 RSVD#E61 SKYLAKE-U-GP PCH strap pin: 071.SKYLA.000U CFG3 B [BDW Only]PHYSICAL_DEBUG_ENABLED (DFX PRIVACY)21 R604 DY 1KR2J-1-GP 0 : ENABLED SET DFX ENABLED BIT CFG[3] IN DEBUG INTERFACE MSR 1 : DISABLED (#543016) CFG4 21 DISPLAY PORT PRESENCE STRAP R605 0 : ENABLED 1KR2J-1-GP An external Display Port device is connected to the Embedded Display Port. CFG[4] 1 : DISABLED (Default) No Physical Display Port attached to Embedded DisplayPort*. No connect for CFG TERMINATIONS #544669 Rev0.52 (CRB) 20140807 david A SKL(#543016): Processor strap CFG[4] should be pulled low to enable embe 543

2 1 D RSVD_TP_BB68 1 RSVD_TP_BB69 1 TP603 TPAD14-OP-GP TP604 TPAD14-OP-GP TP4_BB5 1 TP609 TPAD14-OP-GP TP1_AY4 1 TP610 TPAD14-OP-GP C TP2_BB3 1 TP611 TPAD14-OP-GP B tro-X 1 R602 #54469 CRB. VSS_AY71 2 ZVM# 0R0402-PAD ZVM# 40 RSVD_TP_AW 71 1 TP614 TPAD14-OP-GP +VCCST_CPU RSVD_TP_AW 70 1 TP615 TPAD14-OP-GP MSM# 1 TP617 TPAD14-OP-GP PROC_SELECT# 12 R603 100KR2J-1-GP disable. <Core Design> A edded DisplayPort* Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Document Number CPU_(RESERVED) Rev Size Vegas SKL/KBL-U A00 A3 Monday, June 27, 2016 Sheet 6 of 105 Date: 1 2

5 4 3 +VCCGT Main Func = CPU CPU1M CP CPU1L 12 OF 20 A48 VCCGT A53 VCCGT VCC_CORE CPU POWER 1 OF 4 VCC_CORE A58 VCCGT A62 VCCGT A30 VCC SKYLAKE_ULT VCC G32 A66 VCCGT A34 VCC VCC G33 AA63 VCCGT D A39 VCC VCC G35 AA64 VCCGT A44 VCC VCC G37 AA66 VCCGT AK33 VCC VCC G38 AA67 VCCGT AK35 VCC VCC G40 AA69 VCCGT AK37 VCC VCC G42 AA70 VCCGT AK38 VCC VCC J30 AA71 VCCGT AK40 VCC VCC J33 AC64 VCCGT AL33 VCC VCC J37 AC65 VCCGT AL37 VCC VCC J40 AC66 VCCGT AL40 VCC VCC K33 AC67 VCCGT AM32 VCC VCC K35 AC68 VCCGT AM33 VCC VCC K37 AC69 VCCGT AM35 VCC VCC K38 AC70 VCCGT AM37 VCC VCC K40 AC71 VCCGT AM38 VCC VCC K42 J43 VCCGT G30 VCC VCC K43 J45 VCCGT J46 VCCGT TPAD14-OP-GP TP701 1 +VCCCOREG0 K32 RSVD#KR3S2VD_K32 VCC_SENSE E32 VCC_SENSE 46 J48 VCCGT VSS_SENSE E33 VSS_SENSE 46 J50 VCCGT TPAD14-OP-GP TP702 1 +VCCCOREG1 AK32 J52 VCCGT RSVD#ARKS3VD2_AK32 VIDALERT# B63 J53 VCCGT VIDSCK A63 H _C PU _SVID ALR T # J55 VCCGT 140mA 3A +V_EDRAM_VR AB62 VCCOPC D64 H _C PU _SVID C LK +VCCSTG J56 VCCGT P62 VCCOPC VIDSOUT H _C PU _SVID D AT J58 VCCGT +V1.8S_ED R AM V62 VCCOPC G20 J60 VCCGT VCCSTG +VCCFUSEPRG K48 VCCGT +V_EDRAM_VR VCC_OPC_1P8 1 R703 2 K50 VCCGT K52 VCCGT H63 VCC_OPC_1P8 0R0402-PAD K53 VCCGT K55 VCCGT R704 1 23e 2 VCC_EDRAM_FUSEPRG G61 VCCOPC_SENSE K56 VCCGT VSSOPC_SENSE K58 VCCGT 0R2J-2-GP VCC_CORE K60 VCCGT 100R2F-L1-GP-U L62 VCCGT VCCSENSE_EDRAM_VR AC63 L63 VCCGT VSSSENSE_EDRAM_VR AE63 L64 VCCGT L65 VCCGT +V_EOPIO_VR AE62 VCCEOPIO 1 R710 2 VCC_SENSE 46 L66 VCCGT AG62 VCCEOPIO 2 VSS_SENSE 46 L67 VCCGT VC C SEN SE_EO PIO _VR 1 L68 VCCGT 3A VSSSEN SE_EO PIO _VR AL63 VCCEOPIO_SENSE R711 L69 VCCGT AJ62 VSSEOPIO_SENSE L70 VCCGT 23eC701 2123e 100R2F-L1-GP-U L71 VCCGT SC10U6D3V2MX-GP-U SC10U6D3V2MX-GP-U M62 VCCGT Layout Note: N63 VCCGT 21 C702 N64 VCCGT SKYLAKE-U-GP 1. Place close to CPU N66 VCCGT 2. VCC_SENSE/ VSS_SENSE N67 VCCGT 071.SKYLA.000U N69 VCCGT 3. impedance=50 ohm Length match<25mil J70 VCCGT_S J69 VSSGT_S C +V_EOPIO_VR +V_EOPIO_VR +V_EDRAM_VR R707 46 VCCGT_SENSE 100R2F-L1-GP-U 46 VSSGT_SENSE R701 100R2F-L1-GP-U C703 21 1 23e 2 VCCSENSE_EDRAM_VR 1 23e 2 VC C SEN SE_EO PIO _VR SKYLAKE-U-GP SC10U6D3V2MX-GP-U SC10U6D3V2MX-GP-U 1 23e 2 VSSSENSE_EDRAM_VR 1 23e 2 VSSSEN SE_EO PIO _VR 23e 23e 21 C704 +VCCGT 071.SKY R706 100R2F-L1-GP-U 100R2F-L1-GP-U R708 100R2F-L1-GP-U 1 R712 2 VCCGT_SENSE 46 2 VSSGT_SENSE 46 1 R713 RN701 RN702 change to Single for cost change 2/26 100R2F-L1-GP-U Layout Note: SVID_ Layout Note: 1. Place close to CPU The total Length of Data and Clock (from CPU to each VR) must be equal (±0.1 inch). 2. VCC_SENSE/ VSS_SENSE Route the Alert signal between the Clock and the Data signals. impedance=50 ohm 3. Length match<25mil Elet SVID DATA +VCCST_CPU B CLOSE TO CPU 21 R726 H _C PU _SVID D AT 100R2F-L1-GP-U #544669 1 R709 2 0R0402-PAD VR_SVID_DATA 46 +VCCST_CPU SVID CLOCK 21 R723 #544669 54D9R2F-L1-GP CLOSE TO VR DY H _C PU _SVID C LK 1 R732 2 VR_SVID_CLK 46 0R0402-PAD +VCCST_CPU 21 #544669 R727 CLOSE TO CPU A 56R2J-4-GP H _C PU _SVID ALR T # R728 1 VR_SVID_ALERT# 46 2 220R2J-L2-GP 543

21 13 OF 20 PU POWER 2 OF 4 VCCGT N70 +VCCGT +VDDQ_CPU_CLK 1D2V_S3 SKYLAKE_ULT VCCGT N71 VCCGT R63 +VCCGT 21 SENSE VCCGT R64 21 SENSE VCCGT R65 for 2+3E DY C722 P VCCGT R66 SC1U10V2KX-1GP VCCGT R67 C719 CPU1N 14 OF 20 +VC C IO KYLA.000U VCCGT R68 DY SC1U10V2KX-1GP +VCCIO(ICCMAX.=2.73A VCCGT R69 VCCGT R70 CPU POWER 3 OF 4 +VCCSA VCCGT R71 VCCGT T62 AU23 VDDQ SKYLAKE_ULT VCCIO AK28 D VCCGT U65 AU28 VDDQ VCCIO AK30 C VCCGT U68 1D2V_S3 +VDDQ_CPU_CLK AU35 VDDQ VCCIO AL30 VCCGT U71 AU42 VDDQ VCCIO AL42 VCCGT W63 R705 BB23 VDDQ VCCIO AM28 VCCGT W64 BB32 VDDQ VCCIO AM30 VCCGT W65 12 BB41 VDDQ VCCIO AM42 VCCGT W66 0R0603-PAD BB47 VDDQ VCCGT W67 BB51 VDDQ VCCSA AK23 VCCGT W68 VCCSA AK25 VCCGT W69 SC10U6D3V3MX-GP2 DY1 C715 AM40 VDDQC VCCSA G23 VCCGT W70 VCCSA G25 VCCGT W71 +VCCST_CPU A18 VCCST VCCSA G27 VCCGT Y62 VCCSA G28 SC1U10V2KX-1GP 2 DY1 C716 0.04 A A22 VCCSTG VCCSA J22 VCCGTX AK42 VCCSA J23 VCCGTX AK43 +VCCSTG AL23 VCCPLL_OC VCCSA J27 VCCGTX AK45 VCCSA K23 VCCGTX AK46 SC1U10V2KX-1GP 2 DY1 C717 K20 VCCPLL VCCSA K25 VCCGTX AK48 K21 VCCPLL VCCSA K27 VCCGTX AK50 1D2V_S3 VCCSA K28 VCCGTX AK52 VCCSA K30 VCCGTX AK53 SCD1U16V2KX-3GP2 DY1 C718 VCCGTX AK55 AM23 VCCGTX AK56 +V1.00U _C PU VCCIO_SENSE AM22 VC C IO _VR _F B VCCGTX AK58 VSSIO_SENSE VSSIO _VR _F B VCCGTX AK60 H21 VCCGTX AK70 21 0.12 A VSSSA_SENSE H20 VSSSA_SENSE 46 VCCGTX AL43 SCD1U16V2KX-3GP C720 VCCSA_SENSE VCCSA_SENSE 46 VCCGTX AL46 DY VCCGTX AL50 21 VCCGTX AL53 SCD1U16V2KX-3GP C721 SKYLAKE-U-GP +VC C IO VCCGTX AL56 VCCGTX AL60 071.SKYLA.000U 100R2F-L1-GP-U VCCGTX AM48 VCCGTX AM50 VC C IO _VR _F B 1 R714 2 VCCGTX AM52 VSSIO _VR _F B 2 VCCGTX AM53 1 VCCGTX AM56 R715 VCCGTX AM58 VCCGTX AU58 100R2F-L1-GP-U VCCGTX AU63 VCCGTX BB57 Layout Note: VCCGTX BB66 1. Place close to CPU VCCGTX_SENSE AK62 2. VCC_SENSE/ VSS_SENSE VSSGTX_SENSE AL61 3. impedance=50 ohm Length match<25mil tro-X +VCCSA 100R2F-L1-GP-U _543016: VCCSA_SENSE 1 R716 2 VSSSA_SENSE 2 1 R717 100R2F-L1-GP-U Layout Note: 1. Place close to CPU 2. VCC_SENSE/ VSS_SENSE 3. impedance=50 ohm Length match<25mil B A <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title CPU(VCC_CORE) Size Document Number Rev A2 Vegas SKL/KBL-U A00 Date: Monday, June 27, 2016 Sheet 7 of 105 21

5 4 3 Main Func = CPU D 57 HDMI_DATA2# 57 HDMI_DATA2 HDMI 57 HDMI_DATA1# 57 HDMI_DATA1 57 HDMI_DATA0# 57 HDMI_DATA0 57 HDMI_CLK# 57 HDMI_CLK DP to VGA 56 PCH_DPC_N0 56 PCH_DPC_P0 56 PCH_DPC_N1 56 PCH_DPC_P1 3D3V_S0 C RN801 HDMI2 3 CPU_DP1_CTRL_CLK 57 CPU_DP1_CTRL_CLK 57 CPU_DP1_CTRL_DATA 1 4 CPU_DP1_CTRL_DATA CPU_DP2_CTRL_CL SRN2K2J-1-GP CPU_DP2_CTRL_DA 3D3V_S0 Check +VCCIO TPAD14-OP-GP TP802 RN803 R801 1 DDPD_CTRLDATA 23 CPU_DP2_CTRL_DATA 12 EDP_COMP CPU_DP2_CTRL_CLK 24D9R2F-L-GP 1 Vegas 4 SRN2K2J-1-GP (#543016) eDP_RCOMP Guideline Elet Signal Trace Isolation Resistor Length Width Spacing Value Max = 100 mils eDP_RCOMP 20 mils 25 mils 24.9 Ω ±1% B Strap pin: (#543016) DDI Disabling and Termination Guidelines Port B / Sampled at rising edge of Port C Detected Port Strap Enable Port Disable Port 0 = Port B is not det DDPB_CTRLDATA Port 1 DDPB_CTRLDATA PU to 3.3 V with 2.2-k NC * 1 = Port B is detecte ±5% resistor Port 2 DDPC_CTRLDATA PU to 3.3 V with 2.2-k NC DDPC_CTRLDATA 0 = Port C is not det ±5% resistor * 1 = Port C is detecte These two signals have weak internal pull-down. Design Guideline: Skylake processor signal eDP_RCOMP shoul A 543

21 CPU1A 1 OF 20 D C E55 DDI1_TXN[0] SKYLAKE_ULT EDP_TXN[0] C47 eDP_TX_CPU_N0 55 B F55 DDI1_TXP[0] DDI EDP_TXP[0] C46 eDP_TX_CPU_P0 55 E58 DDI1_TXN[1] EDP_TXN[1] D46 eDP_TX_CPU_N1 55 F58 DDI1_TXP[1] EDP_TXP[1] C45 eDP_TX_CPU_P1 55 F53 DDI1_TXN[2] EDP_TXN[2] A45 G53 DDI1_TXP[2] EDP EDP_TXP[2] B45 eDP_AUX_CPU_N 55 F56 DDI1_TXN[3] EDP_TXN[3] A47 eDP_AUX_CPU_P 55 G56 DDI1_TXP[3] EDP_TXP[3] B47 EDP_DISP_UTIL 1 TP801 TPAD14-OP-GP C50 DDI2_TXN[0] EDP_AUXN E45 D50 DDI2_TXP[0] EDP_AUXP F45 PCH_DPC_AUXN 56 C52 DDI2_TXN[1] PCH_DPC_AUXP 56 D52 DDI2_TXP[1] EDP_DISP_UTIL B52 A50 DDI2_TXN[2] CPU_DP1_HPD 57 B50 DDI2_TXP[2] DDI1_AUXN G50 CPU_DP2_HPD 56 D51 DDI2_TXN[3] DDI1_AUXP F50 SIO_EXT_SMI#_R 24 C51 DDI2_TXP[3] DDI2_AUXN E48 EDP_HPD 55 DDI2_AUXP F48 DISPLAY SIDEBANDS G46 L_BKLT_EN 24 RSVD#G46 F46 L_BKLT_CTRL 55 L13 GPP_E18/DDPB_CTRLCLK Strap RSVD#F46 EDP_VDD_EN 55 L12 GPP_E19/DDPB_CTRLDATA L9 GPP_E13/DDPB_HPD0 L7 LK N7 GPP_E20/DDPC_CTRLCLK Strap GPP_E14/DDPC_HPD1 L6 ATA N8 GPP_E21/DDPC_CTRLDATA GPP_E15/DDPD_HPD2 N9 GPP_E16/DDPE_HPD3 L10 N11 GPP_E22 Strap N12 GPP_E23 GPP_E17/EDP_HPD R12 R11 E52 EDP_RCOMP EDP_BKLTEN U13 SKYLAKE-U-GP EDP_BKLTCTL EDP_VDDEN tro-X 21 071.SKYLA.000U (#543016) The Skylake U/Y processor supports only two DDI ports - Port 1 and Port 2. 3D3V_S0 SIO_EXT_SMI#_R 1 R802 2 10KR2J-3-GP CPU_DP2_HPD f PCH_PW ROK R806 tected. Vegas 100KR2J-1-GP ed. tected. ed. ld be connected to the VCCIO rail via a single 24.9 ±1% Ω resistor. <Core Design> A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Document Number CPU_(DISPLAY) Rev A3 Vegas SKL/KBL-U A00 Date: Monday, June 27, 2016 Sheet 8 of 105 21

5 Elet43 D (Blan C 43 B A 5

321 D C tro-X nking) B 3 <Core Design> Wistron Corporation A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title (Reserved) Size Document Number Rev A4 Vegas SKL/KBL-U A00 Date: Thursday, June 16, 2016 Sheet 9 of 105 2 1

1 C B A D Wistron Corporation Rev 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, A00 Taipei Hsien 221, Taiwan, R.O.C. 105 CPU_(Power CAP1) Vegas SKL/KBL-U Sheet 10 of <Core Design> Document Number Date: Thursday, June 16, 2016 1 Title Size A2 2 5432 (#543016 PDG) 22U 0603 x 8 PC1098X PC1097ro- SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP DY SC22U6D3V3MX-1-GP 43 PC1068let SC22U6D3V3MX-1-GP PC1035 SC22U6D3V3MX-1-GP 21 SC22U6D3V3MX-1-GP DY SC22U6D3V3MX-1-GP PC1067 E SC22U6D3V3MX-1-GP PC1036 SC22U6D3V3MX-1-GP 21 SC22U6D3V3MX-1-GP DY SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP PC1037 SC22U6D3V3MX-1-GP 21PC1066 SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V5MX-2GPDYSC22U6D3V3MX-1-GP 21 SC22U6D3V3MX-1-GP 10U 0603 x 4SC4D7P50V2BN-GP PC1061 PC1065 DY DY DY21 SC22U6D3V5MX-2GPSC22U6D3V3MX-1-GP 21DY SC22U6D3V3MX-1-GP SC4D7P50V2BN-GP PC1060 21PC1054 21 21 SC4D7P50V2BN-GP PC1059 21 21 21 21 SC10U6D3V3MX-GP PC1058 21PC1053 21 21 21DY 21 SC10U6D3V3MX-GP PC1057 PC1064SC22U6D3V5MX-2GP 21PC1051 PC1052 22U 0603 x28 21 21 21 DY DY DY 21DY 21 21 21 21 SC22U6D3V3MX-1-GP PC1063 SC4D7P50V2BN-GP PC1056 21 21 1D2V_S3 21 21 SC22U6D3V3MX-1-GP PC1062 SC10U6D3V3MX-GP PC1055 PC1050 22U 0603 x 22 PC1049 PC1044 PC1069 PC1070 PC1071 PC1072 PC1073 PC1074 PC1075 PC1076 PC1077 PC1078 PC1079 PC1080 PC1081 SC22U6D3V3MX-1-GP PC1082 PC1083 PC1084 PC1085 PC1086 PC1087 PC1088 PC1089 PC1090 PC1091 PC1092 PC1093 PC1094 PC1095 PC109621 SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP 21 SC22U6D3V3MX-1-GP PC1048 DY DY DY 21SC22U6D3V3MX-1-GP 21 SC22U6D3V3MX-1-GPDY DY DY 21SC22U6D3V3MX-1-GP 21 SC22U6D3V3MX-1-GP PC1010 PC1011 PC1012 PC1013 PC1014 PC1015 PC1016 PC1017 PC1018 PC1019 PC1020 SC22U6D3V3MX-1-GP PC1047 21SC22U6D3V3MX-1-GP 21 SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP 21SC22U6D3V3MX-1-GP 21 SC22U6D3V3MX-1-GP 21SC22U6D3V3MX-1-GP PC1021 PC1022 PC1023 PC1024 PC1025 PC1026 PC1027 PC1028 PC1029 PC1030 SC22U6D3V3MX-1-GP VCCSA PC1046 21SC22U6D3V3MX-1-GP 21 SC22U6D3V3MX-1-GP 21SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP 21SC22U6D3V3MX-1-GP 21 SC22U6D3V3MX-1-GP PC1001 PC1002 PC1003 PC1004 PC1005 PC1006 PC1007 PC1008 PC100921SC22U6D3V3MX-1-GP 21SC22U6D3V3MX-1-GP 21SC22U6D3V3MX-1-GP +VCCSA PC1045 21SC22U6D3V3MX-1-GP 21 SC22U6D3V3MX-1-GPDY DY 21SC22U6D3V3MX-1-GP 21SC22U6D3V3MX-1-GP 21SC22U6D3V3MX-1-GP 21SC22U6D3V3MX-1-GP 21 SC22U6D3V3MX-1-GP 21SC22U6D3V3MX-1-GP 21SC22U6D3V3MX-1-GP 21SC22U6D3V3MX-1-GP DY 21SC22U6D3V3MX-1-GP 21 SC22U6D3V3MX-1-GP 21SC22U6D3V3MX-1-GP 21SC22U6D3V3MX-1-GP 21SC22U6D3V3MX-1-GP 21SC22U6D3V3MX-1-GP 21 SC22U6D3V3MX-1-GP CORE 21SC22U6D3V3MX-1-GP 21SC22U6D3V3MX-1-GP 21SC22U6D3V3MX-1-GP 1D0V_S5 PC1038 PC1039 SLICED GT U-line 23e 28W PC1031 PC1032 PC1033 PC1034 PC1041 PC1042 PC104321SC22U6D3V3MX-1-GP 21SC22U6D3V3MX-1-GP 21 SC22U6D3V3MX-1-GP U-line 23e 28W 21SC22U6D3V3MX-1-GP 21SC22U6D3V3MX-1-GP 21SC22U6D3V3MX-1-GP IccMax current-10ms max[A] = 67 A 21SC22U6D3V3MX-1-GP 21SC22U6D3V3MX-1-GP 21 SC22U6D3V3MX-1-GP 5 IccMax current-10ms max = 34 A 21SC22U6D3V3MX-1-GP 21SC22U6D3V3MX-1-GP 21SC22U6D3V3MX-1-GP +VCCIO(ICCMAX.=2.73A) DY 21SC22U6D3V3MX-1-GP 21 21 SC22U6D3V3MX-1-GP 21SC22U6D3V3MX-1-GP 21 21SC22U6D3V3MX-1-GP 21SC22U6D3V3MX-1-GP 21 Main Func = CPU 21SC22U6D3V3MX-1-GP 21 21 21SC22U6D3V3MX-1-GP 21 21SC22U6D3V3MX-1-GP 21SC22U6D3V3MX-1-GP VCC_CORE +VCCIO +VCCGT D C B A

43 21 21 21 C1150 SC1U10V2KX-1GP +V SC1U10V2KX-1GP U-line 23e 28W SC1U10V2KX-1GP C1173 IccMax current-10ms max = 34 A UNSLICED GT 21C1149DYSC1U10V2KX-1GP+VCCMPHYGTAON_1P0_LS_ SC1U10V2KX-1GP 1U 0402 x 5 C1117 SC1U10V2KX-1GP 21SC1U10V2KX-1GP C1180 SC1U10V2KX-1GP 43 1U 0402 x 6 21 21 C1148 C1116 SC1U10V2KX-1GP 21 21 SC1U10V2KX-1GP SC22U6D3V3MX-1-GP SC1U10V2KX-1GP 21C1147SC1U10V2KX-1GPC1182 C1103 SC1U10V2KX-1GP SC1U10V2KX-1GP 21 DY C1174 21 C1138 DY C1102 21 21C1136DY+VCCMPHYGTAON_1P0_LS_SIP C1101 +VCCGT 21 21 VCC_CORE 21 RAILS 2 E1let 5 PCH DERIVED +V1.00A_SIP SC22U6D3V3MX-1-GP +VCCPRIM_CORE +V3.3A_SIP SC22U6D3V3MX-1-GP +V1.8A_SIP SC22U6D3V3MX-1-GP C1108 C1104 C1106 Main Func = CPU 1D0V_S5 R1101 3D3V_S5_PCH 1D8V_S5 A 1 R1117 2 0R1206-PAD 1 R1110 2 2 R1139 1 5 12 0R0603-PAD-2-GP-U 0R0603-PAD-2-GP-U 0R0603-PAD-2-GP-U D C B

2 1 D VCCIO +VCCIO +VCCIO(ICCMAX.=2.73A) C115121C1152 C1153 C1154 21 DY 21 21 21 PC1105 SC1U10V2KX-1GP SC22U6D3V3MX-1-GPSC1U10V2KX-1GP 21 21SC1U10V2KX-1GP 21SC1U10V2KX-1GP PC1106 SC22U6D3V3MX-1-GP C VCCMPHYGTAON_1P0(ICCMAX.=2.12A) tro-X +VCCMPHYGTAON_1P0_LS_SIP Layout Note: _SIP +VCCMPHYGTAON_1P0_LS_SIP 1uF: SC1U10V2KX-1GP C1176 SC1U10V2KX-1GP C1174 near N15 N15 C1172 SC10U6D3V3MX-GP C1175 C1180 near K15 C1173 near AF20 SC22U6D3V3MX-1-GP 21 C1172 near N18 C1184 21 C1175 near AB19 22uF : C1182 C1184 near B 10uF: C1176 near N15 +VCCPRIM_CORE +V3.3A_SIP C1183 SC10U6D3V3MX-GP 21 <Core Design> A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title CPU_(Power CAP2) Rev Document Number Size A00 A3 Vegas SKL/KBL-U 105 Date: Friday, June 24, 2016 Sheet 11 of 1 2

5 4 3 Main Func = DDR4 SODIMM DM1A 1 OF 4 D 5 M_A_A0 144 A0 DQ0 8 M_A_DQ0 5 DM1B 2 OF 4 5 M_A_A1 133 A1 DQ1 7 M_A_DQ1 5 C 5 M_A_A2 132 A2 DQ2 20 M_A_DQ2 5 DQS0_C 11 M_A_DQS_DN0 5 M_A_A3 131 A3 DQ3 21 M_A_DQ3 5 DQS0_T 13 M_A_DQS_DP0 B 5 M_A_A4 128 A4 DQ4 4 M_A_DQ4 5 DQS1_C 32 M_A_DQS_DN1 5 M_A_A5 126 A5 DQ5 3 M_A_DQ5 5 DQS1_T 34 M_A_DQS_DP1 5 M_A_A6 127 A6 DQ6 16 M_A_DQ6 5 DQS2_C 53 M_A_DQS_DN2 5 M_A_A7 122 A7 DQ7 17 M_A_DQ7 5 DQS2_T 55 M_A_DQS_DP2 5 M_A_A8 125 A8 DQ8 28 M_A_DQ8 5 DQS3_C 74 M_A_DQS_DN3 5 M_A_A9 121 A9 DQ9 29 M_A_DQ9 5 DQS3_T 76 M_A_DQS_DP3 5 M_A_A10 146 A10/AP DQ10 41 M_A_DQ10 5 DQS4_C 177 M_A_DQS_DN4 5 M_A_A11 120 A11 DQ11 42 M_A_DQ11 5 DQS4_T 179 M_A_DQS_DP4 5 M_A_A12 119 A12 DQ12 24 M_A_DQ12 5 DQS5_C 198 M_A_DQS_DN5 5 M_A_A13 158 A13 DQ13 25 M_A_DQ13 5 DQS5_T 200 M_A_DQS_DP5 5 M_A_A14 151 WE#/A14 DQ14 38 M_A_DQ14 5 DQS6_C 219 M_A_DQS_DN6 5 M_A_A15 156 CAS#/A15 DQ15 37 M_A_DQ15 5 DQS6_T 221 M_A_DQS_DP6 5 M_A_A16 152 RAS#/A16 DQ16 50 M_A_DQ16 5 DQS7_C 240 M_A_DQS_DN7 DQ17 49 M_A_DQ17 5 DQS7_T 242 M_A_DQS_DP7 5 M_A_BA0 150 BA0 DQ18 62 M_A_DQ18 5 DQS8_C 95 5 M_A_BA1 145 BA1 DQ19 63 M_A_DQ19 5 DQS8_T 97 5 M_A_BG0 115 BG0 DQ20 46 M_A_DQ20 5 5 M_A_BG1 113 BG1 DQ21 45 M_A_DQ21 5 DM0#/DBI0# 12 DQ22 58 M_A_DQ22 5 DM1#/DBI# 33 92 CB0/NC DQ23 59 M_A_DQ23 5 54 91 CB1/NC DQ24 70 M_A_DQ24 5 DM2#/DBI2# 75 101 CB2/NC DQ25 71 M_A_DQ25 5 DM3#/DBI3# 178 105 CB3/NC DQ26 83 M_A_DQ26 5 DM4#/DBI4# 199 88 CB4/NC DQ27 84 M_A_DQ27 5 DM5#/DBI5# 220 87 CB5/NC DQ28 66 M_A_DQ28 5 DM6#/DBI6# 241 100 CB6/NC DQ29 67 M_A_DQ29 5 DM7#/DBI7# 96 104 CB7/NC DQ30 79 M_A_DQ30 5 DM8#/DBI#/NC DQ31 80 M_A_DQ31 5 5 M_A_CLK0 137 CK0_T DQ32 174 M_A_DQ32 5 DDR4-260P-24-GP 5 M_A_CLK#0 139 CK0_C DQ33 173 M_A_DQ33 5 5 M_A_CLK1 138 CK1_T/NF DQ34 187 M_A_DQ34 5 1D2V_S3 DM1C 3 OF 4 5 M_A_CLK#1 140 CK1_C/NF DQ35 186 M_A_DQ35 5 DQ36 170 M_A_DQ36 5 111 VDD VDDSPD 255 5 M_A_CKE0 109 CKE0 DQ37 169 M_A_DQ37 5 112 VDD 5 M_A_CKE1 110 CKE1 DQ38 183 M_A_DQ38 5 117 VDD VPP 257 DQ39 182 M_A_DQ39 5 118 VDD VPP 259 5 M_A_CS#0 149 CS0# DQ40 195 M_A_DQ40 5 123 VDD VTT 258 5 M_A_CS#1 157 CS1# DQ41 194 M_A_DQ41 5 124 VDD 162 C0/CS2#/NC DQ42 207 M_A_DQ42 5 129 VDD 5 M_A_DIMA_ODT0 165 C1/CS3#/NC DQ43 208 M_A_DQ43 5 130 VDD 5 M_A_DIMA_ODT1 DQ44 191 M_A_DQ44 5 135 VDD 155 ODT0 DQ45 190 M_A_DQ45 5 136 VDD SA0_C H A_D IM0 161 ODT1 DQ46 203 M_A_DQ46 5 141 VDD 261 261 SA1_C H A_D IM0 DQ47 204 M_A_DQ47 5 142 VDD 262 262 SA2_C H A_D IM0 256 SA0 DQ48 216 M_A_DQ48 5 147 VDD 260 SA1 DQ49 215 M_A_DQ49 5 148 VDD NP1 NP1 13,18,56,65,67 PCH_SMBDATA 166 SA2 DQ50 228 M_A_DQ50 5 153 VDD NP2 NP2 13,18,56,65,67 PCH_SMBCLK DQ51 229 M_A_DQ51 5 154 VDD 254 SDA DQ52 211 M_A_DQ52 5 159 VDD 253 SCL DQ53 212 M_A_DQ53 5 160 VDD DQ54 224 M_A_DQ54 5 163 VDD DQ55 225 M_A_DQ55 5 1D2V_S3 5,13 DDR4_DRAMRST# 108 RESET# DQ56 237 M_A_DQ56 5 5 M_A_ACT_N 114 ACT# DQ57 236 M_A_DQ57 5 116 ALERT# DQ58 249 M_A_DQ58 5 DDR4-260P-24-GP 5 M_A_ALERT_N 134 EVENT#/NF DQ59 250 M_A_DQ59 5 1 DY 2 T S#_D IMM0_1 DQ60 232 M_A_DQ60 5 R1215 240R2F-1-GP 143 PARITY DQ61 233 M_A_DQ61 5 DQ62 245 M_A_DQ62 5 DDR4_DRAMRST# 5 M_A_PARITY 164 VREFCA DQ63 246 M_A_DQ63 5 M_VR EF _C A_D IMMA 21 ED1217 C1229 DDR4-260P-24-GP 1D2V_S3 21AZ5725-01FDR7G-GP 062.10011.00U1 2 12 1SCD1U16V2KX-3GP DDR4 SWAP 0212 21 21 跟sw確確 2 E1 let 2 1 3D3V_S0 C1208 C1202 C12 21 21 Layout note: closed to Dimm DY 1D2V_S3 SC10U6D3V3MX-GP SC10U6D3V3MX-GP SC10U6D3V3MX-GP 2 R1204 D1Y 10KR2F-L1-GP SA0_C H A_D IM0 2 1 0R0402-PAD R1205 RN1201 R1206 2 V_SM_VREF_CNTA 5 3D3V_S0 14 M_VREF_CA_DIMMA 1 3D3V_S0 23 C1214 C1215 C12 2R2F-GP SRN1KJ-7-GP 2 R1208 D1Y 10KR2F-L1-GP SA1_C H A_D IM0 C1222 2 1 0R0402-PAD SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP SCD022U16V2KX-3GP R1210 +V_VREF_PATH1 R1209 24D9R2F-L-GP 2 R1211 D1Y 10KR2F-L1-GP SA2_C H A_D IM0 2 1 0R0402-PAD R1212 M M M M M M M M M M M M M M M M A 543

2 1 D DM1D 4 OF 4 1D2V_S3 1 VSS VSS 99 2 VSS VSS 102 3D3V_S0 5 VSS VSS 103 6 VSS VSS 106 2D5V_S3 21 C1228 21 R1216 9 VSS VSS 107 0D6V_S0 SC2D2U10V3KX-L-GP 10 VSS VSS 167 DY SCD1U16V2KX-L-GPDY 14 VSS VSS 168 15 VSS VSS 171 18 VSS VSS 172 19 VSS VSS 175 22 VSS VSS 176 23 VSS VSS 180 26 VSS VSS 181 27 VSS VSS 184 30 VSS VSS 185 31 VSS VSS 188 35 VSS VSS 189 36 VSS VSS 192 39 VSS VSS 193 40 VSS VSS 196 43 VSS VSS 197 44 VSS VSS 201 47 VSS VSS 202 48 VSS VSS 205 51 VSS VSS 206 52 VSS VSS 209 56 VSS VSS 210 57 VSS VSS 213 60 VSS VSS 214 61 VSS VSS 217 64 VSS VSS 218 65 VSS VSS 222 68 VSS VSS 223 69 VSS VSS 226 72 VSS VSS 227 73 VSS VSS 230 77 VSS VSS 231 78 VSS VSS 234 81 VSS VSS 235 82 VSS VSS 238 85 VSS VSS 239 86 VSS VSS 243 89 VSS VSS 244 90 VSS VSS 247 93 VSS VSS 248 94 VSS VSS 251 98 VSS VSS 252 DDR4-260P-24-GP UN 0225 C 0D6V_S0 0D6V_S0 0D6V_S0 DY C1223 DY C1230 DY C1224 DY C1227 21 C1226 21 21 21 C1225 21 21 SC1U10V2KX-1GP SC4D7U6D3V2MX-1-GP 2 1 tro-2X1209C1203 C1204 21 21C1205 21 21C1206 C1210 SC1U10V2KX-1GP SC4D7U6D3V2MX-1-GP 21 21 21 21DY SC10U6D3V3MX-GP SC10U6D3V3MX-GP DY SC10U6D3V3MX-GP SC4D7U6D3V2MX-1-GP SC10U6D3V3MX-GP SC10U6D3V3MX-GP SC4D7U6D3V2MX-1-GP for placement modifu 2015/10/19 2D5V_S3 216 C1217 C1218 C1219 C1220 C1221 21 21 DY DY DY DY 21 SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP 21 21 21 DY C1211 DY C1231 DY C1232 C1212 C1207 C1213 DY DY SC1U10V2KX-L1-GP B SC1U10V2KX-1GP SC4D7U6D3V2MX-1-GP SC4D7U6D3V2MX-1-GP SC4D7U6D3V2MX-1-GP SC4D7U6D3V2MX-1-GP M_A_DQS_DN0 M_A_DQS_DN[7:0] 5 M_A_DQS_DN1 M_A_DQS_DP[7:0] 5 M_A_DQS_DN2 M_A_DQS_DN3 M_A_DQS_DN4 M_A_DQS_DN5 M_A_DQS_DN6 M_A_DQS_DN7 M_A_DQS_DP0 M_A_DQS_DP1 M_A_DQS_DP2 M_A_DQS_DP3 M_A_DQS_DP4 M_A_DQS_DP5 M_A_DQS_DP6 M_A_DQS_DP7 A <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title DDR3-SODIMM1 Size Document Number Rev A2 D ate: Vegas SKL/KBL-U A00 Monday, June 27, 2016 Sheet 12 of 106 2 1

5 4 3 Main Func = DDR4 SODIMM D DM2A 1 OF 4 C 5 M_B_A0 144 A0 DQ0 8 M_B_DQ8 5 1D2V_S3 5 M_B_A1 133 A1 DQ1 7 M_B_DQ9 5 5 M_B_A2 132 A2 DQ2 20 M_B_DQ10 5 DM2C 3 OF 4 5 M_B_A3 131 A3 DQ3 21 M_B_DQ11 5 5 M_B_A4 128 A4 DQ4 4 M_B_DQ12 5 111 VDD VDDSPD 255 5 M_B_A5 126 A5 DQ5 3 M_B_DQ13 5 112 VDD 5 M_B_A6 127 A6 DQ6 16 M_B_DQ14 5 117 VDD VPP 257 5 M_B_A7 122 A7 DQ7 17 M_B_DQ15 5 118 VDD VPP 259 5 M_B_A8 125 A8 DQ8 28 M_B_DQ0 5 123 VDD VTT 258 5 M_B_A9 121 A9 DQ9 29 M_B_DQ1 5 124 VDD 5 M_B_A10 146 A10/AP DQ10 41 M_B_DQ2 5 129 VDD 261 261 5 M_B_A11 120 A11 DQ11 42 M_B_DQ3 5 130 VDD 262 262 5 M_B_A12 119 A12 DQ12 24 M_B_DQ4 5 135 VDD 5 M_B_A13 158 A13 DQ13 25 M_B_DQ5 5 136 VDD NP1 NP1 5 M_B_A14 151 WE#/A14 DQ14 38 M_B_DQ6 5 141 VDD NP2 NP2 5 M_B_A15 156 CAS#/A15 DQ15 37 M_B_DQ7 5 142 VDD 5 M_B_A16 152 RAS#/A16 DQ16 50 M_B_DQ16 5 147 VDD DQ17 49 M_B_DQ17 5 148 VDD 12,18,56,65,67 PCH_SMBDATA 5 M_B_BA0 150 BA0 DQ18 62 M_B_DQ18 5 153 VDD 12,18,56,65,67 PCH_SMBCLK 5 M_B_BA1 145 BA1 DQ19 63 M_B_DQ19 5 154 VDD 5 M_B_BG0 115 BG0 DQ20 46 M_B_DQ20 5 159 VDD 5 M_B_BG1 113 BG1 DQ21 45 M_B_DQ21 5 160 VDD DQ22 58 M_B_DQ22 5 163 VDD 92 CB0/NC DQ23 59 M_B_DQ23 5 91 CB1/NC DQ24 70 M_B_DQ24 5 DDR4-260P-23-GP 101 CB2/NC DQ25 71 M_B_DQ25 5 105 CB3/NC DQ26 83 M_B_DQ26 5 DM2B 2 OF 4 88 CB4/NC DQ27 84 M_B_DQ27 5 5 M_B_CLK0 87 CB5/NC DQ28 66 M_B_DQ28 5 DQS0_C 11 M_B_DQS_DN1 5 M_B_CLK#0 100 CB6/NC DQ29 67 M_B_DQ29 5 DQS0_T 13 M_B_DQS_DP1 5 104 CB7/NC DQ30 79 M_B_DQ30 5 DQS1_C 32 M_B_DQS_DN0 5 M_B_CLK1 DQ31 80 M_B_DQ31 5 DQS1_T 34 M_B_DQS_DP0 M_B_CLK#1 137 CK0_T DQ32 174 M_B_DQ32 5 DQS2_C 53 M_B_DQS_DN2 5 139 CK0_C DQ33 173 M_B_DQ33 5 DQS2_T 55 M_B_DQS_DP2 5 M_B_CKE0 138 CK1_T/NF DQ34 187 M_B_DQ34 5 DQS3_C 74 M_B_DQS_DN3 M_B_CKE1 140 CK1_C/NF DQ35 186 M_B_DQ35 5 DQS3_T 76 M_B_DQS_DP3 5 DQ36 170 M_B_DQ36 5 DQS4_C 177 M_B_DQS_DN4 5 M_B_CS#0 109 CKE0 DQ37 169 M_B_DQ37 5 DQS4_T 179 M_B_DQS_DP4 M_B_CS#1 110 CKE1 DQ38 183 M_B_DQ38 5 DQS5_C 198 M_B_DQS_DN5 DQ39 182 M_B_DQ39 5 DQS5_T 200 M_B_DQS_DP5 5 M_B_DIMB_ODT0 149 CS0# DQ40 195 M_B_DQ40 5 DQS6_C 219 M_B_DQS_DN6 5 M_B_DIMB_ODT1 157 CS1# DQ41 194 M_B_DQ41 5 DQS6_T 221 M_B_DQS_DP6 162 C0/CS2#/NC DQ42 207 M_B_DQ42 5 DQS7_C 240 M_B_DQS_DN7 SA0_C H B_D IM0 165 C1/CS3#/NC DQ43 208 M_B_DQ43 5 DQS7_T 242 M_B_DQS_DP7 SA1_C H B_D IM0 DQ44 191 M_B_DQ44 5 DQS8_C 95 SA2_C H B_D IM0 155 ODT0 DQ45 190 M_B_DQ45 5 DQS8_T 97 161 ODT1 DQ46 203 M_B_DQ46 5 DQ47 204 M_B_DQ47 5 DM0#/DBI0# 12 256 SA0 DQ48 216 M_B_DQ48 5 DM1#/DBI# 33 260 SA1 DQ49 215 M_B_DQ49 5 54 166 SA2 DQ50 228 M_B_DQ50 5 DM2#/DBI2# 75 DQ51 229 M_B_DQ51 5 DM3#/DBI3# 178 254 SDA DQ52 211 M_B_DQ52 5 DM4#/DBI4# 199 253 SCL DQ53 212 M_B_DQ53 5 DM5#/DBI5# 220 DQ54 224 M_B_DQ54 5 DM6#/DBI6# 241 1D2V_S3 5,12 DDR4_DRAMRST# 108 RESET# DQ55 225 M_B_DQ55 5 DM7#/DBI7# 96 114 ACT# DQ56 237 M_B_DQ56 5 DM8#/DBI#/NC 5 M_B_ACT_N 116 ALERT# DQ57 236 M_B_DQ57 5 134 EVENT#/NF DQ58 249 M_B_DQ58 5 DDR4-260P-23-GP 1 R1312 2 5 M_B_ALERT_N T S#_D IMM1_1 DQ59 250 M_B_DQ59 5 M_VR EF _C A_D IMMB 143 PARITY DQ60 232 M_B_DQ60 5 DY 240R2F-1-GP DQ61 233 M_B_DQ61 5 164 VREFCA DQ62 245 M_B_DQ62 5 5 M_B_PARITY DQ63 246 M_B_DQ63 5 DDR4-260P-23-GP DDR4 SWAP 0212 062.10011.00T1 跟sw確確 21 C1301 1D2V_S3 21 DDR4_DRAMRST# 2 12 1 21 21 21 21 21 21 2 E1 let 2 1 21 21 SC10U6D3V3MX-GP SC1U10V2KX-1GP3D3V_S0 SC10U6D3V3MX-GP SC1U10V2KX-1GP DY ED1302 SC10U6D3V3MX-GP SC1U10V2KX-1GPDYSA0_C H B_D IM0C1303C1305 AZ5725-01FDR7G-GP SC10U6D3V3MX-GP SC1U10V2KX-1GP2 R1302110KR 2F - L1- G PC1304C1306C13 SC10U6D3V3MX-GP SC1U10V2KX-1GP DY DY DY SCD1U16V2KX-3GP 2 1 0R0402-PAD R1303 Layout note: closed to Dimm 3D3V_S0 2 R1306 110KR 2F - L1- G P SA1_C H B_D IM0 2 C1315 C1316 C1317 C1318 C13 R1307D1Y 0R2J-L-GP DY DY 3D3V_S0 1D2V_S3 DY 2 R1310 110KR 2F - L1- G P SA2_C H B_D IM0 2 B RN1301 R1305 1 0R0402-PAD R1311 14 3 M_VREF_CA_DIMMB 1 2 2 V_SM_VREF_CNTB 5 SRN1KJ-7-GP 2R2F-GP C1323 SCD022U16V2KX-3GP +V_VREF_PATH2 R1309 24D9R2F-L-GP A 543

2 1 3D3V_S0 DM2D 4 OF 4 2D5V_S3 1 VSS VSS 99 0D6V_S0 2 VSS VSS 102 2 1 tro2 -1X C1329 DCY1328 DY 5 VSS VSS 103 SCD1U16V2KX-L-GP 6 VSS VSS 106 21 21SC2D2U10V3KX-L-GP 9 VSS VSS 107 D 21 21 10 VSS VSS 167 C 1 M_B_DQS_DN1 5 14 VSS VSS 168 B 1 M_B_DQS_DP1 5 21 15 VSS VSS 171 0 M_B_DQS_DN0 5 21 18 VSS VSS 172 0 M_B_DQS_DP0 5 19 VSS VSS 175 2 M_B_DQS_DN2 5 21 22 VSS VSS 176 2 M_B_DQS_DP2 5 21 23 VSS VSS 180 3 M_B_DQS_DN3 5 21 26 VSS VSS 181 3 M_B_DQS_DP3 5 2127VSS VSS 184 4 M_B_DQS_DN4 5 30 VSS VSS 185 4 M_B_DQS_DP4 5 2131VSSVSS 188 5 M_B_DQS_DN5 5 2135VSSVSS 189 5 M_B_DQS_DP5 5 2136VSSVSS 192 6 M_B_DQS_DN6 5 2139VSSVSS 193 6 M_B_DQS_DP6 5 2140VSSVSS 196 7 M_B_DQS_DN7 5 2143VSSVSS197 7 M_B_DQS_DP7 5 44 VSS VSS 201 47 VSS VSS 202 1D2V_S3 48 VSS VSS 205 51 VSS VSS 206 52 VSS VSS 209 56 VSS VSS 210 57 VSS VSS 213 60 VSS VSS 214 61 VSS VSS 217 64 VSS VSS 218 65 VSS VSS 222 68 VSS VSS 223 69 VSS VSS 226 72 VSS VSS 227 73 VSS VSS 230 77 VSS VSS 231 78 VSS VSS 234 81 VSS VSS 235 82 VSS VSS 238 85 VSS VSS 239 86 VSS VSS 243 89 VSS VSS 244 90 VSS VSS 247 93 VSS VSS 248 94 VSS VSS 251 98 VSS VSS 252 DDR4-260P-23-GP UN 0225 0D6V_S0 0D6V_S0 0D6V_S0 2D5V_S3 C1312 C1313 C1314 DY C1324 C1325 DY C1311 DY C1330 DY C1331 DY SC1U10V2KX-L1-GP SC1U10V2KX-1GPC1326C1327 307 C1308 SC4D7U6D3V2MX-1-GPC1309C1310 DY SC4D7U6D3V2MX-1-GPDY SC4D7U6D3V2MX-1-GP 319 C1320 SC4D7U6D3V2MX-1-GPC1321C1322 DY SC1U10V2KX-1GPDY SC1U10V2KX-1GP SC10U6D3V3MX-GP SC10U6D3V3MX-GP SC10U6D3V3MX-GP SC1U10V2KX-1GP SC10U6D3V3MX-GP SC1U10V2KX-1GP SC10U6D3V3MX-GP SC1U10V2KX-1GP M_B_DQS_DN0 M_B_DQS_DN[7:0] 5 M_B_DQS_DN1 M_B_DQS_DP[7:0] 5 M_B_DQS_DN2 M_B_DQS_DN3 M_B_DQS_DN4 M_B_DQS_DN5 M_B_DQS_DN6 M_B_DQS_DN7 M_B_DQS_DP0 M_B_DQS_DP1 M_B_DQS_DP2 M_B_DQS_DP3 M_B_DQS_DP4 M_B_DQS_DP5 M_B_DQS_DP6 M_B_DQS_DP7 A <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title DDR3-SODIMM1 Size Document Number Rev A2 Vegas SKL/KBL-U A00 Date: Monday, June 27, 2016 Sheet 13 of 106 21

5 Elet43 D (Blanking) C 43 B A 5

321 D C tro-X B <Core Design> Wistron Corporation A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title (Reserved)_SODIMM _SODIMM4 Size Document Number Rev A4 Vegas SKL/KBL-U A00 Date: Thursday, June 16, 2016 Sheet 14 of 105 321

5 4 3 Main Func = PCH 3D3V_S0 CPU1I 9 OF 20 CSI-2 SKYLAKE_ULT R1503 W IFI_RF_EN 1 DY 2 D A36 CSI2_DN0 CSI2_CLKN0 C37 10KR2J-3-GP B36 CSI2_DP0 CSI2_CLKP0 D37 C38 CSI2_DN1 CSI2_CLKN1 C32 DC resistance < 0.5ohm. D38 CSI2_DP1 CSI2_CLKP1 D32 C36 CSI2_DN2 CSI2_CLKN2 C29 D36 CSI2_DP2 CSI2_CLKP2 D29 A38 CSI2_DN3 CSI2_CLKN3 B26 B38 CSI2_DP3 CSI2_CLKP3 A26 C31 CSI2_DN4 CSI2_COMP E13 CSI2_COMP 1 R1501 2 100R2F-L1-GP-U D31 CSI2_DP4 GPP_D4/FLASHTRIG B7 W IFI_RF_EN W IFI_RF_EN 61 C33 CSI2_DN5 D33 CSI2_DP5 EMMC AP2 [#545659 Rev0 A31 CSI2_DN6 AP1 B31 CSI2_DP6 GPP_F13/EMMC_DATA0 AP3 GPP_F: VCCPGPPF = 1.8V Only A33 CSI2_DN7 GPP_F14/EMMC_DATA1 AN3 B33 CSI2_DP7 GPP_F15/EMMC_DATA2 AN1 R1502 GPP_F16/EMMC_DATA3 AN2 A29 CSI2_DN8 GPP_F17/EMMC_DATA4 AM4 B29 CSI2_DP8 GPP_F18/EMMC_DATA5 AM1 C28 CSI2_DN9 GPP_F19/EMMC_DATA6 D28 CSI2_DP9 GPP_F20/EMMC_DATA7 AM2 A27 CSI2_DN10 AM3 B27 CSI2_DP10 GPP_F21/EMMC_RCLK AP4 C27 CSI2_DN11 GPP_F22/EMMC_CLK D27 CSI2_DP11 GPP_F12/EMMC_CMD EMMC_RCOMP AT1 EMMC_RCOMP 1 2 SKYLAKE-U-GP 200R2F-L-GP C 071.SKYLA.000U Elet B A 543

21 D 0.7] C tro-X B <Core Design> A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Document Number CPU_(CS-2/EMMC) Rev A3 Vegas SKL/KBL-U A00 Date: Monday, June 27, 2016 Sheet 15 of 105 21

5 43 Main Func = PCH #543016: CPU1H 8 OF 20 220 nF nominal capacitors are recommended for Gen 3. 100 nF nominal capacitors are recommended for Gen 2. SKYLAKE_ULT PCIE/USB3/SATA SSIC / USB3 PCI E1_RXN/USB3_5_RXN US B 3 _ 1 _ R X N H8 USB30_RX_CPU_N1 36 (#54565 PCI E1_RXP/USB3_5_RXP US B 3 _ 1 _ R X P G8 USB30_RX_CPU_P1 36 76 PEG_RX_CPU_N0 GEN2/GEN3 C1606 1 SCD1U16V2KX-3GP H1 3 PCI E1_TXN/USB3_5_TXN US B 3 _ 1 _ T X N C13 USB30_T X_CPU_N1 36 USB1 (USB3.0 Port1) 76 PEG_RX_CPU_P0 2 PEG_T X_CPU_N0 G13 PCI E1_TXP/USB3_5_TXP US B 3 _ 1 _ T X P D13 USB30_T X_CPU_P1 36 USB2 (USB3.0 Port2) 76 PEG_T X_GPU_N0 2 PEG_T X_CPU_P0 B17 76 PEG_T X_GPU_P0 GEN2/GEN3 1 A17 PCI E2_RXN/USB3_6_RXN USB3_2_RXN/SSI C_RXN J6 USB30_RX_CPU_N2 36 C1605 SCD1U16V2KX-3GP PCI E2_RXP/USB3_6_RXP USB3_2_RXP/SSI C_RXP H6 USB30_RX_CPU_P2 36 SCD1U16V2KX-3GP G11 PCI E2_TXN/USB3_6_TXN USB3_2_TXN/SSI C_TXN B13 USB30_T X_CPU_N2 36 76 PEG_RX_CPU_N1 GEN2/GEN3 C1608 1 2 PEG_T X_CPU_N1 F11 PCI E2_TXP/USB3_6_TXP USB3_2_TXP/SSI C_TXP A13 USB30_T X_CPU_P2 36 76 PEG_RX_CPU_P1 2 PEG_T X_CPU_P1 D16 GPU 76 PEG_T X_GPU_N1 GEN2/GEN3 1 C16 PCIE3_RXN US B 3 _ 3 _ R X N J10 76 PEG_T X_GPU_P1 C1607 SCD1U16V2KX-3GP PCIE3_RXP US B 3 _ 3 _ R X P H1 0 SCD1U16V2KX-3GP H1 6 PCIE3_TXN US B 3 _ 3 _ T X N B15 76 PEG_RX_CPU_N2 GEN2/GEN3 C1610 1 2 PEG_T X_CPU_N2 G16 PCIE3_TXP US B 3 _ 3 _ T X P A15 76 PEG_RX_CPU_P2 2 PEG_T X_CPU_P2 D17 76 PEG_T X_GPU_N2 GEN2/GEN3 1 C17 PCIE4_RXN US B 3 _ 4 _ R X N E10 76 PEG_T X_GPU_P2 C1609 SCD1U16V2KX-3GP PCIE4_RXP US B 3 _ 4 _ R X P F10 SCD1U16V2KX-3GP G15 PCIE4_TXN US B 3 _ 4 _ T X N C15 D 76 PEG_RX_CPU_N3 GEN2/GEN3 C1612 1 2 PEG_T X_CPU_N3 F15 PCIE4_TXP US B 3 _ 4 _ T X P D15 76 PEG_RX_CPU_P3 2 PEG_T X_CPU_P3 B19 76 PEG_T X_GPU_N3 GEN2/GEN3 1 A19 PCIE5_RXN US B 2 N_ 1 AB9 USB_CPU_PN0 36 USB1 (USB3.0 port1) 76 PEG_T X_GPU_P3 C1611 SCD1U16V2KX-3GP PCIE5_RXP US B 2 P _ 1 AB10 USB_CPU_PP0 36 USB2 (USB3.0 Port2) SCD1U16V2KX-3GP F16 PCIE5_TXN USB3 (IO BD/USB2.0 Port3) WLAN 61 PCIE_RX_CPU_N5 C1601 1 2 PCIE_T X_CPU_N5 E16 PCIE5_TXP US B 2 N_ 2 AD6 USB_CPU_PN1 36 Finger Print (USB2.0 Port4) 61 PCIE_RX_CPU_P5 C1602 1 2 PCIE_T X_CPU_P5 C19 US B 2 P _ 2 AD7 USB_CPU_PP1 36 CAMERA (USB2.0 Port5) 61 PCIE_T X_CON_N5 SCD1U16V2KX-3GP D19 PCIE6_RXN Card Reader (USB2.0 Port6) 61 PCIE_T X_CON_P5 PCIE6_RXP A H3 USB_CPU_PN2 37 Touch Panel (USB2.0 Port7) SCD1U16V2KX-3GP G18 PCIE6_TXN AJ3 USB_CPU_PP2 37 WLAN (USB2.0 Port8) LAN 31 PCIE_RX_CPU_N6 2 PCIE_T X_CPU_N6 F18 PCIE6_TXP US B 2 N_ 3 31 PCIE_RX_CPU_P6 2 PCIE_T X_CPU_P6 D20 US B 2 P _ 3 AD9 USB_CPU_PN3 92 31 PCIE_T X_CON_N6 C20 PCI E7_RXN/SATA0_RXN AD10 USB_CPU_PP3 92 31 PCIE_T X_CON_P6 C1603 1 SCD1U16V2KX-3GP PCI E7_RXP/SATA0_RXP US B 2 N_ 4 C1604 1 F20 PCI E7_TXN/SATA0_TXN US B 2 P _ 4 AJ1 USB_CPU_PN4 55 E20 PCI E7_TXP/SATA0_TXP AJ2 USB_CPU_PP4 55 HDD1 60 SAT A_RX_CPU_N0 B21 USB2 US B 2 N_ 5 ODD 60 SAT A_RX_CPU_P0 A21 PCI E8_RXN/SATA1A_RXN US B 2 P _ 5 AF6 USB_CPU_PN5 33 60 SAT A_T X_CPU_N0 PCI E8_RXP/SATA1A_RXP AF7 USB_CPU_PP5 33 60 SAT A_T X_CPU_P0 G21 PCI E8_TXN/SATA1A_TXN US B 2 N_ 6 F21 PCI E8_TXP/SATA1A_TXP US B 2 P _ 6 A H1 USB_CPU_PN6 55 60 SAT A_RX_CPU_N1 D21 A H2 USB_CPU_PP6 55 60 SAT A_RX_CPU_P1 C21 PCIE9_RXN US B 2 N_ 7 60 SAT A_T X_CPU_N1 PCIE9_RXP US B 2 P _ 7 AF8 USB_CPU_PN7 61 60 SAT A_T X_CPU_P1 E22 PCIE9_TXN AF9 USB_CPU_PP7 61 E23 PCIE9_TXP 1. Trace Width: 4 mils min (breakout) 12-15 mils (trace) B23 US B 2 N_ 8 AG1 Note: Must maintain low DC resistance routing (<0.1 ohm). A23 PCIE10_RXN US B 2 P _ 8 AG2 2. Isolation Spacing: At least 12 mils to any adjacent PCIE10_RXP Layout Note: high speed I/O. F25 PCIE10_TXN US B 2 N_ 9 A H7 E25 PCIE10_TXP US B 2 P _ 9 A H8 D23 DC resistance < 0.5ohm. C23 PCI E_RCOMPN AB6 PCI E_RCOMPP US B 2 N_ 1 0 AG3 F5 US B 2 P _ 1 0 AG4 E5 P R O C _ P R D Y# PROC_PREQ# US B 2 _ C O MP A9 USBCOMP 1 R1603 2 113R2F-GP D56 GPP_A7/PI RQA# USB2_I D C9 D61 D9 USB2_ID BB11 PCI E11_RXN/SATA1B_RXN US B 2 _ V B US S E NS E B9 PCIE_RCOMPN PCI E11_RXP/SATA1B_RXP USB2_VBUSSENSE PCIE_RCOMPP E28 PCI E11_TXN/SATA1B_TXN J1 T PAD14-OP-GP R1604 1 2 E27 PCI E11_TXP/SATA1B_TXP G P P _ E 9 /US B 2 _ O C 0 # J2 USB_OC1# USB_OC0# 35 Unused SATA[3:0]GP T PAD14-OP-GP 100R2F-L1-GP-U XDP_PRDY# D24 PCI E12_RXN/SATA2_RXN G P P _ E 1 0 /US B 2 _ O C 1 # J3 USB_OC2# 3.3V rail or GND us T P1601 XDP_PREQ# C24 PCI E12_RXP/SATA2_RXP G P P _ E 1 1 /US B 2 _ O C 2 # USB_OC3# USB_OC2# 35 motherboard. Either T P1602 1 PIRQA# E30 PCI E12_TXN/SATA2_TXN G P P _ E 1 2 /US B 2 _ O C 3 # H2 USB_OC3# 24 1 F30 PCI E12_TXP/SATA2_TXP H3 (#543016) When used as DEV A25 G4 termination required from B25 G P P _ E 4 /D E V S L P 0 HDD_DEVSLP 60 G P P _ E 5 /D E V S L P 1 H1 3D3V_S0 G P P _ E 6 /D E V S L P 2 SIO_EXT _SCI#_R 24 T P1603 T PAD14-OP-GP GPP_E0/SATAXPCI E0/SATAGP0 GPP_E0/SAT AXPCIE0/SAT AGP0 1 GPP_E1/SATAXPCI E1/SATAGP1 GPP_E2/SATAXPCI E2/SATAGP2 GPP_E2/SAT AXPCIE2/SAT AGP2 1 SAT A_ODD_PRSNT # 60 T P1604 T PAD14-OP-GP 10KR2J-3-GP 2 1R1607 PIRQA# G P P _ E 8 /S A T A L E D # SAT A_LED#_R 64 SKYLAKE-U-GP USB2_ID 1 R1601 2 0R0402-PAD 3D3V_S0 USB2_VBUSSENSE 1 R1602 2 0R0402-PAD 071.SKYLA.000U USB_OC2# C SAT A_ODD_PRSNT # R1608 2 USB_OC3# USB_OC0# 1 USB_OC1# 10KR2J-3-GP PCIE Table USB 2.0 Table (#543016) Unused SATAGP[2:0]/GPP_E[2:0] pins must be terminated to either 3.3 V rail or G using 8.2 KΩ to 10 KΩ on the motherboard. Port Device Share BUS Pair Device Do not use both pull-up and pull-down. Either pull-up or pull-down is acceptable. USB3.0_3 1 N/A USB3.0_4 0 USB3.0 port1 2 N/A SATA0 1 USB3.0 Port2 SATA1 3 WLAN 2 USB2.0 Port3 (IOBD) 4 LAN 3 Finger Print 5(L0~L3) GPU 4 CAMERA 6(L3) HDD 5 Card Reader 6(L2) ODD 6 Touch Panel 6(L0~L1) N/A 7 WLAN Elet #545659 (SKL_PCH_U_Y_EDS Rev0.7) B A 543

2 1 D 59) The xHCI controller supports USB Debug port on all USB3.0 capable ports. pins must be terminated to either sing 8.2K
to 10K
on the r pull-up or pull-down is acceptable. VSLP, no external pull-up or pull-down SATA Host DEVSLP. 3D3V_S0 3D3V_S5_PCH 3D3V_S0 R1610 2 RN802 1 SIO_EXT _SCI#_R 1 2 8 3 SAT A_LED#_R 2 R1606 10KR2J-3-GP 7 4 6 1 C 5 10KR2J-3-GP SRN10KJ-6-GP GND (#543611) The SATALED# signal is open-collector and requires a weak external pull-up (8.2 kΩ to 10 kΩ) to Vcc3_3. tro-X B A <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin T ai Wu Rd., Hsichih, T aipei Hsien 221, T aiwan, R.O.C. T itle CPU_(PCIE/SATA/USB) Size Document Number Vegas SKL/KBL-U Rev A1 A00 Monday, June 27, 2016 Date: 1 Sheet 16 of 105 2

5 43 Main Func = PCH 3D3V_S5 RN1704 8 AC_PRESENT 7 PCH_W AKE# 1 6 PCH_BATLOW # 2 5 G PD 11/LAN PH YPC 3 4 GPD11 pull high by Intel PDG1.3 request SRN10KJ-6-GP BATLOW#: Pull-up required even if not implemented. +VCCPDSW _3P3 24,31,40,55,61,68,76,91 PLT_RST# D 3D3V_S5 1 R1711 2 +V3.3A_SIP 100KR 0R0603-PAD R1701 10KR2J-3-GP Layout note: 3 PAD SHARING 21 RTC_AUX_S5 #544669 (CRB): 330k. TPAD14-OP-GP TP1710 1 2 1 Elet PCH_PLTRST# R1730 SM_IN T R U D ER # 21XDP_DBRESET# 40 H_THERMTRIP_EN DY PM_RSMRST# 330KR2J-L1-GP 24 SYS_PW ROK 0R2J-2-G1P R411 H_CPUPW RGD 12 24,26,40 RESET_OUT# H_VCCST_PW RGD_R H_VCCST_PW RG 3D3V_S5_PCH 2 20KR2J-L2-GP EXT_PW R_GATE# #544669 Rev0.52 CRB: 2 2 60D4R2F-GP SYS_PW ROK R1731 1 2 10KR2J-3-GP ME_SUS_PW R_ACK_R No PL resistor on THERMTRIP#. 1 R1734 PM_PCH_PW ROK R1718 1 PCH_DPW ROK H_CPUPW RGD ME_SUS_PW R_A DY PM_RSMRST# 1 R1706 2 0R0402-PAD SUSACK#_R 1 R1704 2 0R2J-2-GP PCH_W AKE# 21 DY R405 DY for OBFF disable GPD2/LAN_W AKE 21 10KR2J-3-GP 1 2 10KR2J-3-GP G PD 11/LAN PH YP RN1701 +VCCPDSW _3P3 R1707 1 4 PM_RSMRST# 2 3 PM_PCH_PW ROK SRN10KJ-5-GP 10KR2J-3-GP SYS_PW ROK (PDG#543016) WAKE#: Ensure that WAKE# signal Trise (Maximum) is <100 ns. R1717 2 DY 1 24 EC_W AKE# 1 R1710 2 GPD2/LAN_W AKE# 0R0402-PAD C 3D3V_S5 SCD1U16V2KX-3GP C1703 +VCCMPHYGTAON_1P0 DY U1702 SKL: 1.0V 24,27,40,51 SIO_SLP_S3# 1 NC DYVCC 5 2 A 4 +VCCMPHYGTAON_1P0(ICCMAX.=3.5A) 3 GND Y +VC C MPH YG T AO N _1P0_LS_SIP 1D0V_S5 U74LVC1G07G-AL5-R-GP 73.01G07.AHG 1 R1724 2 0R0805-PAD 1 R1735 2 C1704 24,40 ALL_SYS_PW RGD 1 SC10U6D3V3MX-GP 2 0R0805-PAD 3 DY 1 R17 100 EC1709 SCD1U16V2KX-3 B ME_SUS_PW R_ACK_R 1 R1708 2 SUSACK#_R ME_SUS_PW R_ACK_R 0R0402-PAD 24 ME_SUS_PW R_ACK 1 R1709 2 0R0402-PAD 3D3V_AUX_S5 R1727 100KR2J-1-GP 12 NON DS3 12 SCD1U16V2KX-3GPR1726 10KR2J-3-GP 21 S Q1701 D 1KR2J-1-GP R1702 4 3 PM_RSMRST# 1 PCH_RSMRST# 24 G G 2 3V_5V_POK# 5 2 3V_5V_POK_C 1 R1728 2 3V_5V_POK 40,45,53,54 1 0R0402-PAD EC1712 S 6 DY D 2N7002KDW -GP A 84.2N702.A3F 2nd = 84.2N702.E3F 3rd = 75.00601.07C 543

21 1 R1713 2 PCH_PLTRST# 21 0R0402-PAD D 21 C R1715 DY DY C1701 B R2J-1-GP SC220P50V2KX-3GP [#543016 Rev0.7] EXT_PWR_GATE#: Due to a bug on A0, a temporary pull-up resistor will be required to overcome the internal 20k pull-down that is active during the early portion of the power up sequence CPU1K 11 OF 20 SYSTEM POWER MANAGEMENT GPP_B12/SLP_S0# AT11 SIO_SLP_S0# 1 TP1701 TPAD14-OP-GP GPD4/SLP_S3# AP15 SKYLAKE_ULT GPD5/SLP_S4# BA16 SIO_SLP_S5# 1 SIO_SLP_S3# 24,27,40,51 AY16 1 SIO_SLP_S4# 24,40,44,51 AN10 GPP_B13/PLTRST# GPD10/SLP_S5# SLP_SUS# 1 B5 SYS_RESET# AN15 SLP_LAN# 1 TP1703 TPAD14-OP-GP RSMRST# SLP_SUS# AW15 GPD9/SLP_W LAN# 1 TP1702 TPAD14-OP-GP AY17 SLP_LAN# BB17 SIO_SLP_A# TP1704 TPAD14-OP-GP GPD9/SLP_WLAN# AN16 1 TP1705 TPAD14-OP-GP GD A68 PROCPWRGD GPD6/SLP_A# AC_PRESENT TP1706 TPAD14-OP-GP B65 VCCST_PWRGD BA15 PCH_BATLOW # GPD3/PWRBTN# AY15 B6 SYS_PWROK GPD1/ACPRESENT AU13 SIO_PW RBTN# 24 K BA20 PCH_PWROK DSW_PWROK GPD0/BATLOW# BB20 GPP_A11/PME# ACK_R AR13 GPP_A13/SUSWARN#/SUSPWRDNACK INTRUDER# AP11 GPP_A15/SUSACK# GPP_B11/EXT_PWR_GATE# BB15 WAKE# GPP_B2/VRALERT# AU11 PME# TP1707 TPAD14-OP-GP AM15 GPD2/LAN_WAKE# AP16 SM_IN T R U D ER # E# AW17 GPD11/LANPHYPC AC_PRESENT PC AT15 GPD7/RSVD#AT15 AM10 EXT_PW R_GATE# EC1707 AM11 SCD1U16V2KX-3GP 21 DY SKYLAKE-U-GP 071.SKYLA.000U D1702 K AC O K_IN 24,44 A 3D3V_S5 +VCCSTG RB751V-40H-GP C1702 SCD1U16V2KX-3GP SD 83.R2004.G8F Q1702 3D3V_AUX_S5 tro-X 21 43 AC_PRESENT 21 R1737 PM_RSMRST# DY R1722 G5 G 100KR2J-1-GP 1 NON D2S3 PM_RSMRST#_M 2 DY 100KR2J-1-GP NON DS3 61 U1701 DS NC DYVCC 5 H_VCCST_PW RGD_R 2N7002KDW -GP A 4 84.2N702.A3F GND Y 2nd = 84.2N702.E3F 3rd = 75.00601.07C U74LVC1G07G-AL5-R-GP 73.01G07.AHG DY21 EC1708 SCD01U50V2KX-1GP 2 21 R1719 716 47KR2F-GP 0KR2F-L1-GP 3GP XDP_DBRESET# SYS_PW ROK PLT_RST# RESET_OUT# 3V_5V_POK EC1705 DY SC1KP50V2KX-1GP DY DY DY EC1706 21 EC1702 EC1703 SC1KP50V2KX-1GP #543016 Rev0.7 21 1. VCCST_PWRGD is only 1.0 V tolerant. 2. VCCST_PWRGD must go low during Sx pwr states, regardless of the voltage level of VCCST SC1KP50V2KX-1GP 21 AZ5325-01FDR7G-GP EU1701 21 SC1KP50V2KX-1GP 21 A <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title CPU_(POWER MANAGEMENT) Size Document Number Rev A2 Vegas SKL/KBL-U A00 Date: Monday, June 27, 2016 Sheet 17 of 105 21

5 PCH strap pin: 4 PCH strap pin: 3 PCH Prim 24,68,91 Main Func = PCH 3D3V_S5_PCH eSPI or LPC Sampled at rising edge of RSMRST# BOOT HALT SML0ALERT# / This signal has a weak internal pull-down. GPP_C5 0 = LPC Is selected for EC. 1 = eSPI Is selected for EC. 21 DY R1822 SPI0_MOSI 0 = ENABLED 2 12 1 1 = DISABLED This signal has a weak internal pull-down. 1KR2J-1-GP W EAK INTERNAL PU Elet DY R1823 This signal has a weak internal pull-up. G PP_C 5/SML0ALER T # 1KR2J-1-GP D R1835 and R1834 merge to RN1802 Follow Starlord 3D3V_S5_PCH RN1802 SPI_H O LD _R O M 14 SPI_W P_ROM 23 SRN1KJ-7-GP 3D3V_S0 CPU1E 5 Resister value will check later SPI - FLASH SMBUS, SMLINK R2021 2 SIO _R C IN # 24,25 SPI_CLK_ROM 0R0402-PAD 1 R1806 2 SPI_C LK_C PU AV2 SPI0_CLK Strap SKYLAKE_ULT GPP_C0/SM 2 SER IR Q 24,25 SPI_SO_ROM 0R0402-PAD 1 R1807 2 SPI_SO _C PU AW3 SPI0_MISO LPC GPP_C1/SM 1 0R0402-PAD 1 R1808 2 SPI_SI_C PU SPI0_MOSI GPP_C2/SMBA 10KR2J-3-GP 24,25 SPI_SI_ROM 0R0402-PAD 1 R1809 2 SPI_W P_CPU AV3 SPI0_IO2 24,25 0R0402-PAD 1 R1811 2 SPI_H O LD _C PU AW2 SPI0_IO3 GPP_C3/SM R2032 25 SPI_W P_ROM 0R0402-PAD 1 R1812 2 SPI_C S_C PU _N 0 AU4 SPI0_CS0# GPP_C4/SML 25 SPI_HOLD_ROM AU3 SPI0_CS1# GPP_C5/SML0A 1 SPI_C S_R O M_N 0 AU2 SPI0_CS2# 10KR2J-3-GP AU1 Strap SERIRQ PH: TPAD14-OP-GP TP1801 1 CPU_D1_TP M2 SPI - TOUCH GPP_C6/SM PDG: 8.2k M3 GPP_C7/SML CRB: 10k 1 CPU_D3_TP GPP_D1/SPI1_CLK GPP_B23/SML1ALERT#/PC 1 CPU_D4_TP J4 GPP_D2/SPI1_MISO 67 HDD_FALL_INT TPAD14-OP-GP TP1803 1 CPU_D5_TP V1 GPP_D3/SPI1_MOSI DVT1 add FFS 2/18 TPAD14-OP-GP TP1804 1 CPU_D6_TP V2 GPP_D21/SPI1_IO2 TPAD14-OP-GP TP1805 M1 GPP_D22/SPI1_IO3 TPAD14-OP-GP TP1806 GPP_D0/SPI1_CS# GPP_A1/LAD0/ES GPP_A2/LAD1/ES C GPP_A3/LAD2/ES GPP_A4/LAD3/ES 61 CL_CLK G3 C LINK GPP_A5/LFRAME#/ESP G2 GPP_A14/SUS_STAT#/ESPI_R 61 CL_DATA G1 CL_CLK CL_DATA GPP_A9/CLKOUT_LPC0/ESP 61 CL_RST# CL_RST# GPP_A10/CLKOUT GPP_A8/CL RCIN#: 24 SIO _R C IN # AW13 GPP_A0/RCIN# Frequency to Avoid: 33 MHz AY11 GPP_A6/SERIRQ 24,91 SER IR Q SCD1U16V2KX-3GP SKYLAKE-U-GP 20140820 D EC1805 071.SKYLA.000U DY 3D3V_S0 RN1812 1 8 CLKREQ_PCIE#5 2 7 CLKREQ_PEG#0 3 6 CLKREQ_PCIE#1 4 5 CLKREQ_PCIE#2 B SRN10KJ-6-GP 4 CLKREQ_PCIE#3 3 CLKREQ_PCIE#4 RN1813 1 2 SRN10KJ-5-GP CPU1J SC3 10 OF 20 GPU 76 PEG_CLK_CPU# D42 CLKOUT_PCIE_N0 CLOCK SIGNALS WLAN 76 PEG_CLK_CPU C42 CLKOUT_PCIE_P0 SKYLAKE_ULT 79 CLKREQ_PEG#0 AR10 GPP_B5/SRCCLKREQ0# LAN CLKREQ_PEG#0 CLKOUT_ITPXDP_N F4 61 PEG_CLK1_CPU# C LKR EQ _PC IE#1 B42 CLKOUT_PCIE_N1 CLKOUT_ITPXDP_P E 61 PEG_CLK1_CPU C LKR EQ _PC IE#3 A42 CLKOUT_PCIE_P1 61 CLKREQ_PCIE#1 C LKR EQ _PC IE#4 AT7 GPP_B6/SRCCLKREQ1# GPD8/SUSCLK B C LKR EQ _PC IE#5 31 PEG_CLK2_CPU# D41 CLKOUT_PCIE_N2 XTAL24_IN E 31 PEG_CLK2_CPU 4 C41 CLKOUT_PCIE_P2 XTAL24_OUT E 31 CLKREQ_PCIE#2 AT8 GPP_B7/SRCCLKREQ2# XCLK_BIASREF E A D40 CLKOUT_PCIE_N3 C40 CLKOUT_PCIE_P3 RTCX1 A AT10 GPP_B8/SRCCLKREQ3# RTCX2 A B40 CLKOUT_PCIE_N4 SRTCRST# A A40 CLKOUT_PCIE_P4 RTCRST# A AU8 GPP_B9/SRCCLKREQ4# E40 CLKOUT_PCIE_N5 E38 CLKOUT_PCIE_P5 AU7 GPP_B10/SRCCLKREQ5# SKYLAKE-U-GP 071.SKYLA.000U 5 3

2 1 PCH Prim 3D3V_S5_PCH 3D3V_S5_PCH SPI_SI_C PU DY R18242 12 1 SML1_SMBDATA RN1807 1 1KR2J-1-GP SML1_SMBCLK 8 2 SML0_SMBDATA 7 3 DY R1825 SML0_SMBCLK 6 4 5 1KR2J-1-GP G PP_B23/SML1ALER T # SRN2K2J-4-GP R1820 D 150KR2F-L-GP C 21 G PP_C 2/SMBALER T # R1821 21 MEM_SMBCLK MEM_SMBDATA 2K2R2J-2-GP LPC _LAD [3..0] SRN2K2J-1-GP 32 41 RN1811 1 LPC_LAD[3..0] RN1806 81 LPC_LAD2 72 LPC_LAD2_R LPC_LAD1 63 LPC_LAD1_R LPC_LAD3 54 LPC_LAD3_R LPC_LAD0 LPC_LAD0_R SRN0J-7-GP-U 5 OF 20 MBCLK R7 MEM_SMBCLK 3D3V_S5_PCH MBDATA R8 MEM_SMBDATA R10 G PP_C 2/SMBALER T # R1814 ALERT# R9 SML0_SMBCLK SUS_STAT#/LPCPD# 2 DY 1 ML0CLK W2 SML0_SMBDATA L0DATA W1 G PP_C 5/SML0ALER T # 10KR2J-3-GP 3D3V_S0 ALERT# W3 SML1_SMBCLK SML1_SMBCLK 24,79 CLKRUN#_R R1818 ML1CLK V3 SML1_SMBDATA SML1_SMBDATA 24,79 8K2R2F-1-GP L1DATA AM7 G PP_B23/SML1ALER T # 12 CHHOT# SPI_IO0 AY13 LPC_LAD0_R 2 R1801 1 0R0402-PAD LPC_LFRAME# 24,68,91 3D3V_S0 SPI_IO1 BA13 LPC_LAD1_R SPI_IO2 BB13 LPC_LAD2_R SUS_STAT#/LPCPD# 91 2N7002KDW -GP SPI_IO3 AY12 LPC_LAD3_R 61 BA12 LPC_LFRAME#_R PC I_C LK_LPC 0 91 52 RN1810 2 3D3V_S0 PI_CS# BA11 43 1 RESET# PC I_C LK_LPC 1 12 3 AW9 CLKRUN#_R R1819 Q1801 4 PI_CLK AY9 T_LPC1 AW11 0R2J-2-GP CLKRUN# 24,91 LKRUN# SRN10KJ-5-GP MEM_SMBDATA PCH_SMBDATA 12,13,56,65,67 84.2N702.A3F DAIVD tro-X 2nd = 84.2N702.E3F PC I_C LK_LPC 0 R1804 1 LPC 2 0R2J-2-GP CLK_PCI_LPC 68 24 3rd = 75.00601.07C PCH_SMBCLK 12,13,56,65,67 21PC I_C LK_LPC 1 2 0R0402-PAD C LK_PC I_LPC _MEC 1 R1805 MEM_SMBCLK DY21 SC10P50V2JN-4GP 21 EC1801 B 1 2 RTC_X1 XTAL24_IN 1 R1810 2 XT AL24_IN _R C1801 R1815 10MR2J-L-GP RTC_X2 XTAL24_OUT 21 X1802 4 C1803 0R0402-PAD SC3D9P50V2CN-1GP 1 SC15P50V2JN-2-GP 21 R1802 32 X1801 1MR2J-1-GP 41 XTAL-24MHZ-81-GP 82.30004.841 23 C1804 C1802 3D9P50V2CN-1GP 21 XTAL-32D768KHZ-68-GP SC15P50V2JN-2-GP 82.30001.G01 2rd = 82.30001.G11 43 PC IE_C LK_XD P_N 1 TP1807 TPAD14-OP-GP SUSCLK_R E43 PC IE_C LK_XD P_P 1 TP1808 TPAD14-OP-GP RTC_AUX_S5 21 BA17 SUSCLK_R 2 0R0402-PAD SUS_CLK 24 21 1 R1813 DY EC1803 E37 XTAL24_IN +V1.00A_SIP 12 E35 XTAL24_OUT SC4D7P50V2BN-GP 1 R1803 2 32 RN1901 E42 XC LK_BIASR EF 41 SRN20KJ-1-GP 2K7R2F-GP AM18 RTC_X1 AM20 RTC_X2 Intel recommend: 2.71k ohm 5% AN18 SRTC_RST# Q1901 AM16 RTC_RST# G 24 RTCRST_ON A 21 D SRTC_RST# 21 RTC_RST# R1902 SC1U10V2KX-1GP 10KR2J-3-GP S C1901 21 G1901 21 12 SCD1U16V2KX-3GP <Core Design> EC1807 SCD1U16V2KX-3GP EC1806 GAP-OPEN EC1808 SCD1U16V2KX-3GP DY 2N7002K-2-GP C1902 SC1U10V2KX-1GP 84.2N702.J31 2ND = 84.2N702.031 DY DY Wistron Corporation 3rd = 84.07002.I31 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, (#514849) Taipei Hsien 221, Taiwan, R.O.C. Layout: Place at the open door area. Title CPU_(LPC/SPI/SMBUS/CL/CLK) Document Number Size Vegas SKL/KBL-U Rev A2 Monday, June 27, 2016 Sheet 18 of A00 D ate: 105 2 1

5 4 3 Main Func = PCH PCH strap pin: Flash Descriptor Security Overide/ D Intel ME Debug Mode CPU1G HDA_SDOUT Low = Default * AUDIO High = Enable HDA_SYNC/I2S0_SFRM HDA_BLK/I2S0_SCLK The internal pull-down is disabled after HDA_SYNC BA22 HDA_SDO/I2S0_TXD PLTRST# deasserts HDA_BITCLK AY22 HDA_SDI0/I2S0_RXD HDA_SDOUT BB22 HDA_SDI1/I2S1_RXD BA21 HDA_RST#/I2S1_SCLK 27 HDA_SDIN0 AY21 GPP_D23/I2S_MCLK AW 22 I2S1_SFRM I2S1_TXD J5 AY20 GPP_F1/I2S2_SFRM AW 20 GPP_F0/I2S2_SCLK GPP_F2/I2S2_TXD AK7 GPP_F3/I2S2_RXD DY21FC1902 AK6 SC2P50V2CN-GP AK9 EletAK10 C H5 GPP_D19/DMIC_CLK0 D7 GPP_D20/DMIC_DATA0 24,79,85 DGPU_PWROK D8 GPP_D17/DMIC_CLK1 27 SPKR C8 GPP_D18/DMIC_DATA1 AW 5 GPP_B14/SPKR SKYLAKE-U-GP 071.SKYLA.000U PCH strap pin: 3D3V_S0 1 DY 2 1KR2J-1-GP SPKR R2006 B NO REBOOT * Low = Enable (Default) R1904 1 UMA2 100KR2J-1-GP DGPU_P HDA_SPKR High = Disable DYEC1901 1 2 SC10P50V2JN-4GP HDA_CO SC1KP50V2KX-1GP DGPU_P The internal pull-down is disabled after EC1903 2 DY1 PLTRST# deasserts A 543

321 7 OF 20 D C SKYLAKE_ULT SDIO/SDXC AB11 KB_LED_BL_DET_R 65 AB13 GPP_G0/SD_CMD AB12 CPU_A16_TP 1 TP1902 GPP_G1/SD_DATA0 W 12 TPAD14-OP-GP GPP_G2/SD_DATA1 W 11 GPP_G3/SD_DATA2 W 10 SD_RCOMP 1 R1901 2 GPP_G4/SD_DATA3 W8 W7 200R2F-L-GP GPP_G5/SD_CD# GPP_G6/SD_CLK BA9 BB9 GPP_G7/SD_W P AB7 GPP_A17/SD_PW R_EN#/ISH_GP7 GPP_A16/SD_1P8_SEL AF13 SD_RCOMP GPP_F23 tro-X 1 R1907 2 0R0402-PAD HDA_BITCLK B 1 R1908 2 0R0402-PAD HDA_SYNC 21 27 HDA_CODEC_BITCLK 27 HDA_CODEC_SYNC PW ROK 27 HDA_CODEC_SDOUT 1 R1912 2 0R0402-PAD HDA_SDOUT ODEC_BITCLK 1 2 1KR2J-1-GP PW ROK 24 ME_FW P_EC R1909 3 DY FC1901 SC2P50V2CN-GP <Core Design> Wistron Corporation A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size CPU_(AUDIO/SDIO/SDXC) Rev A4 Document Number A00 Vegas SKL/KBL-U 105 Date: Monday, June 27, 2016 Sheet 19 of 2 1

5 4 3 Main Func = PCH EC2002 2 DY1 DGPU_HOLD_RST# 76 SC1KP50V2KX-1GP CPU1F RN2009 4 DGPU_HOLD_RST# LPSS 1 3 DGPU_PW R_EN SKYLAKE_ULT 2 DY AN8 GPP_B15/GSPI0_CS# AP7 GPP_B16/GSPI0_CLK G SRN10KJ-5-GP AP8 GPP_B17/GSPI0_MISO G AR7 GPP_B18/GSPI0_MOSI GPP_D13/ISH_UAR (PDG#543016) If the UART/GPIO functionality is also not used, VR AM_ID 1 Strap GPP_D14/ISH_U GPP_B18/GSPI0_MOSI AM5 GPP_B19/GSPI1_CS# GPP_D16 D 3D3V_S0 the signals can be left as no-connect. 55 DBC_PANEL_EN AN7 GPP_B20/GSPI1_CLK TPAD14-OP-GP 1 GPP_B22 AP5 GPP_B21/GSPI1_MISO R2048 1 DY 2 51KR2J-1-GP LPSS_UART2_RXD TP2008 AN5 GPP_B22/GSPI1_MOSI R2049 1 2 51KR2J-1-GP LPSS_UART2_TXD BO AR D _ID 2 R2046 1 1 2 51KR2J-1-GP 61 BLUETOOTH_EN LPSS_UART2_RXD AB1 GPP_C8/UART0_RXD R2002 1 2 2 10KR2J-3-GP LPSS_UART2_CTS# LPSS_UART2_TXD AB2 GPP_C9/UART0_TXD BLUETOOTH_EN 24 SIO_EXT_W AKE# LPSS_UART2_CTS# GPP_C10/UART0_RTS# 4 W4 GPP_C11/UART0_CTS# 3 DBC_PANEL_EN AB3 KB_DET# GPP_C20/UART2_RXD AD1 GPP_C21/UART2_TXD RN2012 AD2 GPP_C22/UART2_RTS# SRN10KJ-5-GP AD3 GPP_C23/UART2_CTS# AD4 RN2010 4 I2C 0_SD A_T C H _PAD PTP 65 I2C0_SDA_TCH_PAD U7 GPP_C16/I2C0_SDA GPP_C 3 I2C 0_SC L_T C H _PAD 65 I2C0_SCL_TCH_PAD U6 GPP_C17/I2C0_SCL GPP_C 1 GPP_C1 RTC_DET# PCH Prim U8 GPP_C18/I2C1_SDA GPP_C1 2 DY SIO_EXT_W AKE# 3D3V_S5_PCH U9 GPP_C19/I2C1_SCL SX_EXIT_HOLDOF SRN2K2J-1-GP AH9 GPP_F4/I2C2_SDA AH10 GPP_F5/I2C2_SCL 3D3V_S5_PCH SRN10KJ-5-GP RN2011 AH11 GPP_F6/I2C3_SDA 1 AH12 GPP_F7/I2C3_SCL 2 4 3 AF11 GPP_F8/I2C4_SDA AF12 GPP_F9/I2C4_SCL 2 12 1DY R2007 SKYLAKE-U-GP 65 1KR2J-1-GP 071.SKYLA.000U Elet PCH strap pin: No Reboot Sampled at rising edge of PCH_PW ROK GPP_B18/GSPI0_MOSI GSPI0_MOSI / 0 = Disable “No Reboot” mode. DY R2019 For debug USB/UART: GPP_B18 1 = Enable “No Reboot” mode (PCH will disable the TCO 1KR2J-1-GP 5V_S5 C Timer system reboot feature). This function is useful LPSS_UART2_TXD 10 LPSS_UART2_RXD when running ITP/XDP. Veg The signal has a weak internal pull-down. DB2 PRO 1 10 2 DY 20.F1897.004 3 4 TPAD14-OP-GP ACES-CON4-37-GP TP2009 1LPSS_U AR T 2_C T S# Intel has removed EHCI controller from BDW BOARD and proposed to use UART interface for Win7 debug. B V VR AM_ID 1 VRAM A 543

2 1 3D3V_S0 SRN10KJ-5-GP RN2007 6 OF 20 I2C 0_SC L 14 I2C 0_SD A ISH 2 DY 3 I2C 1_SC L GPP_D9 P2 USB_UART_SEL_D9 1 TP2006 TPAD14-OP-GP I2C 1_SD A RN2008 GPP_D10 P3 DGPU_HOLD_RST# RTC_DET# 25 GPP_D11 P4 1 DY 4 GPP_D12 P1 RTC_DET# 3 2 GPP_D5/ISH_I2C0_SDA M4 I2C 0_SD A GPP_D6/ISH_I2C0_SCL N3 I2C 0_SC L SRN2K2J-1-GP GPP_D7/ISH_I2C1_SDA N1 I2C 1_SD A (PDG#543016) Ensure that all I2C interface on-board terminations are pulled up D GPP_D8/ISH_I2C1_SCL N2 I2C 1_SC L to the same voltage rail as the device/end point. C B GPP_F10/I2C5_SDA/ISH_I2C2_SDA AD11 1.8V Only GPP_F11/I2C5_SCL/ISH_I2C2_SCL AD12 RT0_RXD/SML0BDATA/I2C4B_SDA U1 UART0_TXD 1 TP2007 TPAD14-OP-GP DGPU_PW R_EN 85,86 UART0_TXD/SML0BCLK/I2C4B_SCL U2 UART0_RTS# 1 TP2010 TPAD14-OP-GP CAMERA_DET# U3 UART0_CTS# 1 TP2011 TPAD14-OP-GP GPP_D15/ISH_UART0_RTS# U4 6/ISH_UART0_CTS#/SML0BALERT# UART1_RXD 1 TP2012 TPAD14-OP-GP AC1 F F S_IN T 2 C12/UART1_RXD/ISH_UART1_RXD AC2 67 3D3V_S0 C13/UART1_TXD/ISH_UART1_TXD AC3 14/UART1_RTS#/ISH_UART1_RTS# AB4 UART1_CTS# 1 DVT1 add FFS 2/18 R2003 15/UART1_CTS#/ISH_UART1_CTS# TP2015TPAD14-OP-GP 110KR 2J - 3- G2P AY8 PR O J EC T _ID 1 GPP_A18/ISH_GP0 BA8 PR O J EC T _ID 2 KB_DET# 65 GPP_A19/ISH_GP1 BB7 KB_DET# CAMERA_DET# 55 GPP_A20/ISH_GP2 BA7 CAMERA_DET# GPP_A21/ISH_GP3 AY7 TPM_SELECT GPP_A22/ISH_GP4 AW7 GPP_A23/ISH_GP5 AP13 PAN EL_SIZ E_ID 55 FF#/GPP_A12/BM_BUSY#/ISH_GP6 3D3V_S0 3D3V_S0 BIOS strap pin: GPP_A19 GPP_A18 PROJECT_ID2 PROJECT_ID1 R2015 2 12 1 R2017 SKL2 12 1 PROJECT Strap pin 0KR2J-3-GP 10KR2J-3-GP Turis X 0 Vegas X 1 gas PR O J EC T _ID 2 KBL 0 X SKL 1 X O J EC T _ID 1 R2018 KBL 10KR2J-3-GP R2016 0KR2J-3-GP Turis tro-X 3D3V_S0 3D3V_S0 OPS2 12 1 R2005 BIOS strap pin: GPP_C11 R2022 2 12 1TPM BIOS strap pin: GPP_A22 10KR2J-3-GP BOARD_ID2 10KR2J-3-GP TPM_SELECT BIOS UMA/DIS Strap pin BIOS UMA/DIS Strap pin _ID 2 UMA 0 TPM_SELECT TPM 1 DIS 1 0 NON_TPM R2008 R2020 10KR2J-3-GP NON_TPM UMA 10KR2J-3-GP 3D3V_S0 VRAM_2G2 12 1 R2023 BIOS strap pin: GPP_B17 10KR2J-3-GP VRAM_ID1 BIOS VRAM Size Strap pin 1 4G 0 2G 1 R2024 M_4G 10KR2J-3-GP A <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size CPU_(LPSS/ISH) Rev A2 Document Number A00 Vegas SKL/KBL-U Date: Monday, June 27, 2016 Sheet 20 of 105 21

5 43 Main Func = PCH +V1.00A_SIP CPU1O 15 OF 20 D CPU POW ER 4 OF 4 +VCCPRIM_CORE AB19 VCCPRIM_1P0 SKYLAKE_ULT VCCPGPPA AK15 AB20 VCCPRIM_1P0 VCCPGPPB AG15 VCCPRIM_1P0 VCCPGPPC Y16 P18 VCCPGPPD Y15 2.57A VCCPRIM_CORE VCCPGPPE T16 AF18 VCCPRIM_CORE VCCPGPPF AF16 AF19 VCCPRIM_CORE 1.8V Only VCCPGPPG AD15 VCCPRIM_CORE +VCCDSW _1P0 V20 V19 EC2101 C2120 +V1.00A_SIP V21 DCPDSW _1P0 VCCPRIM_3P3 T1 DY +VCCMPHYGTAON_1P0_LS_SIP AL1 SC1U10V2KX-1GP21 AA1 SCD1U25V2KX-L-GP 21 K17 VCCMPHYAON_1P0 VCCPRIM_1P0 21 21 L1 VCCMPHYAON_1P0 AK17 21 21 N15 VCCATS_1P8 AK19 21 N16 BB14 21 N17 VCCMPHYGT_1P0 VCCRTCPRIM_3P3 21 P15 VCCMPHYGT_1P0 BB10 21 P16 VCCMPHYGT_1P0 VCCRTC VCCMPHYGT_1P0 VCCRTC A14 K15 VCCMPHYGT_1P0 L15 K19 +VCCAMPHYPLL_1P0 VCCAMPHYPLL_1P0 DCPRTC V15 VCCAMPHYPLL_1P0 L21 +VCCAPLL_1P0 +V1.00A_SIP AB17 VCCCLK1 N20 Y18 +VCCPDSW _3P3 VCCAPLL_1P0 L19 C AD17 AD18 VCCCLK2 A10 +V3.3A_SIP AJ17 +VCCPAZIO VCCPRIM_1P0 VCCCLK3 AN11 AJ19 VCCPRIM_1P0 AN13 1 R2101 2 0R0402-PAD AJ16 VCCDSW _3P3 VCCCLK4 VCCDSW _3P3 +V3.3A_SIP AF20 VCCDSW _3P3 VCCCLK5 +VCCMPHYGTAON_1P0_LS_SIP AF21 VCCHDA VCCCLK6 +V3.3A_SIP T19 +V1.00A_SIP T20 VCCSPI GPP_B0/CORE_VID0 GPP_B1/CORE_VID1 +VCCMPHYGTAON_1P0_LS_SIP AJ21 VCCSRAM_1P0 AK20 VCCSRAM_1P0 VCCSRAM_1P0 N18 VCCSRAM_1P0 VCCPRIM_3P3 VCCPRIM_1P0 VCCAPLLEBB_1P0 21 SKYLAKE-U-GP Elet 071.SKYLA.000U B +V1.8A_SIP +VCCD +V3.3A_SIP Layout Note: DY SCD1U16V2KX-3GPDYDY DY 1uF: near V19 SC1U10V2KX-1GP C2111 C2105 near AK17 C2108 C2106 near AG15 SCD1U16V2KX-3GP C2107 near Y16 C2110 C2109 near T16 C2110 near AJ19 SC1U10V2KX-1GP C2111 C2109 SC1U10V2KX-1GP C2107 SC1U10V2KX-1GP C2106 SC1U10V2KX-1GP C2105 +VCCAMPHYPLL_1P0 Layout Note: +VCCAPLL_1P0 Layout Note: +V1.00A_SIP +V1.00A_SIP A 22uF: 22uF: SC22U6D3V3MX-1-GP C2113 near K15 SC22U6D3V3MX-1-GP C2113 near K15 SC22U6D3V3MX-1-GP C2113 C2114 C2122 SC1U10V2KX-1GP C2116 21 21 DY DY DY 543

2 1 RTC_AUX_S5 C2119 C2118 C2117 SC1U10V2KX-1GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP +V3.3A_SIP2 1 tro-X DY 5 21 D 5 21 C 21 6 +V1.8A_SIP CAP need close to VCCRTC 5 +V3.3A_SIP 21 21 21+V1.00A_SIPRTC_AUX_S5+VCCPRTC_3P3 +V1.8A_SIP 1 R2107 2 7 +V3.3A_SIP +VCCPRTC_3P3 0R0603-PAD-2-GP-U 9 +VCCMPHYGTAON_1P0_LS_SIP R2112 +VCCAMPHYPLL_1P0 4 0 VCCRTCEXT C2112 1 2 SCD1U16V2KX-3GP 12 +V1.00A_SIP 0R3J-0-U-GP +V1.00A_SIP R2108 +VCCAPLL_1P0 1 0R3J-0-U-GP 2 1 1 TP2102 TPAD14-OP-GP 3 V0.85A_VID1 B DSW _1P0 +V1.00A_SIP Layout Note: SC1U10V2KX-1GPDYDY1uF: near AB19 C2121 C2101 near K17 C2104 near A10 SC1U10V2KX-1GP C2116 near AL1 C2104 C2121 SC1U10V2KX-1GP C2101 SC1U10V2KX-1GP C2103 Layout Note: 1uF: near A10 <Core Design> A C2116 22uF: near K19 Wistron Corporation C2115 near N20 C2119 near L19 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, C2122 Taipei Hsien 221, Taiwan, R.O.C. Title Size Document Number CPU_(POWER1) Rev A3 Friday, June 24, 2016 Vegas SKL/KBL-U A00 Date: Sheet 21 of 105 1 2

5 43 Main Func = PCH CPU1T 20 OF D SKYLAKE_ULT RSVD# SPARE RSVD#E C RSVD#C AW 69 RSVD#AW 69 RSVD#B B AW 68 RSVD#AW 68 RSVD#A RSVD#AU56 RSVD#D AU56 RSVD#AW 48 RSVD#C AW 48 RSVD#C7 RSVD#F RSVD#U12 C7 RSVD#U11 U12 RSVD#H11 U11 H11 SKYLAKE-U-GP Elet 071.SKYLA.000U A 543

3 21 D F 20 #F6 F6 C E3 E3 C11 C11 B11 B11 A11 A11 D12 D12 C12 C12 F52 F52 tro-X B <Core Design> Wistron Corporation A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size CPU_(RSVD) Rev A4 Document Number A00 Vegas SKL/KBL-U 105 Date: Thursday, June 16, 2016 Sheet 22 of 2 1 3

5 43 Main Func = PCH CPU1P 16 OF 20 GND 1 OF 3 TPAD14-OP-GP CPU1Q 17 OF 20 1NCTF_A5 TP2307 A5 VSS SKYLAKE_ULT VSS AL65 1NCTF_A70 A67 VSS VSS AL66 D A70 VSS VSS AM13 GND 2 OF 3 TP2301 AA2 VSS VSS AM21 AA4 VSS VSS AM25 AA65 VSS VSS AM27 AT63 VSS SKYLAKE_ULT VSS BA49 AA68 VSS VSS AM43 AT68 VSS VSS BA53 TPAD14-OP-GP AB15 VSS VSS AM45 AT71 VSS VSS BA57 AB16 VSS VSS AM46 AU10 VSS VSS BA6 C AB18 VSS VSS AM55 AU15 VSS VSS BA62 AB21 VSS VSS AM60 AU20 VSS VSS BA66 AB8 VSS VSS AM61 AU32 VSS VSS EletBA71 AD13 VSS VSS AM68 AU38 VSS VSS BB18 B AD16 VSS VSS AM71 VSS VSS BB26 AD19 VSS VSS AM8 AV1 VSS VSS BB30 AD20 VSS VSS AN20 TP2305 1NCTF_BA1 AV68 VSS VSS BB34 AD21 VSS VSS AN23 TPAD14-OP-GP AV69 VSS VSS BB38 AD62 VSS VSS AN28 AV70 VSS VSS BB43 AD8 VSS VSS AN30 AV71 VSS VSS BB55 AE64 VSS VSS AN32 AW 10 VSS VSS BB6 AE65 VSS VSS AN33 AW 12 VSS VSS BB60 AE66 VSS VSS AN35 AW 14 VSS VSS BB64 AE67 VSS VSS AN37 AW 16 VSS VSS BB67 AE68 VSS VSS AN38 AW 18 VSS VSS BB70 AE69 VSS VSS AN40 AW 21 VSS VSS C1 AF1 VSS VSS AN42 AW 23 VSS VSS C25 AF10 VSS VSS AN58 AW 26 VSS VSS C5 AF15 VSS VSS AN63 AW 28 VSS VSS D10 AF17 VSS VSS AP10 AW 30 VSS VSS D11 AF2 VSS VSS AP18 AW 32 VSS VSS D14 AF4 VSS VSS AP20 AW 34 VSS VSS D18 AF63 VSS VSS AP23 AW 36 VSS VSS D22 AG16 VSS VSS AP28 AW 38 VSS D25 AG17 VSS VSS AP32 VSS VSS D26 AG18 VSS VSS AP35 AW 41 VSS VSS D30 AG19 VSS VSS AP38 AW 43 VSS VSS D34 AG20 VSS VSS AP42 AW 45 VSS VSS D39 AG21 VSS VSS AP58 AW 47 VSS VSS D44 AG71 VSS VSS AP63 AW 49 VSS VSS D45 AH13 VSS VSS AP68 AW 51 VSS VSS D47 AH6 VSS VSS AP70 AW 53 VSS VSS D48 AH63 VSS VSS AR11 AW 55 VSS VSS D53 AH64 VSS VSS AR15 AW 57 VSS VSS D58 AH67 VSS VSS AR16 VSS VSS D6 AJ15 VSS VSS AR20 AW 6 VSS VSS D62 AJ18 VSS VSS AR23 AW 60 VSS VSS D66 AJ20 VSS VSS AR28 AW 62 VSS VSS D69 AJ4 VSS VSS AR35 AW 64 VSS VSS E11 AK11 VSS VSS AR42 AW 66 VSS VSS E15 AK16 VSS VSS AR43 VSS VSS E18 AK18 VSS VSS AR45 AW 8 VSS VSS E21 AK21 VSS VSS AR46 AY66 VSS VSS E46 AK22 VSS VSS AR48 VSS VSS E50 AK27 VSS VSS AR5 B10 VSS VSS E53 AK63 VSS VSS AR50 B14 VSS VSS E56 AK68 VSS VSS AR52 B18 VSS VSS E6 AK69 VSS VSS AR53 B22 VSS VSS E65 AK8 VSS VSS AR55 B30 VSS VSS E71 AL2 VSS VSS AR58 B34 VSS VSS F1 AL28 VSS VSS AR63 B39 VSS VSS F13 AL32 VSS VSS AR8 B44 VSS VSS F2 AL35 VSS VSS AT2 B48 VSS VSS F22 AL38 VSS VSS AT20 B53 VSS VSS F23 AL4 VSS VSS AT23 B58 VSS VSS F27 AL45 VSS VSS AT28 B62 VSS VSS F28 AL48 VSS VSS AT35 B66 VSS VSS F32 AL52 VSS VSS AT4 B71 VSS VSS F33 AL55 VSS VSS AT42 BA1 VSS VSS F35 AL58 VSS VSS AT56 BA10 VSS VSS F37 AL64 VSS VSS AT58 BA14 VSS VSS F38 BA18 VSS VSS F4 BA2 VSS VSS F40 BA23 VSS VSS F42 BA28 VSS VSS BA41 BA32 BA36 F68 BA45 SKYLAKE-U-GP SKYLAKE-U-GP 071.SKYLA.000U 071.SKYLA.000U A 5 43

2 1 D CPU1R 18 OF 20 C B GND 3 OF 3 F8 VSS SKYLAKE_ULT VSS L18 G10 VSS VSS L2 TPAD14-OP-GP G22 VSS VSS L20 G43 VSS VSS L4 NCTF_BB70 1 TP2304 G45 VSS VSS L8 G48 VSS VSS N10 tro-X VSS VSS N13 G5 VSS VSS N19 G52 VSS VSS N21 G55 VSS VSS N6 G58 VSS VSS N65 VSS VSS N68 G6 VSS VSS P17 G60 VSS VSS P19 G63 VSS VSS P20 G66 VSS VSS P21 H15 VSS VSS R13 H18 VSS VSS R6 H71 VSS VSS T15 VSS VSS T17 J11 VSS VSS T18 J13 VSS VSS T2 J25 VSS VSS T21 J28 VSS VSS T4 J32 VSS VSS U10 J35 VSS VSS U63 J38 VSS VSS U64 J42 VSS VSS U66 VSS VSS U67 J8 VSS VSS U69 K16 VSS VSS U70 K18 VSS VSS V16 K22 VSS VSS V17 K61 VSS VSS V18 K63 VSS VSS W 13 K64 VSS VSS W6 K65 VSS VSS W9 K66 VSS VSS Y17 K67 VSS VSS Y19 K68 VSS VSS Y20 K70 VSS VSS Y21 K71 L11 L16 L17 [#543016 Rev0.9] SKYLAKE-U-GP 071.SKYLA.000U <Core Design> A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Document Number CPU_(VSS) Rev A3 Vegas SKL/KBL-U A00 Date: Thursday, June 16, 2016 Sheet 23 of 105 21

543 Main Func = KBC 3D3V_S5 3D3V_S5 3D3V_S5_KBC 3D3V_S5_KBC DY 1D0V_S5 0R0402-PAD SCD1U16V2KX-3GP R2443 R2462 12 10KR2F-2-GP 3D3V_S5 1 R2446 2 2 12 1 PCB_REV 1 R2402 2 EC_VT T 12 R2444 C2406 100KR2F-L1-GP 21 0R0603-PAD SCD1U16V2KX-3GP 0R0402-PAD +VCCST G R2440 BOARD_ID 2 R2474 1BOARD_ID_R +V1.00U_CPU 3D3V_S5_KBC 0R0402-PAD C2408 1 DY 2 0R2J-2-GP R2492 C2421 C2412 C2411 C2410 C2414 C2413 C2417 If don't need RTC alarm wake up, SCD1U16V2KX-3GP 2 1 SCD1U16V2KX-3GP 2 1 SCD1U16V2KX-3GP 2 1 SCD1U16V2KX-3GP 2 1 SCD1U16V2KX-3GP 2 1 SCD1U16V2KX-3GP 2 1 SC2D2U10V3KX-1GP 2 1can change to 3D3V_AUX_S5 21 1 DY 2 C2416 SCD1U16V2KX-3GP 2 1 0R2J-2-GP DY DY DY C2415 Layout Note: SC2D2U10V3KX-1GP 2 1 C2423 EC_AGND D Need very close to EC SCD1U16V2KX-3G2P 1 C2420 3D3V_AUX_S5 RT C_AUX_S5 SCD1U16V2KX-3GP 2 1 DY R247312 12 R2472 0R2J-2-GP 0R0402-PAD ECVBAT EC_AGND 3D3V_AUX_KBC_33 C2428 SCD1U16V2KX-3GP 3D3V_S5_KBC 3D3V_S5_KBC VBAT 122 43 82 KBC24 103 5 19 65 VTR VTR_33_18 54 VTR 1 21 2 65 KSO[0..16] VTR VTR VTR VTR 1 R2403 2 10KR2J-3-GP KSI7 R2450 KSO0 2 GPI O027/KSO00/PVT_I O1 8 SMBDA1 1 R2404 2 10KR2J-3-GP KSI4 100KR2J-1-GP KSO1 14 9 SMBCLK1 1 R2405 2 10KR2J-3-GP KSI2 KSO2 15 GPI O015/KSO01/PVT_CS# GPI O007/SMB01_DATA/SMB01_DATA18 11 1 R2406 2 10KR2J-3-GP KSI1 KSO3 16 12 SMBDA2 KSO4 37 GPI O016/KSO02/PVT_SCLK GPI O010/SMB01_CLK/SMB01_CLK18 89 SMBCLK2 KSO5 38 91 KSO6 39 GPI O017/KSO03/PVT_I O0 GPI O012/SMB02_DATA/SMB02_DATA18 96 L_BKLT _EN_EC KSO7 50 97 GPIO141/SMB04_DAT A/SMB04_DAT A18 KSO9 KSO8 46 GPI O045/BCM_I NT1#/KSO04 GPI O013/SMB02_CLK/SMB02_CLK18 PBAT _PRES# KSO9 68 40 KSO10 72 GPI O046/BCM_DAT1/KSO05 GPI O130/SMB03_DATA/SMB03_DATA18 41 FAN1_T ACH KSO11 74 KSO12 75 GPI O047/BCM_CLK1/KSO06 GPI O131/SMB03_CLK/SMB03_CLK18 44 1 T P2401 T P KSO13 76 45 1 R2407 2 10KR2J-3-GP KSI0 KSO14 77 GPI O025/KSO07/PVT_I O2 GPI O141/SMB04_DATA/SMB04_DATA18 1 R2408 2 10KR2J-3-GP KSI3 KSO15 86 47 1 R2409 2 10KR2J-3-GP KSI5 R2449 KSO16 92 GPI O055/PW M2/KSO08/PVT_I O3 GPI O142/SMB04_CLK/SMB04_CLK18 34 1 R2413 2 10KR2J-3-GP KSI6 100KR2J-1-GP 93 35 DY KSI0 GPI O102/KSO09/CR_STRAP 36 KSI1 98 4 KSI2 99 GPI O106/KSO10 GPI O050/TACH0 Layout Note: MEC1404C KSI3 1 3D3V_S5_KBC KSI4 6 GPI O110/KSO11 GPI O051/TACH1 106 KSI5 7 70 KSI6 104 GPI O111/KSO12 KSI7 105 80 107 GPI O112/PS2_CLK1A/KSO13 GPI O053/PW M0 81 108 GPI O113/PS2_DAT1A/KSO14 GPI O054/PW M1 90 R2427 78 94 1 OPS 2 1 R2425 2 100KR2J-1-GP KSO5 1 R2468 2 100KR2J-1-GP KSO14 79 GPI O125/KSO15 DGPU_PWROK_KBC 1 R2426 2 100KR2J-1-GP KSO7 1 R2477 2 100KR2J-1-GP KSO0 52 95 GPIO030/BCM_INT 0#/PWM4 0R2J-2-GP 1 R2433 2 100KR2J-1-GP KSO12 1 R2480 2 100KR2J-1-GP KSO2 CAP_LED# 88 GPI O132/KSO16 GPI O056/PW M3 1 1 R2447 2 100KR2J-1-GP KSO16 1 R2482 2 100KR2J-1-GP KSO1 101 59 GPI O140/KSO17 GPI O030/BCM_I NT0#/PW M4 102 T P2403 T PA 60 87 65 KSI[0..7] 61 GPI O031/BCM_DAT0/PW M5 62 119 58 GPI O143/KSI 0/DTR# GPI O032/BCM_CLK0/PW M6 120 56 121 57 GPI O144/KSI 1/DCD# GPI O002/PW M7 126 63 127 55 GPI O005/SMB00_DATA/SMB00_DATA18/KSI 2 128 BAT 1_LED# 10 BAT 2_LED# 49 GPI O006/SMB00_CLK/SMB00_CLK18/KSI 3 GPI O157/LED0/TST_CLK_OUT 23 SIO_SLP_S3#_R 53 24 1 R2454 2 100KR2J-1-GP KSO15 1 R2483 2 100KR2J-1-GP KSO3 66 GPI O147/KSI 4/DSR# GPI O156/LED1 22 1 R2486 2 0R2J-2-GP 1 R2459 2 100KR2J-1-GP KSO13 1 R2484 2 100KR2J-1-GP KSO8 1 R2460 2 100KR2J-1-GP KSO11 1 R2488 2 100KR2J-1-GP KSO6 32 GPI O150/KSI 5/RI # GPI O104/LED2 85 1 R2467 2 100KR2J-1-GP KSO10 1 R2494 2 100KR2J-1-GP KSO4 28 20 29 GPI O151/KSI 6/RTS# 25 30 31 GPI O152/KSI 7/CTS# GPI O116/TFDP_DATA/UART_RX 83 27 21 65 CLK_T P_SIO GPI O117/TFDP_CLK/UART_TX 26 67 65 DAT _T P_SIO 69 GPI O114/PS2_CLK0 118 PT P_DIS# Need very clo 71 117 PECI_EC 17 SIO_PWRBT N# 42 GPI O115/PS2_DAT0 GPI O035/SB-TSI _CLK 116 12 33 109 EC_VT T 17 PCH_RSMRST # GPI O026/PS2_CLK1B GPI O033/PECI _DAT/SB_TSI _DAT 110 C2405 R2437 3 111 SC100P50V2JN-3GP 18,68,91 LPC_LAD[3..0] GPI O127/PS2_DAT1B 113 43R2J-GP E 13 114 LPC_LAD0 48 VREF_CPU 115 21 LPC_LAD1 73 LPC_LAD2 GPI O040/LAD0 ICSP_CLOCK DY LPC_LAD3 125 ICSP_DAT A 123 GPI O041/LAD1 GPI O145/I CSP_CLOCK ICSP_CLR GPI O042/LAD2 GPI O146/I CSP_DATA 18,68,91 LPC_LFRAME# GPI O043/LAD3 I CSP_MCLR 17,31,40,55,61,68,76,91 PLT _RST # 2 R2410 1 PCH_PLT RST #_EC GPI O044/LFRAME# EC_MUT E# EC_MUT E# 27 DGPU_PWROK +3VLP 12 18 CLK_PCI_LPC_MEC SIO_EXT _SMI# GPI O064/LRESET# BGPO/GPI O004 DY T P_EN# ALWON 0R0402-PAD C2402 DY 18,91 CLKRUN# GPI O034/PCI _CLK SYSPW R_PRES/GPI O003 VCI_IN1# ALWON 40 SIO_EXT _SCI# POWER_SW_IN# SC220P50V2KX-3GP 18,91 SERIRQ GPI O067/CLKRUN# VCI _OUT/GPI O036 ACAV_IN EC_SPI_CLK 2 R2510 1 EC_SPI_MOSI GPI O063/SER_I RQ VCI _I N1#/GPI O162 EC_SPI_MISO EC2401 DY 10KR2F-2-GP SAT A_LED# GPI O011/SMI #/EMI _I NT# VCI _I N0#/GPI O163 2 R2469 1 0R0402-PAD ACOK_IN 17,44 SCD1U16V2KX-3GP 18 SIO_RCIN# EC_SPI_CS0# GPI O060/KBRST VCI _OVRD_I N/GPI O164 21 RN2401 GPI O061/LPCPD# LCD_VCC_T EST _EN_R 1 R2495 2 0R2J-2-GP LC 4 FA 3 5 EC_SPI_CLK GPI O100/EC_SCI # GPI O160/DAC_0 2 6 EC_SPI_MISO 18,25 SPI_CLK_ROM 1 7 EC_SPI_MOSI GPI O161/DAC_1 18,25 SPI_SO_ROM 8 18,25 SPI_SI_ROM SRN10J-1-GP GPI O126/SHD_SCLK DAC_VREF SCD1U16V2KX-3GP C2429 1 2 3D3V_S5_KBC 64 SAT A_LED# CMP_VOUT 0 R2470 2 18 RT CRST _ON GPI O133/SHD_I O0 CMP_VIN0 CMP_VO VCREF0 CMP_VIN 18,25 SPI_CS_ROM_N0 GPI O134/SHD_I O1 GPI O124/CMP_VOUT0 1 0R0402-PAD GPI O135/SHD_I O2 GPI O020/CMP_VI N0 1 R2490 2 GPI O136/SHD_I O3 GPI O165/CMP_VREF0 0R0402-PAD GPI O123/SHD_CS# CMP_VOUT 1 LCD_T ST 17,40,44,51 SIO_SLP_S4# GPI O120/CMP_VOUT1 GPU_PWR_LEVEL Need very close to EC 43,44 AC_DIS GPI O101/SPI _CLK GPI O021/CMP_VI N1 ALL_SYS_PWRGD assert, BLON_OUT _R 2 DY 1 BLON_OUT _R_R GPI O103/SPI _I O0 GPI O166/CMP_VREF1/UART_CLK delay 10ms; RESET_OUT# assert. 17 ME_SUS_PWR_ACK R2475 0R2J-2-GP GPI O105/SPI _I O1 CMP_ST RAP0 PANEL_BKEN_EC 4,65 INT _T P# 1 R2431 2 PT P_INT #_EC GPI O052/SPI _I O2 GPI O024/CMP_STRAP0 1 R2497 2 0R2J-2-GP BLON_OUT _R MODEL_ID 31 PM_LAN_ENABLE 1 R2491 2 0R0402-PAD LAN_EN GPI O062/SPI _I O3 GPI O023/ADC6/A20M I_ADP SIO_E BOARD_ID 0R0402-PAD GPI O001/SPI _CS#/32KHZ_OUT GPI O022/ADC5 I_SYS I_BAT T USB_EN# GPI O153/ADC4 R2421 2 1 AD_IA 17,40 ALL_SYS_PWRGD 2 R2481 1 0R0402-PAD RUNPWROK RESET_I N#/GPI O014 GPI O154/ADC3 330R2J-3-GP 17,26,40 RESET _OUT # GPI O057/VCC_PW RGD 124 VSS_VBAT GPI O155/ADC2 Need very close to EC SC2200P50V2KX-2GP GPI O107/RESET_OUT# VR_CAP 18 VR_CAP GPI O122/ADC1 12 2 R2428 1 XT AL2 EC_AGND 112 AVSS GPI O121/ADC0 C2435 XT AL1 21 18 SUS_CLK 0R2J-2-GP XTAL2 VSS ADC_VREF 3D3V_S5_KBC VSS XTAL1 VSS R2471 VSS VSS MEC1404-NU-GP 84 PANEL_BKEN_EC 2 DY 51 17 C2427 Elet 64 100 21 12 071.01404.000E C2422 EC_AGND 0R2J-2- I_SYS R2458 21 SCD1U16V2KX-3GP 3D3V_S5_KBC DY 0R2J-2-GP R2493 EC LCD test R2456 XT AL_KBC_2 10KR2F-2-GP 55 EC_BRIGHT NESS 12 21 C2418 0R0402-PAD 55 LCD_T ST _R 1 R2419 2 LCD_T ST SC1U10V2KX-1GP EC_AGND CMP_ST RAP0 0R0402-PAD X2401 1 DY 2 XT AL-32D768KHZ-89-GP SC12P50V2JN-3GPEVT1 2014/10/20C242512082.30003.020112DY EC_AGND C2424DY I_BAT 1 R2445 2 SC12P50V2JN-3GP 0R0402-PAD 100KR2J-1-GP SCD01U50V2KX-1GP Layout Note: C2441 21 B Microchip: Use CL=9p Xtal，C = 10p EC_AGND Connect GND and AGND planes via either 0R resistor or connect directly. EC_AGND EC_GPIO47 High Active 3D3V_S5 3D3V_S5_KBC 21 R2418 R2434 3D3V_S5_KBC 21 100KR2J-1-GP 210R2J-2-GP 3D3V_S5_KBC R2478 121 DY2 100KR2J-1-GP USB_EN# 1 R2479 2 0R0402-PAD USB_PWR_EN# 35 R2414 12 CMP_VOUT 1 1 R2420 2 CMP_VOUT 1_R Q2408 4K7R2J-2-GP EC_DEBUG 2 R2476 1 0R0402-PAD 3D G 0R0402-PAD 12 ICSP_CLOCK ICS D H_PROCHOT #_EC ICSP_DAT A ICS 1 R2416 2 H_PROCHOT # 4,44,46 DY 2 R2463 1 0R0402-PAD S HOST _DEBUG_T X E5 0R0402-PAD C2403 ICSP_CLR 2 R2464 1 0R0402-PAD ICS 2N7002K-2-GP SC47P50V2JN-3GP C2419 R2417 84.2N702.J31 DY 2ND = 84.2N702.031 DY 3rd = 84.07002.I31 DY 2 R2466 1 0R0402-PAD 2 R2465 1 0R0402-PAD A 543

21 3D3V_S5 PCB VERSION A/D(PIN98) PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE R2442 M ODEL_ID_DET(GPIO07) PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE M 00 (SA) 100.0K 10.0K 3.0V 64K9R2F-1-GP X01 (SB) 100.0K 20.0K 2.75V Vegas_SKL_UM A 100.0K 10.0K(64.10025.6DL) 3.0V X02 (SC) 100.0K 33.0K 2.48V MODEL_ID Vegas_KBL_UM A 100.0K 22.1K(64.22125.6DL) 2.702V V X03(SD) 100.0K 47.0K 2.24V SCD1U16V2KX-3GP Turis_SKL_UM A 100.0K 32.4K(64.32425.6DL) 2.492V P A00 (1) 100.0K 64.9K 2.0V 12 Turis_KBL_UM A 100.0K 49.9K(64.49925.6DL) 2.201V 100.0K 76.8 1.87V Vegas_SKL_DIS 100.0K 64.9K(64.64925.6DL) 2.001V Reserved 100.0K 100.0K 1.65V 2 12 1 Vegas_KBL_DIS 100.0K 93.1K(64.93125.6DL) 1.709V Reserved 100.0K 143.0K 1.358V Turis_SKL_DIS 100.0K 120K(64.12035.6DL) 1.499V Reserved 100.0K 174.0K 1.204V Turis_KBL_DIS 100.0K 200K(64.20035.6DL) 1.099V Reserved 100.0K 215.0K 1.048V Reserved MODEL_ID R2441 C2407 100KR2F-L1-GP EC_AGND D 3D3V_S5_KBC SMBCLK1 RN2402 2 SMBDA1 1 3 4 SRN4K7J-8-GP 3D3V_S0 SMBDA1 43,44 3D3V_S5_KBC SMBCLK1 43,44 12 R2430 3D3V_S0 10KR2J-3-GP 2 10KR2J-3-GP PBAT _PRES# R2415 1 2 10KR2J-3-GP SIO_EXT _SCI# SYS_PWROK 17 SIO_EXT _SMI# 1 R2411 2 0R0402-PAD PAD14-OP-GP 1 R2461 2 0R2J-2-GP T OUCH_PANEL_INT R# R2429 1 DY SIO_EXT _SCI#_R 16 PBAT _PRES# SIO_EXT _SMI#_R 8 43,44 DY 1 R2412 2 0R0402-PAD USB_OC3# 16 Touch Panel PH internally. AK FAN_T ACH1 26 R2457 1 DY 2 0R2J-2-GP LID_CL_SIO# 64 D2403 RB751V-40H-GP BKLGT _PWM 65 83.R2004.G8F BEEP 27 DGPU_PWROK 19,79,85 3D3V_S5 AD14-OP-GP 1 R2401 2 BLON_OUT 55 EC_WAKE# L_BKLT _EN_EC 17 0R2J-2-GP RN2405 18 PS_ID 43 DY 27 36 PCIE_WAKE# 31 R24315 DY 2 LID_CL_SIO# 45 T P_EN# 8 L_BKLT _EN 0R2J-2-GP SRN100KJ-5-GP BLON_OUT SIO_SLP_S3# 17,27,40,51 1 22 1 R2436 BAT 1_LED# Q2412 6 BAT T _WHIT E_LED# 65 21 100KR2J-1-GP DY 1 5 3D3V_S5 64 21 2 4 ME_FWP_EC 19 61 3D3V_S5 3 BAT 2_LED# HOST _DEBUG_T X 64 CHG_AMBER_LED# ose to EC 4 LCD_VCC_T EST _EN_R 1 R2487 20R2J-2-GP 2N7002KDW-GP H_PECI DY 84.2N702.A3F SIO_SLP_S3# 17,27,40,51 Q2412 and Q2413 merge 2nd = 84.2N702.E3F ECVBAT 3rd = 75.00601.07C 12 GPIO030/BCM_INT 0#/PWM4 1 R2496 20R2J-2-GP LCD_VCC_T EST _EN 55 D2401 DY 3 R2452 1 L_BKLT _EN 8 C 100KR2J-1-GP 2 BLON_OUT _R 3D3V_AUX_S5 4 add LCD_VCC_TEST_EN R2485 BAT 54C-7-F-3-GP for customer request DVT1 3/1 100KR2J-1-GP DY 75.00054.E7D CD_VCC_T EST _EN 55 R2424 21 12 2nd = 83.R2003.W81 20KR2F-L-GP 21 3rd = 75.00054.A7D AN1_DAC_1 26 Vref = 1.117 temp around 85 3D3V_S0 OUT 0 26 12 IN0_R 26 L 79 3D3V_AUX_S5 R2489 100KR2J-1-GP R2448 C2409 R2453 CAP_LED# 10KR2F-2-GP SCD01U50V2KX-1GP 1KR2J-1-GP S DY D SC2200P50V2KX-2GP tro-X 2N7002K-2-GP CAP_LED#_S 65 84.2N702.J31 EXT _WAKE# 20 +3VLP G 2ND = 84.2N702.031 A 44 Q2414 3rd = 84.07002.I31 3D3V_S0 1 CMP_VIN0_R 26 R2455 -GP For T8 TEMP test 100KR2J-1-GP R2422 1 P_SYS 44,46 I_SYS R2498 LCD_VCC_T EST _EN Power Switch Logic(PSL) 2 0R2J-2-GP 12 330R2J-3-GP DY R2423 64 KBC_PWRBT N# R2432 2 ECVBAT12 2 1 21 R2451 TT 1 boost_mon 44 100KR2J-1-GP SC2200P50V2KX-2GP 330R2J-3-GP 1KR2J-1-GP POWER_SW_IN# C2426 SC1U10V2KX-1GP B Layout Note: Need very close to EC LID_CL_SIO# D2402 A T OUCH_PANEL_INT R# 4,55 PT P_DIS# K RB751V-40H-GP 83.R2004.G8F D2405 A T P_LOCK# 65 K PT P RB751V-40H-GP 83.R2004.G8F D3V_AUX_KBC_R DB3 7 SP_CLK_R 1 SP_DAT A_R 2 51_T XD_R 3 SP_MCLR_R 4 EC_DEBUG 5 6 8 20.K0691.006 ACES-CON6-58-GP A SMBDA2 2 R2438 1 SML1_SMBDAT A SML1_SMBDAT A 18,79 SMBCLK2 0R0402-PAD SML1_SMBCLK SML1_SMBCLK 18,79 2 R2439 1 <Core Design> 0R0402-PAD Wistron Corporation 21F, 88, Sec.1, Hsin T ai Wu Rd., Hsichih, T aipei Hsien 221, T aiwan, R.O.C. T itle KBC SMSC 1404 Size Document Number Rev A1 Date: Vegas SKL/KBL-U A00 Monday, June 27, 2016 Sheet 24 of 105 2 1

54 3 Main Func = SPI Flash D SPI Flash 3D3V_S5_PCH R2501 DY12 RN2501 4K7R2J-2-GP 14 SRN4K7J-8-GP 23 SPI25 C 18,24 SPI_CS_ROM_N0 R2507 1 2 10R2F-L-GP SPI_SO_ROM_R 1 CS# 18,24 SPI_SO_ROM SPI_W P_ROM_R 2 SO/SIO 3 SIO2 4 GND MX25L12 72.12 Elet Main Func = RTC B +RTC_VCC 3D3V_AUX_S5 A AFTP2502 1 +RTC_VCC RTC1 R2502 D2501 3 1KR2J-1-GP 1 PW R 1 21 RTC_PW R GND 2 2 NP1 AFTP2501 NP1 NP2 BAS40C-2-GP NP2 75.00040.07D BAT-40-42010-00211RHF-GP-U2 1 2nd = 75.00040.C 20.F2316.002 Q2505 G 21 R2504 D 10MR2J-L-GP S 2N7002K-2-GP 84.2N702.J31 2ND = 84.2N702.031 543

321 h ROM1(16M) for PCH 3D3V_S5_PCH D C C2501 C2502 SCD1U16V2KX-3GP SC10U10V5KX-2GPDY tro-X O1 VCC 8 3D3V_S5_PCH RN2503 SRN0J-6-GP SPI_CLK_ROM 18,24 21SIO37 14 SPI_SI_ROM 18,24 21SCLK6SPI_HOLD_ROM_R23 21SI/SIO05SPI_CLK_ROM_R SPI_HOLD_ROM 18 SPI_SI_ROM_R SPI_WP_ROM 18 2873FM2I-10G-GP RN2502 SRN0J-6-GP SPI_W P_ROM_R 14 2873.001 23 RTC_AUX_S5 B DY C2503 SCD22U10V2KX-1GP C7D <Core Design> RTC_DET# 20 Wistron Corporation A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Flash/RTC Size Document Number Rev A4 Vegas SKL/KBL-U A00 Date: Monday, June 27, 2016 Sheet 25 of 105 3 21

5 4 3 Main Func = Thermal Sensor D C 3D3V_S5_KBC KBC T8 R26072117,24,40 RESET_OUT# G Q2602 10KR2J-3-GP DY DY R2602 D PURE_HW _SHUTDOW N# 40,79 24 CMP_VOUT0 1 2 THERM_SYS_SHDN# S DY21 C2610 DY 2N7002K-2-GP SCD1U16V2KX-3GP Elet 0R2J-2-GP 84.2N702.J31 2ND = 84.2N702.031 0R0402-PAD 1 R2612 2 Close to KBC Close to Thermal sensor VD_IN1 for system thermal sensor B 3D3V_AUX_S5 3D3V_S5_KBC DY21 21 21 R2608 R2609 25K5R2F-GP 24K9R2F-L-GP 21 C2612 21 CMP_VIN0_R 24 R2610 SCD1U16V2KX-3GP NTC-100K-8-GP C2613 VD_IN1_C SC100P50V2JN-3GP thermistor 1 R2611 2 0R0402-PAD A 543