Laptop Repair Part 1 OCR

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Catalog ~3R-: ~ic.*~~±t&~~~ I Chapter 3 the architecture of the laptop motherboard ·· · ·· ·.. · 1 3.1 Intel xxttf (GMlPM45,& ~ ~) B~~ftj · · ·· ·· 1 5 3.1 The architecture ofIntel double bridges(GM/PM45 and below) ·.. ·5 3.2 Intel.l1f (HM55 ~...t) 8~ ~ftj 5 5 3.2 The architecture oflntel single bridge(above HM55) ·.. 10 3.3 AMD xxl1f (RS780) ~~ftj ·· · · 10 3.3 The architecture ofAMD double bridges(RS780) 3.4 AMD.ttf (A70) ~~ftj .. ·· .. · ·· .. ·· .. ·.. · 3.4 The architecture ofAMD single bridge(A70) 3.5 nVIDIA XX;j;jj: (C51M) ~~ftj 3.5 The architecture ofnVIDIA double bridges (C51M) 3.6 nVIOlA.;j;jj: (MCP67) ~~ftj 3.6 The architecture ofnVIOlA single bridge (MCP67) ~4~ ~ic.*~Mit.*F'HIl~&~~1I¥~\"· Chapter 4 The explanation ofnouns and common concepts of laptop maintenance 4.1 ~Jt!.~ffi% 4.1 Power supply and signal . 4.2 iWiJt!..if~1~Jt!.,.if 4.2 High level and low level . 4.3 ~5f~)JI{~.. 4.3 4.4 4.4 4:5 ~ Scanned by CamScanner

4.b Power good si!-!,nal •· .. ·15 .' } ' t l ' J!4.7 . II lit l''l; ·· 16 4.7 pen ignul 4.8 J\\\".i2\\;(.·j\\@ 4.8 C_t~WJh7 LTi.pJ\\.s}e-l'e3lc. ,tt.'i\"l~o. JInWn sJi~gJn':aI lh Tl.1hJl'~I7II1';lfdSn/.. . 17, •.••••• , •• , 4•9 ······ .. 17 l,::j '5' -(..J 4.9 The exrptQla~nation of the signal name for some manufacturers 4.9.1 4.9.1 Wistron ·.. ·· ···· .. ·.. ··· .. ·· .. ···· .. ·.. ········· .. ···· 18 4.9.2 ii1s: 4.9.2 Quanta 20 4.9.3 f~®! 4.9.3 Asus 23 4.9.4f=:li 4.9.4 Compal ···· .. ······ .. ···24 4.9.5 DELL 4.9.5 DELL 27 4.9.6 'f.:!iIl: 4.9.6 Apple ·.. ·.. ····· .. ···28 4.9.7 9:f~i1s: 4.9.7 Inventec · .. 29 4.9.8 ThinkPad (ffiM) 4.9.8 ThinkPad (IBM) . ~ T~fHt-J~illlJ§lm~ 5.1 rg~l'lg~iifljmffl ~~ . 5.1 The basic application circuit of capacitance . 5.2 ~~.Ilsg~ilflmffl~~ 5.2 The basic application circuit ofthe resistance 5.3 =~&~sg~iIflJ§lffl ~~ . 5.3 The basic application circuit ofthe diode . 5.4 -=J1Hfsg~iIflJ§lffl~S& 5.4 The basic application circuit ofthe audio 5.5 %J~mifsg~iIflJ§lffllti& . 5.5 5.6 5.6 5.7 5.7 ., ' . ~ .'...~ \"ty:.'<1:.' -• -~~~ - -~ \\ Scanned by CamScanner

m .. ,It!.~ ·48 ffl Jt!itl- ···49 tion circuit of the voltage regulator ······················51 ~i!m circuit diagram and the point bitmap .................................................................................... ·51 • uit diagram ...................................................... ··························56 mon point bitmap ...................................................... ······························66 ODofEC and BIOS 68 J,;/J~ and functions of EC 72 fl:itilj: conditions of BIOS ·.. · .. ·· · ·· .. ··80 • ·· .. ·.. ····· .. ·· ··· ess of notebook computer ·• .. · · ·· .. ······ · ······ ·····80 kcomputer ······ ·· ·· · ··8\\ ,,·· · · standard timing · .. ·.. ·.. ····· .. ···· .. ·86 • · · ·.. · ................ ··· .. ·· ........ ·· .... ·· .... ···· .. ····90 ················································90 ........... ·· .... ········ .. ······· .. ··· .. 91 ....... ·· .. ··· .. ·· .......... ········92 ... ·· .. ·93 ................ 94 Scanned by CamScanner

8.2.6 the power and the control signal of ACPI 8.3 1l1'f!~, PWRGD fill,£{. Il!.~;}\" ....... ,.... ·.. ·9 8.3 Clock.PWRGD and tht: res t circuit .. 8.3.1 IIft'l' 1l!.~O ,, , ..................... ·.. <)8 , ., 8.3.1 TPhWe RcGloDckf1c1\\i£rbc'.ul:iItl!.~~ 104 8.3.2 m9Iil 8.3.2 Pft!WJt§R-*JG!JDfIJ¥and the re t circuit ,., , 108 PWM Chapter 9 The explanation ofPWM circuit 108 9.1 PWM rgli'-aft~H 9.1 The inPtWroMducOt~ioTnf1o=JfmP:WllliMMfr circuit 108 112 9.1.1 113 9.1.1 TPhWe Mbriret!f.i~n~rtr1o1'd~·u~c~t)i(orini1o·\"fJ'thfre)(working principle of PWM 9.1.2 9.1.2 TI,e meaning of common English abbreviation in PWM circuit 9.1.3 EI ¥7H.frt!.~ · ·.. · 9.1.3 The boot-strap circuit .• .. 115 9.1.4 ~JlUIl\\rt!).fij~Tirt!ili 9.1.4 Output voltage regulation circuit · • 9.1.5 rt!.Lld'&i~IJrt!:f#· .. ··· .. ·· .. ···· .. ·.. · ·· . · 9.1.5 The voltage detection circuit 9.1.6 rt!.1ftIt;ti~IJrt!:m···· ·· .. ·· .. ·· . 9.1.6 The current detection circuit ·· 9.1.7 T.{f-t~:tt·············· ···· 9.1.7 The working mode 9.2 l~.fJLf4:!.VJ}.·~Jt7Hrr 9.2 Analysis of the standby power chip . 9.2.1 MAX8734A fHfi 9.2.1 Analysis ofMAX8734A . 9.2.2 TPS51125 71'tfi 9.2.2 Analysis ofTPS51125 ,.\":~••:.,. 9.2.3 RT8206AIRT8206B 71'* 9.2.3 Analysis ofRT8206A1RT8206B ,P...!t: 9.3 P3 {ffP;Et!Z Jt*~ 9.3 Analysis of the memory po er suppLy chip 9.3.1 1 L88550A 71'*'\" ,.•'\"•.,'!,~ 9.3.1 Analysis oflSL88550A Scanned by CamScanner

RT8207 :.rHfr············································ 147 .mI.9.2 nalysis of RT8207 152 h 7HJr.4 ~-mF.l!;t L .4 Analysi of the bridge/bus power supply chip J 52 ,.HJr9.4.1 I)i PWM ~llifJ~~ RT8209 9.4.1 Analysis of the single PWM controller RT8209 154 9.4.2 )!)l PWM ~ilJtJ~~ TPS51124 7HJT 9.4.2 Analysis of the dual PWM controller TPS51124 9.5 CPU ~11)~F.l!'HJT·············································································157 9.5 Analysis of CPU core power supply 157 9.S.! CPU VCORE ~rBDgW.~ 9.5.1 The features of CPU VCORE power supply 9.S.2 MAX8770 7Hfi ....... .............................................. ......................... I 60 9.5~ Analysis ofMAX8770 9;-$:3 ISL6260 ~ ............................................................. .... I 73 9.5.3 Au8lysis ofISL6260 9.~ 65'~$J.I~JtISL95831 ~~ 180 .5 omy used chip ISL95831 by HM65 motherboard 9 It626S :StfT ..................... I92 :L6265 by AMD platfonn .. ··· · ············ ·· .. ·202 ·· .. · .. ·· .......... ··· .. · .. ·· .. ·.... · .. ··········202 ··· .. · · .. · ·.. ····· .. ···204 ............. ·.. ·.. ·...... ·.... ·.... ·210 ..· .. ·· .. ·.. ·.. ·· ........ ···227 • !:Ureuit ......... 232 Scanned by CamScanner

Chapter 12 fA=~nalLyAsi-s5o8f9C1oPmHpfaHl ?OIE%M~flUap~tfoJpLc~ir~c~ui'tHrr - 12.1 ····················\"········ .. ···· .. ·2:·,) 12.1 Anal sis of Compal LA_5891 P protecti e isolation and the standb) circuit 12.2 1=~ LA-6631P HiHP~~Eg~1'Hrr \"'··········\"······\"······\"··\"\"·· 26 12.2 A1=na~lyLsiAs -o6f7C5o1mP pHailH?LIA%{-6i!6;3I1'£PlpJ~ro?Htercrtive isolation circuit 2 2 12.3 \"\"\"·\"\"\"\"\"\"\"\"\"\"\"·\"·\"\"\"·\"\"\"· ~13:1f2.3 ~~A~nia-l\\y:siIs~oifcC.o*mEtp!a.l ~LEAt-!6.7j5§I.P~p~rotective isolation circuit ·· .. ····\" ·· .. ··277 ·· .. ···· ···· Chapter 13 Analysis oflnvenyec OEM laptop circuit 13.1 ~~LbZ5: DosXX Dunkel 1.0 f~iHplWi7i!;Eg~ii7H.rr· .......... ·\"\"\"\"\"·\"·\"\"\"\"\"\"\"··· 277 13.1 Analysis oflnventec DosXX Dunkel 1.0 protective isolation circuit 13.2 ~~1J6t DosXX Dunkel 1.0 ffl:mIt~&?Hfi\"'\"'''''''''''''''''''''''''''''''''''''''''''' 283 13.2 Analysis of Inventec DosXX Dunkel 1.0 standby circuit ·.. ········287 13.3 ~~1J6t*f'@.It:m7Hfi\"\"\"\"\"\"'·······\"··················\"··\" 13.3 Analysis of Inventec feature circuit 13.3.1 ocp rQJ!~7tt1T ········· .. ···················· .. ·· .. ·· .. ·· ·············288 13.3.1 Analysis ofOCP circuit 13.3.2 7\\:l§Ilrt!.f'it7tfJT .. ···· .. ·· .. ········ .. ·...... ·.... ······ .. ········· .... ········ .. ···· .. ·.. ··295 13.3.2 Analysis of Big OR GATE circuit 298 m14~ [ntel PC\" 1t-tJ¥ (13115/[7) ~~ *\"Chapter 14 Analysis of Intel PCH sequence(I3/I5/I7) 14. I ~T Intel ME Intel AMT ···· ···..·..·..··· • .. 298 14.1 About Intel ME and Intel AMT 14.2 Intel HM55 ~J~;t:;JttEl.It1\"~7HJi·.. ·.... ·.... ·· .. ···· .. ···· .~.~1Io!l~:'·.:.\"...,. ,-l~\"\"..:....~}.•l!...~ 14.2 Analysis of Intel HM55 series chipset timing sequence 14.3 Intel HM65 *J~1?lJ:.;t:;Jtmlt1\"~7HJi....·.. ········· ... 14.3 Analysis of the chipset timing sequence above Intel HM65 ~15~ $~ K42JR (HM5x) P1J¥~*\" . Chapter 15 Analysis of ASUS K42JR(HM5x) timing sequence 15.1 .. ·.. ·1~fJL;jft~············ ·· ·· .. ···· 15.1 The standby state . 15.2 M:tJt··········· ·· 15.2 Trigger 15.3 7ffJL;jft~··· .. ······ .... ·· ........ ·........··· ..·· 15.3 The boot state . 15.4 rrt~, PG~~tL· .. ··· 15.4 Clock,PG and reset 1ii*~ 16!P- A1286 (HM5x) P1,,~~....~.~~~ Chapter 16 Analysis ofAppleA128~ XIV Scanned by CamScanner

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...... 457 ............ 467 J .... .. ·· .. ·· .. ·· .. ·467 I J ., . .. ···· .... ·470 I2 16 5~) 1 . . , · ...... ·· .. ·492 J J ............... 494 I I .. ·.. · ...... ·497 I .............. 498 ·499 03 Scanned by CamScanner

IJ~ , ..... s . ..• S19 .. SL\\O nd III \\ d 'lillithll\\ \\II III~' pill A.S'I• ........................ .. · · .. · ·542 I ppli 'l\\lioll dill11'il11l , ,.. , , ··············545 ....... , m n luillll' S m:1I~·I\\ . .· . · , . · · \" \" \" , , , , , , , , , , , , , , , , , , , , , , 5·16 ............. ·· .. ················ .. ········· .. · .. ···550 :;w'.:ih~.,-.~.l:i:.h\\o~·•.-•. ' • 554 ............................ 557 563,~\\l...\"\"\"~\"'''''''''' ... Scanned by CamScanner

=====tl ~1.9 ~-I-~pr;r\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"'\" ····· .. ··581 11.9 The network card fault hI,!'.<r.SAT'A.~!..1.10 ··· ···584 -Hz:lJf\"\\ \"J-S< 11)(. 11i-t .....•..........••.•............•.. 586 21.10 SATA interface fault , 21.11 )X1.ffljj11:: lJ t&1lf.t 21.11 The fan interface fault , )88 21.12 ~tJ1ittll~\"\"\"\"\"\"\"\"\"\"\"\"\" 21.12 Crash fault ~221iI $1~~1§~······ 590 Chapter 22 Example of maintenance 590 590 22.1 /f7ftJ1ittll~B<:JtfUi~19~'\"'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' 592 595 22. I The example pf maintenance about don't boot fault 601 606 ~Wtll IBM T61 1'3HJ1. Example I IBM T61 not boot ~f1iJ 211M!! G480 j£*~ilt1'1fm·············································· Example 2 Lenovo G480 inflow water,which cause not boot ~WIJ 3 m-m~iIt~~ Z360 'f'1fm Example 3 lightning stroke cause that Lenovo Z360 does not boot ~f1iJ 4 IBM R60 x:ffl'm····························· ············· .. ·· .. ···· Example 4 IBM R60 no standby ::tWtl 5 fj;.l!iii A42J $ 1I!i'OC!* Example 5 ASUS A42J multiple fauh . ~19tl 6 jf-ilJi3tJ1~$iiJi K42JR xr.Jm··················· Example 6 ASUS K42JR no standby ~f1iJ 7 *~ Aspire 4738G 'f':bnrt! ............•..• Example 7 Acer Aspire 47380 poWi ~f1iJ 8 it<@i K42JR 1':bnrt! . Example 8 ASUS K42JR powered 0 :tf1iJ 9 SONY NS90HS Sil1I1'1fm ...... Example 9 SONY NS90HS .. :t:f1iJ 10 h!!B 410M ~J:.EI! Example 10 Xuri 410M :tWtlll .~ N4030 I3~ Example II DELl:,N40 :tf1iJ 12 *~ LSOO ~ftl!r:r: Scanned by CamScanner

Bxample 12 Toshiba L500 not boot ,. 13 .=.li!. R23 ::ffHfL 63 I Example 13 Samsung R23 not boot ······633 22;2 ~~~'ij:.!tfl.~~f9~·························· ............. 661 Scanned by CamScanner

...... 22.4 Jtft!!.ittpl;1~€fl$~Wtl ··· , 674 674 The maintenance examples of other faults 677 'tif1J 30 Ir-r..w A8E \"t'trl!~I!J.J-m~il\"\"\"'''''''''''·''''''''''''''''·''''·''''·''''''''''''·''''''· Example 30 ASUS A8E large short circuit when install battery 'tif1J 31 IlMl! s10-2 B§11f Example 31 Lenovo s10.2 dark screen Scanned by CamScanner

Chapter Three 3 The architecture of laptop motherboard o the chipset used by the mainstream laptop on the market is onl} two manufacturer.the Intel and AMD Intel is the absolute dominance.Once the most popular nVlDlA has quit the chipset industry in 2010,on the markeuhe notebook computer products \"\"ith nVIOlA chipset are few. 3 1 The architecture of Intel double bridge(GMlPM45 and below) lirtel double bridge architecture.including the 855-GM PM45 chipset. ~~~;J',ddOU~ble bridge architecture.CPU and the orth Bridge are connected through the Orth Bridge also control memory, PCI-E 16X discrete graphics card and card. mini PCI-E slot.etc. 8Ji~ is LPC(Low Pin Count.means one of by EC are keyboard, touch pad LPC bus.or connected the South Scanned by CamScanner

PCB control USB, PCI-E IX, SATA, audio card and other peripheral device. The connection of PCH and EC is still using LPC bus,devices under EC remain unchanged. It was nothing that in the architecture of Intel single bridge,although CPU integrated the graphics card,but the display signal output is not usually output by itself.and after transmitted to PCH through FDI bus.then completed output by PCH.It's different from the next AMD single architecture. The architecture of Intel HM75 chipset as shown in figure 3-2. -2- Scanned by CamScanner

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ZS/HK5 Chief River BLOCK DIAGRAM I=_:A==.,..== r-'- - - - -....,. 0--- intel dill Ivy Bridge PO€ ~ (ij Xl' \"''' i* 8n ..rPGA988 ......, •rS fill cD,\"\"\",XJ7!Jno' ~ \\(I X8 .. ~ ~ Pl,YINTCRT I 2TGr, intel •-Film INT LVOS fill <PCH> c:- 51 I MTA.a-..J INT HOMI I \"\" ..e.t2 1- Panlher Point .. t;i·I:.J;J1,\".~1I1 mBGA989 l6'W!t)li:rtm1 I- Pe-P13 SP1 WLANlWkSUBT P21 at C-.tI\" I 'tl..,..,_. O:J!I .I~ I ,-IIlI\\., t ..\" '~'I'I~ar.) 'OJ:. tltq../lnt.l/u\\'_bl_!\" EC .o_rI La) ::J I I IlPa••,L I si_p un .....I But.~n .,.1 I SATA LI:D II I I VAID' I\"t.ury L&O I I ASaISn I ~\"\" __I ~~ 1&CJlOt.m I I I CA.8UO I II ........ leAN> U:o-'] 3-2 IntelllM7S ,E.;)i·f'.Il~t!;)

,., U~Jh II!II~ J 4~fJ(J~J/:II6~ ~~----_......= = = = = = = = = = =. . . .= ~ 3.3 The architecture of AMD double bridge(RS7~() Because the AMD chipset uses AMD 638-pin PU,so PU can manage IIICInO' y dirculy. The North Bridge manage all PCI-E dcvice,it's difference froln Intcl doublc hridge,pl·i!'.' remember.The North Bridge also integrated the graphics card,and is rcspollsible to output di'lplfly signal. The South Bridge manage audio card, USB, S/\\T/\\, I~ \"etc,and devices ullder I~ , rClnaili \\JnChanged. Here to mention,the BIOS has a variety of work bus,solllc work through X-BUS Iindel Be some work through LPC bus connected in parallel with E ,und some work through Sf'1 bus ected South Bridge independently,this is not Illuch associated with the architecture actually. The architecture ofAMD RS780 as shown in figure 3-3. e architecture of AMD single bridge(A70) AMD chipset A4S(mobile version is ASO) development,it changed to the sin~lc caned FCB.There are a lot of similarities with Intel single bridge,the bridge and devices Care almost the same,so no longer elaborated.The CPU of /\\MD also integrated thc ~ca11ed APU,but it can output the display signal directly,and it's difference with the flntel single bridge. ·teefure ofAMD A70 chipset as shown in figure 3-4. C 67) Scanned by CamScanner

In the architecture of nVlOlA single bridge.the memo!) managed by CPU.and the other i managed b. the Bridge.the large heat release of the bridge.ifs easy to \\\\eld. The architecture ofnVlOlA MCP67 chipset as shown in figure 3-6. I• I • • I I II fi- Scanned by CamScanner

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~~~~~~K.~t, ~**~a-~~.~n~~.~~~o~~~~.~~OO~ ¥*.~J-. ';G~D!~;t1Mi!~~$o Chapter Four The common concepts of laptop and noun explanation About laptop motherboard maintenance,often involving some professional tenninologies of the circuit and signal.To understand the schematic circuit diagram and learn to repair well,we must understand these concepts first. 4.1 Power supply and signal 1£±1N.L. 1f@it!rn1f 5V 1:\\!1li. ~ifJ~73 5V ~I:\\!. jf1fi¥J±tI!1:f\\SJ;fl~ 5V I:\\!lli. ~m ~73m~. ~~~mi¥J~~i£ • •~? On the motherboard,some places have 5V voltage,we called 5V power supply,and some places also have 5V voltage,we called signal,then what's the difference between them? 1. ~Et! l.Power supply ~1:\\!~~~m~~llil:\\!~i¥JI:\\!1li, 1:\\!~~~*oi£I~~~~,~~I:\\!1li~m~~~ EJt~:fiI1f£ 0 \"((0 *~ I:\\!llt:fiI1f£ 7. ~:J!~2&o 1£~ft1t?.5rf, IjffjtB~~ft~i¥J. Power supply is an output current of the voluage and current is~During working,the voltage can not be set higher or 10wer.Ifthe power sURPlyis 10 . SH ~el'I1 set high is not allowed. *1:\\!~~~~m~~ni¥J. ~~~*~ft~ YBAT, 5VALW, +3VO~o The power supply is providing the power to the dcrdl VDDQ, VTT, VBAT, 5VALW, +3VOetc. 1~I:\\!B~~~~~:(m!l4-1 ffi~o The circuit symbol of power supply is +1.5V ? .) -10- Scanned by CamScanner

\" jD=.i~E@.&&IIIJ:j:1. ~lt IJXI;), pp Jr~, 1)(11~~IJA(Jl~ftBilf-'%, ~ul~ 4-2 pfriF. hi the circuit diagram of Apple products.the power supply is generally beginning with PP and en t other special symbols as shown in 4-2. PPQV75 53 MEM 00 4-2 ~:W:f=JMJ~f~tJ:\\:!.iff-'% Figure 4-2 The power supply symbol of Apple products \"*-.iiI!.:Jl~~ [email protected]&&. ¥i1f~±t!1.. ilJi)F ~ ~ It t.iiUflEi::!:-j,j:-it 0 B B~ 3ti RXJj vss, $lie circuit symbol of grounding is shown in figure 4-3 . .....L. (8) (b) Scanned by CamScanner

4.2 4.2 High level and low level ••.~~~~~~~.*~.~n~~*~,~~~mo*~, .~~ml*~o ~.~ ~.~~~~~ ~.*~~, ~~~~~~~ilio@~D~m&~Wm~~~~, 3.3V m~j@j~~o In the digital logic circuitthe low level is represented by O.and the high level is represented by I.The high and low level in the circuit needs to be decided by the circuit,not to be limited to a certain value.But in general.OV is low level and 3.3 is high level. 4.3 Jump and pulse E131'flJ~~m~73ffk~.if-, t!?1l4~~7G, 1nJOO 4-5 ffi~. From high level to jump to a low level,also called the falling edge,as shown in figure 4-5. Figure 4-5 The falling edge wavefonn EI3 j@j~~~73ffk.fl}m;lgiifj, t!?114~-iff-~JIt~ From high jump to low then jump to bigh;a1so 7. -12- Scanned by CamScanner

4.4 The clock signal ~ CLK (CLOCK a~ffii~) , tl!t;ijU~~'tt~:~WjfI1f-tlr:{jt-1-~(j£, 1t~1-~:§ii8~ iJ;iIiIIi'F. It-H+IW.*~1ft;l! Hz <Mftt) 0 1:E±flXJ:1lfiff-1-±B~-~F~F@.~, .~f'Fmlt:Jlt€t~~J::(J(Jm1fii-ttrtRd;ltWH·l', ~~JR~i)i~, rJ1\"!r!' F[=1.~~*tI:J~Rl8~B'.t jn)!t& CPU IW~.~ 100MHz 1lAJ:. *~ PCI i)i~8~®1I!rI~ 33MHz, *~f; PCI-E .. lOOMHz i!ta' USB ~IIiIJi* <;tRJJX;r£i¥H1i=!*J$) (1~!J;j)j*~ 48MHzo {g~t§~ ~~~*tI1ifJ 1W~f+ !Jim**ll 1t!.1li7tfmjJ1H§ 0 1Ytl'tiD. 1*.1 :ff-il'0:1 ~lfr: ff,} ~ I~ ~ 8~ D~- ~~l *[1 It!. _ ~.ift1}. ~f+ffl.!% ~1:E±flXiE1ji;illl 1t!.J§ J3.1I~·t4';t:.:Jt I 1f-iE1tJ§7t~g~~:;: m- Jim _ B;j\"t+fa\"'% 0 l(X:k signal CLK{CLOCK) is to provide a benclmmk for the digital circuit work.so that d vice unified work pace.The basic unit of the clock is Hz(hertz).There is a main ~atiDg:circuit on the main board,the function of this circuit is to provide the clock for all ~i1t:lemain board,for different device,the clock circuit will send different frequency.such as ~~ICY of CPU is more than IOOMHz,to PCI device is 33MHz,to PCI-E device is B controller(integrated in the South Bridge intemal)is 48MHz.But the two connected lit'bilvei:th same clock frequency and voltage to communicate.For example.memory and same clock and voltage to transmit signal nonnally.After main board on nonnally and the clock chip working nonnally,then the clock signal can be can use the oscilloscope or multimeter to measure the clock signal. rR ~-14MHz 1W~*ffl~:(zom 4-8 m~o ighBl ofcloc chip benchmark-14MHz is shown in figure 4-8. ~j.;~\\clhmarK-14MHz Scanned by CamScanner

4.5 4.5 Reset signal ~f\\Lf~-'% RST (RESET O~~~~) n~*1ID:@:}iE.:J;ikill;frr7H€iA1fg,%. ~IJ7ftJtA1, *13z;1]1[ h. i~JAi~t:l!4!.lt4t~7:JMill!.>f; IEn'IWM. ;Jt(\"\"f~ ifLW!, ~JAi%tt!. .>f!oJi~~ .>f~6~¥J @]¥U lUll\\! f. WH,ZlJ, ~1T PCI, JA 3.3V !oJ OV lt46~N@]¥U 3.3V ffJt~--i'-IE1tB1}[f.l1.~t~. 1[ffL i:i.q.-.hVcbF~***RST#, ~lJ PCIRST#, CPURST#, IDERST#~. The literal meaning of reset signal RST is the new signal.Just starting.it will reset automatically,and jump from low level to high level:dllring normal operation,press the reset buttonJrom the high level to jump to the low level then to the high level.For example,for PCI.from 3.3V to jump to OV,then to 3V,which is a normal reset jump.Reset signal is generally expressed as **\"'RST#.such as PCIRST#, CPURST#, IDERST# and so on. ~Z. ~&RR.~~~~4!., ~.1E3IW\".& • • • tt!.~.~\"m*~~1[m, jUl\"'I~J.M1119Jiiii t:l!J.I. IIP!li$Lffi -'%~~:I:..a tt!.1li19 OV. In short,the reset can only be momentary low level,but when the main board works normally.the reset is high level.We said not reset usually,refers to no reset voltage,that is the measurement point voltage ofthe reset signal is OV. ryHJfbtl±lA~ 3.3V ~€i~&, *~j:HTffi1iX; 1.1 V J6f'Fjg CPU 1{i$L, :ta:J1il4-9 fiJT\"ffi. 3.3 V platform reset from the South Bridge after dividing into 1.1 vas the CPU reset shown in fi gllre 4-9. 2llOII2I~ 1414044 00 ~Rev1.11 4.6 1 1- Scanned by CamScanner

po er good Signal PG(POWERGOOO) is used to describe the normal power supply. is UlV\"'lIC(lVe higb. or example after sending the CPU voltage normally.then the CPU power supply send PO signal.The common abbreviations of PG signal are PO, PWRGD, POK, VTTP GD CPUPWRGO,etc. 205 J:f1::iE'WiJEi. 2tw SPOK, :tm~ 4-10 PJT7f-. :r8205 working nonnatly,then send SPOK,is shown in figure 4- J O. VOl f-o'\"-------' POK VFB-2.0v 1114-)0 PO -m-li}1II Figure 4-10 PO signal diagram. 4.7 Scanned by CamScanner

But orne ignal with \"W·.the main board working nonnally must be high. For example, 1999- SHDN# shO\\\\11 in figure 4-12 is the low level control signal for closing MAX 1999. 111ff ffifi!:jf!i::!: EN, PG ~1j§ Ji% ~JJiil.t£ljj~. Timing is through EN, PG and other signals to achieve control. Figure 4-11 the screenshot of VR-PWRGD-CK41 0# signal Figure 4-12 the screenshot of I999-SHDN# signal ==4=.8====J=t==~===11=i=%=:I 4.8 Chip select signal ftm cs ~fi!:;c;ft~1f (Chip Select) • m$~ftitf:EIiiJ-.\\3.~J:~Bti~, fffl~ff­ ~ffiJi%*~*~~J:~~m~~~ffi~~;C;ft~~,~Bt~~~-~ft~ffi%.ftmffi Ji%~mT BIOS ~ft, ~)(-Rim CS#, \"#\" ~jFi~Jt~ff~o Bfi!:El3 CPU 1i:l±I, ~~t milJ1¥H~'F, liE!IJ:!! BIOS 1¥Jo B~flX, IiJI;H}]Z17~Jl9Tm~tf1f& CPU ~N7f~I{'F, ~N BIOS ~~-J.ft~tr-o SPI BIOS JJt4ItiLlnlOO 4-13 WijF, ~tP 1 JJt4I cs#RP BIOS B~ft~ {~-5o 1114-13 SPI BIOS JIlIiftlll -16- Scanned by CamScanner

tP anation of common signal name about some manufacturers. --_.\"- 4!I~raJ, TiIii;tl~-~1t.9i!.r*(jJ,J~.9i!.fJL~f§~ ~l1J;. jffl~i5tllJ]A~ ~ffJoit~ ~tIU1H~, i!-.~tE~ ~~~00 I1t- JE~fHlIllR7t. fP.ffi.'is different in the name of signal,some common types and signal name in ((jIioUJd be noted that not all signal names are the same for each manufacturer.it ~~~.when we read the circuit diagram. Scanned by CamScanner

LID-CLOSE!; close cover switch CLK-E # after CPU power supply being normal.sent the 10\\\\ level that can be used to op n the clock. G792-RST# the high level sent by the temperature control chip when the temperature is normal CK-PWRGD after the South Bridge receiving VRMPWRGD.5ent the high level for opening the clock. i1 ff: Explanation jlil£ll3~~I1J*IrJ:n-1 EE./f fR .y. ~ f:l; S'Im.1! \\ilnw 0P<.r!1. AD... DCBATOUT 3 3V tlGtU/t!t!.. i1t EC fI~Fl!. -3VL rc;1!!.'I:.'!; trJlItt1!~A DCIN ACIN 1fLt!.ZI\\trJ~I£~f,t~~A ACAV IN PWR 55 EN !t)I!..c;HlY1.i.?il£ 25 r.ll.4~ I1J ·5VALW. t3VALW AD INa. AC INa IJI J 7ffrimt(rf;'tj/lLt!n;:trJt2~IJki.y. KHC rWR BTN# LID CL05E11 r.llm~If1.{It!\\!. CLK ENu G79:!. RST/I ~~ EC O!Jili~~ilf1iJ-l}. fltLt! 'f-«~;iliI£3~ttfj J\\. CK_PWRGD I1rF Jf*f\"!tlYiilHi't EC (JlJti~{il1i} ~ll*~ CPU fltEtliE'Ml'lS. £lI:IO!JfltEtl\"l'. iifIlJHf\"Jt.tt'!' .~~~~~iE~~~I1JO!J.!\\!.\"I' ltJ~ftJVRMPWRGDJ6. ~lI:IOIJ.EI!.\"I'. 1lJ-F*JfIJ1ott+ I~/V1../ 4.9.2 J\":..}-,. Quanta w.rjEffil*~'li' fa ~ .gft.m~ 4-2. Some of common signal names about Quanta shown in tab) Table 4-2 the list of orne common ..2\"';~·::!.!.I~ VIN the common point voltage ACIN \\ ACOK adapter detection 3V-AL, 5V-AL, VL 3VPCU, 5VPCU 3V- 5 trigger witch. 3V U , IR Scanned by CamScanner

;power on the trigger signal,press the power key to produce high-low-high signal to Be sent high-low-high effective trigger signal to the South Bridge PWRBTN# ACPI controller signal sent by the South Bridge is used to opening voltage receiving SLP-S5# from the South Bridge,then producing S3 voltage opening receiving SLP-S3# from the South Bridge,then producing SO voltage opening 'c Bild all power supply except the CPU core power supply. ived'1iigh level HWPG signal,delay producing PWROK-EC signal. core voltage power managed the clock open signal from chip,low CK-PWRGD open clock chip after receiving VRMPWRG D. Slm~ CPUPWRGD signal delay buffer Scanned by CamScanner

= BLlC# represent high level,low battery (only for battery model) D/C# inverse relationship with ACIN(for only D/C#.main board without BLlC#) ii'l IJ ~ It Stgn31 Name f1~ If- Explanation VIN o J~.¢.i~l!Jf ACIN. ACOK ilina*1&i'i!I) 3V AL. 5V AL. VL +3VPCU. •5VPCU 3V. 5V f.J(!'llJ~F\\! EC nWf./JUM!. til ~ -g It iii' ff 3V S5 ~~~T~~ffi. ~ffi~m~~. ~R*~~, ~~rrg ... 3VSUS. +5VSUS NBSWON# S3 :tX~nYrt!H,. Jl;J1f.fI~F\\l, III EC ZtW SUSON JFFw DNBSWON# ~i'Jt*.jU!l1..i3f:l-Y-, j1iT~i'J;DfY.:ml\"\"l-:i;'f,-il~-I:;,rJ%:i-Y-'f, EC SLPS4#. SLP.S3# 55 ON EC 1;tWA~JiI'Jj-fl5;-il'Jjff~fI!h~irl \\}!£,+Jt1fAY PWRBTN# SUSON MAINON i¥lt/fUtHOY ACPI12fM:I»fil-Y-, mILn·l J.Il-j-~Ili7fJA, ;)HILII·l mT-tI!.Ili~I'?l VR ON IIWPO EC 1,tW(Mjll'fj~tJLF\\!J~:lrFwfR 1;. JtftJll.J1:t.'l PCU ~iJ~ S5 rl!1f.: PWROK.EC DELA Y VR.PWG EC ll~l£~JlWll'f:tl:*A~ SLP S5#Jrii\"'':En~ S3 rt!!:liJrFwi;'j I; VR.PWRGD.CK410# CK PWRGO EC tl~Utlj$jfli:R*rt:l SLP S3# ~j\"\"1:C(.j SO ~ffiJf 1.:1 ifl-lJ' CPUPWRGO PLTRSTh EC 1;tWA':I CPU ~·C.·rt!It.:JFFwfR~ I'CIRST# CPURST# ~'* CPU ~·C.·fJttl!.~).~~rt:lm1-H't~n~ PO j~UUl1E1ilii* BUC# EC I/l{JIjitlirt!lf'- HWPG fA ~'Fn, j,[Rti\"'':E PWROK EC fa~' O'C# CPU ~·ul\\!.llitl!iU!l!fra-l} CPU ~oUtl!litl!ill'l!JI~Wl>ttliC(.jp.jt'l'7flfHa-lt, il~tt!.lf'- Mfmi&jj VRMPWRGO Ttl, 1,tUJ CK]WROO JfIi1lIl1\\'1'.t:::J.1' _fl'L&tEMftlf~8Il PWROK VRMPWRGO IlllHtLjlljfll'3'~i:l ~i!mr\"1: CPUPWRGD If'-&.~. MftlftE1,tUJ CPUPWRGO ffl i}zTtl. ~M:iill1t1l'!'1,tUJ PLTRST# PCIj[fl'L. /fiT.l:.tt!.JIlt1J[fl'L PCI.l!lil!.J:l'JI.JlU\" ft!li~JAWJtfI~~7f!lliIf1' CPU ll«LftJi}. ~tM~ PLTRSTIIJB1,tW CPURSTII~ CPU itlirt!~. ~~~t&(&mT~~) .!J; ACIN /i.tftLifllJ~. (iiJDffitf DIC#. 'illf BlJCtIfIlJ~-l!t) [)(){> 4.9.3 $fi9i ASUS ip,@j1f1.11t~ ~ra-Ji}~$m~ 4-3. Figure 4-3 AC-BAT-SYS ACIN adapter detection 20- Scanned by CamScanner

SV linear voltage 3V linear voltage +SVAO renamed +5VA after jumper +3VAO renamed +3VA after jumper JP81 0 I +3VA renamed +3VA-EC after through the inductance as the power supply of EC sv standby voltage in S5 donnant state 3¥ standby voltage in S5 donnant state +'SVO renamed +5VSUS after jumper +3VO renamed +3VSUS after jumper SUS voltage power-good signal,to EC the reset signal of the South Bridge ACPI controller,can be understood that the ~~~iYing PWRSW-EC,EC sent PM-PWRBTN# effective trigger to the Scanned by CamScanner

= It -\\ I ) I·e deln. l'd ')l)I1\\S 10 semi VI{-ON aner sending SlJSI1-0NJor opening l' core \\( 1t.1 l E - LK-E EC -cnl VRMPWR to the outh Bridge pin.infonn the South Bridge that CPU core voltage i nom1al CLK-PWRGD the outh Bridge generated CLK-PWRGD to IC clock after receiving \\ RMPWRGD.for opening the clock signal PM-PWROK after receiving ALL-SYSTEM-PWRGD.EC delayed sending PW-PWROK H-CPlJRST# the North Bridge sent H-CPURST# to CPU after receiving PLTRST# signal GATE-PWR-SW# the boot trigger signal L1D-SW# close-lid sleep switch signal,when the machine is closed.the signal is low level L1D-KBC# the close-lid sleep switch detection signal for EC KBCRSM the keyboard wake-up signal FORCE-OFF# the forced shutdown signal,generated by the undervoltage protection circuit HW-PROTECT# CPU overtemperature protection signal OTP-RESET# CPU overtemeprature indication signal .. \"Explanation ACIN ·5VAO ~3VAO ~3VA \"5VO 43VO +5VSUS +3VSUS VSUS ON SUS PWRGD -22- Scanned by CamScanner

EC lt~!{i'IJ I'WRSW ECf/lfi'l,(.II\\ I'M I'WRBTNII (TXdl!lI'l,;.\"'.lm(rn~ I'WRI3TNIIIJ.!WI. so 11!.IL:;n:lri In I} l~lffl~1I:fIJ VRMI'WRGD Jiii\"'1: CLK]WRGD gll·Ii'l' IC. Jlrf JFIJIIott<i'lh \\'; EC ~\\(flj ALL_SYSTEM]WRGD Jf;. JiIl·t&IIII'M I'WROK fa'} Jtffl~\\(flj I'LTRSTf/lo'I r; lii'l.Zlll H CI'URSTII g CPU the list of some common signal names about Compal sigD8.1 is inserted to the adapter and the high level represents that the Scanned by CamScanner

PBTNOUT# the boot trigger signal sent by EC to the South Bridge SYSON S3 voltage open signal SUSP# SO voltage open signal +VCCP the working voltage of CPU front side bus,this voltage distributes in CPU, the North Bridge, the South Bridge +CPU-CORE CPU core voltage VGATE CPU core voltage power-good signal ICH-POK PWROS for the South Bridge,inform the South Bridge system voltage power good BCLK the front side bus clock signal SUS-STAT# sent by the Soth Bridge,the low level indicates that the system will be power-down mode Wi ~ Explanation ra -l} ~ It Signal Name B+ PACIN VL +3VALW, +5VALW ON/OFFBTN# ON/OFF# PBTNOUT# SYSON SUSP# +VCCP VGATE BCLK [){)C> 4.9.5 DEIL -24- Scanned by CamScanner

Figure the list of some common signal names about DELL the motehrboard button battery voltage power adapter voltage input the common point voltage Ee sent a ALWON signal to the system power supply chip,to open the system p wcr overheat protection signal active-low level a low voltage signal generated by the power switch or keyboard,and Ee chip receiv~ the trigger signal,EC sent SUS-ON to used to open the South Bridge Scanned by CamScanner

PGD-IN one of the conditions of that CPU power supply chip sent CLK-EN#, PGOOD and others. CLK-ENABLE# the open signal of clock chip,active-Iow level H-PWRGOOD PGD reset signal sent by the South Bridge to CPU H-RESET# the North Bridge sent CPU reset signal +VCHGR charging output voltage +SBATT Auxiliary battery power supply terminal +PBATT main batter power supply terminal SBAT-PRES# insert the auxiliary battery to detection PBAT-PRES# insert the main battery to detection IMVP-VR-ON open CPU power supply IMVP-PWRGD power supply good signal sent by CPU power supply chip IF! .q. .g ~ Signal Name ... ~ Explanation ALWON RUNPWROK SUSPWROK -26- Scanned by CamScanner

CHGR S!MlT If.1'BAlT JHl CPU fJ~rt! t:::Dt> 4.9.6 •• APPLE • •ifI#,*~m%~~~~4-6. Some ofcornmon signal names about APPLE shown in figure 4-6 Figure 4-6 the list of some signal names about APPLE V42-G3H-REG 3.42V power supply in the condition of G3 equivalent to the linear power Iy of other machines. 3.3V power supply in the condition of S5 provided the standby voltage to the 3.3V power supply ofthe South Bridge RTC circuit common point voltage the indicator signal oflow battery voltage,active-low level S3 state voltage(memory supply) of L8V open signal from all power supply good signal except CPU power supply converge ,.....,...,...c\"'l\"oc~sent by CPU power supply chip after -27 Scanned by CamScanner

MC-ADAPTER-EN the high level signal,olltpllt by SMC after receiving the adapter detection signal SMC-BATT-CHG-EN the charging enable signal,sent by SMC active-high level SMC-BATT-TRICKLE-EN-L the trickle charging signal,sent by SMC.active-low level ACPRN low level ACPRN sent by charging chip after the adapter is detected ONEWIRE-EN ONEWIRE enable signal,for the adapter to identi1)t circuit(the head of power is green) \" ff Explanation fn .y. 'Z It Signal Name G3 :tIC~rR!j 3.42V fJ!!\\! • .mllT:Jtitl!milSR!jt~t.H:J~f\\! S5 :tR~rlY:J 3.3V mil!.. !*WHJj:~!lHJWjmLt!.lli -PP3V42 G3H REG PP3V3 S5 REG mt#fB'1 RTC !\\!2II((oJ 3.3V mf\\! PP3V3 G3 SB RTC ~:Jl< l,( 4!..ffi -PPBUSA G311 PM BATLOW L Il!.tmll!.lIiflH~~m-l}. fLt;Lt!.'JllHt: IV8S3_RUNSS ALL. SYS PWRGD I.8V ((oj S3 :tIC$fI!ffi (~ffmfl!) *.€HB~ VR]WRGOOD_DELA Y Il! CPU fJtfl!~;.l*lY:Jl1TliffM!tfm~'\".!;jiJiBI~ VR PWRGD_O:.505_L CPU mfl!~Jt:iE,*1\"~ CPU 1l!.8£.I6. IiIl't~tI.IB'1!f!.tf fii .y. 'Z ~ CPU fJ!1l!.;c::Jt :iE,*\"1\"~ CPU fl!IDii • .ttI:lHfJaIt.j't-I'CJlJfl1;rt!'Jlra~ SMC_BC ACOK .*' SMC_ADAPTER_EN SMC BATT CUG EN ilil:.ltl!lfilf~. ..Et!.1f'1lf~ SMC_BATT TRICKLE EN_L ACPRN SMC a&jfJiil:hlJ!U*~JS • •wfICJliEt!~-IJ ONEWfRE EN SMC .ttll:l flCJ1t;Et!flt!1!-IJ. ..Et!.lf• • SMC.ttWfICJ~.1t;Et!1!~ • •~.\"... 1t;rt!~Jtltl!lft.~JS~~~~A~ ONEWIRE flfl1fl-lt. lOTiiEII:ISUJIJU (Et!.~M'm [)(){> 4.9.7 ~.ill!~ INVENTEC ~~iE$7t1it mf§-%}i?if;m~4-7. Some of common signal names about INVENTEC Sbo .4-7 +VADP adapter interface voltag ~28 . Scanned by CamScanner

~1.~·:E1N:# adapter enable active-low adapter detection output,it can be used to open the system power suppl) directly common point voltage linear power supply the signal sent by trigger switch to EC the power signal,is sent by EC after EC receiving trigger switch,is used to open the .~~n·:standby power supply under the battery mode the initial reset signal ofEC standby power supply system the adapter intermediate pin,power identification signal M- ff Explanation ~~IBM) shown in figure 4-8 Scanned by CamScanner

In \\, t; Fl' SIIlIl.ll N;l11w 'IV H Explimullun noc K I'W lun I· it~ I\\(~ :!~ Il!. /Ii t \\'_0 jiS~~~ 1)0J\" f.f... LIIIJn~J i 1l!.1I VIN r:!o ~}J\".o:'!'. DISCIIARGE ~~'ln,IJ XI iJUl tl~ m; , ll!.il!!!Jl(Il!.f,·1 \\1 -I'WRSIIUTDOWN VCCJSW Ji/I.!. ~lrf~~~f;.Ij, J[J·:r-~';lmU!I'iC~fr -EXTPWR TB ,i:::H4JIlWfl:)3.3V fl!./I;. J.:H.-PWRSIIUTDOWN, ~1f)tlli,1::·H fJlFl! -EXTPWR ASIC 1Ct1:!.;;:';H-~~ 1±I0~i5:n~:t~If:l:it!IHrt\"1. fl~t1:!.'fH~ -EXTPWR 118 VL5 JOClli·i:::J4 A%1J:l\\C$r.;i¥'~4u~Af;:' ~ DCIN DRV 118S O:Ji5:tf~~~f\"&mtl~'J;JAlaJ,} I;. ~ ~ f~: flJ!11.,i:::Hr:1:.fl~ 5V tJH'lF\\!lli BAT_DR V MI_ON rnTtl!:hIMlli!~CAI1\\Ii\"''l!f • ,;'jt1:!. 'l'U·J 7C3t.\\T-il.!iifi~~I:M\"'fr VCC5M VCC3M TB <'>Jt-ttIlJJ M EMUE'M\"Jii. 1!I~.Ii8lJ 28V _Ji2SV). Ji\"f_iU'JI.tiI TII_DET CA N#ililUilUI' ACDET SWPWRG VREGIN20 BAT_VOLT MPWRG -H8_RESET VDDI5 VCPIN28 BPWRG AMTPWRG -PWRSWITCH. -PWRSW M_BATVOLT MJRCI. _TRCI. 30- Scanned by CamScanner

the adapter voltage the voltage between adapter and common point forced to close adapter,battery discharge signal over-temperature and under-voltage protection signal,used to isolate the 3.3V voltage,output by TB chip,pull-up -PWRSHUTDOWN,to supply power to the the adapter detection signal,output by the charging chip,active-Iow level the adapter detection input signal ofthe Lenovo chip the adapter detection input signal ofH8S efSXTlinearvoltage,generated by the standby chip the spacer tube,used to control adapter,turned-on the adapter spacer tube fully at high tube used to control the battery,isolated the battery in a high level is Scanned by CamScanner

WPWRG the standby voltage good rthe Lcnovo chip VREGI 20 the voltage with a small current generated after the adapter or battery accessing to.for the power upply orTB chip. BAT-VOLT VREGrN20 voltage detection pin,the threshold is 2.9V MPWRG TB chip detects VCC3M, VCCSM are nonnal,sent PClRSMRST# to the South Bridge -H8-RESET the reset sent by Lenovo chip to H8S VDDIS TB chip detects M voltage is nonnal,bootstrap boost 15V.To provide power to xx-DRY orTB chip output VCPIN28 TB chip detects M voltage is nonnal,bootstrap boost 28V(is 25V in fact),N channel field-effect tube for driving and protecting the isolating circuit A-ON A voltage is turned on(S3 voltage,such as memory power supply) B-ON B voltage is turned on(SO voltage,such as the bus PQwer syPPly) B-DRV B voltage drive signal,sent by TB chip BPWRG power-good,sent by TB chip after detecting AMT-ON ME module voltage is turned on SLP-M# sent by the South Bridge,used to contto~ AMTPWRG AMT power-good -PWRSWITCH, -PWRSW BATMON-EN M-BATVOLT M I-DRV, M2-DRV -32- Scanned by CamScanner